T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
2022-02-10 20:57:29 +00:00
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namespace ARMeilleure.Decoders
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{
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class OpCodeT16AluImmZero : OpCodeT16, IOpCode32AluImm
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{
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public int Rd { get; }
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public int Rn { get; }
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2022-02-14 21:06:24 +00:00
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public bool? SetFlags => null;
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T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
2022-02-10 20:57:29 +00:00
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public int Immediate { get; }
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public bool IsRotated { get; }
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2022-02-14 21:06:24 +00:00
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public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImmZero(inst, address, opCode);
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T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
2022-02-10 20:57:29 +00:00
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2022-02-14 21:06:24 +00:00
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public OpCodeT16AluImmZero(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
2022-02-10 20:57:29 +00:00
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{
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Rd = (opCode >> 0) & 0x7;
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Rn = (opCode >> 3) & 0x7;
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Immediate = 0;
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IsRotated = false;
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}
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}
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2022-02-14 21:06:24 +00:00
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}
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