2019-02-04 21:26:05 +00:00
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using ChocolArm64.Decoders;
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using ChocolArm64.Events;
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2019-04-26 04:55:12 +00:00
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using ChocolArm64.IntermediateRepresentation;
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2019-02-04 21:26:05 +00:00
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using System;
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2019-04-26 04:55:12 +00:00
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using System.Reflection.Emit;
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2019-02-04 21:26:05 +00:00
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using System.Threading;
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namespace ChocolArm64.Translation
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{
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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public class Translator : ARMeilleure.Translation.ITranslator
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2019-02-04 21:26:05 +00:00
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{
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private MemoryManager _memory;
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private CpuThreadState _dummyThreadState;
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private TranslatorCache _cache;
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private TranslatorQueue _queue;
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private Thread _backgroundTranslator;
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public event EventHandler<CpuTraceEventArgs> CpuTrace;
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public bool EnableCpuTrace { get; set; }
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private volatile int _threadCount;
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public Translator(MemoryManager memory)
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{
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_memory = memory;
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_dummyThreadState = new CpuThreadState();
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_dummyThreadState.Running = false;
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_cache = new TranslatorCache();
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_queue = new TranslatorQueue();
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}
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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public void Execute(ARMeilleure.State.IExecutionContext ctx, ulong address)
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2019-02-04 21:26:05 +00:00
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{
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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CpuThreadState state = (CpuThreadState)ctx;
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long position = (long)address;
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2019-02-04 21:26:05 +00:00
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if (Interlocked.Increment(ref _threadCount) == 1)
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{
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_backgroundTranslator = new Thread(TranslateQueuedSubs);
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_backgroundTranslator.Start();
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}
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state.CurrentTranslator = this;
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do
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{
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if (EnableCpuTrace)
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{
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CpuTrace?.Invoke(this, new CpuTraceEventArgs(position));
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}
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2019-02-28 02:03:31 +00:00
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if (!_cache.TryGetSubroutine(position, out TranslatedSub sub))
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{
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sub = TranslateLowCq(position, state.GetExecutionMode());
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}
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2019-02-04 21:26:05 +00:00
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2019-02-28 02:03:31 +00:00
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position = sub.Execute(state, _memory);
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2019-02-04 21:26:05 +00:00
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}
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while (position != 0 && state.Running);
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state.CurrentTranslator = null;
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 18:56:22 +00:00
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if (Interlocked.Decrement(ref _threadCount) == 0)
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{
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_queue.ForceSignal();
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}
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2019-02-04 21:26:05 +00:00
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}
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2019-02-28 02:03:31 +00:00
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internal ArmSubroutine GetOrTranslateSubroutine(CpuThreadState state, long position, CallType cs)
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2019-02-04 21:26:05 +00:00
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{
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if (!_cache.TryGetSubroutine(position, out TranslatedSub sub))
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{
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sub = TranslateLowCq(position, state.GetExecutionMode());
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}
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2019-04-26 04:55:12 +00:00
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if (sub.Rejit())
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2019-02-04 21:26:05 +00:00
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{
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2019-02-28 02:03:31 +00:00
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bool isComplete = cs == CallType.Call ||
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cs == CallType.VirtualCall;
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2019-02-04 21:26:05 +00:00
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2019-02-28 02:03:31 +00:00
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_queue.Enqueue(position, state.GetExecutionMode(), TranslationTier.Tier1, isComplete);
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2019-02-04 21:26:05 +00:00
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}
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2019-02-28 02:03:31 +00:00
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return sub.Delegate;
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2019-02-04 21:26:05 +00:00
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}
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private void TranslateQueuedSubs()
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{
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while (_threadCount != 0)
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{
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if (_queue.TryDequeue(out TranslatorQueueItem item))
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{
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bool isCached = _cache.TryGetSubroutine(item.Position, out TranslatedSub sub);
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if (isCached && item.Tier <= sub.Tier)
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{
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continue;
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}
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if (item.Tier == TranslationTier.Tier0)
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{
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TranslateLowCq(item.Position, item.Mode);
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}
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else
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{
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2019-02-28 02:03:31 +00:00
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TranslateHighCq(item.Position, item.Mode, item.IsComplete);
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2019-02-04 21:26:05 +00:00
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}
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}
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else
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{
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_queue.WaitForItems();
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}
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}
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}
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private TranslatedSub TranslateLowCq(long position, ExecutionMode mode)
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{
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2019-04-26 04:55:12 +00:00
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Block[] blocks = Decoder.DecodeBasicBlock(_memory, (ulong)position, mode);
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2019-02-04 21:26:05 +00:00
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2019-04-26 04:55:12 +00:00
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ILEmitterCtx context = new ILEmitterCtx(_memory, _cache, _queue, TranslationTier.Tier0);
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2019-02-04 21:26:05 +00:00
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2019-04-26 04:55:12 +00:00
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BasicBlock[] bbs = EmitAndGetBlocks(context, blocks);
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2019-02-04 21:26:05 +00:00
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2019-04-26 04:55:12 +00:00
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TranslatedSubBuilder builder = new TranslatedSubBuilder(mode);
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2019-02-28 02:03:31 +00:00
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2019-04-26 04:55:12 +00:00
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string name = GetSubroutineName(position);
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2019-02-04 21:26:05 +00:00
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2019-04-26 04:55:12 +00:00
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TranslatedSub subroutine = builder.Build(bbs, name, TranslationTier.Tier0);
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2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
return _cache.GetOrAdd(position, subroutine, GetOpsCount(bbs));
|
2019-02-04 21:26:05 +00:00
|
|
|
}
|
|
|
|
|
2019-02-28 02:03:31 +00:00
|
|
|
private TranslatedSub TranslateHighCq(long position, ExecutionMode mode, bool isComplete)
|
2019-02-04 21:26:05 +00:00
|
|
|
{
|
2019-04-26 04:55:12 +00:00
|
|
|
Block[] blocks = Decoder.DecodeSubroutine(_memory, (ulong)position, mode);
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
ILEmitterCtx context = new ILEmitterCtx(_memory, _cache, _queue, TranslationTier.Tier1);
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
if (blocks[0].Address != (ulong)position)
|
|
|
|
{
|
|
|
|
context.Emit(OpCodes.Br, context.GetLabel(position));
|
|
|
|
}
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
BasicBlock[] bbs = EmitAndGetBlocks(context, blocks);
|
2019-02-28 02:03:31 +00:00
|
|
|
|
|
|
|
isComplete &= !context.HasIndirectJump;
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
TranslatedSubBuilder builder = new TranslatedSubBuilder(mode, isComplete);
|
2019-02-28 02:03:31 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
string name = GetSubroutineName(position);
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
TranslatedSub subroutine = builder.Build(bbs, name, TranslationTier.Tier1, context.HasSlowCall);
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-02-28 02:03:31 +00:00
|
|
|
ForceAheadOfTimeCompilation(subroutine);
|
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
_cache.AddOrUpdate(position, subroutine, GetOpsCount(bbs));
|
2019-02-04 21:26:05 +00:00
|
|
|
|
2019-02-28 02:03:31 +00:00
|
|
|
return subroutine;
|
2019-02-04 21:26:05 +00:00
|
|
|
}
|
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
private static BasicBlock[] EmitAndGetBlocks(ILEmitterCtx context, Block[] blocks)
|
|
|
|
{
|
|
|
|
for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++)
|
|
|
|
{
|
|
|
|
Block block = blocks[blkIndex];
|
|
|
|
|
|
|
|
context.CurrBlock = block;
|
|
|
|
|
|
|
|
context.MarkLabel(context.GetLabel((long)block.Address));
|
|
|
|
|
|
|
|
for (int opcIndex = 0; opcIndex < block.OpCodes.Count; opcIndex++)
|
|
|
|
{
|
|
|
|
OpCode64 opCode = block.OpCodes[opcIndex];
|
|
|
|
|
|
|
|
context.CurrOp = opCode;
|
|
|
|
|
|
|
|
bool isLastOp = opcIndex == block.OpCodes.Count - 1;
|
|
|
|
|
|
|
|
if (isLastOp && block.Branch != null && block.Branch.Address <= block.Address)
|
|
|
|
{
|
|
|
|
context.EmitSynchronization();
|
|
|
|
}
|
|
|
|
|
|
|
|
ILLabel lblPredicateSkip = null;
|
|
|
|
|
|
|
|
if (opCode is OpCode32 op && op.Cond < Condition.Al)
|
|
|
|
{
|
|
|
|
lblPredicateSkip = new ILLabel();
|
|
|
|
|
|
|
|
context.EmitCondBranch(lblPredicateSkip, op.Cond.Invert());
|
|
|
|
}
|
|
|
|
|
|
|
|
opCode.Emitter(context);
|
|
|
|
|
|
|
|
if (lblPredicateSkip != null)
|
|
|
|
{
|
|
|
|
context.MarkLabel(lblPredicateSkip);
|
|
|
|
|
|
|
|
context.ResetBlockStateForPredicatedOp();
|
|
|
|
|
2019-07-02 02:39:22 +00:00
|
|
|
// If this is the last op on the block, and there's no "next" block
|
|
|
|
// after this one, then we have to return right now, with the address
|
|
|
|
// of the next instruction to be executed (in the case that the condition
|
|
|
|
// is false, and the branch was not taken, as all basic blocks should end
|
|
|
|
// with some kind of branch).
|
2019-04-26 04:55:12 +00:00
|
|
|
if (isLastOp && block.Next == null)
|
|
|
|
{
|
|
|
|
context.EmitStoreContext();
|
|
|
|
context.EmitLdc_I8(opCode.Position + opCode.OpCodeSizeInBytes);
|
|
|
|
|
|
|
|
context.Emit(OpCodes.Ret);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return context.GetBlocks();
|
|
|
|
}
|
|
|
|
|
|
|
|
private static string GetSubroutineName(long position)
|
2019-02-04 21:26:05 +00:00
|
|
|
{
|
|
|
|
return $"Sub{position:x16}";
|
|
|
|
}
|
|
|
|
|
2019-04-26 04:55:12 +00:00
|
|
|
private static int GetOpsCount(BasicBlock[] blocks)
|
|
|
|
{
|
|
|
|
int opCount = 0;
|
|
|
|
|
|
|
|
foreach (BasicBlock block in blocks)
|
|
|
|
{
|
|
|
|
opCount += block.Count;
|
|
|
|
}
|
|
|
|
|
|
|
|
return opCount;
|
|
|
|
}
|
|
|
|
|
2019-02-04 21:26:05 +00:00
|
|
|
private void ForceAheadOfTimeCompilation(TranslatedSub subroutine)
|
|
|
|
{
|
|
|
|
subroutine.Execute(_dummyThreadState, null);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|