From 15ccdff751018694050e6ce53685a27e7ddc53ca Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Thu, 10 Feb 2022 18:59:09 +0000
Subject: [PATCH] T16: Implement LSL/LSR/ASR (imm)

---
 ARMeilleure/Decoders/IOpCode32AluRsImm.cs     | 10 +++++++
 ARMeilleure/Decoders/OpCode32AluRsImm.cs      |  2 +-
 ARMeilleure/Decoders/OpCodeT16ShiftImm.cs     | 26 +++++++++++++++++++
 ARMeilleure/Decoders/OpCodeTable.cs           |  1 +
 ARMeilleure/Instructions/InstEmitAluHelper.cs |  4 +--
 Ryujinx.Tests/Cpu/CpuTestThumb.cs             | 25 ++++++++++++++++++
 6 files changed, 65 insertions(+), 3 deletions(-)
 create mode 100644 ARMeilleure/Decoders/IOpCode32AluRsImm.cs
 create mode 100644 ARMeilleure/Decoders/OpCodeT16ShiftImm.cs

diff --git a/ARMeilleure/Decoders/IOpCode32AluRsImm.cs b/ARMeilleure/Decoders/IOpCode32AluRsImm.cs
new file mode 100644
index 000000000..e899a6592
--- /dev/null
+++ b/ARMeilleure/Decoders/IOpCode32AluRsImm.cs
@@ -0,0 +1,10 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluRsImm : IOpCode32Alu
+    {
+        int Rm { get; }
+        int Immediate { get; }
+
+        ShiftType ShiftType { get; }
+    }
+}
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/ARMeilleure/Decoders/OpCode32AluRsImm.cs
index 10fa195bc..a7e7fdc84 100644
--- a/ARMeilleure/Decoders/OpCode32AluRsImm.cs
+++ b/ARMeilleure/Decoders/OpCode32AluRsImm.cs
@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluRsImm : OpCode32Alu
+    class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm
     {
         public int Rm        { get; }
         public int Immediate { get; }
diff --git a/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
new file mode 100644
index 000000000..1d05cebf3
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
@@ -0,0 +1,26 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT16ShiftImm : OpCodeT16, IOpCode32AluRsImm
+    {
+        public int Rd { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+
+        public int Immediate { get; }
+        public ShiftType ShiftType { get; }
+
+        public bool SetFlags { get; }
+
+        public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16ShiftImm(inst, address, opCode, inITBlock);
+
+        public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
+        {
+            Rd        = (opCode >> 0) & 0x7;
+            Rm        = (opCode >> 3) & 0x7;
+            Immediate = (opCode >> 6) & 0x1F;
+            ShiftType = (ShiftType)((opCode >> 11) & 3);
+
+            SetFlags = !inITBlock;
+        }
+    }
+}
diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index 8658d020b..7074707c5 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -974,6 +974,7 @@ namespace ARMeilleure.Decoders
 
 #region "OpCode Table (AArch32, T16/T32)"
             // T16
+            SetT16("000<<xxxxxxxxxxx", InstName.Mov,    InstEmit32.Mov,     OpCodeT16ShiftImm.Create);
             SetT16("010001110xxxx000", InstName.Bx,     InstEmit32.Bx,      OpCodeT16BReg.Create);
 #endregion
 
diff --git a/ARMeilleure/Instructions/InstEmitAluHelper.cs b/ARMeilleure/Instructions/InstEmitAluHelper.cs
index f5951a3e9..9dda15789 100644
--- a/ARMeilleure/Instructions/InstEmitAluHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs
@@ -195,7 +195,7 @@ namespace ARMeilleure.Instructions
 
                 case OpCode32AluImm16 op: return Const(op.Immediate);
 
-                case OpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
+                case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
                 case OpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
 
                 case IOpCode32AluReg op: return GetIntA32(context, op.Rm);
@@ -247,7 +247,7 @@ namespace ARMeilleure.Instructions
         }
 
         // ARM32 helpers.
-        public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32AluRsImm op, bool setCarry)
+        public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode32AluRsImm op, bool setCarry)
         {
             Operand m = GetIntA32(context, op.Rm);
 
diff --git a/Ryujinx.Tests/Cpu/CpuTestThumb.cs b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
index 058bcc50e..b7c1c65f5 100644
--- a/Ryujinx.Tests/Cpu/CpuTestThumb.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
@@ -7,5 +7,30 @@ namespace Ryujinx.Tests.Cpu
     public sealed class CpuTestThumb : CpuTest32
     {
         private const int RndCnt = 2;
+
+        [Test, Pairwise]
+        public void ShiftImm([Range(0u, 2u)] uint shiftType, [Range(1u, 0x1fu)] uint shiftImm, [Random(RndCnt)] uint w1, [Random(RndCnt)] uint w2)
+        {
+            uint opcode = 0x0000; // MOVS <Rd>, <Rm>, <shift> #<amount>
+
+            uint rd = 1;
+            uint rm = 2;
+            opcode |= ((rd & 7) << 0) | ((rm & 7) << 3) | ((shiftImm & 0x1f) << 6) | ((shiftType & 3) << 11);
+
+            SingleThumbOpcode((ushort)opcode, r1: w1, r2: w2, runUnicorn: false);
+
+            switch (shiftType)
+            {
+                case 0:
+                    Assert.That(GetContext().GetX(1), Is.EqualTo((w2 << (int)shiftImm) & 0xffffffffu));
+                    break;
+                case 1:
+                    Assert.That(GetContext().GetX(1), Is.EqualTo((w2 >> (int)shiftImm) & 0xffffffffu));
+                    break;
+                case 2:
+                    Assert.That(GetContext().GetX(1), Is.EqualTo(((int)w2 >> (int)shiftImm) & 0xffffffffu));
+                    break;
+            }
+        }
     }
 }