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Support vectors in write registers

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# Conflicts:
#	src/Ryujinx.HLE/Debugger/Debugger.cs
This commit is contained in:
merry 2022-02-19 15:59:07 +00:00 committed by svc64
parent a9538a54ff
commit 1cef40131a
1 changed files with 50 additions and 18 deletions
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68
src/Ryujinx.HLE/Debugger/Debugger.cs
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@ -1,3 +1,4 @@
using ARMeilleure.State;
using Ryujinx.Common; using Ryujinx.Common;
using Ryujinx.Common.Logging; using Ryujinx.Common.Logging;
using Ryujinx.Memory; using Ryujinx.Memory;
@ -94,19 +95,47 @@ namespace Ryujinx.HLE.Debugger
} }
} }
private bool GdbWriteRegister(Ryujinx.Cpu.IExecutionContext state, int gdbRegId, ulong value) private bool GdbWriteRegister(IExecutionContext state, int gdbRegId, StringStream ss)
{ {
switch (gdbRegId) switch (gdbRegId)
{ {
case >= 0 and <= 31: case >= 0 and <= 31:
state.SetX(gdbRegId, value); {
return true; ulong value = ss.ReadLengthAsHex(16);
state.SetX(gdbRegId, value);
return true;
}
case 32: case 32:
state.DebugPc = value; {
return true; ulong value = ss.ReadLengthAsHex(8);
state.DebugPc = value;
return true;
}
case 33: case 33:
state.Pstate = (uint)value; {
return true; ulong value = ss.ReadLengthAsHex(8);
state.Pstate = (uint)value;
return true;
}
case >= 34 and <= 65:
{
ulong value0 = ss.ReadLengthAsHex(16);
ulong value1 = ss.ReadLengthAsHex(16);
state.SetV(gdbRegId - 34, new V128(value0, value1));
return true;
}
case 66:
{
ulong value = ss.ReadLengthAsHex(8);
state.Fpsr = (uint)value;
return true;
}
case 67:
{
ulong value = ss.ReadLengthAsHex(8);
state.Fpcr = (uint)value;
return true;
}
default: default:
return false; return false;
} }
@ -184,10 +213,10 @@ namespace Ryujinx.HLE.Debugger
goto unknownCommand; goto unknownCommand;
} }
CommandReadGeneralRegisters(); CommandReadRegisters();
break; break;
case 'G': case 'G':
CommandWriteGeneralRegisters(ss); CommandWriteRegisters(ss);
break; break;
case 'H': case 'H':
{ {
@ -217,14 +246,13 @@ namespace Ryujinx.HLE.Debugger
case 'p': case 'p':
{ {
ulong gdbRegId = ss.ReadRemainingAsHex(); ulong gdbRegId = ss.ReadRemainingAsHex();
CommandReadGeneralRegister((int)gdbRegId); CommandReadRegister((int)gdbRegId);
break; break;
} }
case 'P': case 'P':
{ {
ulong gdbRegId = ss.ReadUntilAsHex('='); ulong gdbRegId = ss.ReadUntilAsHex('=');
ulong value = ss.ReadRemainingAsHex(); CommandWriteRegister((int)gdbRegId, ss);
CommandWriteGeneralRegister((int)gdbRegId, value);
break; break;
} }
case 'q': case 'q':
@ -352,7 +380,7 @@ namespace Ryujinx.HLE.Debugger
CommandContinue(null); CommandContinue(null);
} }
void CommandReadGeneralRegisters() void CommandReadRegisters()
{ {
if (gThread == null) if (gThread == null)
{ {
@ -370,7 +398,7 @@ namespace Ryujinx.HLE.Debugger
Reply(registers); Reply(registers);
} }
void CommandWriteGeneralRegisters(StringStream ss) void CommandWriteRegisters(StringStream ss)
{ {
if (gThread == null) if (gThread == null)
{ {
@ -381,7 +409,11 @@ namespace Ryujinx.HLE.Debugger
var ctx = GetThread(gThread.Value); var ctx = GetThread(gThread.Value);
for (int i = 0; i < GdbRegisterCount; i++) for (int i = 0; i < GdbRegisterCount; i++)
{ {
GdbWriteRegister(ctx, i, ss.ReadLengthAsLEHex(GdbRegisterHexSize(i))); if (!GdbWriteRegister(ctx, i, ss))
{
ReplyError();
return;
}
} }
if (ss.IsEmpty()) if (ss.IsEmpty())
@ -451,7 +483,7 @@ namespace Ryujinx.HLE.Debugger
} }
} }
void CommandReadGeneralRegister(int gdbRegId) void CommandReadRegister(int gdbRegId)
{ {
if (gThread == null) if (gThread == null)
{ {
@ -471,7 +503,7 @@ namespace Ryujinx.HLE.Debugger
} }
} }
void CommandWriteGeneralRegister(int gdbRegId, ulong value) void CommandWriteRegister(int gdbRegId, StringStream ss)
{ {
if (gThread == null) if (gThread == null)
{ {
@ -480,7 +512,7 @@ namespace Ryujinx.HLE.Debugger
} }
var ctx = GetThread(gThread.Value); var ctx = GetThread(gThread.Value);
if (GdbWriteRegister(ctx, gdbRegId, value)) if (GdbWriteRegister(ctx, gdbRegId, ss) && ss.IsEmpty())
{ {
ReplyOK(); ReplyOK();
} }