From 3d663a1c8cd07fa7fbccef2dfc074e98cfdafb6d Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Thu, 10 Feb 2022 19:48:11 +0000
Subject: [PATCH] T16: Implement ADDS, SUBS (reg)

---
 ARMeilleure/Decoders/OpCodeT16AddSubReg.cs | 22 +++++++++++++++++++++
 ARMeilleure/Decoders/OpCodeTable.cs        |  2 ++
 Ryujinx.Tests/Cpu/CpuTestThumb.cs          | 23 ++++++++++++++++++++++
 3 files changed, 47 insertions(+)
 create mode 100644 ARMeilleure/Decoders/OpCodeT16AddSubReg.cs

diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs b/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
new file mode 100644
index 000000000..740ab877d
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
@@ -0,0 +1,22 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT16AddSubReg : OpCodeT16, IOpCode32AluReg
+    {
+        public int Rm { get; }
+        public int Rd { get; }
+        public int Rn { get; }
+
+        public bool SetFlags { get; }
+
+        public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubReg(inst, address, opCode, inITBlock);
+
+        public OpCodeT16AddSubReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
+        {
+            Rd = (opCode >> 0) & 0x7;
+            Rn = (opCode >> 3) & 0x7;
+            Rm = (opCode >> 6) & 0x7;
+
+            SetFlags = !inITBlock;
+        }
+    }
+}
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index 7074707c5..bfb249ac9 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -975,6 +975,8 @@ namespace ARMeilleure.Decoders
 #region "OpCode Table (AArch32, T16/T32)"
             // T16
             SetT16("000<<xxxxxxxxxxx", InstName.Mov,    InstEmit32.Mov,     OpCodeT16ShiftImm.Create);
+            SetT16("0001100xxxxxxxxx", InstName.Add,    InstEmit32.Add,     OpCodeT16AddSubReg.Create);
+            SetT16("0001101xxxxxxxxx", InstName.Sub,    InstEmit32.Sub,     OpCodeT16AddSubReg.Create);
             SetT16("010001110xxxx000", InstName.Bx,     InstEmit32.Bx,      OpCodeT16BReg.Create);
 #endregion
 
diff --git a/Ryujinx.Tests/Cpu/CpuTestThumb.cs b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
index b7c1c65f5..92c8ccd24 100644
--- a/Ryujinx.Tests/Cpu/CpuTestThumb.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
@@ -32,5 +32,28 @@ namespace Ryujinx.Tests.Cpu
                     break;
             }
         }
+
+        [Test, Pairwise]
+        public void AddSubReg([Range(0u, 1u)] uint op, [Random(RndCnt)] uint w1, [Random(RndCnt)] uint w2)
+        {
+            uint opcode = 0x1800; // ADDS <Rd>, <Rn>, <Rm>
+
+            uint rd = 0;
+            uint rn = 1;
+            uint rm = 2;
+            opcode |= ((rd & 7) << 0) | ((rn & 7) << 3) | ((rm & 7) << 6) | ((op & 1) << 9);
+
+            SingleThumbOpcode((ushort)opcode, r1: w1, r2: w2, runUnicorn: false);
+
+            switch (op)
+            {
+                case 0:
+                    Assert.That(GetContext().GetX(0), Is.EqualTo((w1 + w2) & 0xffffffffu));
+                    break;
+                case 1:
+                    Assert.That(GetContext().GetX(0), Is.EqualTo((w1 - w2) & 0xffffffffu));
+                    break;
+            }
+        }
     }
 }