From 4a257bf7a1712d26af6249df0ec3b5ec74bfbbe0 Mon Sep 17 00:00:00 2001 From: Merry Date: Mon, 14 Feb 2022 21:06:24 +0000 Subject: [PATCH] Remove inITBlock argument --- ARMeilleure/Decoders/Decoder.cs | 22 +++++++-------- ARMeilleure/Decoders/IOpCode32Alu.cs | 4 +-- ARMeilleure/Decoders/OpCode.cs | 9 ++---- ARMeilleure/Decoders/OpCode32.cs | 6 ++-- ARMeilleure/Decoders/OpCode32Alu.cs | 8 +++--- ARMeilleure/Decoders/OpCode32AluBf.cs | 4 +-- ARMeilleure/Decoders/OpCode32AluImm.cs | 6 ++-- ARMeilleure/Decoders/OpCode32AluImm16.cs | 4 +-- ARMeilleure/Decoders/OpCode32AluMla.cs | 6 ++-- ARMeilleure/Decoders/OpCode32AluReg.cs | 4 +-- ARMeilleure/Decoders/OpCode32AluRsImm.cs | 6 ++-- ARMeilleure/Decoders/OpCode32AluRsReg.cs | 4 +-- ARMeilleure/Decoders/OpCode32AluUmull.cs | 6 ++-- ARMeilleure/Decoders/OpCode32AluUx.cs | 4 +-- ARMeilleure/Decoders/OpCode32BImm.cs | 6 ++-- ARMeilleure/Decoders/OpCode32BReg.cs | 6 ++-- ARMeilleure/Decoders/OpCode32Exception.cs | 4 +-- ARMeilleure/Decoders/OpCode32Mem.cs | 6 ++-- ARMeilleure/Decoders/OpCode32MemImm.cs | 6 ++-- ARMeilleure/Decoders/OpCode32MemImm8.cs | 6 ++-- ARMeilleure/Decoders/OpCode32MemLdEx.cs | 4 +-- ARMeilleure/Decoders/OpCode32MemMult.cs | 6 ++-- ARMeilleure/Decoders/OpCode32MemReg.cs | 4 +-- ARMeilleure/Decoders/OpCode32MemRsImm.cs | 4 +-- ARMeilleure/Decoders/OpCode32MemStEx.cs | 4 +-- ARMeilleure/Decoders/OpCode32MsrReg.cs | 4 +-- ARMeilleure/Decoders/OpCode32Sat.cs | 6 ++-- ARMeilleure/Decoders/OpCode32Sat16.cs | 6 ++-- ARMeilleure/Decoders/OpCode32Simd.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdBase.cs | 2 +- ARMeilleure/Decoders/OpCode32SimdBinary.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdCmpZ.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdCvtFI.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdDupElem.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdDupGP.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdExt.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdImm.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdImm44.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdLong.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMemImm.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMemMult.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMemPair.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMemSingle.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMovGp.cs | 4 +-- .../Decoders/OpCode32SimdMovGpDouble.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdReg.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdRegElem.cs | 4 +-- .../Decoders/OpCode32SimdRegElemLong.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdRegLong.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdRegS.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdRegWide.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdRev.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdS.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdSel.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdShImm.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdShImmLong.cs | 4 +-- .../Decoders/OpCode32SimdShImmNarrow.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdSpecial.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdSqrte.cs | 4 +-- ARMeilleure/Decoders/OpCode32SimdTbl.cs | 4 +-- ARMeilleure/Decoders/OpCode32System.cs | 4 +-- ARMeilleure/Decoders/OpCodeAdr.cs | 6 ++-- ARMeilleure/Decoders/OpCodeAlu.cs | 6 ++-- ARMeilleure/Decoders/OpCodeAluBinary.cs | 6 ++-- ARMeilleure/Decoders/OpCodeAluImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeAluRs.cs | 6 ++-- ARMeilleure/Decoders/OpCodeAluRx.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBImmAl.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBImmCmp.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBImmCond.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBImmTest.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeBfm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeCcmp.cs | 6 ++-- ARMeilleure/Decoders/OpCodeCcmpImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeCcmpReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeCsel.cs | 6 ++-- ARMeilleure/Decoders/OpCodeException.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMem.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMemEx.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMemImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMemLit.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMemPair.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMemReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMov.cs | 6 ++-- ARMeilleure/Decoders/OpCodeMul.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimd.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdCvt.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdExt.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdFcond.cs | 4 +-- ARMeilleure/Decoders/OpCodeSimdFmov.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdIns.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemImm.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemLit.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemMs.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemPair.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdMemSs.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdRegElem.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSimdRegElemF.cs | 4 +-- ARMeilleure/Decoders/OpCodeSimdShImm.cs | 4 +-- ARMeilleure/Decoders/OpCodeSimdTbl.cs | 6 ++-- ARMeilleure/Decoders/OpCodeSystem.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AddSubReg.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AddSubSp.cs | 8 +++--- ARMeilleure/Decoders/OpCodeT16Adr.cs | 4 +-- ARMeilleure/Decoders/OpCodeT16AluImm8.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AluImmZero.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AluRegLow.cs | 10 +++---- ARMeilleure/Decoders/OpCodeT16AluUx.cs | 8 +++--- ARMeilleure/Decoders/OpCodeT16BImm11.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16BImm8.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16BImmCmp.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16BReg.cs | 4 +-- ARMeilleure/Decoders/OpCodeT16Exception.cs | 4 +-- ARMeilleure/Decoders/OpCodeT16IfThen.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16MemImm5.cs | 4 +-- ARMeilleure/Decoders/OpCodeT16MemLit.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16MemMult.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16MemReg.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16MemSp.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16MemStack.cs | 6 ++-- ARMeilleure/Decoders/OpCodeT16ShiftImm.cs | 8 ++---- ARMeilleure/Decoders/OpCodeT16ShiftReg.cs | 8 ++---- ARMeilleure/Decoders/OpCodeT16SpRel.cs | 8 +++--- ARMeilleure/Decoders/OpCodeTable.cs | 2 +- ARMeilleure/Instructions/InstEmitAlu32.cs | 28 +++++++++---------- ARMeilleure/Instructions/InstEmitAluHelper.cs | 18 ++++++++++-- ARMeilleure/Instructions/InstEmitMul32.cs | 20 ++++++------- ARMeilleure/Translation/Translator.cs | 7 +++-- 137 files changed, 405 insertions(+), 409 deletions(-) diff --git a/ARMeilleure/Decoders/Decoder.cs b/ARMeilleure/Decoders/Decoder.cs index 3e423b4c1..0945bea89 100644 --- a/ARMeilleure/Decoders/Decoder.cs +++ b/ARMeilleure/Decoders/Decoder.cs @@ -195,18 +195,18 @@ namespace ARMeilleure.Decoders ulong limitAddress) { ulong address = block.Address; - int inITBlock = 0; + int itBlockSize = 0; OpCode opCode; do { - if (address >= limitAddress && inITBlock == 0) + if (address >= limitAddress && itBlockSize == 0) { break; } - opCode = DecodeOpCode(memory, address, mode, inITBlock > 0); + opCode = DecodeOpCode(memory, address, mode); block.OpCodes.Add(opCode); @@ -214,11 +214,11 @@ namespace ARMeilleure.Decoders if (opCode is OpCodeT16IfThen it) { - inITBlock = it.IfThenBlockSize; + itBlockSize = it.IfThenBlockSize; } - else if (inITBlock > 0) + else if (itBlockSize > 0) { - inITBlock--; + itBlockSize--; } } while (!(IsBranch(opCode) || IsException(opCode))); @@ -325,7 +325,7 @@ namespace ARMeilleure.Decoders opCode.Instruction.Name == InstName.Und; } - public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode, bool inITBlock) + public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode) { int opCode = memory.Read(address); @@ -351,19 +351,19 @@ namespace ARMeilleure.Decoders if (makeOp != null) { - return makeOp(inst, address, opCode, inITBlock); + return makeOp(inst, address, opCode); } else { if (mode == ExecutionMode.Aarch32Thumb) { - return new OpCodeT16(inst, address, opCode, inITBlock); + return new OpCodeT16(inst, address, opCode); } else { - return new OpCode(inst, address, opCode, inITBlock); + return new OpCode(inst, address, opCode); } } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/IOpCode32Alu.cs b/ARMeilleure/Decoders/IOpCode32Alu.cs index 72aea30ef..77fdb02ad 100644 --- a/ARMeilleure/Decoders/IOpCode32Alu.cs +++ b/ARMeilleure/Decoders/IOpCode32Alu.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders int Rd { get; } int Rn { get; } - bool SetFlags { get; } + bool? SetFlags { get; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode.cs b/ARMeilleure/Decoders/OpCode.cs index f06226868..a9d0a8d11 100644 --- a/ARMeilleure/Decoders/OpCode.cs +++ b/ARMeilleure/Decoders/OpCode.cs @@ -14,16 +14,13 @@ namespace ARMeilleure.Decoders public RegisterSize RegisterSize { get; protected set; } - public bool InITBlock { get; } + public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode); - public static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode(inst, address, opCode, inITBlock); - - public OpCode(InstDescriptor inst, ulong address, int opCode, bool inITBlock) + public OpCode(InstDescriptor inst, ulong address, int opCode) { Instruction = inst; Address = address; RawOpCode = opCode; - InITBlock = inITBlock; RegisterSize = RegisterSize.Int64; } @@ -49,4 +46,4 @@ namespace ARMeilleure.Decoders return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32.cs b/ARMeilleure/Decoders/OpCode32.cs index c9fbae8d8..44735a357 100644 --- a/ARMeilleure/Decoders/OpCode32.cs +++ b/ARMeilleure/Decoders/OpCode32.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public Condition Cond { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode); - public OpCode32(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { RegisterSize = RegisterSize.Int32; @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders return (uint)Address + (uint)OpCodeSizeInBytes * 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32Alu.cs b/ARMeilleure/Decoders/OpCode32Alu.cs index ae497878b..8634f5ce9 100644 --- a/ARMeilleure/Decoders/OpCode32Alu.cs +++ b/ARMeilleure/Decoders/OpCode32Alu.cs @@ -5,11 +5,11 @@ namespace ARMeilleure.Decoders public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Alu(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode); - public OpCode32Alu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 12) & 0xf; Rn = (opCode >> 16) & 0xf; @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders SetFlags = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32AluBf.cs b/ARMeilleure/Decoders/OpCode32AluBf.cs index 954e4429f..f8dc6db0d 100644 --- a/ARMeilleure/Decoders/OpCode32AluBf.cs +++ b/ARMeilleure/Decoders/OpCode32AluBf.cs @@ -12,9 +12,9 @@ public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb)); public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb); - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluBf(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode); - public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 12) & 0xf; Rn = (opCode >> 0) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32AluImm.cs b/ARMeilleure/Decoders/OpCode32AluImm.cs index d8ea9ed28..c8b05e6bc 100644 --- a/ARMeilleure/Decoders/OpCode32AluImm.cs +++ b/ARMeilleure/Decoders/OpCode32AluImm.cs @@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders public bool IsRotated { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode); - public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int value = (opCode >> 0) & 0xff; int shift = (opCode >> 8) & 0xf; @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders IsRotated = shift != 0; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32AluImm16.cs b/ARMeilleure/Decoders/OpCode32AluImm16.cs index 86738ef5d..662482719 100644 --- a/ARMeilleure/Decoders/OpCode32AluImm16.cs +++ b/ARMeilleure/Decoders/OpCode32AluImm16.cs @@ -4,9 +4,9 @@ { public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm16(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode); - public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm12 = opCode & 0xfff; int imm4 = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32AluMla.cs b/ARMeilleure/Decoders/OpCode32AluMla.cs index adc528084..748946676 100644 --- a/ARMeilleure/Decoders/OpCode32AluMla.cs +++ b/ARMeilleure/Decoders/OpCode32AluMla.cs @@ -10,11 +10,11 @@ public bool NHigh { get; } public bool MHigh { get; } public bool R { get; } - public bool SetFlags { get; } + public bool? SetFlags { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluMla(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode); - public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0xf; Rm = (opCode >> 8) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32AluReg.cs b/ARMeilleure/Decoders/OpCode32AluReg.cs index fc3c990e0..493a977f0 100644 --- a/ARMeilleure/Decoders/OpCode32AluReg.cs +++ b/ARMeilleure/Decoders/OpCode32AluReg.cs @@ -4,9 +4,9 @@ { public int Rm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode); - public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; } diff --git a/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/ARMeilleure/Decoders/OpCode32AluRsImm.cs index a7e7fdc84..f158d52ac 100644 --- a/ARMeilleure/Decoders/OpCode32AluRsImm.cs +++ b/ARMeilleure/Decoders/OpCode32AluRsImm.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public ShiftType ShiftType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode); - public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 5) & 3); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32AluRsReg.cs b/ARMeilleure/Decoders/OpCode32AluRsReg.cs index 616987727..04740d086 100644 --- a/ARMeilleure/Decoders/OpCode32AluRsReg.cs +++ b/ARMeilleure/Decoders/OpCode32AluRsReg.cs @@ -7,9 +7,9 @@ public ShiftType ShiftType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode); - public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Rs = (opCode >> 8) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32AluUmull.cs b/ARMeilleure/Decoders/OpCode32AluUmull.cs index 7e11c677a..bbdaaeae3 100644 --- a/ARMeilleure/Decoders/OpCode32AluUmull.cs +++ b/ARMeilleure/Decoders/OpCode32AluUmull.cs @@ -10,12 +10,12 @@ public bool NHigh { get; } public bool MHigh { get; } - public bool SetFlags { get; } + public bool? SetFlags { get; } public DataOp DataOp { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUmull(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode); - public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { RdLo = (opCode >> 12) & 0xf; RdHi = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32AluUx.cs b/ARMeilleure/Decoders/OpCode32AluUx.cs index 31eba3bae..57068675d 100644 --- a/ARMeilleure/Decoders/OpCode32AluUx.cs +++ b/ARMeilleure/Decoders/OpCode32AluUx.cs @@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders public int RotateBits => Rotate * 8; public bool Add => Rn != RegisterAlias.Aarch32Pc; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUx(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode); - public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rotate = (opCode >> 10) & 0x3; } diff --git a/ARMeilleure/Decoders/OpCode32BImm.cs b/ARMeilleure/Decoders/OpCode32BImm.cs index d5d3add69..e7f5d6db1 100644 --- a/ARMeilleure/Decoders/OpCode32BImm.cs +++ b/ARMeilleure/Decoders/OpCode32BImm.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode); - public OpCode32BImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { uint pc = GetPc(); @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32BReg.cs b/ARMeilleure/Decoders/OpCode32BReg.cs index 2ed8364db..8939c0de3 100644 --- a/ARMeilleure/Decoders/OpCode32BReg.cs +++ b/ARMeilleure/Decoders/OpCode32BReg.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { public int Rm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode); - public OpCode32BReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = opCode & 0xf; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32Exception.cs b/ARMeilleure/Decoders/OpCode32Exception.cs index 41343d474..b4edcc100 100644 --- a/ARMeilleure/Decoders/OpCode32Exception.cs +++ b/ARMeilleure/Decoders/OpCode32Exception.cs @@ -4,9 +4,9 @@ { public int Id { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Exception(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode); - public OpCode32Exception(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Id = opCode & 0xFFFFFF; } diff --git a/ARMeilleure/Decoders/OpCode32Mem.cs b/ARMeilleure/Decoders/OpCode32Mem.cs index bad605b0d..0869a4fd0 100644 --- a/ARMeilleure/Decoders/OpCode32Mem.cs +++ b/ARMeilleure/Decoders/OpCode32Mem.cs @@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders public bool IsLoad { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Mem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode); - public OpCode32Mem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 12) & 0xf; Rn = (opCode >> 16) & 0xf; @@ -36,4 +36,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad || inst.Name == InstName.Ldrd; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32MemImm.cs b/ARMeilleure/Decoders/OpCode32MemImm.cs index 98e02dc06..fa10e04ee 100644 --- a/ARMeilleure/Decoders/OpCode32MemImm.cs +++ b/ARMeilleure/Decoders/OpCode32MemImm.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCode32MemImm : OpCode32Mem { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode); - public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = opCode & 0xfff; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32MemImm8.cs b/ARMeilleure/Decoders/OpCode32MemImm8.cs index f4f62dfa7..248ee8e65 100644 --- a/ARMeilleure/Decoders/OpCode32MemImm8.cs +++ b/ARMeilleure/Decoders/OpCode32MemImm8.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCode32MemImm8 : OpCode32Mem { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm8(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode); - public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm4L = (opCode >> 0) & 0xf; int imm4H = (opCode >> 8) & 0xf; @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders Immediate = imm4L | (imm4H << 4); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32MemLdEx.cs b/ARMeilleure/Decoders/OpCode32MemLdEx.cs index 9ca97b052..520113f46 100644 --- a/ARMeilleure/Decoders/OpCode32MemLdEx.cs +++ b/ARMeilleure/Decoders/OpCode32MemLdEx.cs @@ -4,9 +4,9 @@ { public int Rd { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemLdEx(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode); - public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0xf; } diff --git a/ARMeilleure/Decoders/OpCode32MemMult.cs b/ARMeilleure/Decoders/OpCode32MemMult.cs index 775090554..87ba2bf96 100644 --- a/ARMeilleure/Decoders/OpCode32MemMult.cs +++ b/ARMeilleure/Decoders/OpCode32MemMult.cs @@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders public bool IsLoad { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemMult(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode); - public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 16) & 0xf; @@ -54,4 +54,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32MemReg.cs b/ARMeilleure/Decoders/OpCode32MemReg.cs index 422e7c7e5..786f37fab 100644 --- a/ARMeilleure/Decoders/OpCode32MemReg.cs +++ b/ARMeilleure/Decoders/OpCode32MemReg.cs @@ -4,9 +4,9 @@ { public int Rm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode); - public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; } diff --git a/ARMeilleure/Decoders/OpCode32MemRsImm.cs b/ARMeilleure/Decoders/OpCode32MemRsImm.cs index 430b450dd..dc5f0fd35 100644 --- a/ARMeilleure/Decoders/OpCode32MemRsImm.cs +++ b/ARMeilleure/Decoders/OpCode32MemRsImm.cs @@ -5,9 +5,9 @@ public int Rm { get; } public ShiftType ShiftType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemRsImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode); - public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; diff --git a/ARMeilleure/Decoders/OpCode32MemStEx.cs b/ARMeilleure/Decoders/OpCode32MemStEx.cs index 4ab50b161..dcf93b224 100644 --- a/ARMeilleure/Decoders/OpCode32MemStEx.cs +++ b/ARMeilleure/Decoders/OpCode32MemStEx.cs @@ -4,9 +4,9 @@ { public int Rd { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemStEx(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode); - public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 12) & 0xf; Rt = (opCode >> 0) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32MsrReg.cs b/ARMeilleure/Decoders/OpCode32MsrReg.cs index 0eb071aee..d897ffd80 100644 --- a/ARMeilleure/Decoders/OpCode32MsrReg.cs +++ b/ARMeilleure/Decoders/OpCode32MsrReg.cs @@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders public bool Banked { get; } public int Rn { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MsrReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode); - public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { R = ((opCode >> 22) & 1) != 0; Mask = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32Sat.cs b/ARMeilleure/Decoders/OpCode32Sat.cs index 6a92c24b0..35c5cf47a 100644 --- a/ARMeilleure/Decoders/OpCode32Sat.cs +++ b/ARMeilleure/Decoders/OpCode32Sat.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public ShiftType ShiftType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode); - public OpCode32Sat(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0xf; Imm5 = (opCode >> 7) & 0x1f; @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 5) & 2); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32Sat16.cs b/ARMeilleure/Decoders/OpCode32Sat16.cs index b67c6f7e9..01f4d3b23 100644 --- a/ARMeilleure/Decoders/OpCode32Sat16.cs +++ b/ARMeilleure/Decoders/OpCode32Sat16.cs @@ -6,13 +6,13 @@ namespace ARMeilleure.Decoders public int Rd { get; } public int SatImm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat16(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode); - public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0xf; Rd = (opCode >> 12) & 0xf; SatImm = (opCode >> 16) & 0xf; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCode32Simd.cs b/ARMeilleure/Decoders/OpCode32Simd.cs index 5be28c742..51f390561 100644 --- a/ARMeilleure/Decoders/OpCode32Simd.cs +++ b/ARMeilleure/Decoders/OpCode32Simd.cs @@ -7,9 +7,9 @@ public bool F { get; protected set; } public bool U { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Simd(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode); - public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 20) & 0x3; Q = ((opCode >> 6) & 0x1) != 0; diff --git a/ARMeilleure/Decoders/OpCode32SimdBase.cs b/ARMeilleure/Decoders/OpCode32SimdBase.cs index 87f02863f..183378b97 100644 --- a/ARMeilleure/Decoders/OpCode32SimdBase.cs +++ b/ARMeilleure/Decoders/OpCode32SimdBase.cs @@ -47,6 +47,6 @@ namespace ARMeilleure.Decoders throw new InvalidOperationException(); } - public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { } + public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } } diff --git a/ARMeilleure/Decoders/OpCode32SimdBinary.cs b/ARMeilleure/Decoders/OpCode32SimdBinary.cs index f9b97f874..72347b94c 100644 --- a/ARMeilleure/Decoders/OpCode32SimdBinary.cs +++ b/ARMeilleure/Decoders/OpCode32SimdBinary.cs @@ -5,9 +5,9 @@ /// class OpCode32SimdBinary : OpCode32SimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdBinary(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode); - public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = 3; diff --git a/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs b/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs index 8a3f76874..c3c295a55 100644 --- a/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs +++ b/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs @@ -2,9 +2,9 @@ { class OpCode32SimdCmpZ : OpCode32Simd { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCmpZ(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode); - public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 18) & 0x3; diff --git a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs index 70fca07bb..30725eba7 100644 --- a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs +++ b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs @@ -2,9 +2,9 @@ { class OpCode32SimdCvtFI : OpCode32SimdS { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCvtFI(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode); - public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Opc = (opCode >> 7) & 0x1; diff --git a/ARMeilleure/Decoders/OpCode32SimdDupElem.cs b/ARMeilleure/Decoders/OpCode32SimdDupElem.cs index 9462af915..9918d7a84 100644 --- a/ARMeilleure/Decoders/OpCode32SimdDupElem.cs +++ b/ARMeilleure/Decoders/OpCode32SimdDupElem.cs @@ -4,9 +4,9 @@ { public int Index { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupElem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode); - public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { var opc = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32SimdDupGP.cs b/ARMeilleure/Decoders/OpCode32SimdDupGP.cs index 14af75751..2aef836f6 100644 --- a/ARMeilleure/Decoders/OpCode32SimdDupGP.cs +++ b/ARMeilleure/Decoders/OpCode32SimdDupGP.cs @@ -7,9 +7,9 @@ public int Rt { get; } public bool Q { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupGP(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode); - public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8. if (Size == -1) diff --git a/ARMeilleure/Decoders/OpCode32SimdExt.cs b/ARMeilleure/Decoders/OpCode32SimdExt.cs index 162953678..cdb305df8 100644 --- a/ARMeilleure/Decoders/OpCode32SimdExt.cs +++ b/ARMeilleure/Decoders/OpCode32SimdExt.cs @@ -4,9 +4,9 @@ { public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdExt(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode); - public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = (opCode >> 8) & 0xf; Size = 0; diff --git a/ARMeilleure/Decoders/OpCode32SimdImm.cs b/ARMeilleure/Decoders/OpCode32SimdImm.cs index 6beff184e..678f30646 100644 --- a/ARMeilleure/Decoders/OpCode32SimdImm.cs +++ b/ARMeilleure/Decoders/OpCode32SimdImm.cs @@ -6,9 +6,9 @@ public long Immediate { get; } public int Elems => GetBytesCount() >> Size; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode); - public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Vd = (opCode >> 12) & 0xf; Vd |= (opCode >> 18) & 0x10; diff --git a/ARMeilleure/Decoders/OpCode32SimdImm44.cs b/ARMeilleure/Decoders/OpCode32SimdImm44.cs index 60508398f..a2be6e648 100644 --- a/ARMeilleure/Decoders/OpCode32SimdImm44.cs +++ b/ARMeilleure/Decoders/OpCode32SimdImm44.cs @@ -7,9 +7,9 @@ public int Size { get; } public int Elems { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm44(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode); - public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 8) & 0x3; diff --git a/ARMeilleure/Decoders/OpCode32SimdLong.cs b/ARMeilleure/Decoders/OpCode32SimdLong.cs index 475b92cb9..9cde8fffd 100644 --- a/ARMeilleure/Decoders/OpCode32SimdLong.cs +++ b/ARMeilleure/Decoders/OpCode32SimdLong.cs @@ -4,9 +4,9 @@ { public bool U { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdLong(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode); - public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm3h = (opCode >> 19) & 0x7; diff --git a/ARMeilleure/Decoders/OpCode32SimdMemImm.cs b/ARMeilleure/Decoders/OpCode32SimdMemImm.cs index d95cbf663..8a163f090 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMemImm.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMemImm.cs @@ -8,9 +8,9 @@ public bool Add { get; } public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode); - public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = opCode & 0xff; diff --git a/ARMeilleure/Decoders/OpCode32SimdMemMult.cs b/ARMeilleure/Decoders/OpCode32SimdMemMult.cs index 9a69c18a8..33caf0926 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMemMult.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMemMult.cs @@ -12,9 +12,9 @@ public bool DoubleWidth { get; } public bool Add { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemMult(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode); - public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs index 6d643ef08..4cee05e82 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs @@ -24,9 +24,9 @@ namespace ARMeilleure.Decoders public int Regs { get; } public int Increment { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemPair(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode); - public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Vd = (opCode >> 12) & 0xf; Vd |= (opCode >> 18) & 0x10; diff --git a/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs b/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs index d5cc7938e..e90c22271 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs @@ -15,9 +15,9 @@ namespace ARMeilleure.Decoders public bool Replicate { get; } public int Increment { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemSingle(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode); - public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Vd = (opCode >> 12) & 0xf; Vd |= (opCode >> 18) & 0x10; diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGp.cs b/ARMeilleure/Decoders/OpCode32SimdMovGp.cs index e774915bf..8e2c84fb6 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMovGp.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMovGp.cs @@ -11,9 +11,9 @@ public int Opc1 { get; } public int Opc2 { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGp(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode); - public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { // Which one is used is instruction dependant. Op = (opCode >> 20) & 0x1; diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs b/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs index c65a5e7f2..dc89b719b 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs @@ -9,9 +9,9 @@ public int Rt2 { get; } public int Op { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpDouble(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode); - public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { // Which one is used is instruction dependant. Op = (opCode >> 20) & 0x1; diff --git a/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs b/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs index c36d56fe3..56e46413e 100644 --- a/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs +++ b/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs @@ -11,9 +11,9 @@ public int Index { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpElem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode); - public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Op = (opCode >> 20) & 0x1; U = ((opCode >> 23) & 1) != 0; diff --git a/ARMeilleure/Decoders/OpCode32SimdReg.cs b/ARMeilleure/Decoders/OpCode32SimdReg.cs index 6abf40ebd..50d1d24d5 100644 --- a/ARMeilleure/Decoders/OpCode32SimdReg.cs +++ b/ARMeilleure/Decoders/OpCode32SimdReg.cs @@ -8,9 +8,9 @@ public int In => GetQuadwordSubindex(Vn) << (3 - Size); public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1)); - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode); - public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf); diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs index 38ed4295d..0802a17b7 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs @@ -2,9 +2,9 @@ { class OpCode32SimdRegElem : OpCode32SimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode); - public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = ((opCode >> 24) & 0x1) != 0; F = ((opCode >> 8) & 0x1) != 0; diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs index 833e34bef..e3ffed7d1 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs @@ -2,9 +2,9 @@ { class OpCode32SimdRegElemLong : OpCode32SimdRegElem { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElemLong(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode); - public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = false; F = false; diff --git a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs index 0208acb2d..c8ca9b498 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs @@ -4,9 +4,9 @@ { public bool Polynomial { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegLong(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode); - public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = false; RegisterSize = RegisterSize.Simd64; diff --git a/ARMeilleure/Decoders/OpCode32SimdRegS.cs b/ARMeilleure/Decoders/OpCode32SimdRegS.cs index c2600e882..07dffb4fc 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegS.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegS.cs @@ -4,9 +4,9 @@ { public int Vn { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegS(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode); - public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { bool single = Size != 3; if (single) diff --git a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs index 87ef334f4..9a3993fae 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs @@ -2,9 +2,9 @@ { class OpCode32SimdRegWide : OpCode32SimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegWide(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode); - public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = false; RegisterSize = RegisterSize.Simd64; diff --git a/ARMeilleure/Decoders/OpCode32SimdRev.cs b/ARMeilleure/Decoders/OpCode32SimdRev.cs index b92f5336d..88b45c7d7 100644 --- a/ARMeilleure/Decoders/OpCode32SimdRev.cs +++ b/ARMeilleure/Decoders/OpCode32SimdRev.cs @@ -2,9 +2,9 @@ { class OpCode32SimdRev : OpCode32SimdCmpZ { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRev(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode); - public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { if (Opc + Size >= 3) { diff --git a/ARMeilleure/Decoders/OpCode32SimdS.cs b/ARMeilleure/Decoders/OpCode32SimdS.cs index 34e490237..7bf6af474 100644 --- a/ARMeilleure/Decoders/OpCode32SimdS.cs +++ b/ARMeilleure/Decoders/OpCode32SimdS.cs @@ -8,9 +8,9 @@ public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint]. public int Size { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdS(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode); - public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Opc = (opCode >> 15) & 0x3; Opc2 = (opCode >> 16) & 0x7; diff --git a/ARMeilleure/Decoders/OpCode32SimdSel.cs b/ARMeilleure/Decoders/OpCode32SimdSel.cs index 857a6c4e9..0832b3a39 100644 --- a/ARMeilleure/Decoders/OpCode32SimdSel.cs +++ b/ARMeilleure/Decoders/OpCode32SimdSel.cs @@ -4,9 +4,9 @@ { public OpCode32SimdSelMode Cc { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSel(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode); - public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3); } diff --git a/ARMeilleure/Decoders/OpCode32SimdShImm.cs b/ARMeilleure/Decoders/OpCode32SimdShImm.cs index 3a49ce544..5e234ba2e 100644 --- a/ARMeilleure/Decoders/OpCode32SimdShImm.cs +++ b/ARMeilleure/Decoders/OpCode32SimdShImm.cs @@ -4,9 +4,9 @@ { public int Shift { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode); - public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm6 = (opCode >> 16) & 0x3f; int limm6 = ((opCode >> 1) & 0x40) | imm6; diff --git a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs index fdb9bc16a..3ca55ed6f 100644 --- a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs +++ b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs @@ -4,9 +4,9 @@ { public int Shift { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmLong(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode); - public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Q = false; RegisterSize = RegisterSize.Simd64; diff --git a/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs b/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs index 8bc1e616b..93b05cbab 100644 --- a/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs +++ b/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs @@ -2,8 +2,8 @@ { class OpCode32SimdShImmNarrow : OpCode32SimdShImm { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmNarrow(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode); - public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { } + public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } } diff --git a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs index 41fdcdf80..1f1411f08 100644 --- a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs +++ b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs @@ -5,9 +5,9 @@ public int Rt { get; } public int Sreg { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSpecial(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode); - public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 12) & 0xf; Sreg = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCode32SimdSqrte.cs b/ARMeilleure/Decoders/OpCode32SimdSqrte.cs index e7abb1cbd..74cb4cb68 100644 --- a/ARMeilleure/Decoders/OpCode32SimdSqrte.cs +++ b/ARMeilleure/Decoders/OpCode32SimdSqrte.cs @@ -2,9 +2,9 @@ { class OpCode32SimdSqrte : OpCode32Simd { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSqrte(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode); - public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = (opCode >> 18) & 0x1; F = ((opCode >> 8) & 0x1) != 0; diff --git a/ARMeilleure/Decoders/OpCode32SimdTbl.cs b/ARMeilleure/Decoders/OpCode32SimdTbl.cs index 0384e6fc7..4308aae14 100644 --- a/ARMeilleure/Decoders/OpCode32SimdTbl.cs +++ b/ARMeilleure/Decoders/OpCode32SimdTbl.cs @@ -4,9 +4,9 @@ { public int Length { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdTbl(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode); - public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Length = (opCode >> 8) & 3; Size = 0; diff --git a/ARMeilleure/Decoders/OpCode32System.cs b/ARMeilleure/Decoders/OpCode32System.cs index c2b92942c..89e93349b 100644 --- a/ARMeilleure/Decoders/OpCode32System.cs +++ b/ARMeilleure/Decoders/OpCode32System.cs @@ -11,9 +11,9 @@ public int Coproc { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32System(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode); - public OpCode32System(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Opc1 = (opCode >> 21) & 0x7; CRn = (opCode >> 16) & 0xf; diff --git a/ARMeilleure/Decoders/OpCodeAdr.cs b/ARMeilleure/Decoders/OpCodeAdr.cs index c7ec0fb79..1f5610472 100644 --- a/ARMeilleure/Decoders/OpCodeAdr.cs +++ b/ARMeilleure/Decoders/OpCodeAdr.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAdr(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); - public OpCodeAdr(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; @@ -16,4 +16,4 @@ namespace ARMeilleure.Decoders Immediate |= ((long)opCode >> 29) & 3; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeAlu.cs b/ARMeilleure/Decoders/OpCodeAlu.cs index 70fc19d88..6be0314ef 100644 --- a/ARMeilleure/Decoders/OpCodeAlu.cs +++ b/ARMeilleure/Decoders/OpCodeAlu.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public DataOp DataOp { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAlu(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode); - public OpCodeAlu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeAluBinary.cs b/ARMeilleure/Decoders/OpCodeAluBinary.cs index f8f8ca90b..4413581ca 100644 --- a/ARMeilleure/Decoders/OpCodeAluBinary.cs +++ b/ARMeilleure/Decoders/OpCodeAluBinary.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { public int Rm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluBinary(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode); - public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeAluImm.cs b/ARMeilleure/Decoders/OpCodeAluImm.cs index 5aa5d040e..920594202 100644 --- a/ARMeilleure/Decoders/OpCodeAluImm.cs +++ b/ARMeilleure/Decoders/OpCodeAluImm.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders { public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode); - public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { if (DataOp == DataOp.Arithmetic) { @@ -37,4 +37,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeAluRs.cs b/ARMeilleure/Decoders/OpCodeAluRs.cs index a8fc95b0c..71f39659e 100644 --- a/ARMeilleure/Decoders/OpCodeAluRs.cs +++ b/ARMeilleure/Decoders/OpCodeAluRs.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public ShiftType ShiftType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRs(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode); - public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int shift = (opCode >> 10) & 0x3f; @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 22) & 0x3); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeAluRx.cs b/ARMeilleure/Decoders/OpCodeAluRx.cs index 12617d840..16690b26a 100644 --- a/ARMeilleure/Decoders/OpCodeAluRx.cs +++ b/ARMeilleure/Decoders/OpCodeAluRx.cs @@ -7,13 +7,13 @@ namespace ARMeilleure.Decoders public IntType IntType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRx(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode); - public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Shift = (opCode >> 10) & 0x7; IntType = (IntType)((opCode >> 13) & 0x7); Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBImm.cs b/ARMeilleure/Decoders/OpCodeBImm.cs index b03239254..2848c1409 100644 --- a/ARMeilleure/Decoders/OpCodeBImm.cs +++ b/ARMeilleure/Decoders/OpCodeBImm.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { public long Immediate { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode); - public OpCodeBImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { } + public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBImmAl.cs b/ARMeilleure/Decoders/OpCodeBImmAl.cs index 37da568cc..6c4b28c6c 100644 --- a/ARMeilleure/Decoders/OpCodeBImmAl.cs +++ b/ARMeilleure/Decoders/OpCodeBImmAl.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeBImmAl : OpCodeBImm { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmAl(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode); - public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/ARMeilleure/Decoders/OpCodeBImmCmp.cs index cbd3e6ace..c477ddecf 100644 --- a/ARMeilleure/Decoders/OpCodeBImmCmp.cs +++ b/ARMeilleure/Decoders/OpCodeBImmCmp.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int Rt { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCmp(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode); - public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = opCode & 0x1f; @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBImmCond.cs b/ARMeilleure/Decoders/OpCodeBImmCond.cs index edc5c5e9d..7a51a0720 100644 --- a/ARMeilleure/Decoders/OpCodeBImmCond.cs +++ b/ARMeilleure/Decoders/OpCodeBImmCond.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public Condition Cond { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCond(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode); - public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int o0 = (opCode >> 4) & 1; @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBImmTest.cs b/ARMeilleure/Decoders/OpCodeBImmTest.cs index 99ebc722e..4403a0b23 100644 --- a/ARMeilleure/Decoders/OpCodeBImmTest.cs +++ b/ARMeilleure/Decoders/OpCodeBImmTest.cs @@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders public int Rt { get; } public int Bit { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmTest(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode); - public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = opCode & 0x1f; @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders Bit |= (opCode >> 26) & 0x20; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBReg.cs b/ARMeilleure/Decoders/OpCodeBReg.cs index a38f7e71a..c29b63914 100644 --- a/ARMeilleure/Decoders/OpCodeBReg.cs +++ b/ARMeilleure/Decoders/OpCodeBReg.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int Rn { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode); - public OpCodeBReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int op4 = (opCode >> 0) & 0x1f; int op2 = (opCode >> 16) & 0x1f; @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 5) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeBfm.cs b/ARMeilleure/Decoders/OpCodeBfm.cs index 232798ad6..57d0450d5 100644 --- a/ARMeilleure/Decoders/OpCodeBfm.cs +++ b/ARMeilleure/Decoders/OpCodeBfm.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public int Pos { get; } public int Shift { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBfm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode); - public OpCodeBfm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { var bm = DecoderHelper.DecodeBitMask(opCode, false); @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders Shift = bm.Shift; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeCcmp.cs b/ARMeilleure/Decoders/OpCodeCcmp.cs index f9c1026d0..c25138d27 100644 --- a/ARMeilleure/Decoders/OpCodeCcmp.cs +++ b/ARMeilleure/Decoders/OpCodeCcmp.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public Condition Cond { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmp(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode); - public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int o3 = (opCode >> 4) & 1; @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders Rd = RegisterAlias.Zr; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/ARMeilleure/Decoders/OpCodeCcmpImm.cs index 9a02319a2..9d6acf196 100644 --- a/ARMeilleure/Decoders/OpCodeCcmpImm.cs +++ b/ARMeilleure/Decoders/OpCodeCcmpImm.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { public long Immediate => RmImm; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode); - public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { } + public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/ARMeilleure/Decoders/OpCodeCcmpReg.cs index 4b5e175f5..349afa120 100644 --- a/ARMeilleure/Decoders/OpCodeCcmpReg.cs +++ b/ARMeilleure/Decoders/OpCodeCcmpReg.cs @@ -8,8 +8,8 @@ namespace ARMeilleure.Decoders public ShiftType ShiftType => ShiftType.Lsl; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode); - public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { } + public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeCsel.cs b/ARMeilleure/Decoders/OpCodeCsel.cs index edfee22eb..3bd87b182 100644 --- a/ARMeilleure/Decoders/OpCodeCsel.cs +++ b/ARMeilleure/Decoders/OpCodeCsel.cs @@ -6,12 +6,12 @@ namespace ARMeilleure.Decoders public Condition Cond { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCsel(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode); - public OpCodeCsel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 16) & 0x1f; Cond = (Condition)((opCode >> 12) & 0xf); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeException.cs b/ARMeilleure/Decoders/OpCodeException.cs index 3b84990c1..eee636405 100644 --- a/ARMeilleure/Decoders/OpCodeException.cs +++ b/ARMeilleure/Decoders/OpCodeException.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { public int Id { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeException(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode); - public OpCodeException(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Id = (opCode >> 5) & 0xffff; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMem.cs b/ARMeilleure/Decoders/OpCodeMem.cs index 6e888c3c3..ecbb175b3 100644 --- a/ARMeilleure/Decoders/OpCodeMem.cs +++ b/ARMeilleure/Decoders/OpCodeMem.cs @@ -7,13 +7,13 @@ namespace ARMeilleure.Decoders public int Size { get; protected set; } public bool Extend64 { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode); - public OpCodeMem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; Size = (opCode >> 30) & 0x3; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMemEx.cs b/ARMeilleure/Decoders/OpCodeMemEx.cs index 3e018b29d..01e327d36 100644 --- a/ARMeilleure/Decoders/OpCodeMemEx.cs +++ b/ARMeilleure/Decoders/OpCodeMemEx.cs @@ -5,12 +5,12 @@ namespace ARMeilleure.Decoders public int Rt2 { get; } public int Rs { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemEx(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode); - public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt2 = (opCode >> 10) & 0x1f; Rs = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMemImm.cs b/ARMeilleure/Decoders/OpCodeMemImm.cs index c27eeae3b..3acd0dfdb 100644 --- a/ARMeilleure/Decoders/OpCodeMemImm.cs +++ b/ARMeilleure/Decoders/OpCodeMemImm.cs @@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders Unsigned } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode); - public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; WBack = ((opCode >> 24) & 1) == 0; @@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMemLit.cs b/ARMeilleure/Decoders/OpCodeMemLit.cs index 0210bbe0c..2ee1afd02 100644 --- a/ARMeilleure/Decoders/OpCodeMemLit.cs +++ b/ARMeilleure/Decoders/OpCodeMemLit.cs @@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders public bool Signed { get; } public bool Prefetch { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemLit(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode); - public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = opCode & 0x1f; @@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMemPair.cs b/ARMeilleure/Decoders/OpCodeMemPair.cs index e805dca0a..f0999a543 100644 --- a/ARMeilleure/Decoders/OpCodeMemPair.cs +++ b/ARMeilleure/Decoders/OpCodeMemPair.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int Rt2 { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemPair(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode); - public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt2 = (opCode >> 10) & 0x1f; WBack = ((opCode >> 23) & 0x1) != 0; @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMemReg.cs b/ARMeilleure/Decoders/OpCodeMemReg.cs index 361156663..4cd02c253 100644 --- a/ARMeilleure/Decoders/OpCodeMemReg.cs +++ b/ARMeilleure/Decoders/OpCodeMemReg.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public IntType IntType { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode); - public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Shift = ((opCode >> 12) & 0x1) != 0; IntType = (IntType)((opCode >> 13) & 0x7); @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders Extend64 = ((opCode >> 22) & 0x3) == 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMov.cs b/ARMeilleure/Decoders/OpCodeMov.cs index e665d700d..be320dd9b 100644 --- a/ARMeilleure/Decoders/OpCodeMov.cs +++ b/ARMeilleure/Decoders/OpCodeMov.cs @@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders public int Bit { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMov(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode); - public OpCodeMov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int p1 = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeMul.cs b/ARMeilleure/Decoders/OpCodeMul.cs index d0f0370f6..9b1dd37b8 100644 --- a/ARMeilleure/Decoders/OpCodeMul.cs +++ b/ARMeilleure/Decoders/OpCodeMul.cs @@ -5,12 +5,12 @@ namespace ARMeilleure.Decoders public int Rm { get; } public int Ra { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMul(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode); - public OpCodeMul(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Ra = (opCode >> 10) & 0x1f; Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimd.cs b/ARMeilleure/Decoders/OpCodeSimd.cs index 07fe2b5fb..c0ac09997 100644 --- a/ARMeilleure/Decoders/OpCodeSimd.cs +++ b/ARMeilleure/Decoders/OpCodeSimd.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public int Opc { get; } public int Size { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimd(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode); - public OpCodeSimd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/ARMeilleure/Decoders/OpCodeSimdCvt.cs index 60791da46..48446c908 100644 --- a/ARMeilleure/Decoders/OpCodeSimdCvt.cs +++ b/ARMeilleure/Decoders/OpCodeSimdCvt.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int FBits { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdCvt(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode); - public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int scale = (opCode >> 10) & 0x3f; int sf = (opCode >> 31) & 0x1; @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdExt.cs b/ARMeilleure/Decoders/OpCodeSimdExt.cs index 29e9a4fa5..0a3359e13 100644 --- a/ARMeilleure/Decoders/OpCodeSimdExt.cs +++ b/ARMeilleure/Decoders/OpCodeSimdExt.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { public int Imm4 { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdExt(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode); - public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Imm4 = (opCode >> 11) & 0xf; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/ARMeilleure/Decoders/OpCodeSimdFcond.cs index 27438eb78..aa16e0c19 100644 --- a/ARMeilleure/Decoders/OpCodeSimdFcond.cs +++ b/ARMeilleure/Decoders/OpCodeSimdFcond.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders public Condition Cond { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFcond(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode); - public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); diff --git a/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/ARMeilleure/Decoders/OpCodeSimdFmov.cs index 01c61a073..d0d9c89a7 100644 --- a/ARMeilleure/Decoders/OpCodeSimdFmov.cs +++ b/ARMeilleure/Decoders/OpCodeSimdFmov.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders public long Immediate { get; } public int Size { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFmov(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode); - public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int type = (opCode >> 22) & 0x3; @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdImm.cs b/ARMeilleure/Decoders/OpCodeSimdImm.cs index 8c39ee2c9..420b4501f 100644 --- a/ARMeilleure/Decoders/OpCodeSimdImm.cs +++ b/ARMeilleure/Decoders/OpCodeSimdImm.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders public long Immediate { get; } public int Size { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode); - public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; @@ -104,4 +104,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdIns.cs b/ARMeilleure/Decoders/OpCodeSimdIns.cs index 675a138c6..820656163 100644 --- a/ARMeilleure/Decoders/OpCodeSimdIns.cs +++ b/ARMeilleure/Decoders/OpCodeSimdIns.cs @@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders public int SrcIndex { get; } public int DstIndex { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdIns(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode); - public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm4 = (opCode >> 11) & 0xf; int imm5 = (opCode >> 16) & 0x1f; @@ -33,4 +33,4 @@ namespace ARMeilleure.Decoders DstIndex = imm5 >> (Size + 1); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/ARMeilleure/Decoders/OpCodeSimdMemImm.cs index b0469875c..14a9d7c9c 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemImm.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemImm.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode); - public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size |= (opCode >> 21) & 4; @@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/ARMeilleure/Decoders/OpCodeSimdMemLit.cs index 66525e601..55b43dae8 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemLit.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemLit.cs @@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders public bool Signed => false; public bool Prefetch => false; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemLit(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode); - public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int opc = (opCode >> 30) & 3; @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders Size = opc + 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/ARMeilleure/Decoders/OpCodeSimdMemMs.cs index 61523830d..c7d4b35f0 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemMs.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemMs.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public int Elems { get; } public bool WBack { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemMs(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode); - public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { switch ((opCode >> 12) & 0xf) { @@ -45,4 +45,4 @@ namespace ARMeilleure.Decoders Elems = (GetBitsCount() >> 3) >> Size; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/ARMeilleure/Decoders/OpCodeSimdMemPair.cs index 28b1b4fc1..697163896 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemPair.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemPair.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemPair(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode); - public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = ((opCode >> 30) & 3) + 2; @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders DecodeImm(opCode); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs index fa14f6717..be7b25b9d 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode); - public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size |= (opCode >> 21) & 4; @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/ARMeilleure/Decoders/OpCodeSimdMemSs.cs index b7259a5d4..4ed859635 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemSs.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemSs.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public bool Replicate { get; } public bool WBack { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemSs(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode); - public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int size = (opCode >> 10) & 3; int s = (opCode >> 12) & 1; @@ -94,4 +94,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdReg.cs b/ARMeilleure/Decoders/OpCodeSimdReg.cs index b56ca6f92..731d1a6f5 100644 --- a/ARMeilleure/Decoders/OpCodeSimdReg.cs +++ b/ARMeilleure/Decoders/OpCodeSimdReg.cs @@ -6,13 +6,13 @@ namespace ARMeilleure.Decoders public int Ra { get; } public int Rm { get; protected set; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode); - public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Bit3 = ((opCode >> 3) & 0x1) != 0; Ra = (opCode >> 10) & 0x1f; Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/ARMeilleure/Decoders/OpCodeSimdRegElem.cs index a1b285149..403fd172c 100644 --- a/ARMeilleure/Decoders/OpCodeSimdRegElem.cs +++ b/ARMeilleure/Decoders/OpCodeSimdRegElem.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int Index { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdRegElem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdRegElem(inst, address, opCode); - public OpCodeSimdRegElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { switch (Size) { @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs index 3b2b191ad..d46dd57ed 100644 --- a/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs +++ b/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs @@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders { public int Index { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdRegElemF(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdRegElemF(inst, address, opCode); - public OpCodeSimdRegElemF(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdRegElemF(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { switch ((opCode >> 21) & 3) // sz:L { diff --git a/ARMeilleure/Decoders/OpCodeSimdShImm.cs b/ARMeilleure/Decoders/OpCodeSimdShImm.cs index a14ef67fb..7064f1d2d 100644 --- a/ARMeilleure/Decoders/OpCodeSimdShImm.cs +++ b/ARMeilleure/Decoders/OpCodeSimdShImm.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders { public int Imm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdShImm(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdShImm(inst, address, opCode); - public OpCodeSimdShImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Imm = (opCode >> 16) & 0x7f; diff --git a/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/ARMeilleure/Decoders/OpCodeSimdTbl.cs index 5e7806c47..3a7ef6aba 100644 --- a/ARMeilleure/Decoders/OpCodeSimdTbl.cs +++ b/ARMeilleure/Decoders/OpCodeSimdTbl.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeSimdTbl : OpCodeSimdReg { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdTbl(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdTbl(inst, address, opCode); - public OpCodeSimdTbl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Size = ((opCode >> 13) & 3) + 1; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeSystem.cs b/ARMeilleure/Decoders/OpCodeSystem.cs index 1b1741a34..34fae84cf 100644 --- a/ARMeilleure/Decoders/OpCodeSystem.cs +++ b/ARMeilleure/Decoders/OpCodeSystem.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public int Op1 { get; } public int Op0 { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSystem(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSystem(inst, address, opCode); - public OpCodeSystem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 0) & 0x1f; Op2 = (opCode >> 5) & 0x7; @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders Op0 = ((opCode >> 19) & 0x1) | 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16.cs b/ARMeilleure/Decoders/OpCodeT16.cs index 4c7945f90..9fef0ebf2 100644 --- a/ARMeilleure/Decoders/OpCodeT16.cs +++ b/ARMeilleure/Decoders/OpCodeT16.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders { class OpCodeT16 : OpCode32 { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16(inst, address, opCode); - public OpCodeT16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Cond = Condition.Al; OpCodeSizeInBytes = 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs index 18afa76ab..95f180548 100644 --- a/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs +++ b/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs @@ -5,22 +5,20 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; public int Immediate { get; } public bool IsRotated { get; } - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubImm3(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubImm3(inst, address, opCode); - public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rn = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x7; IsRotated = false; - - SetFlags = !inITBlock; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs b/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs index 740ab877d..2a407b2d2 100644 --- a/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs +++ b/ARMeilleure/Decoders/OpCodeT16AddSubReg.cs @@ -6,17 +6,15 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubReg(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubReg(inst, address, opCode); - public OpCodeT16AddSubReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AddSubReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rn = (opCode >> 3) & 0x7; Rm = (opCode >> 6) & 0x7; - - SetFlags = !inITBlock; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs b/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs index 8f68ef184..8d60ab983 100644 --- a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs +++ b/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs @@ -5,17 +5,17 @@ namespace ARMeilleure.Decoders public int Rd => 13; public int Rn => 13; - public bool SetFlags => false; + public bool? SetFlags => false; public int Immediate { get; } public bool IsRotated => false; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubSp(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubSp(inst, address, opCode); - public OpCodeT16AddSubSp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AddSubSp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Immediate = ((opCode >> 0) & 0x7f) << 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16Adr.cs b/ARMeilleure/Decoders/OpCodeT16Adr.cs index 4e95fa9a0..ef14791d9 100644 --- a/ARMeilleure/Decoders/OpCodeT16Adr.cs +++ b/ARMeilleure/Decoders/OpCodeT16Adr.cs @@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders public bool Add => true; public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16Adr(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Adr(inst, address, opCode); - public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 8) & 7; diff --git a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs index 082bcb851..673a46045 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs @@ -5,22 +5,20 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; public int Immediate { get; } public bool IsRotated { get; } - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AluImm8(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImm8(inst, address, opCode); - public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 8) & 0x7; Rn = (opCode >> 8) & 0x7; Immediate = (opCode >> 0) & 0xff; IsRotated = false; - - SetFlags = !inITBlock; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs b/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs index bbe5573d9..b23f8fe03 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluImmZero.cs @@ -5,22 +5,20 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; public int Immediate { get; } public bool IsRotated { get; } - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AluImmZero(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImmZero(inst, address, opCode); - public OpCodeT16AluImmZero(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AluImmZero(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rn = (opCode >> 3) & 0x7; Immediate = 0; IsRotated = false; - - SetFlags = !inITBlock; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs b/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs index e4765641a..6d5ac8fd3 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs @@ -6,17 +6,15 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => false; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AluRegHigh(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluRegHigh(inst, address, opCode); - public OpCodeT16AluRegHigh(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AluRegHigh(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = ((opCode >> 0) & 0x7) | ((opCode >> 4) & 0x8); Rn = ((opCode >> 0) & 0x7) | ((opCode >> 4) & 0x8); Rm = (opCode >> 3) & 0xf; - - SetFlags = false; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs b/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs index d8fcb0c75..b37b4f661 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluRegLow.cs @@ -6,17 +6,15 @@ public int Rd { get; } public int Rn { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AluRegLow(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluRegLow(inst, address, opCode); - public OpCodeT16AluRegLow(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AluRegLow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rn = (opCode >> 0) & 0x7; Rm = (opCode >> 3) & 0x7; - - SetFlags = !inITBlock; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16AluUx.cs b/ARMeilleure/Decoders/OpCodeT16AluUx.cs index 3debb761e..11d3a8fe8 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluUx.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluUx.cs @@ -6,17 +6,17 @@ namespace ARMeilleure.Decoders public int Rd { get; } public int Rn { get; } - public bool SetFlags => false; + public bool? SetFlags => false; public int RotateBits => 0; public bool Add => false; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AluUx(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluUx(inst, address, opCode); - public OpCodeT16AluUx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rm = (opCode >> 3) & 0x7; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16BImm11.cs b/ARMeilleure/Decoders/OpCodeT16BImm11.cs index 2f52839de..42ebec4f6 100644 --- a/ARMeilleure/Decoders/OpCodeT16BImm11.cs +++ b/ARMeilleure/Decoders/OpCodeT16BImm11.cs @@ -4,12 +4,12 @@ { public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16BImm11(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImm11(inst, address, opCode); - public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int imm = (opCode << 21) >> 20; Immediate = GetPc() + imm; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16BImm8.cs b/ARMeilleure/Decoders/OpCodeT16BImm8.cs index d70327dc2..9b3a4ad1b 100644 --- a/ARMeilleure/Decoders/OpCodeT16BImm8.cs +++ b/ARMeilleure/Decoders/OpCodeT16BImm8.cs @@ -4,9 +4,9 @@ { public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16BImm8(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImm8(inst, address, opCode); - public OpCodeT16BImm8(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16BImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Cond = (Condition)((opCode >> 8) & 0xf); @@ -14,4 +14,4 @@ Immediate = GetPc() + imm; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs b/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs index d1850b8b3..ab7ae13f7 100644 --- a/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs +++ b/ARMeilleure/Decoders/OpCodeT16BImmCmp.cs @@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders public int Immediate { get; } - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16BImmCmp(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImmCmp(inst, address, opCode); - public OpCodeT16BImmCmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16BImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rn = (opCode >> 0) & 0x7; @@ -16,4 +16,4 @@ namespace ARMeilleure.Decoders Immediate = (int)GetPc() + imm; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16BReg.cs b/ARMeilleure/Decoders/OpCodeT16BReg.cs index 65fbc8bbb..3122cd07e 100644 --- a/ARMeilleure/Decoders/OpCodeT16BReg.cs +++ b/ARMeilleure/Decoders/OpCodeT16BReg.cs @@ -4,9 +4,9 @@ { public int Rm { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16BReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BReg(inst, address, opCode); - public OpCodeT16BReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rm = (opCode >> 3) & 0xf; } diff --git a/ARMeilleure/Decoders/OpCodeT16Exception.cs b/ARMeilleure/Decoders/OpCodeT16Exception.cs index 08763d405..bb0050834 100644 --- a/ARMeilleure/Decoders/OpCodeT16Exception.cs +++ b/ARMeilleure/Decoders/OpCodeT16Exception.cs @@ -4,9 +4,9 @@ { public int Id { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16Exception(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Exception(inst, address, opCode); - public OpCodeT16Exception(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Id = opCode & 0xFF; } diff --git a/ARMeilleure/Decoders/OpCodeT16IfThen.cs b/ARMeilleure/Decoders/OpCodeT16IfThen.cs index da5b2dc06..bf84d1d30 100644 --- a/ARMeilleure/Decoders/OpCodeT16IfThen.cs +++ b/ARMeilleure/Decoders/OpCodeT16IfThen.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public int IfThenBlockSize { get { return IfThenBlockConds.Length; } } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16IfThen(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16IfThen(inst, address, opCode); - public OpCodeT16IfThen(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16IfThen(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { List conds = new(); @@ -31,4 +31,4 @@ namespace ARMeilleure.Decoders IfThenBlockConds = conds.ToArray(); } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/ARMeilleure/Decoders/OpCodeT16MemImm5.cs index a2b1f9e8a..13a16809d 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemImm5.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemImm5.cs @@ -14,9 +14,9 @@ namespace ARMeilleure.Decoders public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemImm5(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemImm5(inst, address, opCode); - public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 0) & 7; Rn = (opCode >> 3) & 7; diff --git a/ARMeilleure/Decoders/OpCodeT16MemLit.cs b/ARMeilleure/Decoders/OpCodeT16MemLit.cs index d9203f61b..4be1ee84b 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemLit.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemLit.cs @@ -12,12 +12,12 @@ public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemLit(inst, address, opCode, inITBlock); - public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode); + public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 8) & 7; Immediate = (opCode & 0xff) << 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/ARMeilleure/Decoders/OpCodeT16MemMult.cs index b0fd11c0a..841d0f852 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemMult.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemMult.cs @@ -12,9 +12,9 @@ namespace ARMeilleure.Decoders public bool IsLoad { get; } public int Offset { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemMult(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemMult(inst, address, opCode); - public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { RegisterMask = opCode & 0xff; Rn = (opCode >> 8) & 7; @@ -38,4 +38,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16MemReg.cs b/ARMeilleure/Decoders/OpCodeT16MemReg.cs index 2ff448473..71100112e 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemReg.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemReg.cs @@ -13,9 +13,9 @@ public int Immediate => throw new System.InvalidOperationException(); - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemReg(inst, address, opCode); - public OpCodeT16MemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 0) & 7; Rn = (opCode >> 3) & 7; @@ -24,4 +24,4 @@ IsLoad = ((opCode >> 9) & 7) >= 3; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16MemSp.cs b/ARMeilleure/Decoders/OpCodeT16MemSp.cs index e3b117d4c..7b2956c86 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemSp.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemSp.cs @@ -12,9 +12,9 @@ public int Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemSp(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemSp(inst, address, opCode); - public OpCodeT16MemSp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16MemSp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 8) & 7; @@ -23,4 +23,4 @@ Immediate = ((opCode >> 0) & 0xff) << 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16MemStack.cs b/ARMeilleure/Decoders/OpCodeT16MemStack.cs index 1b5c4125c..c527e105a 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemStack.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemStack.cs @@ -12,9 +12,9 @@ namespace ARMeilleure.Decoders public bool IsLoad { get; } public int Offset { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemStack(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemStack(inst, address, opCode); - public OpCodeT16MemStack(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16MemStack(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int extra = (opCode >> 8) & 1; int regCount = BitOperations.PopCount((uint)opCode & 0x1ff); @@ -38,4 +38,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs index 1d05cebf3..a540026ec 100644 --- a/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs +++ b/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs @@ -9,18 +9,16 @@ public int Immediate { get; } public ShiftType ShiftType { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16ShiftImm(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16ShiftImm(inst, address, opCode); - public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 0x7; Rm = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x1F; ShiftType = (ShiftType)((opCode >> 11) & 3); - - SetFlags = !inITBlock; } } } diff --git a/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs b/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs index 1553ecb70..9f8982814 100644 --- a/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs +++ b/ARMeilleure/Decoders/OpCodeT16ShiftReg.cs @@ -10,11 +10,11 @@ public ShiftType ShiftType { get; } - public bool SetFlags { get; } + public bool? SetFlags => null; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16ShiftReg(inst, address, opCode, inITBlock); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16ShiftReg(inst, address, opCode); - public OpCodeT16ShiftReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 0) & 7; Rm = (opCode >> 0) & 7; @@ -22,8 +22,6 @@ Rs = (opCode >> 3) & 7; ShiftType = (ShiftType)(((opCode >> 6) & 1) | ((opCode >> 7) & 2)); - - SetFlags = !inITBlock; } } } diff --git a/ARMeilleure/Decoders/OpCodeT16SpRel.cs b/ARMeilleure/Decoders/OpCodeT16SpRel.cs index 28ad0de38..dc3c4cf54 100644 --- a/ARMeilleure/Decoders/OpCodeT16SpRel.cs +++ b/ARMeilleure/Decoders/OpCodeT16SpRel.cs @@ -5,18 +5,18 @@ namespace ARMeilleure.Decoders public int Rd { get; } public int Rn => 13; - public bool SetFlags => false; + public bool? SetFlags => false; public int Immediate { get; } public bool IsRotated => false; - public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16SpRel(inst, address, opCode, inITBlock); + public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16SpRel(inst, address, opCode); - public OpCodeT16SpRel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) + public OpCodeT16SpRel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = (opCode >> 8) & 0x7; Immediate = ((opCode >> 0) & 0xff) << 2; } } -} \ No newline at end of file +} diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs index 245f4e013..1ea8885b1 100644 --- a/ARMeilleure/Decoders/OpCodeTable.cs +++ b/ARMeilleure/Decoders/OpCodeTable.cs @@ -6,7 +6,7 @@ namespace ARMeilleure.Decoders { static class OpCodeTable { - public delegate OpCode MakeOp(InstDescriptor inst, ulong address, int opCode, bool inITBlock); + public delegate OpCode MakeOp(InstDescriptor inst, ulong address, int opCode); private const int FastLookupSize = 0x1000; diff --git a/ARMeilleure/Instructions/InstEmitAlu32.cs b/ARMeilleure/Instructions/InstEmitAlu32.cs index 66b8a8a7e..1cbc0765d 100644 --- a/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Instructions Operand res = context.Add(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -44,7 +44,7 @@ namespace ARMeilleure.Instructions res = context.Add(res, carry); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -64,7 +64,7 @@ namespace ARMeilleure.Instructions Operand res = context.BitwiseAnd(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -110,7 +110,7 @@ namespace ARMeilleure.Instructions Operand res = context.BitwiseAnd(n, context.BitwiseNot(m)); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions Operand res = context.BitwiseExclusiveOr(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -175,7 +175,7 @@ namespace ARMeilleure.Instructions Operand m = GetAluM(context); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, m); } @@ -204,7 +204,7 @@ namespace ARMeilleure.Instructions Operand res = context.Multiply(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -219,7 +219,7 @@ namespace ARMeilleure.Instructions Operand res = context.BitwiseNot(m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -236,7 +236,7 @@ namespace ARMeilleure.Instructions Operand res = context.BitwiseOr(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -315,7 +315,7 @@ namespace ARMeilleure.Instructions res = context.Subtract(res, borrow); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -335,7 +335,7 @@ namespace ARMeilleure.Instructions Operand res = context.Subtract(m, n); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -359,7 +359,7 @@ namespace ARMeilleure.Instructions res = context.Subtract(res, borrow); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -420,7 +420,7 @@ namespace ARMeilleure.Instructions Operand res = context.Subtract(n, m); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); @@ -836,7 +836,7 @@ namespace ARMeilleure.Instructions { IOpCode32Alu op = (IOpCode32Alu)context.CurrOp; - EmitGenericAluStoreA32(context, op.Rd, op.SetFlags, value); + EmitGenericAluStoreA32(context, op.Rd, ShouldSetFlags(context), value); } } } diff --git a/ARMeilleure/Instructions/InstEmitAluHelper.cs b/ARMeilleure/Instructions/InstEmitAluHelper.cs index 9d5bd19e4..fe5557677 100644 --- a/ARMeilleure/Instructions/InstEmitAluHelper.cs +++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs @@ -12,6 +12,18 @@ namespace ARMeilleure.Instructions { static class InstEmitAluHelper { + public static bool ShouldSetFlags(ArmEmitterContext context) + { + IOpCode32Alu op = (IOpCode32Alu)context.CurrOp; + + if (op.SetFlags == null) + { + return !context.IsInIfThenBlock; + } + + return op.SetFlags.Value; + } + public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d) { SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0))); @@ -185,7 +197,7 @@ namespace ARMeilleure.Instructions // ARM32. case IOpCode32AluImm op: { - if (op.SetFlags && op.IsRotated) + if (ShouldSetFlags(context) && op.IsRotated) { SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31)); } @@ -265,7 +277,7 @@ namespace ARMeilleure.Instructions if (shift != 0) { - setCarry &= op.SetFlags; + setCarry &= ShouldSetFlags(context); switch (op.ShiftType) { @@ -312,7 +324,7 @@ namespace ARMeilleure.Instructions Operand zeroResult = m; Operand shiftResult = m; - setCarry &= op.SetFlags; + setCarry &= ShouldSetFlags(context); switch (op.ShiftType) { diff --git a/ARMeilleure/Instructions/InstEmitMul32.cs b/ARMeilleure/Instructions/InstEmitMul32.cs index 92ed47728..868a1f421 100644 --- a/ARMeilleure/Instructions/InstEmitMul32.cs +++ b/ARMeilleure/Instructions/InstEmitMul32.cs @@ -33,7 +33,7 @@ namespace ARMeilleure.Instructions Operand res = context.Add(a, context.Multiply(n, m)); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } @@ -250,13 +250,13 @@ namespace ARMeilleure.Instructions Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32))); Operand lo = context.ConvertI64ToI32(res); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } - EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi); - EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo); + EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi); + EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo); } public static void Smulw_(ArmEmitterContext context) @@ -320,13 +320,13 @@ namespace ARMeilleure.Instructions Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32))); Operand lo = context.ConvertI64ToI32(res); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } - EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi); - EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo); + EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi); + EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo); } private static void EmitMlal(ArmEmitterContext context, bool signed) @@ -356,13 +356,13 @@ namespace ARMeilleure.Instructions Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32))); Operand lo = context.ConvertI64ToI32(res); - if (op.SetFlags) + if (ShouldSetFlags(context)) { EmitNZFlagsCheck(context, res); } - EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi); - EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo); + EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi); + EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo); } private static void UpdateQFlag(ArmEmitterContext context, Operand q) diff --git a/ARMeilleure/Translation/Translator.cs b/ARMeilleure/Translation/Translator.cs index c9779bf56..4962a8460 100644 --- a/ARMeilleure/Translation/Translator.cs +++ b/ARMeilleure/Translation/Translator.cs @@ -385,8 +385,6 @@ namespace ARMeilleure.Translation lblPredicateSkip = Label(); InstEmitFlowHelper.EmitCondBranch(context, lblPredicateSkip, context.CurrentIfThenBlockCond.Invert()); - - context.AdvanceIfThenBlockState(); } if (opCode is OpCode32 op && op.Cond < Condition.Al) @@ -409,6 +407,11 @@ namespace ARMeilleure.Translation { context.MarkLabel(lblPredicateSkip); } + + if (context.IsInIfThenBlock && opCode.Instruction.Name != InstName.It) + { + context.AdvanceIfThenBlockState(); + } } } }