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Improve HyrbidAllocator
This commit is contained in:
FICTURE7
parent
5ff5fe47ba
commit
4c8753f484
2 changed files with 232 additions and 173 deletions
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@ -41,10 +41,10 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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public bool IsBlockLocal => _first == _last;
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public LocalInfo(OperandType type, int uses, int blkIndex)
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public LocalInfo(Operand local, int uses, int blkIndex)
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{
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Uses = uses;
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Type = type;
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Type = local.Type;
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UsesAllocated = 0;
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Sequence = 0;
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@ -72,7 +72,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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}
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}
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private const int MaxIROperands = 4;
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private const int RegistersCount = 16;
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// The "visited" state is stored in the MSB of the local's value.
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private const ulong VisitedMask = 1ul << 63;
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@ -173,7 +174,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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}
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SetVisited(dest);
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GetLocalInfo(dest) = new LocalInfo(dest.Type, UsesCount(dest), block.Index);
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GetLocalInfo(dest) = new LocalInfo(dest, UsesCount(dest), block.Index);
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}
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}
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else if (dest.Kind == OperandKind.Register)
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@ -193,7 +194,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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_blockInfo[block.Index] = new BlockInfo(hasCall, intFixedRegisters, vecFixedRegisters);
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}
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int sequence = 0;
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Operand[] intActive = new Operand[RegistersCount];
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Operand[] vecActive = new Operand[RegistersCount];
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for (int index = cfg.PostOrderBlocks.Length - 1; index >= 0; index--)
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{
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@ -204,74 +206,22 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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int intLocalFreeRegisters = intFreeRegisters & ~blkInfo.IntFixedRegisters;
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int vecLocalFreeRegisters = vecFreeRegisters & ~blkInfo.VecFixedRegisters;
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int intCallerSavedRegisters = blkInfo.HasCall ? regMasks.IntCallerSavedRegisters : 0;
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int vecCallerSavedRegisters = blkInfo.HasCall ? regMasks.VecCallerSavedRegisters : 0;
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if (blkInfo.HasCall)
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{
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intLocalFreeRegisters &= ~regMasks.IntCallerSavedRegisters;
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vecLocalFreeRegisters &= ~regMasks.VecCallerSavedRegisters;
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}
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int intSpillTempRegisters = SelectSpillTemps(
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intCallerSavedRegisters & ~blkInfo.IntFixedRegisters,
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intLocalFreeRegisters);
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int vecSpillTempRegisters = SelectSpillTemps(
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vecCallerSavedRegisters & ~blkInfo.VecFixedRegisters,
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vecLocalFreeRegisters);
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intLocalFreeRegisters &= ~(intSpillTempRegisters | intCallerSavedRegisters);
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vecLocalFreeRegisters &= ~(vecSpillTempRegisters | vecCallerSavedRegisters);
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int intActiveRegisters = 0;
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int vecActiveRegisters = 0;
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for (Operation node = block.Operations.First; node != default; node = node.ListNext)
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{
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int intLocalUse = 0;
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int vecLocalUse = 0;
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Operand AllocateRegister(Operand local)
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{
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ref LocalInfo info = ref GetLocalInfo(local);
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info.UsesAllocated++;
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Debug.Assert(info.UsesAllocated <= info.Uses);
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if (info.Register != default)
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{
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if (info.UsesAllocated == info.Uses)
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{
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Register reg = info.Register.GetRegister();
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if (local.Type.IsInteger())
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{
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intLocalFreeRegisters |= 1 << reg.Index;
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}
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else
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{
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vecLocalFreeRegisters |= 1 << reg.Index;
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}
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}
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return info.Register;
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}
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else
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{
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Operand temp = info.Temp;
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if (temp == default || info.Sequence != sequence)
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{
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temp = local.Type.IsInteger()
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? GetSpillTemp(local, intSpillTempRegisters, ref intLocalUse)
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: GetSpillTemp(local, vecSpillTempRegisters, ref vecLocalUse);
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info.Sequence = sequence;
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info.Temp = temp;
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}
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Operation fillOp = Operation(Instruction.Fill, temp, info.SpillOffset);
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block.Operations.AddBefore(node, fillOp);
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return temp;
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}
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}
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bool folded = false;
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int intCurrActiveRegisters = 0;
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int vecCurrActiveRegisters = 0;
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// If operation is a copy of a local and that local is living on the stack, we turn the copy into
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// a fill, instead of inserting a fill before it.
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if (node.Instruction == Instruction.Copy)
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@ -282,7 +232,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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{
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ref LocalInfo info = ref GetLocalInfo(source);
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if (info.Register == default)
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if (info.Register == default && info.SpillOffset != default)
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{
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Operation fillOp = Operation(Instruction.Fill, node.Destination, info.SpillOffset);
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@ -296,13 +246,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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}
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}
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// If the operation is folded to a fill, no need ot inspect sources; since sources of fills are
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// constant operands which does not require registers.
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if (!folded)
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{
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foreach (ref Operand source in node.SourcesUnsafe)
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{
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if (source.Kind == OperandKind.LocalVariable)
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{
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source = AllocateRegister(source);
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source = UseRegister(source);
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}
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else if (source.Kind == OperandKind.Memory)
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{
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@ -310,142 +262,251 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
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if (memOp.BaseAddress != default)
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{
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memOp.BaseAddress = AllocateRegister(memOp.BaseAddress);
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memOp.BaseAddress = UseRegister(memOp.BaseAddress);
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}
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if (memOp.Index != default)
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{
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memOp.Index = AllocateRegister(memOp.Index);
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memOp.Index = UseRegister(memOp.Index);
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}
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}
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}
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}
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int intLocalAsg = 0;
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int vecLocalAsg = 0;
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foreach (ref Operand dest in node.DestinationsUnsafe)
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{
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if (dest.Kind != OperandKind.LocalVariable)
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if (dest.Kind == OperandKind.LocalVariable)
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{
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continue;
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dest = DefRegister(dest);
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}
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}
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ref LocalInfo info = ref GetLocalInfo(dest);
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if (info.UsesAllocated == 0)
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{
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int mask = dest.Type.IsInteger()
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? intLocalFreeRegisters
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: vecLocalFreeRegisters;
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if (info.IsBlockLocal && mask != 0)
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{
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int selectedReg = BitOperations.TrailingZeroCount(mask);
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info.Register = Register(selectedReg, info.Type.ToRegisterType(), info.Type);
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if (dest.Type.IsInteger())
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{
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intLocalFreeRegisters &= ~(1 << selectedReg);
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intUsedRegisters |= 1 << selectedReg;
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}
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else
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{
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vecLocalFreeRegisters &= ~(1 << selectedReg);
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vecUsedRegisters |= 1 << selectedReg;
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}
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}
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else
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{
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info.Register = default;
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info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes()));
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}
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}
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Operand UseRegister(Operand local)
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{
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ref LocalInfo info = ref GetLocalInfo(local);
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info.UsesAllocated++;
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Debug.Assert(info.UsesAllocated <= info.Uses);
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if (info.Register != default)
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// If the local does not have a register, allocate one and reload the local from the stack.
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if (info.Register == default)
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{
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dest = info.Register;
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info.Uses++;
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info.Register = DefRegister(local);
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FillRegister(ref info, node);
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}
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Operand result = info.Register;
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Register reg = info.Register.GetRegister();
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if (local.Type.IsInteger())
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{
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intCurrActiveRegisters |= 1 << reg.Index;
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}
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else
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{
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Operand temp = info.Temp;
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vecCurrActiveRegisters |= 1 << reg.Index;
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}
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if (temp == default || info.Sequence != sequence)
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// If we've reached the last use of the local, we can free the register "gracefully".
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if (info.UsesAllocated == info.Uses)
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{
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// If the local is not a block local, we have to spill it; otherwise this would cause
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// issues when the local is used a in a loop.
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if (!info.IsBlockLocal)
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{
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temp = dest.Type.IsInteger()
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? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg)
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: GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
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info.Sequence = sequence;
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info.Temp = temp;
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SpillRegister(ref info, node);
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}
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dest = temp;
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if (local.Type.IsInteger())
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{
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intActiveRegisters &= ~(1 << reg.Index);
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intActive[reg.Index] = default;
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}
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else
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{
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vecActiveRegisters &= ~(1 << reg.Index);
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vecActive[reg.Index] = default;
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}
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Operation spillOp = Operation(Instruction.Spill, default, info.SpillOffset, temp);
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block.Operations.AddAfter(node, spillOp);
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node = spillOp;
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info.Register = default;
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}
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return result;
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}
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Operand DefRegister(Operand local)
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{
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ref LocalInfo info = ref GetLocalInfo(local);
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info.UsesAllocated++;
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Debug.Assert(info.UsesAllocated <= info.Uses);
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// If the local already has a register it is living in, return that register.
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if (info.Register != default)
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{
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return info.Register;
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}
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int mask = local.Type.IsInteger()
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? intLocalFreeRegisters & ~(intActiveRegisters | intCurrActiveRegisters)
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: vecLocalFreeRegisters & ~(vecActiveRegisters | vecCurrActiveRegisters);
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int selectedReg;
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// If we have inactive registers available, use one of them.
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if (mask != 0)
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{
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selectedReg = BitOperations.TrailingZeroCount(mask);
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}
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// Otherwise we spill an active register and use the that register.
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else
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{
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int spillReg;
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int spillMask;
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Operand spillLocal;
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Operand[] spillActive;
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if (local.Type.IsInteger())
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{
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spillMask = intActiveRegisters & ~intCurrActiveRegisters;
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spillActive = intActive;
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}
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else
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{
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spillMask = vecActiveRegisters & ~vecCurrActiveRegisters;
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spillActive = vecActive;
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}
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// The heuristic will select the first register which is holding a non block local. This is
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// based on the assumption that block locals are more likely to be used next.
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//
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// TODO: Quite often, this assumption is not necessarily true, investigate other heuristics.
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int tempMask = spillMask;
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do
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{
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spillReg = BitOperations.TrailingZeroCount(tempMask);
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spillLocal = spillActive[spillReg];
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if (!GetLocalInfo(spillLocal).IsBlockLocal)
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{
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break;
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}
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tempMask &= ~(1 << spillReg);
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}
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while (tempMask != 0);
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SpillRegister(ref GetLocalInfo(spillLocal), node);
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selectedReg = spillReg;
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}
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info.Register = Register(selectedReg, local.Type.ToRegisterType(), local.Type);
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// Move selected register to the active set.
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if (local.Type.IsInteger())
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{
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intUsedRegisters |= 1 << selectedReg;
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intActiveRegisters |= 1 << selectedReg;
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intCurrActiveRegisters |= 1 << selectedReg;
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intActive[selectedReg] = local;
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}
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else
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{
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vecUsedRegisters |= 1 << selectedReg;
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vecActiveRegisters |= 1 << selectedReg;
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vecCurrActiveRegisters |= 1 << selectedReg;
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vecActive[selectedReg] = local;
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}
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return info.Register;
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}
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}
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// If there are still registers in the active set after allocation of the block, we spill them for the
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// next block.
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if ((intActiveRegisters | vecActiveRegisters) != 0)
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{
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// If the block has 0 successors then the control flow exits. This means we can skip spilling and
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// since we're exiting anyways.
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bool needSpill = block.SuccessorsCount > 0;
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Operation dummyNode = block.Append(Operation(Instruction.Extended, default));
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while (intActiveRegisters != 0)
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{
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int reg = BitOperations.TrailingZeroCount(intActiveRegisters);
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ref LocalInfo info = ref GetLocalInfo(intActive[reg]);
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if (needSpill && !info.IsBlockLocal)
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{
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SpillRegister(ref info, dummyNode);
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}
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else
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{
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info.Register = default;
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}
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intActiveRegisters &= ~(1 << reg);
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intActive[reg] = default;
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}
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sequence++;
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while (vecActiveRegisters != 0)
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{
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int reg = BitOperations.TrailingZeroCount(vecActiveRegisters);
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ref LocalInfo info = ref GetLocalInfo(vecActive[reg]);
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intUsedRegisters |= intLocalAsg | intLocalUse;
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vecUsedRegisters |= vecLocalAsg | vecLocalUse;
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if (needSpill && !info.IsBlockLocal)
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{
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SpillRegister(ref info, dummyNode);
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}
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else
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{
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info.Register = default;
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}
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vecActiveRegisters &= ~(1 << reg);
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vecActive[reg] = default;
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}
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block.Operations.Remove(dummyNode);
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}
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void FillRegister(ref LocalInfo info, Operation node)
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{
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Debug.Assert(info.Register != default);
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Debug.Assert(info.SpillOffset != default);
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Operation fillOp = Operation(Instruction.Fill, info.Register, info.SpillOffset);
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block.Operations.AddBefore(node, fillOp);
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}
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void SpillRegister(ref LocalInfo info, Operation node)
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{
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Debug.Assert(info.Register != default);
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if (info.SpillOffset == default)
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{
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info.SpillOffset = Const(stackAlloc.Allocate(info.Type));
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}
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Operation spillOp = Operation(Instruction.Spill, default, info.SpillOffset, info.Register);
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block.Operations.AddBefore(node, spillOp);
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info.Register = default;
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}
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}
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return new AllocationResult(intUsedRegisters, vecUsedRegisters, stackAlloc.TotalSize);
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}
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private static int SelectSpillTemps(int mask0, int mask1)
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{
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int selection = 0;
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int count = 0;
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while (count < MaxIROperands && mask0 != 0)
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{
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int mask = mask0 & -mask0;
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selection |= mask;
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mask0 &= ~mask;
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count++;
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}
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while (count < MaxIROperands && mask1 != 0)
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{
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int mask = mask1 & -mask1;
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selection |= mask;
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mask1 &= ~mask;
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count++;
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}
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Debug.Assert(count == MaxIROperands, "No enough registers for spill temps.");
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return selection;
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}
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private static Operand GetSpillTemp(Operand local, int freeMask, ref int useMask)
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{
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int selectedReg = BitOperations.TrailingZeroCount(freeMask & ~useMask);
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useMask |= 1 << selectedReg;
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return Register(selectedReg, local.Type.ToRegisterType(), local.Type);
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}
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private static int UsesCount(Operand local)
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{
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return local.AssignmentsCount + local.UsesCount;
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@ -118,7 +118,7 @@ namespace ARMeilleure.IntermediateRepresentation
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oldBlock = block;
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}
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public void Append(Operation node)
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public Operation Append(Operation node)
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{
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Operation last = Operations.Last;
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@ -127,7 +127,7 @@ namespace ARMeilleure.IntermediateRepresentation
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{
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Operations.AddLast(node);
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return;
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return node;
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}
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switch (last.Instruction)
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@ -135,12 +135,10 @@ namespace ARMeilleure.IntermediateRepresentation
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case Instruction.Return:
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case Instruction.Tailcall:
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case Instruction.BranchIf:
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Operations.AddBefore(last, node);
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||||
break;
|
||||
return Operations.AddBefore(last, node);
|
||||
|
||||
default:
|
||||
Operations.AddLast(node);
|
||||
break;
|
||||
return Operations.AddLast(node);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue