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Decoders: Add InITBlock argument

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This commit is contained in:
merry 2022-02-10 16:38:54 +00:00
parent ce71f9144e
commit 5c2e780d40
108 changed files with 219 additions and 219 deletions
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6
ARMeilleure/Decoders/Decoder.cs
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@ -315,7 +315,7 @@ namespace ARMeilleure.Decoders
opCode.Instruction.Name == InstName.Und; opCode.Instruction.Name == InstName.Und;
} }
public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode) public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode, bool inITBlock = false)
{ {
int opCode = memory.Read<int>(address); int opCode = memory.Read<int>(address);
@ -341,11 +341,11 @@ namespace ARMeilleure.Decoders
if (makeOp != null) if (makeOp != null)
{ {
return makeOp(inst, address, opCode); return makeOp(inst, address, opCode, inITBlock);
} }
else else
{ {
return new OpCode(inst, address, opCode); return new OpCode(inst, address, opCode, inITBlock);
} }
} }
} }

12
ARMeilleure/Decoders/OpCode.cs
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@ -14,14 +14,16 @@ namespace ARMeilleure.Decoders
public RegisterSize RegisterSize { get; protected set; } public RegisterSize RegisterSize { get; protected set; }
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode); public bool InITBlock { get; }
public OpCode(InstDescriptor inst, ulong address, int opCode) public static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode(inst, address, opCode, inITBlock);
public OpCode(InstDescriptor inst, ulong address, int opCode, bool inITBlock)
{ {
Address = address;
RawOpCode = opCode;
Instruction = inst; Instruction = inst;
Address = address;
RawOpCode = opCode;
InITBlock = inITBlock;
RegisterSize = RegisterSize.Int64; RegisterSize = RegisterSize.Int64;
} }

4
ARMeilleure/Decoders/OpCode32.cs
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@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public Condition Cond { get; protected set; } public Condition Cond { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32(inst, address, opCode, inITBlock);
public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
RegisterSize = RegisterSize.Int32; RegisterSize = RegisterSize.Int32;

4
ARMeilleure/Decoders/OpCode32Alu.cs
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@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public bool SetFlags { get; } public bool SetFlags { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Alu(inst, address, opCode, inITBlock);
public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Alu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = (opCode >> 12) & 0xf; Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf; Rn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluBf.cs
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@ -12,9 +12,9 @@
public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb)); public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb); public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluBf(inst, address, opCode, inITBlock);
public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = (opCode >> 12) & 0xf; Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 0) & 0xf; Rn = (opCode >> 0) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluImm.cs
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@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool IsRotated { get; } public bool IsRotated { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm(inst, address, opCode, inITBlock);
public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int value = (opCode >> 0) & 0xff; int value = (opCode >> 0) & 0xff;
int shift = (opCode >> 8) & 0xf; int shift = (opCode >> 8) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluImm16.cs
View file

@ -4,9 +4,9 @@
{ {
public int Immediate { get; } public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm16(inst, address, opCode, inITBlock);
public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int imm12 = opCode & 0xfff; int imm12 = opCode & 0xfff;
int imm4 = (opCode >> 16) & 0xf; int imm4 = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluMla.cs
View file

@ -12,9 +12,9 @@
public bool R { get; } public bool R { get; }
public bool SetFlags { get; } public bool SetFlags { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluMla(inst, address, opCode, inITBlock);
public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rn = (opCode >> 0) & 0xf; Rn = (opCode >> 0) & 0xf;
Rm = (opCode >> 8) & 0xf; Rm = (opCode >> 8) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluReg.cs
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@ -4,9 +4,9 @@
{ {
public int Rm { get; } public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluReg(inst, address, opCode, inITBlock);
public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 0) & 0xf; Rm = (opCode >> 0) & 0xf;
} }

4
ARMeilleure/Decoders/OpCode32AluRsImm.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; } public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsImm(inst, address, opCode, inITBlock);
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 0) & 0xf; Rm = (opCode >> 0) & 0xf;
Immediate = (opCode >> 7) & 0x1f; Immediate = (opCode >> 7) & 0x1f;

4
ARMeilleure/Decoders/OpCode32AluRsReg.cs
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@ -7,9 +7,9 @@
public ShiftType ShiftType { get; } public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsReg(inst, address, opCode, inITBlock);
public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 0) & 0xf; Rm = (opCode >> 0) & 0xf;
Rs = (opCode >> 8) & 0xf; Rs = (opCode >> 8) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluUmull.cs
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@ -13,9 +13,9 @@
public bool SetFlags { get; } public bool SetFlags { get; }
public DataOp DataOp { get; } public DataOp DataOp { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUmull(inst, address, opCode, inITBlock);
public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
RdLo = (opCode >> 12) & 0xf; RdLo = (opCode >> 12) & 0xf;
RdHi = (opCode >> 16) & 0xf; RdHi = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluUx.cs
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@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public int RotateBits => Rotate * 8; public int RotateBits => Rotate * 8;
public bool Add => Rn != RegisterAlias.Aarch32Pc; public bool Add => Rn != RegisterAlias.Aarch32Pc;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUx(inst, address, opCode, inITBlock);
public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rotate = (opCode >> 10) & 0x3; Rotate = (opCode >> 10) & 0x3;
} }

4
ARMeilleure/Decoders/OpCode32BImm.cs
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@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public long Immediate { get; } public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BImm(inst, address, opCode, inITBlock);
public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32BImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
uint pc = GetPc(); uint pc = GetPc();

4
ARMeilleure/Decoders/OpCode32BReg.cs
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@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Rm { get; } public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BReg(inst, address, opCode, inITBlock);
public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32BReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = opCode & 0xf; Rm = opCode & 0xf;
} }

4
ARMeilleure/Decoders/OpCode32Exception.cs
View file

@ -4,9 +4,9 @@
{ {
public int Id { get; } public int Id { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Exception(inst, address, opCode, inITBlock);
public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Exception(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Id = opCode & 0xFFFFFF; Id = opCode & 0xFFFFFF;
} }

4
ARMeilleure/Decoders/OpCode32Mem.cs
View file

@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders
public bool IsLoad { get; } public bool IsLoad { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Mem(inst, address, opCode, inITBlock);
public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Mem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = (opCode >> 12) & 0xf; Rt = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf; Rn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32MemImm.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCode32MemImm : OpCode32Mem class OpCode32MemImm : OpCode32Mem
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm(inst, address, opCode, inITBlock);
public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Immediate = opCode & 0xfff; Immediate = opCode & 0xfff;
} }

4
ARMeilleure/Decoders/OpCode32MemImm8.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCode32MemImm8 : OpCode32Mem class OpCode32MemImm8 : OpCode32Mem
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm8(inst, address, opCode, inITBlock);
public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int imm4L = (opCode >> 0) & 0xf; int imm4L = (opCode >> 0) & 0xf;
int imm4H = (opCode >> 8) & 0xf; int imm4H = (opCode >> 8) & 0xf;

4
ARMeilleure/Decoders/OpCode32MemLdEx.cs
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@ -4,9 +4,9 @@
{ {
public int Rd { get; } public int Rd { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemLdEx(inst, address, opCode, inITBlock);
public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = opCode & 0xf; Rd = opCode & 0xf;
} }

4
ARMeilleure/Decoders/OpCode32MemMult.cs
View file

@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders
public bool IsLoad { get; } public bool IsLoad { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemMult(inst, address, opCode, inITBlock);
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rn = (opCode >> 16) & 0xf; Rn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32MemReg.cs
View file

@ -4,9 +4,9 @@
{ {
public int Rm { get; } public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemReg(inst, address, opCode, inITBlock);
public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 0) & 0xf; Rm = (opCode >> 0) & 0xf;
} }

4
ARMeilleure/Decoders/OpCode32MemRsImm.cs
View file

@ -5,9 +5,9 @@
public int Rm { get; } public int Rm { get; }
public ShiftType ShiftType { get; } public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemRsImm(inst, address, opCode, inITBlock);
public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 0) & 0xf; Rm = (opCode >> 0) & 0xf;
Immediate = (opCode >> 7) & 0x1f; Immediate = (opCode >> 7) & 0x1f;

4
ARMeilleure/Decoders/OpCode32MemStEx.cs
View file

@ -4,9 +4,9 @@
{ {
public int Rd { get; } public int Rd { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemStEx(inst, address, opCode, inITBlock);
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = (opCode >> 12) & 0xf; Rd = (opCode >> 12) & 0xf;
Rt = (opCode >> 0) & 0xf; Rt = (opCode >> 0) & 0xf;

4
ARMeilleure/Decoders/OpCode32MsrReg.cs
View file

@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders
public bool Banked { get; } public bool Banked { get; }
public int Rn { get; } public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MsrReg(inst, address, opCode, inITBlock);
public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
R = ((opCode >> 22) & 1) != 0; R = ((opCode >> 22) & 1) != 0;
Mask = (opCode >> 16) & 0xf; Mask = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32Sat.cs
View file

@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; } public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat(inst, address, opCode, inITBlock);
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Sat(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rn = (opCode >> 0) & 0xf; Rn = (opCode >> 0) & 0xf;
Imm5 = (opCode >> 7) & 0x1f; Imm5 = (opCode >> 7) & 0x1f;

4
ARMeilleure/Decoders/OpCode32Sat16.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public int Rd { get; } public int Rd { get; }
public int SatImm { get; } public int SatImm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat16(inst, address, opCode, inITBlock);
public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rn = (opCode >> 0) & 0xf; Rn = (opCode >> 0) & 0xf;
Rd = (opCode >> 12) & 0xf; Rd = (opCode >> 12) & 0xf;

4
ARMeilleure/Decoders/OpCode32Simd.cs
View file

@ -7,9 +7,9 @@
public bool F { get; protected set; } public bool F { get; protected set; }
public bool U { get; } public bool U { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Simd(inst, address, opCode, inITBlock);
public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = (opCode >> 20) & 0x3; Size = (opCode >> 20) & 0x3;
Q = ((opCode >> 6) & 0x1) != 0; Q = ((opCode >> 6) & 0x1) != 0;

2
ARMeilleure/Decoders/OpCode32SimdBase.cs
View file

@ -47,6 +47,6 @@ namespace ARMeilleure.Decoders
throw new InvalidOperationException(); throw new InvalidOperationException();
} }
public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
} }
} }

4
ARMeilleure/Decoders/OpCode32SimdBinary.cs
View file

@ -5,9 +5,9 @@
/// </summary> /// </summary>
class OpCode32SimdBinary : OpCode32SimdReg class OpCode32SimdBinary : OpCode32SimdReg
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdBinary(inst, address, opCode, inITBlock);
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = 3; Size = 3;

4
ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdCmpZ : OpCode32Simd class OpCode32SimdCmpZ : OpCode32Simd
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCmpZ(inst, address, opCode, inITBlock);
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = (opCode >> 18) & 0x3; Size = (opCode >> 18) & 0x3;

4
ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdCvtFI : OpCode32SimdS class OpCode32SimdCvtFI : OpCode32SimdS
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCvtFI(inst, address, opCode, inITBlock);
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Opc = (opCode >> 7) & 0x1; Opc = (opCode >> 7) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdDupElem.cs
View file

@ -4,9 +4,9 @@
{ {
public int Index { get; } public int Index { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupElem(inst, address, opCode, inITBlock);
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
var opc = (opCode >> 16) & 0xf; var opc = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdDupGP.cs
View file

@ -7,9 +7,9 @@
public int Rt { get; } public int Rt { get; }
public bool Q { get; } public bool Q { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupGP(inst, address, opCode, inITBlock);
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8. Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8.
if (Size == -1) if (Size == -1)

4
ARMeilleure/Decoders/OpCode32SimdExt.cs
View file

@ -4,9 +4,9 @@
{ {
public int Immediate { get; } public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdExt(inst, address, opCode, inITBlock);
public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Immediate = (opCode >> 8) & 0xf; Immediate = (opCode >> 8) & 0xf;
Size = 0; Size = 0;

4
ARMeilleure/Decoders/OpCode32SimdImm.cs
View file

@ -6,9 +6,9 @@
public long Immediate { get; } public long Immediate { get; }
public int Elems => GetBytesCount() >> Size; public int Elems => GetBytesCount() >> Size;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm(inst, address, opCode, inITBlock);
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Vd = (opCode >> 12) & 0xf; Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10; Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdImm44.cs
View file

@ -7,9 +7,9 @@
public int Size { get; } public int Size { get; }
public int Elems { get; } public int Elems { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm44(inst, address, opCode, inITBlock);
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = (opCode >> 8) & 0x3; Size = (opCode >> 8) & 0x3;

4
ARMeilleure/Decoders/OpCode32SimdLong.cs
View file

@ -4,9 +4,9 @@
{ {
public bool U { get; } public bool U { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdLong(inst, address, opCode, inITBlock);
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int imm3h = (opCode >> 19) & 0x7; int imm3h = (opCode >> 19) & 0x7;

4
ARMeilleure/Decoders/OpCode32SimdMemImm.cs
View file

@ -8,9 +8,9 @@
public bool Add { get; } public bool Add { get; }
public int Immediate { get; } public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemImm(inst, address, opCode, inITBlock);
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Immediate = opCode & 0xff; Immediate = opCode & 0xff;

4
ARMeilleure/Decoders/OpCode32SimdMemMult.cs
View file

@ -12,9 +12,9 @@
public bool DoubleWidth { get; } public bool DoubleWidth { get; }
public bool Add { get; } public bool Add { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemMult(inst, address, opCode, inITBlock);
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rn = (opCode >> 16) & 0xf; Rn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdMemPair.cs
View file

@ -24,9 +24,9 @@ namespace ARMeilleure.Decoders
public int Regs { get; } public int Regs { get; }
public int Increment { get; } public int Increment { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemPair(inst, address, opCode, inITBlock);
public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Vd = (opCode >> 12) & 0xf; Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10; Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
View file

@ -15,9 +15,9 @@ namespace ARMeilleure.Decoders
public bool Replicate { get; } public bool Replicate { get; }
public int Increment { get; } public int Increment { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemSingle(inst, address, opCode, inITBlock);
public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Vd = (opCode >> 12) & 0xf; Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10; Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdMovGp.cs
View file

@ -11,9 +11,9 @@
public int Opc1 { get; } public int Opc1 { get; }
public int Opc2 { get; } public int Opc2 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGp(inst, address, opCode, inITBlock);
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
// Which one is used is instruction dependant. // Which one is used is instruction dependant.
Op = (opCode >> 20) & 0x1; Op = (opCode >> 20) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
View file

@ -9,9 +9,9 @@
public int Rt2 { get; } public int Rt2 { get; }
public int Op { get; } public int Op { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpDouble(inst, address, opCode, inITBlock);
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
// Which one is used is instruction dependant. // Which one is used is instruction dependant.
Op = (opCode >> 20) & 0x1; Op = (opCode >> 20) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
View file

@ -11,9 +11,9 @@
public int Index { get; } public int Index { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpElem(inst, address, opCode, inITBlock);
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Op = (opCode >> 20) & 0x1; Op = (opCode >> 20) & 0x1;
U = ((opCode >> 23) & 1) != 0; U = ((opCode >> 23) & 1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdReg.cs
View file

@ -8,9 +8,9 @@
public int In => GetQuadwordSubindex(Vn) << (3 - Size); public int In => GetQuadwordSubindex(Vn) << (3 - Size);
public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1)); public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdReg(inst, address, opCode, inITBlock);
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf); Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);

4
ARMeilleure/Decoders/OpCode32SimdRegElem.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdRegElem : OpCode32SimdReg class OpCode32SimdRegElem : OpCode32SimdReg
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElem(inst, address, opCode, inITBlock);
public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Q = ((opCode >> 24) & 0x1) != 0; Q = ((opCode >> 24) & 0x1) != 0;
F = ((opCode >> 8) & 0x1) != 0; F = ((opCode >> 8) & 0x1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdRegElemLong : OpCode32SimdRegElem class OpCode32SimdRegElemLong : OpCode32SimdRegElem
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElemLong(inst, address, opCode, inITBlock);
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Q = false; Q = false;
F = false; F = false;

4
ARMeilleure/Decoders/OpCode32SimdRegLong.cs
View file

@ -4,9 +4,9 @@
{ {
public bool Polynomial { get; } public bool Polynomial { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegLong(inst, address, opCode, inITBlock);
public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Q = false; Q = false;
RegisterSize = RegisterSize.Simd64; RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdRegS.cs
View file

@ -4,9 +4,9 @@
{ {
public int Vn { get; } public int Vn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegS(inst, address, opCode, inITBlock);
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
bool single = Size != 3; bool single = Size != 3;
if (single) if (single)

4
ARMeilleure/Decoders/OpCode32SimdRegWide.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdRegWide : OpCode32SimdReg class OpCode32SimdRegWide : OpCode32SimdReg
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegWide(inst, address, opCode, inITBlock);
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Q = false; Q = false;
RegisterSize = RegisterSize.Simd64; RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdRev.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdRev : OpCode32SimdCmpZ class OpCode32SimdRev : OpCode32SimdCmpZ
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRev(inst, address, opCode, inITBlock);
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
if (Opc + Size >= 3) if (Opc + Size >= 3)
{ {

4
ARMeilleure/Decoders/OpCode32SimdS.cs
View file

@ -8,9 +8,9 @@
public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint]. public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
public int Size { get; protected set; } public int Size { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdS(inst, address, opCode, inITBlock);
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Opc = (opCode >> 15) & 0x3; Opc = (opCode >> 15) & 0x3;
Opc2 = (opCode >> 16) & 0x7; Opc2 = (opCode >> 16) & 0x7;

4
ARMeilleure/Decoders/OpCode32SimdSel.cs
View file

@ -4,9 +4,9 @@
{ {
public OpCode32SimdSelMode Cc { get; } public OpCode32SimdSelMode Cc { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSel(inst, address, opCode, inITBlock);
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3); Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
} }

4
ARMeilleure/Decoders/OpCode32SimdShImm.cs
View file

@ -4,9 +4,9 @@
{ {
public int Shift { get; } public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImm(inst, address, opCode, inITBlock);
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int imm6 = (opCode >> 16) & 0x3f; int imm6 = (opCode >> 16) & 0x3f;
int limm6 = ((opCode >> 1) & 0x40) | imm6; int limm6 = ((opCode >> 1) & 0x40) | imm6;

4
ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
View file

@ -4,9 +4,9 @@
{ {
public int Shift { get; } public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmLong(inst, address, opCode, inITBlock);
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Q = false; Q = false;
RegisterSize = RegisterSize.Simd64; RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
View file

@ -2,8 +2,8 @@
{ {
class OpCode32SimdShImmNarrow : OpCode32SimdShImm class OpCode32SimdShImmNarrow : OpCode32SimdShImm
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmNarrow(inst, address, opCode, inITBlock);
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
} }
} }

4
ARMeilleure/Decoders/OpCode32SimdSpecial.cs
View file

@ -5,9 +5,9 @@
public int Rt { get; } public int Rt { get; }
public int Sreg { get; } public int Sreg { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSpecial(inst, address, opCode, inITBlock);
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = (opCode >> 12) & 0xf; Rt = (opCode >> 12) & 0xf;
Sreg = (opCode >> 16) & 0xf; Sreg = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdSqrte.cs
View file

@ -2,9 +2,9 @@
{ {
class OpCode32SimdSqrte : OpCode32Simd class OpCode32SimdSqrte : OpCode32Simd
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSqrte(inst, address, opCode, inITBlock);
public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = (opCode >> 18) & 0x1; Size = (opCode >> 18) & 0x1;
F = ((opCode >> 8) & 0x1) != 0; F = ((opCode >> 8) & 0x1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdTbl.cs
View file

@ -4,9 +4,9 @@
{ {
public int Length { get; } public int Length { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdTbl(inst, address, opCode, inITBlock);
public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Length = (opCode >> 8) & 3; Length = (opCode >> 8) & 3;
Size = 0; Size = 0;

4
ARMeilleure/Decoders/OpCode32System.cs
View file

@ -11,9 +11,9 @@
public int Coproc { get; } public int Coproc { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32System(inst, address, opCode, inITBlock);
public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCode32System(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Opc1 = (opCode >> 21) & 0x7; Opc1 = (opCode >> 21) & 0x7;
CRn = (opCode >> 16) & 0xf; CRn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCodeAdr.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; } public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAdr(inst, address, opCode, inITBlock);
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAdr(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;

4
ARMeilleure/Decoders/OpCodeAlu.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public DataOp DataOp { get; } public DataOp DataOp { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAlu(inst, address, opCode, inITBlock);
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAlu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ARMeilleure/Decoders/OpCodeAluBinary.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Rm { get; } public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluBinary(inst, address, opCode, inITBlock);
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
} }

4
ARMeilleure/Decoders/OpCodeAluImm.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
{ {
public long Immediate { get; } public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluImm(inst, address, opCode, inITBlock);
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
if (DataOp == DataOp.Arithmetic) if (DataOp == DataOp.Arithmetic)
{ {

4
ARMeilleure/Decoders/OpCodeAluRs.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; } public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRs(inst, address, opCode, inITBlock);
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int shift = (opCode >> 10) & 0x3f; int shift = (opCode >> 10) & 0x3f;

4
ARMeilleure/Decoders/OpCodeAluRx.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public IntType IntType { get; } public IntType IntType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRx(inst, address, opCode, inITBlock);
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Shift = (opCode >> 10) & 0x7; Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);

4
ARMeilleure/Decoders/OpCodeBImm.cs
View file

@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders
{ {
public long Immediate { get; protected set; } public long Immediate { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImm(inst, address, opCode, inITBlock);
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } public OpCodeBImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
} }
} }

4
ARMeilleure/Decoders/OpCodeBImmAl.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCodeBImmAl : OpCodeBImm class OpCodeBImmAl : OpCodeBImm
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmAl(inst, address, opCode, inITBlock);
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode); Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
} }

4
ARMeilleure/Decoders/OpCodeBImmCmp.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Rt { get; } public int Rt { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCmp(inst, address, opCode, inITBlock);
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ARMeilleure/Decoders/OpCodeBImmCond.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public Condition Cond { get; } public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCond(inst, address, opCode, inITBlock);
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int o0 = (opCode >> 4) & 1; int o0 = (opCode >> 4) & 1;

4
ARMeilleure/Decoders/OpCodeBImmTest.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int Rt { get; } public int Rt { get; }
public int Bit { get; } public int Bit { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmTest(inst, address, opCode, inITBlock);
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ARMeilleure/Decoders/OpCodeBReg.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Rn { get; } public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBReg(inst, address, opCode, inITBlock);
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int op4 = (opCode >> 0) & 0x1f; int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f; int op2 = (opCode >> 16) & 0x1f;

4
ARMeilleure/Decoders/OpCodeBfm.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Pos { get; } public int Pos { get; }
public int Shift { get; } public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBfm(inst, address, opCode, inITBlock);
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeBfm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
var bm = DecoderHelper.DecodeBitMask(opCode, false); var bm = DecoderHelper.DecodeBitMask(opCode, false);

4
ARMeilleure/Decoders/OpCodeCcmp.cs
View file

@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; } public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmp(inst, address, opCode, inITBlock);
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int o3 = (opCode >> 4) & 1; int o3 = (opCode >> 4) & 1;

4
ARMeilleure/Decoders/OpCodeCcmpImm.cs
View file

@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders
{ {
public long Immediate => RmImm; public long Immediate => RmImm;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpImm(inst, address, opCode, inITBlock);
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
} }
} }

4
ARMeilleure/Decoders/OpCodeCcmpReg.cs
View file

@ -8,8 +8,8 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType => ShiftType.Lsl; public ShiftType ShiftType => ShiftType.Lsl;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpReg(inst, address, opCode, inITBlock);
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
} }
} }

4
ARMeilleure/Decoders/OpCodeCsel.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; } public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCsel(inst, address, opCode, inITBlock);
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeCsel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
Cond = (Condition)((opCode >> 12) & 0xf); Cond = (Condition)((opCode >> 12) & 0xf);

4
ARMeilleure/Decoders/OpCodeException.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Id { get; } public int Id { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeException(inst, address, opCode, inITBlock);
public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeException(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Id = (opCode >> 5) & 0xffff; Id = (opCode >> 5) & 0xffff;
} }

4
ARMeilleure/Decoders/OpCodeMem.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Size { get; protected set; } public int Size { get; protected set; }
public bool Extend64 { get; protected set; } public bool Extend64 { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMem(inst, address, opCode, inITBlock);
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = (opCode >> 0) & 0x1f; Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ARMeilleure/Decoders/OpCodeMemEx.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int Rt2 { get; } public int Rt2 { get; }
public int Rs { get; } public int Rs { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemEx(inst, address, opCode, inITBlock);
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f; Rs = (opCode >> 16) & 0x1f;

4
ARMeilleure/Decoders/OpCodeMemImm.cs
View file

@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders
Unsigned Unsigned
} }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemImm(inst, address, opCode, inITBlock);
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Extend64 = ((opCode >> 22) & 3) == 2; Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0; WBack = ((opCode >> 24) & 1) == 0;

4
ARMeilleure/Decoders/OpCodeMemLit.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool Signed { get; } public bool Signed { get; }
public bool Prefetch { get; } public bool Prefetch { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemLit(inst, address, opCode, inITBlock);
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt = opCode & 0x1f; Rt = opCode & 0x1f;

4
ARMeilleure/Decoders/OpCodeMemPair.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Rt2 { get; } public int Rt2 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemPair(inst, address, opCode, inITBlock);
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rt2 = (opCode >> 10) & 0x1f; Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0; WBack = ((opCode >> 23) & 0x1) != 0;

4
ARMeilleure/Decoders/OpCodeMemReg.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public IntType IntType { get; } public IntType IntType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemReg(inst, address, opCode, inITBlock);
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Shift = ((opCode >> 12) & 0x1) != 0; Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);

4
ARMeilleure/Decoders/OpCodeMov.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public int Bit { get; } public int Bit { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMov(inst, address, opCode, inITBlock);
public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int p1 = (opCode >> 22) & 1; int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1; int sf = (opCode >> 31) & 1;

4
ARMeilleure/Decoders/OpCodeMul.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int Rm { get; } public int Rm { get; }
public int Ra { get; } public int Ra { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMul(inst, address, opCode, inITBlock);
public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeMul(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Ra = (opCode >> 10) & 0x1f; Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;

4
ARMeilleure/Decoders/OpCodeSimd.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Opc { get; } public int Opc { get; }
public int Size { get; protected set; } public int Size { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimd(inst, address, opCode, inITBlock);
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;

4
ARMeilleure/Decoders/OpCodeSimdCvt.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int FBits { get; } public int FBits { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdCvt(inst, address, opCode, inITBlock);
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int scale = (opCode >> 10) & 0x3f; int scale = (opCode >> 10) & 0x3f;
int sf = (opCode >> 31) & 0x1; int sf = (opCode >> 31) & 0x1;

4
ARMeilleure/Decoders/OpCodeSimdExt.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{ {
public int Imm4 { get; } public int Imm4 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdExt(inst, address, opCode, inITBlock);
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Imm4 = (opCode >> 11) & 0xf; Imm4 = (opCode >> 11) & 0xf;
} }

4
ARMeilleure/Decoders/OpCodeSimdFcond.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; } public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFcond(inst, address, opCode, inITBlock);
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Nzcv = (opCode >> 0) & 0xf; Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf); Cond = (Condition)((opCode >> 12) & 0xf);

4
ARMeilleure/Decoders/OpCodeSimdFmov.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; } public long Immediate { get; }
public int Size { get; } public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFmov(inst, address, opCode, inITBlock);
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int type = (opCode >> 22) & 0x3; int type = (opCode >> 22) & 0x3;

4
ARMeilleure/Decoders/OpCodeSimdImm.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; } public long Immediate { get; }
public int Size { get; } public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdImm(inst, address, opCode, inITBlock);
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Rd = opCode & 0x1f; Rd = opCode & 0x1f;

4
ARMeilleure/Decoders/OpCodeSimdIns.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int SrcIndex { get; } public int SrcIndex { get; }
public int DstIndex { get; } public int DstIndex { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdIns(inst, address, opCode, inITBlock);
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int imm4 = (opCode >> 11) & 0xf; int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f; int imm5 = (opCode >> 16) & 0x1f;

4
ARMeilleure/Decoders/OpCodeSimdMemImm.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemImm(inst, address, opCode, inITBlock);
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

4
ARMeilleure/Decoders/OpCodeSimdMemLit.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool Signed => false; public bool Signed => false;
public bool Prefetch => false; public bool Prefetch => false;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemLit(inst, address, opCode, inITBlock);
public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int opc = (opCode >> 30) & 3; int opc = (opCode >> 30) & 3;

4
ARMeilleure/Decoders/OpCodeSimdMemMs.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Elems { get; } public int Elems { get; }
public bool WBack { get; } public bool WBack { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemMs(inst, address, opCode, inITBlock);
public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
switch ((opCode >> 12) & 0xf) switch ((opCode >> 12) & 0xf)
{ {

4
ARMeilleure/Decoders/OpCodeSimdMemPair.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemPair(inst, address, opCode, inITBlock);
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size = ((opCode >> 30) & 3) + 2; Size = ((opCode >> 30) & 3) + 2;

4
ARMeilleure/Decoders/OpCodeSimdMemReg.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{ {
class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
{ {
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemReg(inst, address, opCode, inITBlock);
public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
Size |= (opCode >> 21) & 4; Size |= (opCode >> 21) & 4;

4
ARMeilleure/Decoders/OpCodeSimdMemSs.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public bool Replicate { get; } public bool Replicate { get; }
public bool WBack { get; } public bool WBack { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode); public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemSs(inst, address, opCode, inITBlock);
public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{ {
int size = (opCode >> 10) & 3; int size = (opCode >> 10) & 3;
int s = (opCode >> 12) & 1; int s = (opCode >> 12) & 1;

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