From 65c20a5360190eb7edb5289aa0cde52d3bd53c30 Mon Sep 17 00:00:00 2001 From: TSR Berry <20988865+TSRBerry@users.noreply.github.com> Date: Sat, 8 Jul 2023 20:36:40 +0200 Subject: [PATCH] Disable all CPU tests --- src/Ryujinx.Tests/Cpu/CpuTestAlu.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestBf32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestBfm.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestCsel.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestMisc.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestMov.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestMul.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestMul32.cs | 6 +-- src/Ryujinx.Tests/Cpu/CpuTestSimd.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs | 7 +-- src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto32.cs | 7 +-- src/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 47 ++----------------- src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs | 7 ++- src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestSystem.cs | 8 ++-- src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs | 8 +++- src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs | 8 +++- src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs | 9 ++-- src/Ryujinx.Tests/Cpu/CpuTestThumb.cs | 9 ++-- 46 files changed, 152 insertions(+), 223 deletions(-) diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 9c1876c8c..34756afea 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -1,11 +1,10 @@ -#define Alu +// #define Alu -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Alu")] + [Collection("Alu")] public sealed class CpuTestAlu : CpuTest { #if Alu diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs index 41365c624..d11ec4813 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAlu32.cs @@ -1,10 +1,10 @@ -#define Alu32 +// #define Alu32 -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Alu32")] + [Collection("Alu32")] public sealed class CpuTestAlu32 : CpuTest32 { #if Alu32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs index 1e48086b2..f40c621e2 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary.cs @@ -1,11 +1,10 @@ -#define AluBinary +// #define AluBinary -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluBinary")] + [Collection("AluBinary")] public sealed class CpuTestAluBinary : CpuTest { #if AluBinary diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs index 43d054368..9c2700fa3 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluBinary32.cs @@ -1,12 +1,11 @@ -#define AluBinary32 +// #define AluBinary32 -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluBinary32")] + [Collection("AluBinary32")] public sealed class CpuTestAluBinary32 : CpuTest32 { #if AluBinary32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs index 5c00cbc45..f77eab171 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs @@ -1,10 +1,10 @@ -#define AluImm +// #define AluImm -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluImm")] + [Collection("AluImm")] public sealed class CpuTestAluImm : CpuTest { #if AluImm diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs index eeeef085c..2708ba3ea 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs @@ -1,10 +1,10 @@ -#define AluRs32 +// #define AluRs32 -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluImm32")] + [Collection("AluImm32")] public sealed class CpuTestAluImm32 : CpuTest32 { #if AluRs32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs index f63360c21..e8e60974e 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -1,10 +1,10 @@ -#define AluRs +// #define AluRs -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluRs")] + [Collection("AluRs")] public sealed class CpuTestAluRs : CpuTest { #if AluRs diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs index 0e71b1839..0d70ef890 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRs32.cs @@ -1,10 +1,10 @@ -#define AluRs32 +// #define AluRs32 -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluRs32")] + [Collection("AluRs32")] public sealed class CpuTestAluRs32 : CpuTest32 { #if AluRs32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs index 9897bdba3..03c1a2f4f 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestAluRx.cs @@ -1,10 +1,10 @@ -#define AluRx +// #define AluRx -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("AluRx")] + [Collection("AluRx")] public sealed class CpuTestAluRx : CpuTest { #if AluRx diff --git a/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs b/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs index 197171b8d..9579d73e7 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestBf32.cs @@ -1,11 +1,10 @@ -#define Bf32 +// #define Bf32 -using NUnit.Framework; -using System; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Bf32")] + [Collection("Bf32")] public sealed class CpuTestBf32 : CpuTest32 { #if Bf32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs index ed911d058..2e7b6ddc1 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -1,10 +1,10 @@ -#define Bfm +// #define Bfm -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Bfm")] + [Collection("Bfm")] public sealed class CpuTestBfm : CpuTest { #if Bfm diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs index 1bad4c87d..e46cb9d1a 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs @@ -1,10 +1,10 @@ -#define CcmpImm +// #define CcmpImm -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("CcmpImm")] + [Collection("CcmpImm")] public sealed class CpuTestCcmpImm : CpuTest { #if CcmpImm diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs index 27fe24118..cff338881 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs @@ -1,10 +1,10 @@ -#define CcmpReg +// #define CcmpReg -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("CcmpReg")] + [Collection("CcmpReg")] public sealed class CpuTestCcmpReg : CpuTest { #if CcmpReg diff --git a/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs index 86b1f092a..9ed2fd5d0 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestCsel.cs @@ -1,10 +1,10 @@ -#define Csel +// #define Csel -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Csel")] + [Collection("Csel")] public sealed class CpuTestCsel : CpuTest { #if Csel diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs index aab009766..dc058ab91 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs @@ -1,13 +1,10 @@ -#define Misc +// #define Misc -using ARMeilleure.State; -using NUnit.Framework; -using System; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Misc")] + [Collection("Misc")] public sealed class CpuTestMisc : CpuTest { #if Misc diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs index e984a1584..23c3791b7 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc32.cs @@ -1,12 +1,10 @@ -#define Misc32 +// #define Misc32 -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Misc32")] + [Collection("Misc32")] public sealed class CpuTestMisc32 : CpuTest32 { #if Misc32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMov.cs b/src/Ryujinx.Tests/Cpu/CpuTestMov.cs index c8ee3857e..225b8994d 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMov.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMov.cs @@ -1,10 +1,10 @@ -#define Mov +// #define Mov -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Mov")] + [Collection("Mov")] public sealed class CpuTestMov : CpuTest { #if Mov diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMul.cs b/src/Ryujinx.Tests/Cpu/CpuTestMul.cs index 164ed9773..ba5a37c5a 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMul.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMul.cs @@ -1,10 +1,10 @@ -#define Mul +// #define Mul -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Mul")] + [Collection("Mul")] public sealed class CpuTestMul : CpuTest { #if Mul diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs b/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs index 7e4b4c062..1b731192e 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMul32.cs @@ -1,10 +1,10 @@ -#define Mul32 +// #define Mul32 -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Mul32")] + [Collection("Mul32")] public sealed class CpuTestMul32 : CpuTest32 { #if Mul32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs index eb763618d..bce7225e0 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -1,13 +1,10 @@ -#define Simd +// #define Simd -using ARMeilleure.State; -using NUnit.Framework; -using System; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Simd")] + [Collection("Simd")] public sealed class CpuTestSimd : CpuTest { #if Simd diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs index 6087a6834..dc0059205 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs @@ -1,12 +1,10 @@ -#define Simd32 +// #define Simd32 -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Simd32")] + [Collection("Simd32")] public sealed class CpuTestSimd32 : CpuTest32 { #if Simd32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index 80612f1c7..76b709c5d 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -1,12 +1,12 @@ +// #define SimdCrypto // https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf -using ARMeilleure.State; -using NUnit.Framework; - namespace Ryujinx.Tests.Cpu { public class CpuTestSimdCrypto : CpuTest { +#if SimdCrypto + [Test, Description("AESD .16B, .16B")] public void Aesd_V([Values(0u)] uint rd, [Values(1u)] uint rn, @@ -140,5 +140,6 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } +#endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto32.cs index 60076da47..f1c74112b 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCrypto32.cs @@ -1,12 +1,12 @@ +// #define SimdCrypto32 // https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf -using ARMeilleure.State; -using NUnit.Framework; - namespace Ryujinx.Tests.Cpu { public class CpuTestSimdCrypto32 : CpuTest32 { +#if SimdCrypto32 + [Test, Description("AESD.8 , ")] public void Aesd_V([Values(0u)] uint rd, [Values(2u)] uint rm, @@ -150,5 +150,6 @@ namespace Ryujinx.Tests.Cpu // Unicorn does not yet support crypto instructions in A32. // CompareAgainstUnicorn(); } +#endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs index 007c0f8cb..06d23f73f 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs @@ -1,13 +1,10 @@ -#define SimdCvt +// #define SimdCvt -using ARMeilleure.State; -using NUnit.Framework; -using System; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdCvt")] + [Collection("SimdCvt")] public sealed class CpuTestSimdCvt : CpuTest { #if SimdCvt diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs index ba201a480..9deb3100d 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs @@ -1,13 +1,10 @@ -#define SimdCvt32 +// #define SimdCvt32 -using ARMeilleure.State; -using NUnit.Framework; -using System; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdCvt32")] + [Collection("SimdCvt32")] public sealed class CpuTestSimdCvt32 : CpuTest32 { #if SimdCvt32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs index 59bc4cb7e..a52334f78 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdExt.cs @@ -1,11 +1,10 @@ -#define SimdExt +// #define SimdExt -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdExt")] + [Collection("SimdExt")] public sealed class CpuTestSimdExt : CpuTest { #if SimdExt diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs index d6d12b278..e4a7e128e 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdFcond.cs @@ -1,12 +1,10 @@ -#define SimdFcond +// #define SimdFcond -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdFcond")] + [Collection("SimdFcond")] public sealed class CpuTestSimdFcond : CpuTest { #if SimdFcond diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs index 0c2582695..2cfddaaaf 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs @@ -1,11 +1,10 @@ -#define SimdFmov +// #define SimdFmov -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdFmov")] + [Collection("SimdFmov")] public sealed class CpuTestSimdFmov : CpuTest { #if SimdFmov diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs index 27e3b41a0..dcfba08fb 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs @@ -1,12 +1,10 @@ -#define SimdImm +// #define SimdImm -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdImm")] + [Collection("SimdImm")] public sealed class CpuTestSimdImm : CpuTest { #if SimdImm diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs index 83dc07707..f36241780 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs @@ -1,11 +1,10 @@ -#define SimdIns +// #define SimdIns -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdIns")] + [Collection("SimdIns")] public sealed class CpuTestSimdIns : CpuTest { #if SimdIns diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs index 819d9300b..c0ccc2e3c 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs @@ -1,11 +1,10 @@ -#define SimdLogical32 +// #define SimdLogical32 -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdLogical32")] + [Collection("SimdLogical32")] public sealed class CpuTestSimdLogical32 : CpuTest32 { #if SimdLogical32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs index d59e963b5..3de06b477 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs @@ -1,13 +1,10 @@ -#define SimdMemory32 +// #define SimdMemory32 -using ARMeilleure.State; -using NUnit.Framework; -using Ryujinx.Memory; -using System; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdMemory32")] + [Collection("SimdMemory32")] public sealed class CpuTestSimdMemory32 : CpuTest32 { private static readonly uint _testOffset = DataBaseAddress + 0x500; diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs index 85f77fff1..b6cf0b86f 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs @@ -1,11 +1,10 @@ -#define SimdMov32 +// #define SimdMov32 -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdMov32")] + [Collection("SimdMov32")] public sealed class CpuTestSimdMov32 : CpuTest32 { #if SimdMov32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index 207f76089..a02d400e8 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -1,12 +1,10 @@ -#define SimdReg +// #define SimdReg -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdReg")] + [Collection("SimdReg")] public sealed class CpuTestSimdReg : CpuTest { #if SimdReg diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 38e08bf89..8bcd143dd 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -1,13 +1,10 @@ -#define SimdReg32 +// #define SimdReg32 -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; -using System.Runtime.InteropServices; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdReg32")] + [Collection("SimdReg32")] public sealed class CpuTestSimdReg32 : CpuTest32 { #if SimdReg32 @@ -908,44 +905,6 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - - [Test, Pairwise] - public void Vp_Add_Long_Accumulate([Values(0u, 2u, 4u, 8u)] uint rd, - [Values(0u, 2u, 4u, 8u)] uint rm, - [Values(0u, 1u, 2u)] uint size, - [Random(RndCnt)] ulong z, - [Random(RndCnt)] ulong a, - [Random(RndCnt)] ulong b, - [Values] bool q, - [Values] bool unsigned) - { - uint opcode = 0xF3B00600; // VPADAL.S8 D0, Q0 - - if (q) - { - opcode |= 1 << 6; - rm <<= 1; - rd <<= 1; - } - - if (unsigned) - { - opcode |= 1 << 7; - } - - opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); - opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); - - opcode |= size << 18; - - V128 v0 = MakeVectorE0E1(z, z); - V128 v1 = MakeVectorE0E1(a, z); - V128 v2 = MakeVectorE0E1(b, z); - - SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); - - CompareAgainstUnicorn(); - } #endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs index 23c6961f9..033c03fcc 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs @@ -1,11 +1,10 @@ -#define SimdRegElem +// #define SimdRegElem -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdRegElem")] + [Collection("SimdRegElem")] public sealed class CpuTestSimdRegElem : CpuTest { #if SimdRegElem diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem32.cs index 49aab0513..cbe52d1c8 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElem32.cs @@ -1,11 +1,10 @@ -#define SimdRegElem32 +// #define SimdRegElem32 -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdRegElem32")] + [Collection("SimdRegElem32")] public sealed class CpuTestSimdRegElem32 : CpuTest32 { #if SimdRegElem32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs index 1b670da76..869db8869 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdRegElemF.cs @@ -1,12 +1,10 @@ -#define SimdRegElemF +// #define SimdRegElemF -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdRegElemF")] + [Collection("SimdRegElemF")] public sealed class CpuTestSimdRegElemF : CpuTest { #if SimdRegElemF diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs index 9816bc2cc..dbc018f9f 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs @@ -1,13 +1,10 @@ -#define SimdShImm +// #define SimdShImm -using ARMeilleure.State; -using NUnit.Framework; -using System; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdShImm")] + [Collection("SimdShImm")] public sealed class CpuTestSimdShImm : CpuTest { #if SimdShImm diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs index 39b50867f..4d3c3f429 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs @@ -1,11 +1,10 @@ -#define SimdShImm32 +// #define SimdShImm32 -using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdShImm32")] + [Collection("SimdShImm32")] public sealed class CpuTestSimdShImm32 : CpuTest32 { #if SimdShImm32 diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs index 78af6fe4e..02cb49ce8 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs @@ -1,12 +1,10 @@ -#define SimdTbl +// #define SimdTbl -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("SimdTbl")] + [Collection("SimdTbl")] public sealed class CpuTestSimdTbl : CpuTest { #if SimdTbl diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSystem.cs b/src/Ryujinx.Tests/Cpu/CpuTestSystem.cs index 6c498ef0f..a975bbc83 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSystem.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSystem.cs @@ -1,12 +1,10 @@ -#define System +// #define System -using ARMeilleure.State; -using NUnit.Framework; -using System.Collections.Generic; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("System")] + [Collection("System")] public sealed class CpuTestSystem : CpuTest { #if System diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs index a0d46692c..304b4d73c 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs @@ -1,10 +1,13 @@ -using NUnit.Framework; +// #define T32Alu + +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("T32Alu")] + [Collection("T32Alu")] public sealed class CpuTestT32Alu : CpuTest32 { +#if T32Alu [Test] public void TestT32AluRsImm([ValueSource(nameof(RsImmTestCases))] PrecomputedThumbTestCase test) { @@ -1010,5 +1013,6 @@ namespace Ryujinx.Tests.Cpu FinalRegs = new uint[] { 0x2bb00694, 0x1c56a4c0, 0xc5cc4a3e, 0xc627c1ab, 0xe0cc0e5c, 0x1f3d71a4, 0x897d57b8, 0x0d4a7208, 0x433b7b88, 0xaaf24fd6, 0x2438f5f8, 0x9875e64a, 0xda475f22, 0x66d5e2e7, 0x00000001, 0x700001f0 }, }, }; +#endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs index 01159afc6..4b291b083 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs @@ -1,11 +1,14 @@ +// #define T32Flow + using ARMeilleure.State; -using NUnit.Framework; +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("T32Flow")] + [Collection("T32Flow")] public sealed class CpuTestT32Flow : CpuTest32 { +#if T32Flow [Test] public void TestT32B1() { @@ -163,5 +166,6 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x7)); Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false)); } +#endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs index 94ccb950c..97efbe322 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs @@ -1,11 +1,13 @@ -using NUnit.Framework; -using System; +// #define T32Mem + +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("T32Mem")] + [Collection("T32Mem")] public sealed class CpuTestT32Mem : CpuTest32 { +#if T32Mem [Test] public void TestT32MemImm([ValueSource(nameof(ImmTestCases))] PrecomputedMemoryThumbTestCase test) { @@ -517,5 +519,6 @@ namespace Ryujinx.Tests.Cpu MemoryDelta = Array.Empty<(ulong Address, ushort Value)>(), }, }; +#endif } } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestThumb.cs b/src/Ryujinx.Tests/Cpu/CpuTestThumb.cs index 6111e53fa..2cda2a8d5 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestThumb.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestThumb.cs @@ -1,11 +1,13 @@ -using ARMeilleure.State; -using NUnit.Framework; +// #define Thumb + +using Xunit; namespace Ryujinx.Tests.Cpu { - [Category("Thumb")] + [Collection("Thumb")] public sealed class CpuTestThumb : CpuTest32 { +#if Thumb private const int RndCnt = 2; public static uint RotateRight(uint value, int count) @@ -880,5 +882,6 @@ namespace Ryujinx.Tests.Cpu FinalRegs = new uint[] { 0x000019d4, 0x00000000, 0x00001828, 0x7d000000, 0x977f681b, 0x0000182e, 0x00007d12, 0x00000067, 0x77b1c835, 0x00004100, 0x000010c8, 0x0000000e, 0x79708dab, 0x977f655b, 0x00000000, 0x200001d0 }, }, }; +#endif } }