mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2024-11-15 01:25:25 +00:00
Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdCrypto.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
43c4e7c78d
commit
68300368d7
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@ -374,10 +374,12 @@ namespace ChocolArm64
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SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V, typeof(AOpCodeSimdReg));
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SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
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SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg));
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SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
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SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
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SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
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SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg));
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SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm));
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SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg));
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SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V, typeof(AOpCodeSimdReg));
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@ -407,6 +409,7 @@ namespace ChocolArm64
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SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
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SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
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SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
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SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
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@ -449,6 +452,7 @@ namespace ChocolArm64
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SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd));
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SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V, typeof(AOpCodeSimdReg));
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SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V, typeof(AOpCodeSimdReg));
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@ -461,6 +465,7 @@ namespace ChocolArm64
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SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg));
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SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
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SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
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SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg));
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SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
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SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
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SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
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@ -1042,6 +1042,28 @@ namespace ChocolArm64.Instruction
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Shadd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr);
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});
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}
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public static void Shsub_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr);
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});
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}
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public static void Smax_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(long), typeof(long) };
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@ -1181,6 +1203,20 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingNarrowOpSxZx(Context, () => { });
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}
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public static void Srhadd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpSx(Context, () =>
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{
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr);
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});
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}
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public static void Ssubw_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
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@ -1303,28 +1339,20 @@ namespace ChocolArm64.Instruction
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{
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Context.Emit(OpCodes.Add);
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Context.EmitLdc_I4(1);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Umin_V(AILEmitterCtx Context)
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public static void Uhsub_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Sub);
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Uminp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Umax_V(AILEmitterCtx Context)
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@ -1345,6 +1373,24 @@ namespace ChocolArm64.Instruction
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EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Umin_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorBinaryOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Uminp_V(AILEmitterCtx Context)
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{
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Type[] Types = new Type[] { typeof(ulong), typeof(ulong) };
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MethodInfo MthdInfo = typeof(Math).GetMethod(nameof(Math.Min), Types);
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EmitVectorPairwiseOpZx(Context, () => Context.EmitCall(MthdInfo));
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}
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public static void Umull_V(AILEmitterCtx Context)
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{
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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@ -1380,6 +1426,20 @@ namespace ChocolArm64.Instruction
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EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
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}
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public static void Urhadd_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpZx(Context, () =>
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{
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Add);
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Context.Emit(OpCodes.Ldc_I4_1);
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Context.Emit(OpCodes.Shr_Un);
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});
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}
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public static void Usqadd_S(AILEmitterCtx Context)
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{
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EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
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@ -119,22 +119,42 @@ namespace Ryujinx.Tests.Cpu
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protected static Vector128<float> MakeVectorE0(double E0)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(E0)));
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}
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protected static Vector128<float> MakeVectorE0E1(double E0, double E1)
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{
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return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1),
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BitConverter.DoubleToInt64Bits(E0)));
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<long, float>(
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Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), BitConverter.DoubleToInt64Bits(E0)));
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}
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protected static Vector128<float> MakeVectorE1(double E1)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<long, float>(Sse2.SetVector128(BitConverter.DoubleToInt64Bits(E1), 0));
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}
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protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
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{
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if (!Sse41.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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long Value = Sse41.Extract(Sse.StaticCast<float, long>(Vector), Index);
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return BitConverter.Int64BitsToDouble(Value);
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@ -142,26 +162,51 @@ namespace Ryujinx.Tests.Cpu
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protected static Vector128<float> MakeVectorE0(ulong E0)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, E0));
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}
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protected static Vector128<float> MakeVectorE0E1(ulong E0, ulong E1)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, E0));
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}
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protected static Vector128<float> MakeVectorE1(ulong E1)
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{
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if (!Sse2.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(E1, 0));
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}
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protected static ulong GetVectorE0(Vector128<float> Vector)
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{
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if (!Sse41.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)0);
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}
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protected static ulong GetVectorE1(Vector128<float> Vector)
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{
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if (!Sse41.IsSupported)
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{
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throw new PlatformNotSupportedException();
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}
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), (byte)1);
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}
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}
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@ -1245,11 +1245,11 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Explicit, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] // 1250 tests.
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[Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")]
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public void Sha256su0_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Random(5)] ulong Z0, [Random(5)] ulong Z1,
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[Random(5)] ulong A0, [Random(5)] ulong A1)
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[Random(RndCnt * 2)] ulong Z0, [Random(RndCnt * 2)] ulong Z1,
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[Random(RndCnt * 2)] ulong A0, [Random(RndCnt * 2)] ulong A1)
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{
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uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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@ -10,7 +10,7 @@ namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestSimdCrypto : CpuTest
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{
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[Test, Explicit, Description("AESD <Vd>.16B, <Vn>.16B")]
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[Test, Description("AESD <Vd>.16B, <Vn>.16B")]
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public void Aesd_V([Values(0u)] uint Rd,
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[Values(1u)] uint Rn,
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[Values(0x7B5B546573745665ul)] ulong ValueH,
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@ -39,7 +39,7 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Explicit, Description("AESE <Vd>.16B, <Vn>.16B")]
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[Test, Description("AESE <Vd>.16B, <Vn>.16B")]
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public void Aese_V([Values(0u)] uint Rd,
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[Values(1u)] uint Rn,
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[Values(0x7B5B546573745665ul)] ulong ValueH,
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@ -68,7 +68,7 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Explicit, Description("AESIMC <Vd>.16B, <Vn>.16B")]
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[Test, Description("AESIMC <Vd>.16B, <Vn>.16B")]
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public void Aesimc_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(0x8DCAB9DC035006BCul)] ulong ValueH,
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@ -100,7 +100,7 @@ namespace Ryujinx.Tests.Cpu
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}
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}
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[Test, Explicit, Description("AESMC <Vd>.16B, <Vn>.16B")]
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[Test, Description("AESMC <Vd>.16B, <Vn>.16B")]
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public void Aesmc_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(0x627A6F6644B109C8ul)] ulong ValueH,
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@ -1690,8 +1690,8 @@ namespace Ryujinx.Tests.Cpu
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
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{
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uint Opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B
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@ -1721,8 +1721,8 @@ namespace Ryujinx.Tests.Cpu
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
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[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
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{
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uint Opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B
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@ -1747,13 +1747,13 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Explicit, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
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[Test, Pairwise, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")]
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public void Sha256h_V([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[Random(3)] ulong Z0, [Random(3)] ulong Z1,
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[Random(3)] ulong A0, [Random(3)] ulong A1,
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[Random(3)] ulong B0, [Random(3)] ulong B1)
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[Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
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[Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
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[Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
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{
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uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S
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Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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@ -1784,13 +1784,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
|
||||
[Test, Pairwise, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")]
|
||||
public void Sha256h2_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[Random(3)] ulong Z0, [Random(3)] ulong Z1,
|
||||
[Random(3)] ulong A0, [Random(3)] ulong A1,
|
||||
[Random(3)] ulong B0, [Random(3)] ulong B1)
|
||||
[Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
|
||||
[Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
|
||||
[Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
|
@ -1821,13 +1821,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Explicit, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")] // 2916 tests.
|
||||
[Test, Pairwise, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")]
|
||||
public void Sha256su1_V([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[Random(3)] ulong Z0, [Random(3)] ulong Z1,
|
||||
[Random(3)] ulong A0, [Random(3)] ulong A1,
|
||||
[Random(3)] ulong B0, [Random(3)] ulong B1)
|
||||
[Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
|
||||
[Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
|
||||
[Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
|
||||
{
|
||||
uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
|
|
@ -1858,6 +1858,130 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Shadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E200400; // SHADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Shadd_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x4E200400; // SHADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Shsub_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E202400; // SHSUB V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Shsub_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x4E202400; // SHSUB V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
@ -2278,13 +2402,75 @@ namespace Ryujinx.Tests.Cpu
|
|||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Srhadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E201400; // SRHADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Srhadd_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x4E201400; // SRHADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B
|
||||
|
|
@ -2314,8 +2500,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B
|
||||
|
|
@ -2870,8 +3056,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B
|
||||
|
|
@ -2901,8 +3087,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B
|
||||
|
|
@ -2927,6 +3113,130 @@ namespace Ryujinx.Tests.Cpu
|
|||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uhadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E200400; // UHADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uhadd_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x6E200400; // UHADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uhsub_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E202400; // UHSUB V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uhsub_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x6E202400; // UHSUB V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
|
||||
public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
|
@ -3137,13 +3447,75 @@ namespace Ryujinx.Tests.Cpu
|
|||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Urhadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E201400; // URHADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Urhadd_V_16B_8H_4S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
|
||||
{
|
||||
uint Opcode = 0x6E201400; // URHADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
|
||||
{
|
||||
uint Opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B
|
||||
|
|
@ -3173,8 +3545,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
|
||||
{
|
||||
uint Opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B
|
||||
|
|
|
|||
|
|
@ -5251,6 +5251,88 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// shadd_advsimd.html
|
||||
public static void Shadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
Elem(result, e, esize, sum.SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// shsub_advsimd.html
|
||||
public static void Shsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
Elem(result, e, esize, diff.SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqadd_advsimd.html#SQADD_asisdsame_only
|
||||
public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -5651,6 +5733,44 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// srhadd_advsimd.html
|
||||
public static void Srhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// ssubw_advsimd.html
|
||||
public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -6143,6 +6263,88 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// uhadd_advsimd.html
|
||||
public static void Uhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
Elem(result, e, esize, sum.SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uhsub_advsimd.html
|
||||
public static void Uhsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
Elem(result, e, esize, diff.SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqadd_advsimd.html#UQADD_asisdsame_only
|
||||
public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
@ -6339,6 +6541,44 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// urhadd_advsimd.html
|
||||
public static void Urhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size == '11' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1));
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// usubw_advsimd.html
|
||||
public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue