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John Clemis 2018-08-08 20:58:42 -05:00 committed by GitHub
commit 728c9f8008
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50 changed files with 3599 additions and 572 deletions
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22
ChocolArm64/AOpCodeTable.cs
View file

@ -267,11 +267,13 @@ namespace ChocolArm64
SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg));
SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg));
SetA64("0x0011100x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx011010xxxxxxxxxx", AInstEmit.Fmaxnm_S, typeof(AOpCodeSimdReg));
SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", AInstEmit.Fmaxnm_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg));
SetA64("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg));
SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg));
SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", AInstEmit.Fminnm_V, typeof(AOpCodeSimdReg));
SetA64("010111111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Se, typeof(AOpCodeSimdRegElemF));
SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg));
SetA64("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF));
@ -374,7 +376,15 @@ namespace ChocolArm64
SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Smlsl_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg));
SetA64("01011110xx100000011110xxxxxxxxxx", AInstEmit.Sqabs_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd));
SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg));
SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd));
SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm));
SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg));
SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg));
SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd));
SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd));
SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
@ -402,6 +412,8 @@ namespace ChocolArm64
SetA64("01111110111xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Subhn_V, typeof(AOpCodeSimdReg));
SetA64("01011110xx100000001110xxxxxxxxxx", AInstEmit.Suqadd_S, typeof(AOpCodeSimd));
SetA64("0>001110<<100000001110xxxxxxxxxx", AInstEmit.Suqadd_V, typeof(AOpCodeSimd));
SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl));
SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg));
SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg));
@ -423,6 +435,10 @@ namespace ChocolArm64
SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Uminp_V, typeof(AOpCodeSimdReg));
SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns));
SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg));
SetA64("01111110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_V, typeof(AOpCodeSimdReg));
SetA64("01111110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_S, typeof(AOpCodeSimdReg));
SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg));
SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
@ -430,6 +446,8 @@ namespace ChocolArm64
SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd));
SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Usubw_V, typeof(AOpCodeSimdReg));

196
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -335,98 +335,66 @@ namespace ChocolArm64.Instruction
public static void Fmax_S(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
EmitScalarBinaryOpF(Context, () =>
{
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MaxF));
}
else if (Op.Size == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Max));
}
else
{
throw new InvalidOperationException();
}
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.Max));
});
}
public static void Fmax_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
EmitVectorBinaryOpF(Context, () =>
{
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MaxF));
}
else if (Op.Size == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Max));
}
else
{
throw new InvalidOperationException();
}
});
}
public static void Fmin_S(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
EmitScalarBinaryOpF(Context, () =>
{
if (Op.Size == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MinF));
}
else if (Op.Size == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Min));
}
else
{
throw new InvalidOperationException();
}
});
}
public static void Fmin_V(AILEmitterCtx Context)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int SizeF = Op.Size & 1;
EmitVectorBinaryOpF(Context, () =>
{
if (SizeF == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MinF));
}
else if (SizeF == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Min));
}
else
{
throw new InvalidOperationException();
}
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.Max));
});
}
public static void Fmaxnm_S(AILEmitterCtx Context)
{
Fmax_S(Context);
EmitScalarBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.MaxNum));
});
}
public static void Fmaxnm_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.MaxNum));
});
}
public static void Fmin_S(AILEmitterCtx Context)
{
EmitScalarBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.Min));
});
}
public static void Fmin_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.Min));
});
}
public static void Fminnm_S(AILEmitterCtx Context)
{
Fmin_S(Context);
EmitScalarBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.MinNum));
});
}
public static void Fminnm_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpF(Context, () =>
{
EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.MinNum));
});
}
public static void Fmla_Se(AILEmitterCtx Context)
@ -1052,6 +1020,46 @@ namespace ChocolArm64.Instruction
EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Mul));
}
public static void Sqabs_S(AILEmitterCtx Context)
{
EmitScalarSaturatingUnaryOpSx(Context, () => EmitAbs(Context));
}
public static void Sqabs_V(AILEmitterCtx Context)
{
EmitVectorSaturatingUnaryOpSx(Context, () => EmitAbs(Context));
}
public static void Sqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
}
public static void Sqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add);
}
public static void Sqneg_S(AILEmitterCtx Context)
{
EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Sqneg_V(AILEmitterCtx Context)
{
EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg));
}
public static void Sqsub_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
}
public static void Sqsub_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Sub);
}
public static void Sqxtn_S(AILEmitterCtx Context)
{
EmitScalarSaturatingNarrowOpSxSx(Context, () => { });
@ -1099,6 +1107,16 @@ namespace ChocolArm64.Instruction
EmitHighNarrow(Context, () => Context.Emit(OpCodes.Sub), Round: false);
}
public static void Suqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Accumulate);
}
public static void Suqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Accumulate);
}
public static void Uaba_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpZx(Context, () =>
@ -1221,6 +1239,26 @@ namespace ChocolArm64.Instruction
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
}
public static void Uqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Add);
}
public static void Uqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Add);
}
public static void Uqsub_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Sub);
}
public static void Uqsub_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Sub);
}
public static void Uqxtn_S(AILEmitterCtx Context)
{
EmitScalarSaturatingNarrowOpZxZx(Context, () => { });
@ -1231,6 +1269,16 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpZxZx(Context, () => { });
}
public static void Usqadd_S(AILEmitterCtx Context)
{
EmitScalarSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
}
public static void Usqadd_V(AILEmitterCtx Context)
{
EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
}
public static void Usubw_V(AILEmitterCtx Context)
{
EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));

394
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -336,17 +336,21 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
if (Opers.HasFlag(OperFlags.Rd))
bool Rd = (Opers & OperFlags.Rd) != 0;
bool Rn = (Opers & OperFlags.Rn) != 0;
bool Rm = (Opers & OperFlags.Rm) != 0;
if (Rd)
{
EmitVectorExtract(Context, Op.Rd, 0, Op.Size, Signed);
}
if (Opers.HasFlag(OperFlags.Rn))
if (Rn)
{
EmitVectorExtract(Context, Op.Rn, 0, Op.Size, Signed);
}
if (Opers.HasFlag(OperFlags.Rm))
if (Rm)
{
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, 0, Op.Size, Signed);
}
@ -377,17 +381,21 @@ namespace ChocolArm64.Instruction
int SizeF = Op.Size & 1;
if (Opers.HasFlag(OperFlags.Ra))
bool Ra = (Opers & OperFlags.Ra) != 0;
bool Rn = (Opers & OperFlags.Rn) != 0;
bool Rm = (Opers & OperFlags.Rm) != 0;
if (Ra)
{
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Ra, 0, SizeF);
}
if (Opers.HasFlag(OperFlags.Rn))
if (Rn)
{
EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
}
if (Opers.HasFlag(OperFlags.Rm))
if (Rm)
{
EmitVectorExtractF(Context, ((AOpCodeSimdReg)Op).Rm, 0, SizeF);
}
@ -769,7 +777,7 @@ namespace ChocolArm64.Instruction
Emit();
EmitVectorInsertTmp(Context, Pairs + Index, Op.Size);
EmitVectorInsertTmp(Context, Index, Op.Size);
EmitVectorInsertTmp(Context, Index, Op.Size);
}
Context.EmitLdvectmp();
@ -781,56 +789,241 @@ namespace ChocolArm64.Instruction
}
}
[Flags]
public enum SaturatingFlags
{
Scalar = 1 << 0,
Signed = 1 << 1,
Add = 1 << 2,
Sub = 1 << 3,
Accumulate = 1 << 4,
ScalarSx = Scalar | Signed,
ScalarZx = Scalar,
VectorSx = Signed,
VectorZx = 0,
}
public static void EmitScalarSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingUnaryOpSx(Context, Emit, SaturatingFlags.ScalarSx);
}
public static void EmitVectorSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingUnaryOpSx(Context, Emit, SaturatingFlags.VectorSx);
}
public static void EmitSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit, SaturatingFlags Flags)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
bool Scalar = (Flags & SaturatingFlags.Scalar) != 0;
int Bytes = Op.GetBitsCount() >> 3;
int Elems = !Scalar ? Bytes >> Op.Size : 1;
if (Scalar)
{
EmitVectorZeroLowerTmp(Context);
}
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtractSx(Context, Op.Rn, Index, Op.Size);
Emit();
EmitUnarySignedSatQAbsOrNeg(Context, Op.Size);
EmitVectorInsertTmp(Context, Index, Op.Size);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void EmitScalarSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
{
EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarSx | Flags);
}
public static void EmitScalarSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
{
EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarZx | Flags);
}
public static void EmitVectorSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags)
{
EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorSx | Flags);
}
public static void EmitVectorSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags)
{
EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorZx | Flags);
}
public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, SaturatingFlags Flags)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
bool Scalar = (Flags & SaturatingFlags.Scalar) != 0;
bool Signed = (Flags & SaturatingFlags.Signed) != 0;
bool Add = (Flags & SaturatingFlags.Add) != 0;
bool Sub = (Flags & SaturatingFlags.Sub) != 0;
bool Accumulate = (Flags & SaturatingFlags.Accumulate) != 0;
int Bytes = Op.GetBitsCount() >> 3;
int Elems = !Scalar ? Bytes >> Op.Size : 1;
if (Scalar)
{
EmitVectorZeroLowerTmp(Context);
}
if (Add || Sub)
{
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed);
if (Op.Size <= 2)
{
Context.Emit(Add ? OpCodes.Add : OpCodes.Sub);
EmitSatQ(Context, Op.Size, true, Signed);
}
else /* if (Op.Size == 3) */
{
if (Add)
{
EmitBinarySatQAdd(Context, Signed);
}
else /* if (Sub) */
{
EmitBinarySatQSub(Context, Signed);
}
}
EmitVectorInsertTmp(Context, Index, Op.Size);
}
}
else if (Accumulate)
{
for (int Index = 0; Index < Elems; Index++)
{
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, !Signed);
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
if (Op.Size <= 2)
{
Context.Emit(OpCodes.Add);
EmitSatQ(Context, Op.Size, true, Signed);
}
else /* if (Op.Size == 3) */
{
EmitBinarySatQAccumulate(Context, Signed);
}
EmitVectorInsertTmp(Context, Index, Op.Size);
}
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
[Flags]
public enum SaturatingNarrowFlags
{
Scalar = 1 << 0,
SignedSrc = 1 << 1,
SignedDst = 1 << 2,
ScalarSxSx = Scalar | SignedSrc | SignedDst,
ScalarSxZx = Scalar | SignedSrc,
ScalarZxSx = Scalar | SignedDst,
ScalarZxZx = Scalar,
VectorSxSx = SignedSrc | SignedDst,
VectorSxZx = SignedSrc,
VectorZxSx = SignedDst,
VectorZxZx = 0
}
public static void EmitScalarSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, true, true, true);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarSxSx);
}
public static void EmitScalarSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, true, false, true);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarSxZx);
}
public static void EmitScalarSaturatingNarrowOpZxSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarZxSx);
}
public static void EmitScalarSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, false, false, true);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.ScalarZxZx);
}
public static void EmitVectorSaturatingNarrowOpSxSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, true, true, false);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorSxSx);
}
public static void EmitVectorSaturatingNarrowOpSxZx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, true, false, false);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorSxZx);
}
public static void EmitVectorSaturatingNarrowOpZxSx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorZxSx);
}
public static void EmitVectorSaturatingNarrowOpZxZx(AILEmitterCtx Context, Action Emit)
{
EmitSaturatingNarrowOp(Context, Emit, false, false, false);
EmitSaturatingNarrowOp(Context, Emit, SaturatingNarrowFlags.VectorZxZx);
}
public static void EmitSaturatingNarrowOp(
AILEmitterCtx Context,
Action Emit,
bool SignedSrc,
bool SignedDst,
bool Scalar)
public static void EmitSaturatingNarrowOp(AILEmitterCtx Context, Action Emit, SaturatingNarrowFlags Flags)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
int Elems = !Scalar ? 8 >> Op.Size : 1;
bool Scalar = (Flags & SaturatingNarrowFlags.Scalar) != 0;
bool SignedSrc = (Flags & SaturatingNarrowFlags.SignedSrc) != 0;
bool SignedDst = (Flags & SaturatingNarrowFlags.SignedDst) != 0;
int ESize = 8 << Op.Size;
int Elems = !Scalar ? 8 >> Op.Size : 1;
int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
long TMaxValue = SignedDst ? (1 << (ESize - 1)) - 1 : (long)(~0UL >> (64 - ESize));
long TMinValue = SignedDst ? -((1 << (ESize - 1))) : 0;
Context.EmitLdc_I8(0L);
Context.EmitSttmp();
if (Scalar)
{
EmitVectorZeroLowerTmp(Context);
}
if (Part != 0)
{
@ -840,47 +1033,11 @@ namespace ChocolArm64.Instruction
for (int Index = 0; Index < Elems; Index++)
{
AILLabel LblLe = new AILLabel();
AILLabel LblGeEnd = new AILLabel();
EmitVectorExtract(Context, Op.Rn, Index, Op.Size + 1, SignedSrc);
Emit();
Context.Emit(OpCodes.Dup);
Context.EmitLdc_I8(TMaxValue);
Context.Emit(SignedSrc ? OpCodes.Ble_S : OpCodes.Ble_Un_S, LblLe);
Context.Emit(OpCodes.Pop);
Context.EmitLdc_I8(TMaxValue);
Context.EmitLdc_I8(0x8000000L);
Context.EmitSttmp();
Context.Emit(OpCodes.Br_S, LblGeEnd);
Context.MarkLabel(LblLe);
Context.Emit(OpCodes.Dup);
Context.EmitLdc_I8(TMinValue);
Context.Emit(SignedSrc ? OpCodes.Bge_S : OpCodes.Bge_Un_S, LblGeEnd);
Context.Emit(OpCodes.Pop);
Context.EmitLdc_I8(TMinValue);
Context.EmitLdc_I8(0x8000000L);
Context.EmitSttmp();
Context.MarkLabel(LblGeEnd);
if (Scalar)
{
EmitVectorZeroLowerTmp(Context);
}
EmitSatQ(Context, Op.Size, SignedSrc, SignedDst);
EmitVectorInsertTmp(Context, Part + Index, Op.Size);
}
@ -892,13 +1049,120 @@ namespace ChocolArm64.Instruction
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
// TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
public static void EmitSatQ(
AILEmitterCtx Context,
int SizeDst,
bool SignedSrc,
bool SignedDst)
{
if (SizeDst > 2)
{
throw new ArgumentOutOfRangeException(nameof(SizeDst));
}
Context.EmitLdc_I4(SizeDst);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
if (SignedSrc)
{
ASoftFallback.EmitCall(Context, SignedDst
? nameof(ASoftFallback.SignedSrcSignedDstSatQ)
: nameof(ASoftFallback.SignedSrcUnsignedDstSatQ));
}
else
{
ASoftFallback.EmitCall(Context, SignedDst
? nameof(ASoftFallback.UnsignedSrcSignedDstSatQ)
: nameof(ASoftFallback.UnsignedSrcUnsignedDstSatQ));
}
}
// TSrc (8bit, 16bit, 32bit, 64bit) == TDst (8bit, 16bit, 32bit, 64bit); signed.
public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context, int Size)
{
int ESize = 8 << Size;
long TMaxValue = (1L << (ESize - 1)) - 1L;
long TMinValue = -(1L << (ESize - 1));
AILLabel LblFalse = new AILLabel();
Context.Emit(OpCodes.Dup);
Context.Emit(OpCodes.Neg);
Context.EmitLdc_I8(TMinValue);
Context.Emit(OpCodes.Ceq);
Context.Emit(OpCodes.Brfalse_S, LblFalse);
Context.Emit(OpCodes.Pop);
EmitSetFpsrQCFlag(Context);
Context.EmitLdc_I8(TMaxValue);
Context.MarkLabel(LblFalse);
}
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQAdd(AILEmitterCtx Context, bool Signed)
{
if (((AOpCodeSimdReg)Context.CurrOp).Size < 3)
{
throw new InvalidOperationException();
}
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
ASoftFallback.EmitCall(Context, Signed
? nameof(ASoftFallback.BinarySignedSatQAdd)
: nameof(ASoftFallback.BinaryUnsignedSatQAdd));
}
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQSub(AILEmitterCtx Context, bool Signed)
{
if (((AOpCodeSimdReg)Context.CurrOp).Size < 3)
{
throw new InvalidOperationException();
}
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
ASoftFallback.EmitCall(Context, Signed
? nameof(ASoftFallback.BinarySignedSatQSub)
: nameof(ASoftFallback.BinaryUnsignedSatQSub));
}
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
public static void EmitBinarySatQAccumulate(AILEmitterCtx Context, bool Signed)
{
if (((AOpCodeSimd)Context.CurrOp).Size < 3)
{
throw new InvalidOperationException();
}
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
ASoftFallback.EmitCall(Context, Signed
? nameof(ASoftFallback.BinarySignedSatQAcc)
: nameof(ASoftFallback.BinaryUnsignedSatQAcc));
}
public static void EmitSetFpsrQCFlag(AILEmitterCtx Context)
{
const int QCFlagBit = 27;
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr));
Context.EmitLdtmp();
Context.Emit(OpCodes.Conv_I4);
Context.EmitLdc_I4(1 << QCFlagBit);
Context.Emit(OpCodes.Or);
Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr));
}

268
ChocolArm64/Instruction/ASoftFallback.cs
View file

@ -1,3 +1,4 @@
using ChocolArm64.State;
using ChocolArm64.Translation;
using System;
@ -10,6 +11,273 @@ namespace ChocolArm64.Instruction
Context.EmitCall(typeof(ASoftFallback), MthdName);
}
public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State)
{
long Add = op1 + op2;
if ((~(op1 ^ op2) & (op1 ^ Add)) < 0L)
{
SetFpsrQCFlag(State);
if (op1 < 0L)
{
return long.MinValue;
}
else
{
return long.MaxValue;
}
}
else
{
return Add;
}
}
public static ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2, AThreadState State)
{
ulong Add = op1 + op2;
if ((Add < op1) && (Add < op2))
{
SetFpsrQCFlag(State);
return ulong.MaxValue;
}
else
{
return Add;
}
}
public static long BinarySignedSatQSub(long op1, long op2, AThreadState State)
{
long Sub = op1 - op2;
if (((op1 ^ op2) & (op1 ^ Sub)) < 0L)
{
SetFpsrQCFlag(State);
if (op1 < 0L)
{
return long.MinValue;
}
else
{
return long.MaxValue;
}
}
else
{
return Sub;
}
}
public static ulong BinaryUnsignedSatQSub(ulong op1, ulong op2, AThreadState State)
{
ulong Sub = op1 - op2;
if (op1 < op2)
{
SetFpsrQCFlag(State);
return ulong.MinValue;
}
else
{
return Sub;
}
}
public static long BinarySignedSatQAcc(ulong op1, long op2, AThreadState State)
{
if (op1 <= (ulong)long.MaxValue)
{
// op1 from ulong.MinValue to (ulong)long.MaxValue
// op2 from long.MinValue to long.MaxValue
long Add = (long)op1 + op2;
if ((~op2 & Add) < 0L)
{
SetFpsrQCFlag(State);
return long.MaxValue;
}
else
{
return Add;
}
}
else if (op2 >= 0L)
{
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
// op2 from (long)ulong.MinValue to long.MaxValue
SetFpsrQCFlag(State);
return long.MaxValue;
}
else
{
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
// op2 from long.MinValue to (long)ulong.MinValue - 1L
ulong Add = op1 + (ulong)op2;
if (Add > (ulong)long.MaxValue)
{
SetFpsrQCFlag(State);
return long.MaxValue;
}
else
{
return (long)Add;
}
}
}
public static ulong BinaryUnsignedSatQAcc(long op1, ulong op2, AThreadState State)
{
if (op1 >= 0L)
{
// op1 from (long)ulong.MinValue to long.MaxValue
// op2 from ulong.MinValue to ulong.MaxValue
ulong Add = (ulong)op1 + op2;
if ((Add < (ulong)op1) && (Add < op2))
{
SetFpsrQCFlag(State);
return ulong.MaxValue;
}
else
{
return Add;
}
}
else if (op2 > (ulong)long.MaxValue)
{
// op1 from long.MinValue to (long)ulong.MinValue - 1L
// op2 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
return (ulong)op1 + op2;
}
else
{
// op1 from long.MinValue to (long)ulong.MinValue - 1L
// op2 from ulong.MinValue to (ulong)long.MaxValue
long Add = op1 + (long)op2;
if (Add < (long)ulong.MinValue)
{
SetFpsrQCFlag(State);
return ulong.MinValue;
}
else
{
return (ulong)Add;
}
}
}
public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
{
int ESize = 8 << Size;
long TMaxValue = (1L << (ESize - 1)) - 1L;
long TMinValue = -(1L << (ESize - 1));
if (op > TMaxValue)
{
SetFpsrQCFlag(State);
return TMaxValue;
}
else if (op < TMinValue)
{
SetFpsrQCFlag(State);
return TMinValue;
}
else
{
return op;
}
}
public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State)
{
int ESize = 8 << Size;
ulong TMaxValue = (1UL << ESize) - 1UL;
ulong TMinValue = 0UL;
if (op > (long)TMaxValue)
{
SetFpsrQCFlag(State);
return TMaxValue;
}
else if (op < (long)TMinValue)
{
SetFpsrQCFlag(State);
return TMinValue;
}
else
{
return (ulong)op;
}
}
public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State)
{
int ESize = 8 << Size;
long TMaxValue = (1L << (ESize - 1)) - 1L;
if (op > (ulong)TMaxValue)
{
SetFpsrQCFlag(State);
return TMaxValue;
}
else
{
return (long)op;
}
}
public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State)
{
int ESize = 8 << Size;
ulong TMaxValue = (1UL << ESize) - 1UL;
if (op > TMaxValue)
{
SetFpsrQCFlag(State);
return TMaxValue;
}
else
{
return op;
}
}
private static void SetFpsrQCFlag(AThreadState State)
{
const int QCFlagBit = 27;
State.Fpsr |= 1 << QCFlagBit;
}
public static ulong CountLeadingSigns(ulong Value, int Size)
{
Value ^= Value >> 1;

284
ChocolArm64/Instruction/ASoftFloat.cs
View file

@ -79,7 +79,7 @@ namespace ChocolArm64.Instruction
if (scaled == 0)
{
// Zero -> Infinity
return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7ff0000000000000));
return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7FF0000000000000));
}
// Denormal
@ -94,7 +94,7 @@ namespace ChocolArm64.Instruction
if (x_sign != 0)
{
// Negative -> NaN
return BitConverter.Int64BitsToDouble((long)0x7ff8000000000000);
return BitConverter.Int64BitsToDouble((long)0x7FF8000000000000);
}
if (x_exp == 0x7ff && scaled == 0)
@ -153,7 +153,7 @@ namespace ChocolArm64.Instruction
if (scaled == 0)
{
// Zero -> Infinity
return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7ff0000000000000));
return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7FF0000000000000));
}
// Denormal
@ -208,8 +208,8 @@ namespace ChocolArm64.Instruction
ulong op1_other = op1_bits & 0x7FFFFFFFFFFFFFFF;
ulong op2_other = op2_bits & 0x7FFFFFFFFFFFFFFF;
bool inf1 = op1_other == 0x7ff0000000000000;
bool inf2 = op2_other == 0x7ff0000000000000;
bool inf1 = op1_other == 0x7FF0000000000000;
bool inf2 = op2_other == 0x7FF0000000000000;
bool zero1 = op1_other == 0;
bool zero2 = op2_other == 0;
@ -220,7 +220,7 @@ namespace ChocolArm64.Instruction
else if (inf1 || inf2)
{
// Infinity
return BitConverter.Int64BitsToDouble((long)(0x7ff0000000000000 | (op1_sign ^ op2_sign)));
return BitConverter.Int64BitsToDouble((long)(0x7FF0000000000000 | (op1_sign ^ op2_sign)));
}
return 2.0 + op1 * op2;
@ -261,5 +261,277 @@ namespace ChocolArm64.Instruction
uint new_exp = (uint)((exponent + 127) & 0xFF) << 23;
return BitConverter.Int32BitsToSingle((int)((x_sign << 31) | new_exp | (x_mantissa << 13)));
}
public static float MaxNum(float op1, float op2)
{
uint op1_bits = (uint)BitConverter.SingleToInt32Bits(op1);
uint op2_bits = (uint)BitConverter.SingleToInt32Bits(op2);
if (IsQNaN(op1_bits) && !IsQNaN(op2_bits))
{
op1 = float.NegativeInfinity;
}
else if (!IsQNaN(op1_bits) && IsQNaN(op2_bits))
{
op2 = float.NegativeInfinity;
}
return Max(op1, op2);
}
public static double MaxNum(double op1, double op2)
{
ulong op1_bits = (ulong)BitConverter.DoubleToInt64Bits(op1);
ulong op2_bits = (ulong)BitConverter.DoubleToInt64Bits(op2);
if (IsQNaN(op1_bits) && !IsQNaN(op2_bits))
{
op1 = double.NegativeInfinity;
}
else if (!IsQNaN(op1_bits) && IsQNaN(op2_bits))
{
op2 = double.NegativeInfinity;
}
return Max(op1, op2);
}
public static float Max(float op1, float op2)
{
// Fast path
if (op1 > op2)
{
return op1;
}
if (op1 < op2 || (op1 == op2 && op2 != 0))
{
return op2;
}
uint op1_bits = (uint)BitConverter.SingleToInt32Bits(op1);
uint op2_bits = (uint)BitConverter.SingleToInt32Bits(op2);
// Handle NaN cases
if (ProcessNaNs(op1_bits, op2_bits, out uint op_bits))
{
return BitConverter.Int32BitsToSingle((int)op_bits);
}
// Return the most positive zero
if ((op1_bits & op2_bits) == 0x80000000u)
{
return BitConverter.Int32BitsToSingle(int.MinValue);
}
return 0;
}
public static double Max(double op1, double op2)
{
// Fast path
if (op1 > op2)
{
return op1;
}
if (op1 < op2 || (op1 == op2 && op2 != 0))
{
return op2;
}
ulong op1_bits = (ulong)BitConverter.DoubleToInt64Bits(op1);
ulong op2_bits = (ulong)BitConverter.DoubleToInt64Bits(op2);
// Handle NaN cases
if (ProcessNaNs(op1_bits, op2_bits, out ulong op_bits))
{
return BitConverter.Int64BitsToDouble((long)op_bits);
}
// Return the most positive zero
if ((op1_bits & op2_bits) == 0x8000000000000000ul)
{
return BitConverter.Int64BitsToDouble(long.MinValue);
}
return 0;
}
public static float MinNum(float op1, float op2)
{
uint op1_bits = (uint)BitConverter.SingleToInt32Bits(op1);
uint op2_bits = (uint)BitConverter.SingleToInt32Bits(op2);
if (IsQNaN(op1_bits) && !IsQNaN(op2_bits))
{
op1 = float.PositiveInfinity;
}
else if (!IsQNaN(op1_bits) && IsQNaN(op2_bits))
{
op2 = float.PositiveInfinity;
}
return Min(op1, op2);
}
public static double MinNum(double op1, double op2)
{
ulong op1_bits = (ulong)BitConverter.DoubleToInt64Bits(op1);
ulong op2_bits = (ulong)BitConverter.DoubleToInt64Bits(op2);
if (IsQNaN(op1_bits) && !IsQNaN(op2_bits))
{
op1 = double.PositiveInfinity;
}
else if (!IsQNaN(op1_bits) && IsQNaN(op2_bits))
{
op2 = double.PositiveInfinity;
}
return Min(op1, op2);
}
public static float Min(float op1, float op2)
{
// Fast path
if (op1 < op2)
{
return op1;
}
if (op1 > op2 || (op1 == op2 && op2 != 0))
{
return op2;
}
uint op1_bits = (uint)BitConverter.SingleToInt32Bits(op1);
uint op2_bits = (uint)BitConverter.SingleToInt32Bits(op2);
// Handle NaN cases
if (ProcessNaNs(op1_bits, op2_bits, out uint op_bits))
{
return BitConverter.Int32BitsToSingle((int)op_bits);
}
// Return the most negative zero
if ((op1_bits | op2_bits) == 0x80000000u)
{
return BitConverter.Int32BitsToSingle(int.MinValue);
}
return 0;
}
public static double Min(double op1, double op2)
{
// Fast path
if (op1 < op2)
{
return op1;
}
if (op1 > op2 || (op1 == op2 && op2 != 0))
{
return op2;
}
ulong op1_bits = (ulong)BitConverter.DoubleToInt64Bits(op1);
ulong op2_bits = (ulong)BitConverter.DoubleToInt64Bits(op2);
// Handle NaN cases
if (ProcessNaNs(op1_bits, op2_bits, out ulong op_bits))
{
return BitConverter.Int64BitsToDouble((long)op_bits);
}
// Return the most negative zero
if ((op1_bits | op2_bits) == 0x8000000000000000ul)
{
return BitConverter.Int64BitsToDouble(long.MinValue);
}
return 0;
}
private static bool ProcessNaNs(uint op1_bits, uint op2_bits, out uint op_bits)
{
if (IsSNaN(op1_bits))
{
op_bits = op1_bits | (1u << 22); // op1 is SNaN, return QNaN op1
}
else if (IsSNaN(op2_bits))
{
op_bits = op2_bits | (1u << 22); // op2 is SNaN, return QNaN op2
}
else if (IsQNaN(op1_bits))
{
op_bits = op1_bits; // op1 is QNaN, return QNaN op1
}
else if (IsQNaN(op2_bits))
{
op_bits = op2_bits; // op2 is QNaN, return QNaN op2
}
else
{
op_bits = 0;
return false;
}
return true;
}
private static bool ProcessNaNs(ulong op1_bits, ulong op2_bits, out ulong op_bits)
{
if (IsSNaN(op1_bits))
{
op_bits = op1_bits | (1ul << 51); // op1 is SNaN, return QNaN op1
}
else if (IsSNaN(op2_bits))
{
op_bits = op2_bits | (1ul << 51); // op2 is SNaN, return QNaN op2
}
else if (IsQNaN(op1_bits))
{
op_bits = op1_bits; // op1 is QNaN, return QNaN op1
}
else if (IsQNaN(op2_bits))
{
op_bits = op2_bits; // op2 is QNaN, return QNaN op2
}
else
{
op_bits = 0;
return false;
}
return true;
}
private static bool IsQNaN(uint op_bits)
{
return (op_bits & 0x007FFFFF) != 0 &&
(op_bits & 0x7FC00000) == 0x7FC00000;
}
private static bool IsQNaN(ulong op_bits)
{
return (op_bits & 0x000FFFFFFFFFFFFF) != 0 &&
(op_bits & 0x7FF8000000000000) == 0x7FF8000000000000;
}
private static bool IsSNaN(uint op_bits)
{
return (op_bits & 0x007FFFFF) != 0 &&
(op_bits & 0x7FC00000) == 0x7F800000;
}
private static bool IsSNaN(ulong op_bits)
{
return (op_bits & 0x000FFFFFFFFFFFFF) != 0 &&
(op_bits & 0x7FF8000000000000) == 0x7FF0000000000000;
}
}
}

80
ChocolArm64/Instruction/AVectorHelper.cs
View file

@ -93,86 +93,6 @@ namespace ChocolArm64.Instruction
Value < ulong.MinValue ? ulong.MinValue : (ulong)Value;
}
public static double Max(double LHS, double RHS)
{
if (LHS == 0.0 && RHS == 0.0)
{
if (BitConverter.DoubleToInt64Bits(LHS) < 0 &&
BitConverter.DoubleToInt64Bits(RHS) < 0)
return -0.0;
return 0.0;
}
if (LHS > RHS)
return LHS;
if (double.IsNaN(LHS))
return LHS;
return RHS;
}
public static float MaxF(float LHS, float RHS)
{
if (LHS == 0.0 && RHS == 0.0)
{
if (BitConverter.SingleToInt32Bits(LHS) < 0 &&
BitConverter.SingleToInt32Bits(RHS) < 0)
return -0.0f;
return 0.0f;
}
if (LHS > RHS)
return LHS;
if (float.IsNaN(LHS))
return LHS;
return RHS;
}
public static double Min(double LHS, double RHS)
{
if (LHS == 0.0 && RHS == 0.0)
{
if (BitConverter.DoubleToInt64Bits(LHS) < 0 ||
BitConverter.DoubleToInt64Bits(RHS) < 0)
return -0.0;
return 0.0;
}
if (LHS < RHS)
return LHS;
if (double.IsNaN(LHS))
return LHS;
return RHS;
}
public static float MinF(float LHS, float RHS)
{
if (LHS == 0.0 && RHS == 0.0)
{
if (BitConverter.SingleToInt32Bits(LHS) < 0 ||
BitConverter.SingleToInt32Bits(RHS) < 0)
return -0.0f;
return 0.0f;
}
if (LHS < RHS)
return LHS;
if (float.IsNaN(LHS))
return LHS;
return RHS;
}
public static double Round(double Value, int Fpcr)
{
switch ((ARoundMode)((Fpcr >> 22) & 3))

10
ChocolArm64/Memory/AMemory.cs
View file

@ -160,23 +160,23 @@ namespace ChocolArm64.Memory
return HostPageSize;
}
public bool[] IsRegionModified(long Position, long Size)
public (bool[], long) IsRegionModified(long Position, long Size)
{
if (!RuntimeInformation.IsOSPlatform(OSPlatform.Windows))
{
return null;
return (null, 0);
}
long EndPos = Position + Size;
if ((ulong)EndPos < (ulong)Position)
{
return null;
return (null, 0);
}
if ((ulong)EndPos > AMemoryMgr.RamSize)
{
return null;
return (null, 0);
}
IntPtr MemAddress = new IntPtr(RamPtr + Position);
@ -201,7 +201,7 @@ namespace ChocolArm64.Memory
Modified[(VA - Position) / HostPageSize] = true;
}
return Modified;
return (Modified, Count);
}
public IntPtr GetHostAddress(long Position, long Size)

3
Ryujinx.Audio/OpenAL/OpenALAudioOut.cs
View file

@ -222,7 +222,8 @@ namespace Ryujinx.Audio.OpenAL
Td.CallReleaseCallbackIfNeeded();
}
Thread.Yield();
//If it's not slept it will waste cycles
Thread.Sleep(10);
}
while (KeepPolling);
}

1
Ryujinx.Graphics/Gal/GalTextureFormat.cs
View file

@ -5,6 +5,7 @@ namespace Ryujinx.Graphics.Gal
R32G32B32A32 = 0x1,
R16G16B16A16 = 0x3,
A8B8G8R8 = 0x8,
A2B10G10R10 = 0x9,
R32 = 0xf,
BC6H_SF16 = 0x10,
BC6H_UF16 = 0x11,

1
Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs
View file

@ -132,6 +132,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
case GalTextureFormat.R32G32B32A32: return (PixelFormat.Rgba, PixelType.Float);
case GalTextureFormat.R16G16B16A16: return (PixelFormat.Rgba, PixelType.HalfFloat);
case GalTextureFormat.A8B8G8R8: return (PixelFormat.Rgba, PixelType.UnsignedByte);
case GalTextureFormat.A2B10G10R10: return (PixelFormat.Rgba, PixelType.UnsignedInt2101010Reversed);
case GalTextureFormat.R32: return (PixelFormat.Red, PixelType.Float);
case GalTextureFormat.A1B5G5R5: return (PixelFormat.Rgba, PixelType.UnsignedShort5551);
case GalTextureFormat.B5G6R5: return (PixelFormat.Rgb, PixelType.UnsignedShort565);

14
Ryujinx.Graphics/Gal/OpenGL/OGLRasterizer.cs
View file

@ -278,7 +278,19 @@ namespace Ryujinx.Graphics.Gal.OpenGL
int Size = AttribElements[Attrib.Size];
int Offset = Attrib.Offset;
GL.VertexAttribPointer(Attrib.Index, Size, Type, Normalize, Stride, Offset);
if (Attrib.Type == GalVertexAttribType.Sint ||
Attrib.Type == GalVertexAttribType.Uint)
{
IntPtr Pointer = new IntPtr(Offset);
VertexAttribIntegerType IType = (VertexAttribIntegerType)Type;
GL.VertexAttribIPointer(Attrib.Index, Size, IType, Stride, Pointer);
}
else
{
GL.VertexAttribPointer(Attrib.Index, Size, Type, Normalize, Stride, Offset);
}
}
}

29
Ryujinx.Graphics/Gal/Shader/GlslDecompiler.cs
View file

@ -23,8 +23,6 @@ namespace Ryujinx.Graphics.Gal.Shader
private const int MaxVertexInput = 3;
private static string[] ElemTypes = new string[] { "float", "vec2", "vec3", "vec4" };
private GlslDecl Decl;
private ShaderHeader Header, HeaderB;
@ -266,7 +264,7 @@ namespace Ryujinx.Graphics.Gal.Shader
{
if (DeclInfo.Index >= 0)
{
SB.AppendLine(IdentationStr + "layout (location = " + DeclInfo.Index + ") " + GetDecl(DeclInfo) + "; ");
SB.AppendLine(IdentationStr + "layout (location = " + DeclInfo.Index + ") vec4 " + DeclInfo.Name + "; ");
}
}
@ -297,7 +295,7 @@ namespace Ryujinx.Graphics.Gal.Shader
{
if (DeclInfo.Index >= 0)
{
SB.AppendLine("layout (location = " + DeclInfo.Index + ") " + InOut + " " + GetDecl(DeclInfo) + ";");
SB.AppendLine("layout (location = " + DeclInfo.Index + ") " + InOut + " vec4 " + DeclInfo.Name + ";");
Count++;
}
@ -331,7 +329,7 @@ namespace Ryujinx.Graphics.Gal.Shader
}
else if (DeclInfo.Name == GlslDecl.FragmentOutputName)
{
Name = "layout (location = 0) out " + GetDecl(DeclInfo) + Suffix + ";" + Environment.NewLine;
Name = "layout (location = 0) out vec4 " + DeclInfo.Name + Suffix + ";" + Environment.NewLine;
}
else
{
@ -354,7 +352,14 @@ namespace Ryujinx.Graphics.Gal.Shader
private string GetDecl(ShaderDeclInfo DeclInfo)
{
return ElemTypes[DeclInfo.Size - 1] + " " + DeclInfo.Name;
if (DeclInfo.Size == 4)
{
return "vec4 " + DeclInfo.Name;
}
else
{
return "float " + DeclInfo.Name;
}
}
private void PrintMain()
@ -370,13 +375,11 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderDeclInfo DeclInfo = KV.Value;
string Swizzle = ".xyzw".Substring(0, DeclInfo.Size + 1);
if (Decl.ShaderType == GalShaderType.Geometry)
{
for (int Vertex = 0; Vertex < MaxVertexInput; Vertex++)
{
string Dst = Attr.Name + "[" + Vertex + "]" + Swizzle;
string Dst = Attr.Name + "[" + Vertex + "]";
string Src = "block_in[" + Vertex + "]." + DeclInfo.Name;
@ -385,7 +388,7 @@ namespace Ryujinx.Graphics.Gal.Shader
}
else
{
SB.AppendLine(IdentationStr + Attr.Name + Swizzle + " = " + DeclInfo.Name + ";");
SB.AppendLine(IdentationStr + Attr.Name + " = " + DeclInfo.Name + ";");
}
}
@ -418,8 +421,6 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderDeclInfo DeclInfo = KV.Value;
string Swizzle = ".xyzw".Substring(0, DeclInfo.Size + 1);
string Name = Attr.Name;
if (Decl.ShaderType == GalShaderType.Geometry)
@ -427,7 +428,7 @@ namespace Ryujinx.Graphics.Gal.Shader
Name += "[0]";
}
SB.AppendLine(Identation + DeclInfo.Name + " = " + Name + Swizzle + ";");
SB.AppendLine(Identation + DeclInfo.Name + " = " + Name + ";");
}
if (Decl.ShaderType == GalShaderType.Vertex)
@ -1258,4 +1259,4 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new ArgumentException(nameof(Node));
}
}
}
}

11
Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs
View file

@ -871,11 +871,12 @@ namespace Ryujinx.Graphics.Gal.Shader
private static void EmitSet(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper)
{
bool NegA = ((OpCode >> 43) & 1) != 0;
bool AbsB = ((OpCode >> 44) & 1) != 0;
bool BoolFloat = ((OpCode >> 52) & 1) != 0;
bool NegB = ((OpCode >> 53) & 1) != 0;
bool AbsA = ((OpCode >> 54) & 1) != 0;
bool NegA = ((OpCode >> 43) & 1) != 0;
bool AbsB = ((OpCode >> 44) & 1) != 0;
bool NegB = ((OpCode >> 53) & 1) != 0;
bool AbsA = ((OpCode >> 54) & 1) != 0;
bool BoolFloat = ((OpCode >> (IsFloat ? 52 : 44)) & 1) != 0;
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;

177
Ryujinx.HLE/Font/SharedFontManager.cs Normal file
View file

@ -0,0 +1,177 @@
using ChocolArm64.Exceptions;
using ChocolArm64.Memory;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.OsHle;
using Ryujinx.HLE.OsHle.Handles;
using Ryujinx.HLE.Resource;
using System;
using System.Collections.Generic;
using System.IO;
namespace Ryujinx.HLE.Font
{
public class SharedFontManager
{
private const uint SharedMemorySize = 0x1100000;
private Logger Log;
private string FontsPath;
private object ShMemLock;
private (AMemory, long, long)[] ShMemPositions;
private Dictionary<SharedFontType, byte[]> FontData;
private uint[] LoadedFonts;
public SharedFontManager(Logger Log, string SystemPath)
{
this.Log = Log;
this.FontsPath = Path.Combine(SystemPath, "fonts");
ShMemLock = new object();
ShMemPositions = new(AMemory, long, long)[0];
FontData = new Dictionary<SharedFontType, byte[]>()
{
{ SharedFontType.JapanUsEurope, GetData("FontStandard") },
{ SharedFontType.SimplifiedChinese, GetData("FontChineseSimplified") },
{ SharedFontType.SimplifiedChineseEx, GetData("FontExtendedChineseSimplified") },
{ SharedFontType.TraditionalChinese, GetData("FontChineseTraditional") },
{ SharedFontType.Korean, GetData("FontKorean") },
{ SharedFontType.NintendoEx, GetData("FontNintendoExtended") }
};
int FontMemoryUsage = 0;
foreach (byte[] data in FontData.Values)
{
FontMemoryUsage += data.Length;
FontMemoryUsage += 0x8;
}
if (FontMemoryUsage > SharedMemorySize)
{
throw new InvalidSystemResourceException($"The sum of all fonts size exceed the shared memory size. Please make sure that the fonts don't exceed {SharedMemorySize} bytes in total. (actual size: {FontMemoryUsage} bytes)");
}
LoadedFonts = new uint[FontData.Count];
}
public byte[] GetData(string FontName)
{
string FontFilePath = Path.Combine(FontsPath, $"{FontName}.ttf");
if (File.Exists(FontFilePath))
{
return File.ReadAllBytes(FontFilePath);
}
else
{
throw new InvalidSystemResourceException($"Font \"{FontName}.ttf\" not found. Please provide it in \"{FontsPath}\".");
}
}
public void MapFont(SharedFontType FontType, AMemory Memory, long Position)
{
uint SharedMemoryAddressOffset = GetSharedMemoryAddressOffset(FontType);
// TODO: find what are the 8 bytes before the font
Memory.WriteUInt64(Position + SharedMemoryAddressOffset - 8, 0);
Memory.WriteBytes(Position + SharedMemoryAddressOffset, FontData[FontType]);
}
public void PropagateNewMapFont(SharedFontType Type)
{
lock (ShMemLock)
{
foreach ((AMemory Memory, long Position, long Size) in ShMemPositions)
{
AMemoryMapInfo MemoryInfo = Memory.Manager.GetMapInfo(Position);
if (MemoryInfo == null)
{
throw new VmmPageFaultException(Position);
}
// The memory is read only, we need to changes that to add the new font
AMemoryPerm originalPerms = MemoryInfo.Perm;
Memory.Manager.Reprotect(Position, Size, AMemoryPerm.RW);
MapFont(Type, Memory, Position);
Memory.Manager.Reprotect(Position, Size, originalPerms);
}
}
}
internal void ShMemMap(object sender, EventArgs e)
{
HSharedMem SharedMem = (HSharedMem)sender;
lock (ShMemLock)
{
ShMemPositions = SharedMem.GetVirtualPositions();
(AMemory Memory, long Position, long Size) = ShMemPositions[ShMemPositions.Length - 1];
for (int Type = 0; Type < LoadedFonts.Length; Type++)
{
if (LoadedFonts[(int)Type] == 1)
{
MapFont((SharedFontType)Type, Memory, Position);
}
}
}
}
internal void ShMemUnmap(object sender, EventArgs e)
{
HSharedMem SharedMem = (HSharedMem)sender;
lock (ShMemLock)
{
ShMemPositions = SharedMem.GetVirtualPositions();
}
}
public void Load(SharedFontType FontType)
{
if (LoadedFonts[(int)FontType] == 0)
{
PropagateNewMapFont(FontType);
}
LoadedFonts[(int)FontType] = 1;
}
public uint GetLoadState(SharedFontType FontType)
{
if (LoadedFonts[(int)FontType] != 1)
{
// Some games don't request a load, so we need to load it here.
Load(FontType);
return 0;
}
return LoadedFonts[(int)FontType];
}
public uint GetFontSize(SharedFontType FontType)
{
return (uint)FontData[FontType].Length;
}
public uint GetSharedMemoryAddressOffset(SharedFontType FontType)
{
uint Pos = 0x8;
for (SharedFontType Type = SharedFontType.JapanUsEurope; Type < FontType; Type++)
{
Pos += GetFontSize(Type);
Pos += 0x8;
}
return Pos;
}
public int Count => FontData.Count;
}
}

4
Ryujinx.HLE/OsHle/Services/Pl/SharedFontType.cs → Ryujinx.HLE/Font/SharedFontType.cs
View file

@ -1,6 +1,6 @@
namespace Ryujinx.HLE.OsHle.Services.Pl
namespace Ryujinx.HLE.Font
{
enum SharedFontType
public enum SharedFontType
{
JapanUsEurope = 0,
SimplifiedChinese = 1,

34
Ryujinx.HLE/Gpu/Engines/NvGpuEngine3d.cs
View file

@ -25,6 +25,8 @@ namespace Ryujinx.HLE.Gpu.Engines
private HashSet<long> FrameBuffers;
private List<long>[] UploadedKeys;
public NvGpuEngine3d(NvGpu Gpu)
{
this.Gpu = Gpu;
@ -57,6 +59,13 @@ namespace Ryujinx.HLE.Gpu.Engines
}
FrameBuffers = new HashSet<long>();
UploadedKeys = new List<long>[(int)NvGpuBufferType.Count];
for (int i = 0; i < UploadedKeys.Length; i++)
{
UploadedKeys[i] = new List<long>();
}
}
public void CallMethod(NvGpuVmm Vmm, NvGpuPBEntry PBEntry)
@ -516,7 +525,7 @@ namespace Ryujinx.HLE.Gpu.Engines
if (Gpu.Renderer.Texture.TryGetCachedTexture(Key, Size, out GalTexture Texture))
{
if (NewTexture.Equals(Texture) && !Vmm.IsRegionModified(Key, Size, NvGpuBufferType.Texture))
if (NewTexture.Equals(Texture) && !QueryKeyUpload(Vmm, Key, Size, NvGpuBufferType.Texture))
{
Gpu.Renderer.Texture.Bind(Key, TexIndex);
@ -593,7 +602,7 @@ namespace Ryujinx.HLE.Gpu.Engines
bool IboCached = Gpu.Renderer.Rasterizer.IsIboCached(IboKey, (uint)IbSize);
if (!IboCached || Vmm.IsRegionModified(IboKey, (uint)IbSize, NvGpuBufferType.Index))
if (!IboCached || QueryKeyUpload(Vmm, IboKey, (uint)IbSize, NvGpuBufferType.Index))
{
IntPtr DataAddress = Vmm.GetHostAddress(IndexPosition, IbSize);
@ -657,7 +666,7 @@ namespace Ryujinx.HLE.Gpu.Engines
bool VboCached = Gpu.Renderer.Rasterizer.IsVboCached(VboKey, VbSize);
if (!VboCached || Vmm.IsRegionModified(VboKey, VbSize, NvGpuBufferType.Vertex))
if (!VboCached || QueryKeyUpload(Vmm, VboKey, VbSize, NvGpuBufferType.Vertex))
{
IntPtr DataAddress = Vmm.GetHostAddress(VertexPosition, VbSize);
@ -692,6 +701,11 @@ namespace Ryujinx.HLE.Gpu.Engines
if (Mode == 0)
{
foreach (List<long> Uploaded in UploadedKeys)
{
Uploaded.Clear();
}
//Write mode.
Vmm.WriteInt32(Position, Seq);
}
@ -774,5 +788,19 @@ namespace Ryujinx.HLE.Gpu.Engines
{
return FrameBuffers.Contains(Position);
}
private bool QueryKeyUpload(NvGpuVmm Vmm, long Key, long Size, NvGpuBufferType Type)
{
List<long> Uploaded = UploadedKeys[(int)Type];
if (Uploaded.Contains(Key))
{
return false;
}
Uploaded.Add(Key);
return Vmm.IsRegionModified(Key, Size, Type);
}
}
}

93
Ryujinx.HLE/Gpu/Memory/NvGpuVmmCache.cs
View file

@ -19,12 +19,14 @@ namespace Ryujinx.HLE.Gpu.Memory
public Range(long Start, long End)
{
this.Start = Start;
this.End = End;
this.End = End;
}
}
private List<Range>[] Regions;
private HashSet<long> ResidencyKeys;
public LinkedListNode<long> Node { get; set; }
public int Timestamp { get; private set; }
@ -37,6 +39,27 @@ namespace Ryujinx.HLE.Gpu.Memory
{
Regions[Index] = new List<Range>();
}
ResidencyKeys = new HashSet<long>();
}
public void AddResidency(long Key)
{
ResidencyKeys.Add(Key);
}
public void RemoveResidency(HashSet<long>[] Residency, long PageSize)
{
for (int i = 0; i < (int)NvGpuBufferType.Count; i++)
{
foreach (Range Region in Regions[i])
{
foreach (long Key in ResidencyKeys)
{
Residency[Region.Start / PageSize].Remove(Key);
}
}
}
}
public bool AddRange(long Start, long End, NvGpuBufferType BufferType)
@ -89,6 +112,10 @@ namespace Ryujinx.HLE.Gpu.Memory
private LinkedList<long> SortedCache;
private HashSet<long>[] Residency;
private long ResidencyPageSize;
private int CpCount;
public NvGpuVmmCache()
@ -100,7 +127,7 @@ namespace Ryujinx.HLE.Gpu.Memory
public bool IsRegionModified(AMemory Memory, NvGpuBufferType BufferType, long PA, long Size)
{
bool[] Modified = Memory.IsRegionModified(PA, Size);
(bool[] Modified, long ModifiedCount) = Memory.IsRegionModified(PA, Size);
if (Modified == null)
{
@ -111,8 +138,19 @@ namespace Ryujinx.HLE.Gpu.Memory
long PageSize = Memory.GetHostPageSize();
EnsureResidencyInitialized(PageSize);
bool HasResidents = AddResidency(PA, Size);
if (!HasResidents && ModifiedCount == 0)
{
return false;
}
long Mask = PageSize - 1;
long ResidencyKey = PA;
long PAEnd = PA + Size;
bool RegMod = false;
@ -147,6 +185,8 @@ namespace Ryujinx.HLE.Gpu.Memory
Cache[Key] = Cp;
}
Cp.AddResidency(ResidencyKey);
Cp.Node = SortedCache.AddLast(Key);
RegMod |= Cp.AddRange(PA, PAPgEnd, BufferType);
@ -159,6 +199,53 @@ namespace Ryujinx.HLE.Gpu.Memory
return RegMod;
}
private bool AddResidency(long PA, long Size)
{
long PageSize = ResidencyPageSize;
long Mask = PageSize - 1;
long Key = PA;
bool ResidentFound = false;
for (long Cursor = PA & ~Mask; Cursor < ((PA + Size + PageSize - 1) & ~Mask); Cursor += PageSize)
{
long PageIndex = Cursor / PageSize;
Residency[PageIndex].Add(Key);
if (Residency[PageIndex].Count > 1)
{
ResidentFound = true;
}
}
return ResidentFound;
}
private void EnsureResidencyInitialized(long PageSize)
{
if (Residency == null)
{
Residency = new HashSet<long>[AMemoryMgr.RamSize / PageSize];
for (int i = 0; i < Residency.Length; i++)
{
Residency[i] = new HashSet<long>();
}
ResidencyPageSize = PageSize;
}
else
{
if (ResidencyPageSize != PageSize)
{
throw new InvalidOperationException("Tried to change residency page size");
}
}
}
private void ClearCachedPagesIfNeeded()
{
if (CpCount <= MaxCpCount)
@ -179,6 +266,8 @@ namespace Ryujinx.HLE.Gpu.Memory
CachedPage Cp = Cache[Key];
Cp.RemoveResidency(Residency, ResidencyPageSize);
Cache.Remove(Key);
CpCount -= Cp.GetTotalCount();

1
Ryujinx.HLE/Gpu/Texture/TextureHelper.cs
View file

@ -41,6 +41,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Texture.Width * Texture.Height * 8;
case GalTextureFormat.A8B8G8R8:
case GalTextureFormat.A2B10G10R10:
case GalTextureFormat.R32:
case GalTextureFormat.ZF32:
case GalTextureFormat.BF10GF11RF11:

1
Ryujinx.HLE/Gpu/Texture/TextureReader.cs
View file

@ -13,6 +13,7 @@ namespace Ryujinx.HLE.Gpu.Texture
case GalTextureFormat.R32G32B32A32: return Read16Bpp (Memory, Texture);
case GalTextureFormat.R16G16B16A16: return Read8Bpp (Memory, Texture);
case GalTextureFormat.A8B8G8R8: return Read4Bpp (Memory, Texture);
case GalTextureFormat.A2B10G10R10: return Read4Bpp (Memory, Texture);
case GalTextureFormat.R32: return Read4Bpp (Memory, Texture);
case GalTextureFormat.BF10GF11RF11: return Read4Bpp (Memory, Texture);
case GalTextureFormat.Z24S8: return Read4Bpp (Memory, Texture);

10
Ryujinx.HLE/Hid/Hid.cs
View file

@ -67,7 +67,7 @@ namespace Ryujinx.HLE.Input
private object ShMemLock;
private (AMemory, long)[] ShMemPositions;
private (AMemory, long, long)[] ShMemPositions;
public Hid(Logger Log)
{
@ -75,7 +75,7 @@ namespace Ryujinx.HLE.Input
ShMemLock = new object();
ShMemPositions = new (AMemory, long)[0];
ShMemPositions = new (AMemory, long, long)[0];
}
internal void ShMemMap(object sender, EventArgs e)
@ -86,7 +86,7 @@ namespace Ryujinx.HLE.Input
{
ShMemPositions = SharedMem.GetVirtualPositions();
(AMemory Memory, long Position) = ShMemPositions[ShMemPositions.Length - 1];
(AMemory Memory, long Position, long Size) = ShMemPositions[ShMemPositions.Length - 1];
for (long Offset = 0; Offset < Horizon.HidSize; Offset += 8)
{
@ -167,7 +167,7 @@ namespace Ryujinx.HLE.Input
{
lock (ShMemLock)
{
foreach ((AMemory Memory, long Position) in ShMemPositions)
foreach ((AMemory Memory, long Position, long Size) in ShMemPositions)
{
long ControllerOffset = Position + HidControllersOffset;
@ -218,7 +218,7 @@ namespace Ryujinx.HLE.Input
{
lock (ShMemLock)
{
foreach ((AMemory Memory, long Position) in ShMemPositions)
foreach ((AMemory Memory, long Position, long Size) in ShMemPositions)
{
long TouchScreenOffset = Position + HidTouchScreenOffset;

1
Ryujinx.HLE/Logging/LogClass.cs
View file

@ -4,6 +4,7 @@ namespace Ryujinx.HLE.Logging
{
Audio,
Cpu,
Font,
Gpu,
Hid,
Kernel,

14
Ryujinx.HLE/OsHle/Handles/HSharedMem.cs
View file

@ -6,37 +6,37 @@ namespace Ryujinx.HLE.OsHle.Handles
{
class HSharedMem
{
private List<(AMemory, long)> Positions;
private List<(AMemory, long, long)> Positions;
public EventHandler<EventArgs> MemoryMapped;
public EventHandler<EventArgs> MemoryUnmapped;
public HSharedMem()
{
Positions = new List<(AMemory, long)>();
Positions = new List<(AMemory, long, long)>();
}
public void AddVirtualPosition(AMemory Memory, long Position)
public void AddVirtualPosition(AMemory Memory, long Position, long Size)
{
lock (Positions)
{
Positions.Add((Memory, Position));
Positions.Add((Memory, Position, Size));
MemoryMapped?.Invoke(this, EventArgs.Empty);
}
}
public void RemoveVirtualPosition(AMemory Memory, long Position)
public void RemoveVirtualPosition(AMemory Memory, long Position, long Size)
{
lock (Positions)
{
Positions.Remove((Memory, Position));
Positions.Remove((Memory, Position, Size));
MemoryUnmapped?.Invoke(this, EventArgs.Empty);
}
}
public (AMemory, long)[] GetVirtualPositions()
public (AMemory, long, long)[] GetVirtualPositions()
{
return Positions.ToArray();
}

20
Ryujinx.HLE/OsHle/Horizon.cs
View file

@ -1,4 +1,5 @@
using Ryujinx.HLE.Loaders.Executables;
using Ryujinx.HLE.Loaders.Npdm;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.OsHle.Handles;
using System;
@ -76,6 +77,25 @@ namespace Ryujinx.HLE.OsHle
}
}
void LoadNpdm(string FileName)
{
string File = Directory.GetFiles(ExeFsDir, FileName)[0];
Ns.Log.PrintInfo(LogClass.Loader, "Loading Title Metadata...");
using (FileStream Input = new FileStream(File, FileMode.Open))
{
MainProcess.Metadata = new Npdm(Input);
}
}
LoadNpdm("*.npdm");
if (!MainProcess.Metadata.Is64Bits)
{
throw new NotImplementedException("32-bit titles are unsupported!");
}
LoadNso("rtld");
MainProcess.SetEmptyArgs();

14
Ryujinx.HLE/OsHle/IdDictionary.cs
View file

@ -8,8 +8,6 @@ namespace Ryujinx.HLE.OsHle
{
private ConcurrentDictionary<int, object> Objs;
private int FreeIdHint = 1;
public IdDictionary()
{
Objs = new ConcurrentDictionary<int, object>();
@ -21,16 +19,6 @@ namespace Ryujinx.HLE.OsHle
}
public int Add(object Data)
{
if (Objs.TryAdd(FreeIdHint, Data))
{
return FreeIdHint++;
}
return AddSlow(Data);
}
private int AddSlow(object Data)
{
for (int Id = 1; Id < int.MaxValue; Id++)
{
@ -67,8 +55,6 @@ namespace Ryujinx.HLE.OsHle
{
if (Objs.TryRemove(Id, out object Obj))
{
FreeIdHint = Id;
return Obj;
}

14
Ryujinx.HLE/OsHle/Ipc/IpcHandleDesc.cs
View file

@ -47,13 +47,15 @@ namespace Ryujinx.HLE.OsHle.Ipc
HasPId = true;
}
public static IpcHandleDesc MakeCopy(int Handle) => new IpcHandleDesc(
new int[] { Handle },
new int[0]);
public static IpcHandleDesc MakeCopy(params int[] Handles)
{
return new IpcHandleDesc(Handles, new int[0]);
}
public static IpcHandleDesc MakeMove(int Handle) => new IpcHandleDesc(
new int[0],
new int[] { Handle });
public static IpcHandleDesc MakeMove(params int[] Handles)
{
return new IpcHandleDesc(new int[0], Handles);
}
public byte[] GetBytes()
{

6
Ryujinx.HLE/OsHle/Ipc/IpcHandler.cs
View file

@ -21,7 +21,8 @@ namespace Ryujinx.HLE.OsHle.Ipc
{
BinaryReader ReqReader = new BinaryReader(Raw);
if (Request.Type == IpcMessageType.Request)
if (Request.Type == IpcMessageType.Request ||
Request.Type == IpcMessageType.RequestWithContext)
{
Response.Type = IpcMessageType.Response;
@ -44,7 +45,8 @@ namespace Ryujinx.HLE.OsHle.Ipc
Response.RawData = ResMS.ToArray();
}
}
else if (Request.Type == IpcMessageType.Control)
else if (Request.Type == IpcMessageType.Control ||
Request.Type == IpcMessageType.ControlWithContext)
{
long Magic = ReqReader.ReadInt64();
long CmdId = ReqReader.ReadInt64();

4
Ryujinx.HLE/OsHle/Ipc/IpcMessage.cs
View file

@ -15,7 +15,7 @@ namespace Ryujinx.HLE.OsHle.Ipc
public List<IpcBuffDesc> ExchangeBuff { get; private set; }
public List<IpcRecvListBuffDesc> RecvListBuff { get; private set; }
public List<int> ResponseObjIds { get; private set; }
public List<int> ObjectIds { get; private set; }
public byte[] RawData { get; set; }
@ -27,7 +27,7 @@ namespace Ryujinx.HLE.OsHle.Ipc
ExchangeBuff = new List<IpcBuffDesc>();
RecvListBuff = new List<IpcRecvListBuffDesc>();
ResponseObjIds = new List<int>();
ObjectIds = new List<int>();
}
public IpcMessage(byte[] Data, long CmdPtr) : this()

10
Ryujinx.HLE/OsHle/Ipc/IpcMessageType.cs
View file

@ -2,9 +2,11 @@ namespace Ryujinx.HLE.OsHle.Ipc
{
enum IpcMessageType
{
Response = 0,
CloseSession = 2,
Request = 4,
Control = 5
Response = 0,
CloseSession = 2,
Request = 4,
Control = 5,
RequestWithContext = 6,
ControlWithContext = 7
}
}

8
Ryujinx.HLE/OsHle/Kernel/SvcHandler.cs
View file

@ -22,7 +22,7 @@ namespace Ryujinx.HLE.OsHle.Kernel
private ConcurrentDictionary<KThread, AutoResetEvent> SyncWaits;
private HashSet<(HSharedMem, long)> MappedSharedMems;
private HashSet<(HSharedMem, long, long)> MappedSharedMems;
private ulong CurrentHeapSize;
@ -83,7 +83,7 @@ namespace Ryujinx.HLE.OsHle.Kernel
SyncWaits = new ConcurrentDictionary<KThread, AutoResetEvent>();
MappedSharedMems = new HashSet<(HSharedMem, long)>();
MappedSharedMems = new HashSet<(HSharedMem, long, long)>();
}
static SvcHandler()
@ -138,9 +138,9 @@ namespace Ryujinx.HLE.OsHle.Kernel
{
lock (MappedSharedMems)
{
foreach ((HSharedMem SharedMem, long Position) in MappedSharedMems)
foreach ((HSharedMem SharedMem, long Position, long Size) in MappedSharedMems)
{
SharedMem.RemoveVirtualPosition(Memory, Position);
SharedMem.RemoveVirtualPosition(Memory, Position, Size);
}
MappedSharedMems.Clear();

10
Ryujinx.HLE/OsHle/Kernel/SvcMemory.cs
View file

@ -174,15 +174,15 @@ namespace Ryujinx.HLE.OsHle.Kernel
AMemoryHelper.FillWithZeros(Memory, Src, (int)Size);
SharedMem.AddVirtualPosition(Memory, Src, Size);
Memory.Manager.Reprotect(Src, Size, (AMemoryPerm)Perm);
lock (MappedSharedMems)
{
MappedSharedMems.Add((SharedMem, Src));
MappedSharedMems.Add((SharedMem, Src, Size));
}
SharedMem.AddVirtualPosition(Memory, Src);
ThreadState.X0 = 0;
}
@ -210,11 +210,11 @@ namespace Ryujinx.HLE.OsHle.Kernel
{
Memory.Manager.Unmap(Src, Size, (int)MemoryType.SharedMemory);
SharedMem.RemoveVirtualPosition(Memory, Src);
SharedMem.RemoveVirtualPosition(Memory, Src, Size);
lock (MappedSharedMems)
{
MappedSharedMems.Remove((SharedMem, Src));
MappedSharedMems.Remove((SharedMem, Src, Size));
}
ThreadState.X0 = 0;

1
Ryujinx.HLE/OsHle/Kernel/SvcSystem.cs
View file

@ -242,7 +242,6 @@ namespace Ryujinx.HLE.OsHle.Kernel
Process.Scheduler.Suspend(CurrThread);
IpcMessage Cmd = new IpcMessage(CmdData, CmdPtr);
long Result = IpcHandler.IpcCall(Ns, Process, Memory, Session, Cmd, CmdPtr);
Thread.Yield();

3
Ryujinx.HLE/OsHle/Process.cs
View file

@ -4,6 +4,7 @@ using ChocolArm64.Memory;
using ChocolArm64.State;
using Ryujinx.HLE.Loaders;
using Ryujinx.HLE.Loaders.Executables;
using Ryujinx.HLE.Loaders.Npdm;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.OsHle.Diagnostics;
using Ryujinx.HLE.OsHle.Exceptions;
@ -48,6 +49,8 @@ namespace Ryujinx.HLE.OsHle
public AppletStateMgr AppletState { get; private set; }
public Npdm Metadata { get; set; }
private SvcHandler SvcHandler;
private ConcurrentDictionary<int, AThread> TlsSlots;

10
Ryujinx.HLE/OsHle/Services/Am/ISelfController.cs
View file

@ -27,6 +27,7 @@ namespace Ryujinx.HLE.OsHle.Services.Am
{ 13, SetFocusHandlingMode },
{ 14, SetRestartMessageEnabled },
{ 16, SetOutOfFocusSuspendingEnabled },
{ 19, SetScreenShotImageOrientation },
{ 50, SetHandlesRequestToDisplay }
};
@ -123,6 +124,15 @@ namespace Ryujinx.HLE.OsHle.Services.Am
return 0;
}
public long SetScreenShotImageOrientation(ServiceCtx Context)
{
int Orientation = Context.RequestData.ReadInt32();
Context.Ns.Log.PrintStub(LogClass.ServiceAm, "Stubbed.");
return 0;
}
public long SetHandlesRequestToDisplay(ServiceCtx Context)
{
bool Enable = Context.RequestData.ReadByte() != 0 ? true : false;

39
Ryujinx.HLE/OsHle/Services/IpcService.cs
View file

@ -50,9 +50,18 @@ namespace Ryujinx.HLE.OsHle.Services
int DomainWord0 = Context.RequestData.ReadInt32();
int DomainObjId = Context.RequestData.ReadInt32();
long Padding = Context.RequestData.ReadInt64();
int DomainCmd = (DomainWord0 >> 0) & 0xff;
int InputObjCount = (DomainWord0 >> 8) & 0xff;
int DataPayloadSize = (DomainWord0 >> 16) & 0xffff;
int DomainCmd = DomainWord0 & 0xff;
Context.RequestData.BaseStream.Seek(0x10 + DataPayloadSize, SeekOrigin.Begin);
for (int Index = 0; Index < InputObjCount; Index++)
{
Context.Request.ObjectIds.Add(Context.RequestData.ReadInt32());
}
Context.RequestData.BaseStream.Seek(0x10, SeekOrigin.Begin);
if (DomainCmd == 1)
{
@ -88,14 +97,14 @@ namespace Ryujinx.HLE.OsHle.Services
if (IsDomain)
{
foreach (int Id in Context.Response.ResponseObjIds)
foreach (int Id in Context.Response.ObjectIds)
{
Context.ResponseData.Write(Id);
}
Context.ResponseData.BaseStream.Seek(0, SeekOrigin.Begin);
Context.ResponseData.Write(Context.Response.ResponseObjIds.Count);
Context.ResponseData.Write(Context.Response.ObjectIds.Count);
}
Context.ResponseData.BaseStream.Seek(IsDomain ? 0x10 : 0, SeekOrigin.Begin);
@ -117,7 +126,7 @@ namespace Ryujinx.HLE.OsHle.Services
if (Service.IsDomain)
{
Context.Response.ResponseObjIds.Add(Service.Add(Obj));
Context.Response.ObjectIds.Add(Service.Add(Obj));
}
else
{
@ -129,6 +138,26 @@ namespace Ryujinx.HLE.OsHle.Services
}
}
protected static T GetObject<T>(ServiceCtx Context, int Index) where T : IpcService
{
IpcService Service = Context.Session.Service;
if (!Service.IsDomain)
{
int Handle = Context.Request.HandleDesc.ToMove[Index];
KSession Session = Context.Process.HandleTable.GetData<KSession>(Handle);
return Session?.Service is T ? (T)Session.Service : null;
}
int ObjId = Context.Request.ObjectIds[Index];
IIpcService Obj = Service.GetObject(ObjId);
return Obj is T ? (T)Obj : null;
}
private int Add(IIpcService Obj)
{
return DomainObjects.Add(Obj);

18
Ryujinx.HLE/OsHle/Services/Nifm/IRequest.cs
View file

@ -12,7 +12,8 @@ namespace Ryujinx.HLE.OsHle.Services.Nifm
public override IReadOnlyDictionary<int, ServiceProcessRequest> Commands => m_Commands;
private KEvent Event;
private KEvent Event0;
private KEvent Event1;
public IRequest()
{
@ -26,12 +27,13 @@ namespace Ryujinx.HLE.OsHle.Services.Nifm
{ 11, SetConnectionConfirmationOption }
};
Event = new KEvent();
Event0 = new KEvent();
Event1 = new KEvent();
}
public long GetRequestState(ServiceCtx Context)
{
Context.ResponseData.Write(0);
Context.ResponseData.Write(1);
Context.Ns.Log.PrintStub(LogClass.ServiceNifm, "Stubbed.");
@ -45,13 +47,12 @@ namespace Ryujinx.HLE.OsHle.Services.Nifm
return 0;
}
//GetSystemEventReadableHandles() -> (KObject, KObject)
public long GetSystemEventReadableHandles(ServiceCtx Context)
{
//FIXME: Is this supposed to return 2 events?
int Handle = Context.Process.HandleTable.OpenHandle(Event);
int Handle0 = Context.Process.HandleTable.OpenHandle(Event0);
int Handle1 = Context.Process.HandleTable.OpenHandle(Event1);
Context.Response.HandleDesc = IpcHandleDesc.MakeMove(Handle);
Context.Response.HandleDesc = IpcHandleDesc.MakeCopy(Handle0, Handle1);
return 0;
}
@ -86,7 +87,8 @@ namespace Ryujinx.HLE.OsHle.Services.Nifm
{
if (Disposing)
{
Event.Dispose();
Event0.Dispose();
Event1.Dispose();
}
}
}

72
Ryujinx.HLE/OsHle/Services/Pl/ISharedFontManager.cs
View file

@ -1,3 +1,4 @@
using Ryujinx.HLE.Font;
using Ryujinx.HLE.OsHle.Ipc;
using System.Collections.Generic;
@ -13,11 +14,12 @@ namespace Ryujinx.HLE.OsHle.Services.Pl
{
m_Commands = new Dictionary<int, ServiceProcessRequest>()
{
{ 0, RequestLoad },
{ 1, GetLoadState },
{ 2, GetFontSize },
{ 3, GetSharedMemoryAddressOffset },
{ 4, GetSharedMemoryNativeHandle }
{ 0, RequestLoad },
{ 1, GetLoadState },
{ 2, GetFontSize },
{ 3, GetSharedMemoryAddressOffset },
{ 4, GetSharedMemoryNativeHandle },
{ 5, GetSharedFontInOrderOfPriority }
};
}
@ -25,26 +27,34 @@ namespace Ryujinx.HLE.OsHle.Services.Pl
{
SharedFontType FontType = (SharedFontType)Context.RequestData.ReadInt32();
Context.Ns.Font.Load(FontType);
return 0;
}
public long GetLoadState(ServiceCtx Context)
{
Context.ResponseData.Write(1); //Loaded
SharedFontType FontType = (SharedFontType)Context.RequestData.ReadInt32();
Context.ResponseData.Write(Context.Ns.Font.GetLoadState(FontType));
return 0;
}
public long GetFontSize(ServiceCtx Context)
{
Context.ResponseData.Write(Horizon.FontSize);
SharedFontType FontType = (SharedFontType)Context.RequestData.ReadInt32();
Context.ResponseData.Write(Context.Ns.Font.GetFontSize(FontType));
return 0;
}
public long GetSharedMemoryAddressOffset(ServiceCtx Context)
{
Context.ResponseData.Write(0);
SharedFontType FontType = (SharedFontType)Context.RequestData.ReadInt32();
Context.ResponseData.Write(Context.Ns.Font.GetSharedMemoryAddressOffset(FontType));
return 0;
}
@ -57,5 +67,51 @@ namespace Ryujinx.HLE.OsHle.Services.Pl
return 0;
}
private uint AddFontToOrderOfPriorityList(ServiceCtx Context, SharedFontType FontType, uint BufferPos, out uint LoadState)
{
long TypesPosition = Context.Request.ReceiveBuff[0].Position;
long TypesSize = Context.Request.ReceiveBuff[0].Size;
long OffsetsPosition = Context.Request.ReceiveBuff[1].Position;
long OffsetsSize = Context.Request.ReceiveBuff[1].Size;
long FontSizeBufferPosition = Context.Request.ReceiveBuff[2].Position;
long FontSizeBufferSize = Context.Request.ReceiveBuff[2].Size;
LoadState = Context.Ns.Font.GetLoadState(FontType);
if (BufferPos >= TypesSize || BufferPos >= OffsetsSize || BufferPos >= FontSizeBufferSize)
{
return 0;
}
Context.Memory.WriteUInt32(TypesPosition + BufferPos, (uint)FontType);
Context.Memory.WriteUInt32(OffsetsPosition + BufferPos, Context.Ns.Font.GetSharedMemoryAddressOffset(FontType));
Context.Memory.WriteUInt32(FontSizeBufferPosition + BufferPos, Context.Ns.Font.GetFontSize(FontType));
BufferPos += 4;
return BufferPos;
}
public long GetSharedFontInOrderOfPriority(ServiceCtx Context)
{
ulong LanguageCode = Context.RequestData.ReadUInt64();
uint LoadedCount = 0;
uint BufferPos = 0;
uint Loaded = 0;
for (int Type = 0; Type < Context.Ns.Font.Count; Type++)
{
BufferPos = AddFontToOrderOfPriorityList(Context, (SharedFontType)Type, BufferPos, out Loaded);
LoadedCount += Loaded;
}
Context.ResponseData.Write(LoadedCount);
Context.ResponseData.Write(Context.Ns.Font.Count);
return 0;
}
}
}

1
Ryujinx.HLE/OsHle/SystemStateMgr.cs
View file

@ -1,3 +1,4 @@
using Ryujinx.HLE.Loaders.Npdm;
using System;
namespace Ryujinx.HLE.OsHle

13
Ryujinx.HLE/Resource/InvalidSystemResourceException.cs Normal file
View file

@ -0,0 +1,13 @@
using System;
namespace Ryujinx.HLE.Resource
{
public class InvalidSystemResourceException : Exception
{
public InvalidSystemResourceException(string message)
: base(message)
{
}
}
}

2
Ryujinx.HLE/Ryujinx.HLE.csproj
View file

@ -1,4 +1,4 @@
<Project Sdk="Microsoft.NET.Sdk">
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<TargetFramework>netcoreapp2.1</TargetFramework>

12
Ryujinx.HLE/Switch.cs
View file

@ -1,5 +1,6 @@
using Ryujinx.Audio;
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Font;
using Ryujinx.HLE.Gpu;
using Ryujinx.HLE.Input;
using Ryujinx.HLE.Logging;
@ -27,6 +28,8 @@ namespace Ryujinx.HLE
public Hid Hid { get; private set; }
public SharedFontManager Font { get; private set; }
public event EventHandler Finish;
public Switch(IGalRenderer Renderer, IAalOutput AudioOut)
@ -57,8 +60,13 @@ namespace Ryujinx.HLE
Hid = new Hid(Log);
Os.HidSharedMem.MemoryMapped += Hid.ShMemMap;
Os.HidSharedMem.MemoryUnmapped += Hid.ShMemUnmap;
Font = new SharedFontManager(Log, VFs.GetSystemPath());
Os.HidSharedMem.MemoryMapped += Hid.ShMemMap;
Os.HidSharedMem.MemoryUnmapped += Hid.ShMemUnmap;
Os.FontSharedMem.MemoryMapped += Font.ShMemMap;
Os.FontSharedMem.MemoryUnmapped += Font.ShMemUnmap;
}
public void LoadCart(string ExeFsDir, string RomFsFile = null)

3
Ryujinx.HLE/VirtualFileSystem.cs
View file

@ -8,6 +8,7 @@ namespace Ryujinx.HLE
private const string BasePath = "RyuFs";
private const string NandPath = "nand";
private const string SdCardPath = "sdmc";
private const string SystemPath = "system";
public Stream RomFs { get; private set; }
@ -45,6 +46,8 @@ namespace Ryujinx.HLE
public string GetGameSavesPath() => MakeDirAndGetFullPath(NandPath);
public string GetSystemPath() => MakeDirAndGetFullPath(SystemPath);
public string SwitchPathToSystemPath(string SwitchPath)
{
string[] Parts = SwitchPath.Split(":");

446
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View file

@ -22,6 +22,17 @@ namespace Ryujinx.Tests.Cpu
}
#region "ValueSource"
private static ulong[] _1B1H1S1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
0x0000000000000080ul, 0x00000000000000FFul,
0x0000000000007FFFul, 0x0000000000008000ul,
0x000000000000FFFFul, 0x000000007FFFFFFFul,
0x0000000080000000ul, 0x00000000FFFFFFFFul,
0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
@ -1126,6 +1137,192 @@ namespace Ryujinx.Tests.Cpu
});
}
[Test, Description("SQABS <V><d>, <V><n>")]
public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x5E207800; // SQABS B0, B0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqabs_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E207800; // SQABS V0.8B, V0.8B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x4E207800; // SQABS V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQNEG <V><d>, <V><n>")]
public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x7E207800; // SQNEG B0, B0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqneg_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E207800; // SQNEG V0.8B, V0.8B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x6E207800; // SQNEG V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTN <Vb><d>, <Va><n>")]
public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
@ -1138,12 +1335,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1151,7 +1351,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1166,12 +1366,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1179,7 +1382,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1194,12 +1397,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1207,7 +1413,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
@ -1222,12 +1428,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1235,7 +1444,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1250,12 +1459,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1263,7 +1475,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1278,12 +1490,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1291,7 +1506,100 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SUQADD <V><d>, <V><n>")]
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x5E203800; // SUQADD B0, B0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Suqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E203800; // SUQADD V0.8B, V0.8B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x4E203800; // SUQADD V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
@ -1306,12 +1614,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1319,7 +1630,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1334,12 +1645,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1347,7 +1661,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
@ -1362,12 +1676,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
@ -1375,7 +1692,100 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("USQADD <V><d>, <V><n>")]
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x7E203800; // USQADD B0, B0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Usqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E203800; // USQADD V0.8B, V0.8B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x6E203800; // USQADD V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]

24
Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
View file

@ -19,9 +19,9 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x1E224820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x000000007F7FFFFFul)]
[TestCase(0x1E224820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
[TestCase(0x1E224820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
[TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
[TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
[TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
[TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)]
[TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)]
[TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)]
[TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)]
[TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
[TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
@ -45,9 +45,9 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)]
[TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
[TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)]
[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")]
[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u)]
[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u)]
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)]
public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
{
uint Opcode = 0x4E22F420;
@ -71,9 +71,9 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x1E225820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x00000000807FFFFFul)]
[TestCase(0x1E225820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
[TestCase(0x1E225820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
[TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
[TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
[TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
[TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)]
[TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)]
[TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)]
[TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
@ -97,9 +97,9 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu)]
[TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
[TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)]
[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")]
[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u)]
[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u)]
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)]
public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
{
uint Opcode = 0x4EA2F420;

431
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
View file

@ -22,6 +22,17 @@ namespace Ryujinx.Tests.Cpu
}
#region "ValueSource"
private static ulong[] _1B1H1S1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
0x0000000000000080ul, 0x00000000000000FFul,
0x0000000000007FFFul, 0x0000000000008000ul,
0x000000000000FFFFul, 0x000000007FFFFFFFul,
0x0000000080000000ul, 0x00000000FFFFFFFFul,
0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
@ -1721,6 +1732,216 @@ namespace Ryujinx.Tests.Cpu
});
}
[Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x5E200C00; // SQADD B0, B0, B0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E200C00; // SQADD V0.8B, V0.8B, V0.8B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x4E200C00; // SQADD V0.16B, V0.16B, V0.16B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
Vector128<float> V2 = MakeVectorE0E1(B, B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SQSUB <V><d>, <V><n>, <V><m>")]
public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x5E202C00; // SQSUB B0, B0, B0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E202C00; // SQSUB V0.8B, V0.8B, V0.8B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x4E202C00; // SQSUB V0.16B, V0.16B, V0.16B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
Vector128<float> V2 = MakeVectorE0E1(B, B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
@ -2370,6 +2591,216 @@ namespace Ryujinx.Tests.Cpu
});
}
[Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x7E200C00; // UQADD B0, B0, B0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E200C00; // UQADD V0.8B, V0.8B, V0.8B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x6E200C00; // UQADD V0.16B, V0.16B, V0.16B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
Vector128<float> V2 = MakeVectorE0E1(B, B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("UQSUB <V><d>, <V><n>, <V><m>")]
public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
{
uint Opcode = 0x7E202C00; // UQSUB B0, B0, B0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E202C00; // UQSUB V0.8B, V0.8B, V0.8B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.V(1, new Bits(A));
AArch64.V(2, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x6E202C00; // UQSUB V0.16B, V0.16B, V0.16B
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
Vector128<float> V2 = MakeVectorE0E1(B, B);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
Shared.FPSR = new Bits((uint)Fpsr);
SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
}
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,

776
Ryujinx.Tests/Cpu/Tester/Instructions.cs
View file

@ -3060,6 +3060,210 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// sqabs_advsimd.html#SQABS_asisdmisc_R
public static void Sqabs_S(Bits size, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool neg = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
BigInteger element;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element = SInt(Elem(operand, e, esize));
if (neg)
{
element = -element;
}
else
{
element = Abs(element);
}
(Bits _result, bool _sat) = SignedSatQ(element, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqabs_advsimd.html#SQABS_asimdmisc_R
public static void Sqabs_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool neg = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
BigInteger element;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element = SInt(Elem(operand, e, esize));
if (neg)
{
element = -element;
}
else
{
element = Abs(element);
}
(Bits _result, bool _sat) = SignedSatQ(element, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqneg_advsimd.html#SQNEG_asisdmisc_R
public static void Sqneg_S(Bits size, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool neg = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
BigInteger element;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element = SInt(Elem(operand, e, esize));
if (neg)
{
element = -element;
}
else
{
element = Abs(element);
}
(Bits _result, bool _sat) = SignedSatQ(element, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqneg_advsimd.html#SQNEG_asimdmisc_R
public static void Sqneg_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool neg = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
BigInteger element;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element = SInt(Elem(operand, e, esize));
if (neg)
{
element = -element;
}
else
{
element = Abs(element);
}
(Bits _result, bool _sat) = SignedSatQ(element, esize);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqxtn_advsimd.html#SQXTN_asisdmisc_N
public static void Sqxtn_S(Bits size, Bits Rn, Bits Rd)
{
@ -3228,6 +3432,96 @@ namespace Ryujinx.Tests.Cpu.Tester
Vpart(d, part, result);
}
// suqadd_advsimd.html#SUQADD_asisdmisc_R
public static void Suqadd_S(Bits size, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
Bits operand2 = V(datasize, d);
BigInteger op1;
BigInteger op2;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
op1 = Int(Elem(operand, e, esize), !unsigned);
op2 = Int(Elem(operand2, e, esize), unsigned);
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// suqadd_advsimd.html#SUQADD_asimdmisc_R
public static void Suqadd_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
Bits operand2 = V(datasize, d);
BigInteger op1;
BigInteger op2;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
op1 = Int(Elem(operand, e, esize), !unsigned);
op2 = Int(Elem(operand2, e, esize), unsigned);
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// uqxtn_advsimd.html#UQXTN_asisdmisc_N
public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd)
{
@ -3316,6 +3610,96 @@ namespace Ryujinx.Tests.Cpu.Tester
Vpart(d, part, result);
}
// usqadd_advsimd.html#USQADD_asisdmisc_R
public static void Usqadd_S(Bits size, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
Bits operand2 = V(datasize, d);
BigInteger op1;
BigInteger op2;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
op1 = Int(Elem(operand, e, esize), !unsigned);
op2 = Int(Elem(operand2, e, esize), unsigned);
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// usqadd_advsimd.html#USQADD_asimdmisc_R
public static void Usqadd_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand = V(datasize, n);
Bits operand2 = V(datasize, d);
BigInteger op1;
BigInteger op2;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
op1 = Int(Elem(operand, e, esize), !unsigned);
op2 = Int(Elem(operand2, e, esize), unsigned);
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// xtn_advsimd.html
public static void Xtn_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
@ -4593,6 +4977,202 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// sqadd_advsimd.html#SQADD_asisdsame_only
public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger sum;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
sum = element1 + element2;
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqadd_advsimd.html#SQADD_asimdsame_only
public static void Sqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger sum;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
sum = element1 + element2;
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqsub_advsimd.html#SQSUB_asisdsame_only
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger diff;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
diff = element1 - element2;
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// sqsub_advsimd.html#SQSUB_asimdsame_only
public static void Sqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = false;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger diff;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
diff = element1 - element2;
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// ssubw_advsimd.html
public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
@ -5085,6 +5665,202 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// uqadd_advsimd.html#UQADD_asisdsame_only
public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger sum;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
sum = element1 + element2;
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// uqadd_advsimd.html#UQADD_asimdsame_only
public static void Uqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger sum;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
sum = element1 + element2;
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// uqsub_advsimd.html#UQSUB_asisdsame_only
public static void Uqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
int esize = 8 << (int)UInt(size);
int datasize = esize;
int elements = 1;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger diff;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
diff = element1 - element2;
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// uqsub_advsimd.html#UQSUB_asimdsame_only
public static void Uqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
const bool U = true;
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
bool unsigned = (U == true);
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
BigInteger element1;
BigInteger element2;
BigInteger diff;
bool sat;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Int(Elem(operand1, e, esize), unsigned);
element2 = Int(Elem(operand2, e, esize), unsigned);
diff = element1 - element2;
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
Elem(result, e, esize, _result);
sat = _sat;
if (sat)
{
/* FPSR.QC = '1'; */
FPSR[27] = true; // TODO: Add named fields.
}
}
V(d, result);
}
// usubw_advsimd.html
public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{

4
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
View file

@ -1193,9 +1193,9 @@ namespace Ryujinx.Tests.Cpu.Tester
result = BigInteger.Pow(2, N) - 1;
saturated = true;
}
else if (i < 0)
else if (i < (BigInteger)0)
{
result = 0;
result = (BigInteger)0;
saturated = true;
}
else

102
Ryujinx/Config.cs
View file

@ -14,11 +14,6 @@ namespace Ryujinx
public static JoyConKeyboard JoyConKeyboard { get; private set; }
public static JoyConController JoyConController { get; private set; }
public static float GamePadDeadzone { get; private set; }
public static bool GamePadEnable { get; private set; }
public static int GamePadIndex { get; private set; }
public static float GamePadTriggerThreshold { get; private set; }
public static void Read(Logger Log)
{
string IniFolder = Path.GetDirectoryName(Assembly.GetEntryAssembly().Location);
@ -37,11 +32,6 @@ namespace Ryujinx
Log.SetEnable(LogLevel.Warning, Convert.ToBoolean(Parser.Value("Logging_Enable_Warn")));
Log.SetEnable(LogLevel.Error, Convert.ToBoolean(Parser.Value("Logging_Enable_Error")));
GamePadEnable = Convert.ToBoolean(Parser.Value("GamePad_Enable"));
GamePadIndex = Convert.ToInt32 (Parser.Value("GamePad_Index"));
GamePadDeadzone = (float)Convert.ToDouble (Parser.Value("GamePad_Deadzone"), CultureInfo.InvariantCulture);
GamePadTriggerThreshold = (float)Convert.ToDouble (Parser.Value("GamePad_Trigger_Threshold"), CultureInfo.InvariantCulture);
string[] FilteredLogClasses = Parser.Value("Logging_Filtered_Classes").Split(',', StringSplitOptions.RemoveEmptyEntries);
//When the classes are specified on the list, we only
@ -70,9 +60,9 @@ namespace Ryujinx
}
}
JoyConKeyboard = new JoyConKeyboard
{
Left = new JoyConKeyboardLeft
JoyConKeyboard = new JoyConKeyboard(
new JoyConKeyboardLeft
{
StickUp = Convert.ToInt16(Parser.Value("Controls_Left_JoyConKeyboard_Stick_Up")),
StickDown = Convert.ToInt16(Parser.Value("Controls_Left_JoyConKeyboard_Stick_Down")),
@ -88,7 +78,7 @@ namespace Ryujinx
ButtonZL = Convert.ToInt16(Parser.Value("Controls_Left_JoyConKeyboard_Button_ZL"))
},
Right = new JoyConKeyboardRight
new JoyConKeyboardRight
{
StickUp = Convert.ToInt16(Parser.Value("Controls_Right_JoyConKeyboard_Stick_Up")),
StickDown = Convert.ToInt16(Parser.Value("Controls_Right_JoyConKeyboard_Stick_Down")),
@ -102,37 +92,69 @@ namespace Ryujinx
ButtonPlus = Convert.ToInt16(Parser.Value("Controls_Right_JoyConKeyboard_Button_Plus")),
ButtonR = Convert.ToInt16(Parser.Value("Controls_Right_JoyConKeyboard_Button_R")),
ButtonZR = Convert.ToInt16(Parser.Value("Controls_Right_JoyConKeyboard_Button_ZR"))
}
};
});
JoyConController = new JoyConController
{
Left = new JoyConControllerLeft
JoyConController = new JoyConController(
Convert.ToBoolean(Parser.Value("GamePad_Enable")),
Convert.ToInt32 (Parser.Value("GamePad_Index")),
(float)Convert.ToDouble (Parser.Value("GamePad_Deadzone"), CultureInfo.InvariantCulture),
(float)Convert.ToDouble (Parser.Value("GamePad_Trigger_Threshold"), CultureInfo.InvariantCulture),
new JoyConControllerLeft
{
Stick = Parser.Value("Controls_Left_JoyConController_Stick"),
StickButton = Parser.Value("Controls_Left_JoyConController_Stick_Button"),
DPadUp = Parser.Value("Controls_Left_JoyConController_DPad_Up"),
DPadDown = Parser.Value("Controls_Left_JoyConController_DPad_Down"),
DPadLeft = Parser.Value("Controls_Left_JoyConController_DPad_Left"),
DPadRight = Parser.Value("Controls_Left_JoyConController_DPad_Right"),
ButtonMinus = Parser.Value("Controls_Left_JoyConController_Button_Minus"),
ButtonL = Parser.Value("Controls_Left_JoyConController_Button_L"),
ButtonZL = Parser.Value("Controls_Left_JoyConController_Button_ZL")
Stick = ToID(Parser.Value("Controls_Left_JoyConController_Stick")),
StickButton = ToID(Parser.Value("Controls_Left_JoyConController_Stick_Button")),
DPadUp = ToID(Parser.Value("Controls_Left_JoyConController_DPad_Up")),
DPadDown = ToID(Parser.Value("Controls_Left_JoyConController_DPad_Down")),
DPadLeft = ToID(Parser.Value("Controls_Left_JoyConController_DPad_Left")),
DPadRight = ToID(Parser.Value("Controls_Left_JoyConController_DPad_Right")),
ButtonMinus = ToID(Parser.Value("Controls_Left_JoyConController_Button_Minus")),
ButtonL = ToID(Parser.Value("Controls_Left_JoyConController_Button_L")),
ButtonZL = ToID(Parser.Value("Controls_Left_JoyConController_Button_ZL"))
},
Right = new JoyConControllerRight
new JoyConControllerRight
{
Stick = Parser.Value("Controls_Right_JoyConController_Stick"),
StickButton = Parser.Value("Controls_Right_JoyConController_Stick_Button"),
ButtonA = Parser.Value("Controls_Right_JoyConController_Button_A"),
ButtonB = Parser.Value("Controls_Right_JoyConController_Button_B"),
ButtonX = Parser.Value("Controls_Right_JoyConController_Button_X"),
ButtonY = Parser.Value("Controls_Right_JoyConController_Button_Y"),
ButtonPlus = Parser.Value("Controls_Right_JoyConController_Button_Plus"),
ButtonR = Parser.Value("Controls_Right_JoyConController_Button_R"),
ButtonZR = Parser.Value("Controls_Right_JoyConController_Button_ZR")
}
};
Stick = ToID(Parser.Value("Controls_Right_JoyConController_Stick")),
StickButton = ToID(Parser.Value("Controls_Right_JoyConController_Stick_Button")),
ButtonA = ToID(Parser.Value("Controls_Right_JoyConController_Button_A")),
ButtonB = ToID(Parser.Value("Controls_Right_JoyConController_Button_B")),
ButtonX = ToID(Parser.Value("Controls_Right_JoyConController_Button_X")),
ButtonY = ToID(Parser.Value("Controls_Right_JoyConController_Button_Y")),
ButtonPlus = ToID(Parser.Value("Controls_Right_JoyConController_Button_Plus")),
ButtonR = ToID(Parser.Value("Controls_Right_JoyConController_Button_R")),
ButtonZR = ToID(Parser.Value("Controls_Right_JoyConController_Button_ZR"))
});
}
private static ControllerInputID ToID(string Key)
{
switch (Key.ToUpper())
{
case "LSTICK": return ControllerInputID.LStick;
case "DPADUP": return ControllerInputID.DPadUp;
case "DPADDOWN": return ControllerInputID.DPadDown;
case "DPADLEFT": return ControllerInputID.DPadLeft;
case "DPADRIGHT": return ControllerInputID.DPadRight;
case "BACK": return ControllerInputID.Back;
case "LSHOULDER": return ControllerInputID.LShoulder;
case "LTRIGGER": return ControllerInputID.LTrigger;
case "RSTICK": return ControllerInputID.RStick;
case "A": return ControllerInputID.A;
case "B": return ControllerInputID.B;
case "X": return ControllerInputID.X;
case "Y": return ControllerInputID.Y;
case "START": return ControllerInputID.Start;
case "RSHOULDER": return ControllerInputID.RShoulder;
case "RTRIGGER": return ControllerInputID.RTrigger;
case "LJOYSTICK": return ControllerInputID.LJoystick;
case "RJOYSTICK": return ControllerInputID.RJoystick;
default: return ControllerInputID.Invalid;
}
}
}

188
Ryujinx/Ui/GLScreen.cs
View file

@ -4,6 +4,7 @@ using OpenTK.Input;
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE;
using Ryujinx.HLE.Input;
using Ryujinx.UI.Input;
using System;
using System.Threading;
@ -16,9 +17,6 @@ namespace Ryujinx
private const int TouchScreenWidth = 1280;
private const int TouchScreenHeight = 720;
private const float TouchScreenRatioX = (float)TouchScreenWidth / TouchScreenHeight;
private const float TouchScreenRatioY = (float)TouchScreenHeight / TouchScreenWidth;
private const int TargetFPS = 60;
private Switch Ns;
@ -49,10 +47,6 @@ namespace Ryujinx
Location = new Point(
(DisplayDevice.Default.Width / 2) - (Width / 2),
(DisplayDevice.Default.Height / 2) - (Height / 2));
ResizeEvent = false;
TitleEvent = false;
}
private void RenderLoop()
@ -127,60 +121,9 @@ namespace Ryujinx
Title = NewTitle;
}
}
}
}
private bool IsGamePadButtonPressedFromString(GamePadState GamePad, string Button)
{
if (Button.ToUpper() == "LTRIGGER" || Button.ToUpper() == "RTRIGGER")
{
return GetGamePadTriggerFromString(GamePad, Button) >= Config.GamePadTriggerThreshold;
}
else
{
return (GetGamePadButtonFromString(GamePad, Button) == ButtonState.Pressed);
}
}
private ButtonState GetGamePadButtonFromString(GamePadState GamePad, string Button)
{
switch (Button.ToUpper())
{
case "A": return GamePad.Buttons.A;
case "B": return GamePad.Buttons.B;
case "X": return GamePad.Buttons.X;
case "Y": return GamePad.Buttons.Y;
case "LSTICK": return GamePad.Buttons.LeftStick;
case "RSTICK": return GamePad.Buttons.RightStick;
case "LSHOULDER": return GamePad.Buttons.LeftShoulder;
case "RSHOULDER": return GamePad.Buttons.RightShoulder;
case "DPADUP": return GamePad.DPad.Up;
case "DPADDOWN": return GamePad.DPad.Down;
case "DPADLEFT": return GamePad.DPad.Left;
case "DPADRIGHT": return GamePad.DPad.Right;
case "START": return GamePad.Buttons.Start;
case "BACK": return GamePad.Buttons.Back;
default: throw new ArgumentException();
}
}
private float GetGamePadTriggerFromString(GamePadState GamePad, string Trigger)
{
switch (Trigger.ToUpper())
{
case "LTRIGGER": return GamePad.Triggers.Left;
case "RTRIGGER": return GamePad.Triggers.Right;
default: throw new ArgumentException();
}
}
private Vector2 GetJoystickAxisFromString(GamePadState GamePad, string Joystick)
{
switch (Joystick.ToUpper())
{
case "LJOYSTICK": return GamePad.ThumbSticks.Left;
case "RJOYSTICK": return new Vector2(-GamePad.ThumbSticks.Right.Y, -GamePad.ThumbSticks.Right.X);
default: throw new ArgumentException();
//Polling becomes expensive if it's not slept
Thread.Sleep(1);
}
}
@ -190,95 +133,37 @@ namespace Ryujinx
HidJoystickPosition LeftJoystick;
HidJoystickPosition RightJoystick;
int LeftJoystickDX = 0;
int LeftJoystickDY = 0;
int RightJoystickDX = 0;
int RightJoystickDY = 0;
float AnalogStickDeadzone = Config.GamePadDeadzone;
int LeftJoystickDX = 0;
int LeftJoystickDY = 0;
int RightJoystickDX = 0;
int RightJoystickDY = 0;
//Keyboard Input
if (Keyboard.HasValue)
{
KeyboardState Keyboard = this.Keyboard.Value;
if (Keyboard[Key.Escape]) this.Exit();
CurrentButton = Config.JoyConKeyboard.GetButtons(Keyboard);
//LeftJoystick
if (Keyboard[(Key)Config.JoyConKeyboard.Left.StickUp]) LeftJoystickDY = short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.StickDown]) LeftJoystickDY = -short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.StickLeft]) LeftJoystickDX = -short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.StickRight]) LeftJoystickDX = short.MaxValue;
(LeftJoystickDX, LeftJoystickDY) = Config.JoyConKeyboard.GetLeftStick(Keyboard);
//LeftButtons
if (Keyboard[(Key)Config.JoyConKeyboard.Left.StickButton]) CurrentButton |= HidControllerButtons.KEY_LSTICK;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.DPadUp]) CurrentButton |= HidControllerButtons.KEY_DUP;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.DPadDown]) CurrentButton |= HidControllerButtons.KEY_DDOWN;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.DPadLeft]) CurrentButton |= HidControllerButtons.KEY_DLEFT;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.DPadRight]) CurrentButton |= HidControllerButtons.KEY_DRIGHT;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.ButtonMinus]) CurrentButton |= HidControllerButtons.KEY_MINUS;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.ButtonL]) CurrentButton |= HidControllerButtons.KEY_L;
if (Keyboard[(Key)Config.JoyConKeyboard.Left.ButtonZL]) CurrentButton |= HidControllerButtons.KEY_ZL;
//RightJoystick
if (Keyboard[(Key)Config.JoyConKeyboard.Right.StickUp]) RightJoystickDY = short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.StickDown]) RightJoystickDY = -short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.StickLeft]) RightJoystickDX = -short.MaxValue;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.StickRight]) RightJoystickDX = short.MaxValue;
//RightButtons
if (Keyboard[(Key)Config.JoyConKeyboard.Right.StickButton]) CurrentButton |= HidControllerButtons.KEY_RSTICK;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonA]) CurrentButton |= HidControllerButtons.KEY_A;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonB]) CurrentButton |= HidControllerButtons.KEY_B;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonX]) CurrentButton |= HidControllerButtons.KEY_X;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonY]) CurrentButton |= HidControllerButtons.KEY_Y;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonPlus]) CurrentButton |= HidControllerButtons.KEY_PLUS;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonR]) CurrentButton |= HidControllerButtons.KEY_R;
if (Keyboard[(Key)Config.JoyConKeyboard.Right.ButtonZR]) CurrentButton |= HidControllerButtons.KEY_ZR;
(RightJoystickDX, RightJoystickDY) = Config.JoyConKeyboard.GetRightStick(Keyboard);
}
//Controller Input
if (Config.GamePadEnable)
CurrentButton |= Config.JoyConController.GetButtons();
//Keyboard has priority stick-wise
if (LeftJoystickDX == 0 && LeftJoystickDY == 0)
{
GamePadState GamePad = OpenTK.Input.GamePad.GetState(Config.GamePadIndex);
//LeftButtons
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.DPadUp)) CurrentButton |= HidControllerButtons.KEY_DUP;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.DPadDown)) CurrentButton |= HidControllerButtons.KEY_DDOWN;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.DPadLeft)) CurrentButton |= HidControllerButtons.KEY_DLEFT;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.DPadRight)) CurrentButton |= HidControllerButtons.KEY_DRIGHT;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.StickButton)) CurrentButton |= HidControllerButtons.KEY_LSTICK;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.ButtonMinus)) CurrentButton |= HidControllerButtons.KEY_MINUS;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.ButtonL)) CurrentButton |= HidControllerButtons.KEY_L;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Left.ButtonZL)) CurrentButton |= HidControllerButtons.KEY_ZL;
//RightButtons
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonA)) CurrentButton |= HidControllerButtons.KEY_A;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonB)) CurrentButton |= HidControllerButtons.KEY_B;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonX)) CurrentButton |= HidControllerButtons.KEY_X;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonY)) CurrentButton |= HidControllerButtons.KEY_Y;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.StickButton)) CurrentButton |= HidControllerButtons.KEY_RSTICK;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonPlus)) CurrentButton |= HidControllerButtons.KEY_PLUS;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonR)) CurrentButton |= HidControllerButtons.KEY_R;
if (IsGamePadButtonPressedFromString(GamePad, Config.JoyConController.Right.ButtonZR)) CurrentButton |= HidControllerButtons.KEY_ZR;
//LeftJoystick
if (GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).X >= AnalogStickDeadzone
|| GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).X <= -AnalogStickDeadzone)
LeftJoystickDX = (int)(GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).X * short.MaxValue);
if (GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).Y >= AnalogStickDeadzone
|| GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).Y <= -AnalogStickDeadzone)
LeftJoystickDY = (int)(GetJoystickAxisFromString(GamePad, Config.JoyConController.Left.Stick).Y * short.MaxValue);
//RightJoystick
if (GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).X >= AnalogStickDeadzone
|| GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).X <= -AnalogStickDeadzone)
RightJoystickDX = (int)(GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).X * short.MaxValue);
if (GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).Y >= AnalogStickDeadzone
|| GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).Y <= -AnalogStickDeadzone)
RightJoystickDY = (int)(GetJoystickAxisFromString(GamePad, Config.JoyConController.Right.Stick).Y * short.MaxValue);
(LeftJoystickDX, LeftJoystickDY) = Config.JoyConController.GetLeftStick();
}
if (RightJoystickDX == 0 && RightJoystickDY == 0)
{
(RightJoystickDX, RightJoystickDY) = Config.JoyConController.GetRightStick();
}
LeftJoystick = new HidJoystickPosition
{
DX = LeftJoystickDX,
@ -302,13 +187,13 @@ namespace Ryujinx
int ScrnWidth = Width;
int ScrnHeight = Height;
if (Width > Height * TouchScreenRatioX)
if (Width > (Height * TouchScreenWidth) / TouchScreenHeight)
{
ScrnWidth = (int)(Height * TouchScreenRatioX);
ScrnWidth = (Height * TouchScreenWidth) / TouchScreenHeight;
}
else
{
ScrnHeight = (int)(Width * TouchScreenRatioY);
ScrnHeight = (Width * TouchScreenHeight) / TouchScreenWidth;
}
int StartX = (Width - ScrnWidth) >> 1;
@ -325,8 +210,8 @@ namespace Ryujinx
int ScrnMouseX = Mouse.X - StartX;
int ScrnMouseY = Mouse.Y - StartY;
int MX = (int)(((float)ScrnMouseX / ScrnWidth) * TouchScreenWidth);
int MY = (int)(((float)ScrnMouseY / ScrnHeight) * TouchScreenHeight);
int MX = (ScrnMouseX * TouchScreenWidth) / ScrnWidth;
int MY = (ScrnMouseY * TouchScreenHeight) / ScrnHeight;
HidTouchPoint CurrentPoint = new HidTouchPoint
{
@ -397,6 +282,29 @@ namespace Ryujinx
protected override void OnKeyDown(KeyboardKeyEventArgs e)
{
bool ToggleFullscreen = e.Key == Key.F11 ||
(e.Modifiers.HasFlag(KeyModifiers.Alt) && e.Key == Key.Enter);
if (WindowState == WindowState.Fullscreen)
{
if (e.Key == Key.Escape || ToggleFullscreen)
{
WindowState = WindowState.Normal;
}
}
else
{
if (e.Key == Key.Escape)
{
Exit();
}
if (ToggleFullscreen)
{
WindowState = WindowState.Fullscreen;
}
}
Keyboard = e.Keyboard;
}

226
Ryujinx/Ui/JoyConController.cs
View file

@ -1,38 +1,216 @@
using System;
using System.Collections.Generic;
using System.Text;
using OpenTK;
using OpenTK.Input;
using Ryujinx.HLE.Input;
using System;
namespace Ryujinx.UI.Input
{
public enum ControllerInputID
{
Invalid,
LStick,
DPadUp,
DPadDown,
DPadLeft,
DPadRight,
Back,
LShoulder,
RStick,
A,
B,
X,
Y,
Start,
RShoulder,
LTrigger,
RTrigger,
LJoystick,
RJoystick
}
public struct JoyConControllerLeft
{
public string Stick;
public string StickButton;
public string DPadUp;
public string DPadDown;
public string DPadLeft;
public string DPadRight;
public string ButtonMinus;
public string ButtonL;
public string ButtonZL;
public ControllerInputID Stick;
public ControllerInputID StickButton;
public ControllerInputID DPadUp;
public ControllerInputID DPadDown;
public ControllerInputID DPadLeft;
public ControllerInputID DPadRight;
public ControllerInputID ButtonMinus;
public ControllerInputID ButtonL;
public ControllerInputID ButtonZL;
}
public struct JoyConControllerRight
{
public string Stick;
public string StickButton;
public string ButtonA;
public string ButtonB;
public string ButtonX;
public string ButtonY;
public string ButtonPlus;
public string ButtonR;
public string ButtonZR;
public ControllerInputID Stick;
public ControllerInputID StickButton;
public ControllerInputID ButtonA;
public ControllerInputID ButtonB;
public ControllerInputID ButtonX;
public ControllerInputID ButtonY;
public ControllerInputID ButtonPlus;
public ControllerInputID ButtonR;
public ControllerInputID ButtonZR;
}
public struct JoyConController
public class JoyConController
{
public JoyConControllerLeft Left;
public JoyConControllerRight Right;
public bool Enabled { private set; get; }
public int Index { private set; get; }
public float Deadzone { private set; get; }
public float TriggerThreshold { private set; get; }
public JoyConControllerLeft Left { private set; get; }
public JoyConControllerRight Right { private set; get; }
public JoyConController(
bool Enabled,
int Index,
float Deadzone,
float TriggerThreshold,
JoyConControllerLeft Left,
JoyConControllerRight Right)
{
this.Enabled = Enabled;
this.Index = Index;
this.Deadzone = Deadzone;
this.TriggerThreshold = TriggerThreshold;
this.Left = Left;
this.Right = Right;
//Unmapped controllers are problematic, skip them
if (GamePad.GetName(Index) == "Unmapped Controller")
{
this.Enabled = false;
}
}
public HidControllerButtons GetButtons()
{
if (!Enabled)
{
return 0;
}
GamePadState GpState = GamePad.GetState(Index);
HidControllerButtons Buttons = 0;
if (IsPressed(GpState, Left.DPadUp)) Buttons |= HidControllerButtons.KEY_DUP;
if (IsPressed(GpState, Left.DPadDown)) Buttons |= HidControllerButtons.KEY_DDOWN;
if (IsPressed(GpState, Left.DPadLeft)) Buttons |= HidControllerButtons.KEY_DLEFT;
if (IsPressed(GpState, Left.DPadRight)) Buttons |= HidControllerButtons.KEY_DRIGHT;
if (IsPressed(GpState, Left.StickButton)) Buttons |= HidControllerButtons.KEY_LSTICK;
if (IsPressed(GpState, Left.ButtonMinus)) Buttons |= HidControllerButtons.KEY_MINUS;
if (IsPressed(GpState, Left.ButtonL)) Buttons |= HidControllerButtons.KEY_L;
if (IsPressed(GpState, Left.ButtonZL)) Buttons |= HidControllerButtons.KEY_ZL;
if (IsPressed(GpState, Right.ButtonA)) Buttons |= HidControllerButtons.KEY_A;
if (IsPressed(GpState, Right.ButtonB)) Buttons |= HidControllerButtons.KEY_B;
if (IsPressed(GpState, Right.ButtonX)) Buttons |= HidControllerButtons.KEY_X;
if (IsPressed(GpState, Right.ButtonY)) Buttons |= HidControllerButtons.KEY_Y;
if (IsPressed(GpState, Right.StickButton)) Buttons |= HidControllerButtons.KEY_RSTICK;
if (IsPressed(GpState, Right.ButtonPlus)) Buttons |= HidControllerButtons.KEY_PLUS;
if (IsPressed(GpState, Right.ButtonR)) Buttons |= HidControllerButtons.KEY_R;
if (IsPressed(GpState, Right.ButtonZR)) Buttons |= HidControllerButtons.KEY_ZR;
return Buttons;
}
public (short, short) GetLeftStick()
{
if (!Enabled)
{
return (0, 0);
}
return GetStick(Left.Stick);
}
public (short, short) GetRightStick()
{
if (!Enabled)
{
return (0, 0);
}
return GetStick(Right.Stick);
}
private (short, short) GetStick(ControllerInputID Joystick)
{
GamePadState GpState = GamePad.GetState(Index);
switch (Joystick)
{
case ControllerInputID.LJoystick:
return ApplyDeadzone(GpState.ThumbSticks.Left);
case ControllerInputID.RJoystick:
return ApplyDeadzone(GpState.ThumbSticks.Right);
default:
return (0, 0);
}
}
private (short, short) ApplyDeadzone(Vector2 Axis)
{
return (ClampAxis(MathF.Abs(Axis.X) > Deadzone ? Axis.X : 0f),
ClampAxis(MathF.Abs(Axis.Y) > Deadzone ? Axis.Y : 0f));
}
private static short ClampAxis(float Value)
{
if (Value <= -short.MaxValue)
{
return -short.MaxValue;
}
else
{
return (short)(Value * short.MaxValue);
}
}
private bool IsPressed(GamePadState GpState, ControllerInputID Button)
{
switch (Button)
{
case ControllerInputID.A: return GpState.Buttons.A == ButtonState.Pressed;
case ControllerInputID.B: return GpState.Buttons.B == ButtonState.Pressed;
case ControllerInputID.X: return GpState.Buttons.X == ButtonState.Pressed;
case ControllerInputID.Y: return GpState.Buttons.Y == ButtonState.Pressed;
case ControllerInputID.LStick: return GpState.Buttons.LeftStick == ButtonState.Pressed;
case ControllerInputID.RStick: return GpState.Buttons.RightStick == ButtonState.Pressed;
case ControllerInputID.LShoulder: return GpState.Buttons.LeftShoulder == ButtonState.Pressed;
case ControllerInputID.RShoulder: return GpState.Buttons.RightShoulder == ButtonState.Pressed;
case ControllerInputID.DPadUp: return GpState.DPad.Up == ButtonState.Pressed;
case ControllerInputID.DPadDown: return GpState.DPad.Down == ButtonState.Pressed;
case ControllerInputID.DPadLeft: return GpState.DPad.Left == ButtonState.Pressed;
case ControllerInputID.DPadRight: return GpState.DPad.Right == ButtonState.Pressed;
case ControllerInputID.Start: return GpState.Buttons.Start == ButtonState.Pressed;
case ControllerInputID.Back: return GpState.Buttons.Back == ButtonState.Pressed;
case ControllerInputID.LTrigger: return GpState.Triggers.Left >= TriggerThreshold;
case ControllerInputID.RTrigger: return GpState.Triggers.Right >= TriggerThreshold;
//Using thumbsticks as buttons is not common, but it would be nice not to ignore them
case ControllerInputID.LJoystick:
return GpState.ThumbSticks.Left.X >= Deadzone ||
GpState.ThumbSticks.Left.Y >= Deadzone;
case ControllerInputID.RJoystick:
return GpState.ThumbSticks.Right.X >= Deadzone ||
GpState.ThumbSticks.Right.Y >= Deadzone;
default:
return false;
}
}
}
}

66
Ryujinx/Ui/JoyConKeyboard.cs
View file

@ -1,3 +1,6 @@
using OpenTK.Input;
using Ryujinx.HLE.Input;
namespace Ryujinx.UI.Input
{
public struct JoyConKeyboardLeft
@ -32,9 +35,68 @@ namespace Ryujinx.UI.Input
public int ButtonZR;
}
public struct JoyConKeyboard
public class JoyConKeyboard
{
public JoyConKeyboardLeft Left;
public JoyConKeyboardLeft Left;
public JoyConKeyboardRight Right;
public JoyConKeyboard(
JoyConKeyboardLeft Left,
JoyConKeyboardRight Right)
{
this.Left = Left;
this.Right = Right;
}
public HidControllerButtons GetButtons(KeyboardState Keyboard)
{
HidControllerButtons Buttons = 0;
if (Keyboard[(Key)Left.StickButton]) Buttons |= HidControllerButtons.KEY_LSTICK;
if (Keyboard[(Key)Left.DPadUp]) Buttons |= HidControllerButtons.KEY_DUP;
if (Keyboard[(Key)Left.DPadDown]) Buttons |= HidControllerButtons.KEY_DDOWN;
if (Keyboard[(Key)Left.DPadLeft]) Buttons |= HidControllerButtons.KEY_DLEFT;
if (Keyboard[(Key)Left.DPadRight]) Buttons |= HidControllerButtons.KEY_DRIGHT;
if (Keyboard[(Key)Left.ButtonMinus]) Buttons |= HidControllerButtons.KEY_MINUS;
if (Keyboard[(Key)Left.ButtonL]) Buttons |= HidControllerButtons.KEY_L;
if (Keyboard[(Key)Left.ButtonZL]) Buttons |= HidControllerButtons.KEY_ZL;
if (Keyboard[(Key)Right.StickButton]) Buttons |= HidControllerButtons.KEY_RSTICK;
if (Keyboard[(Key)Right.ButtonA]) Buttons |= HidControllerButtons.KEY_A;
if (Keyboard[(Key)Right.ButtonB]) Buttons |= HidControllerButtons.KEY_B;
if (Keyboard[(Key)Right.ButtonX]) Buttons |= HidControllerButtons.KEY_X;
if (Keyboard[(Key)Right.ButtonY]) Buttons |= HidControllerButtons.KEY_Y;
if (Keyboard[(Key)Right.ButtonPlus]) Buttons |= HidControllerButtons.KEY_PLUS;
if (Keyboard[(Key)Right.ButtonR]) Buttons |= HidControllerButtons.KEY_R;
if (Keyboard[(Key)Right.ButtonZR]) Buttons |= HidControllerButtons.KEY_ZR;
return Buttons;
}
public (short, short) GetLeftStick(KeyboardState Keyboard)
{
short DX = 0;
short DY = 0;
if (Keyboard[(Key)Left.StickUp]) DY = short.MaxValue;
if (Keyboard[(Key)Left.StickDown]) DY = -short.MaxValue;
if (Keyboard[(Key)Left.StickLeft]) DX = -short.MaxValue;
if (Keyboard[(Key)Left.StickRight]) DX = short.MaxValue;
return (DX, DY);
}
public (short, short) GetRightStick(KeyboardState Keyboard)
{
short DX = 0;
short DY = 0;
if (Keyboard[(Key)Right.StickUp]) DY = short.MaxValue;
if (Keyboard[(Key)Right.StickDown]) DY = -short.MaxValue;
if (Keyboard[(Key)Right.StickLeft]) DX = -short.MaxValue;
if (Keyboard[(Key)Right.StickRight]) DX = short.MaxValue;
return (DX, DY);
}
}
}