From 7a09aea0dca080aed06d161c7407cac9cfa50bd5 Mon Sep 17 00:00:00 2001
From: merry <git@mary.rs>
Date: Thu, 10 Feb 2022 19:59:17 +0000
Subject: [PATCH] T16: Implement ADDS, SUBS (3-bit immediate)

---
 ARMeilleure/Decoders/IOpCode32AluImm.cs       |  9 +++++++
 ARMeilleure/Decoders/OpCode32AluImm.cs        |  2 +-
 ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs   | 26 +++++++++++++++++++
 ARMeilleure/Decoders/OpCodeTable.cs           |  2 ++
 ARMeilleure/Instructions/InstEmitAluHelper.cs |  2 +-
 Ryujinx.Tests/Cpu/CpuTestThumb.cs             | 22 ++++++++++++++++
 6 files changed, 61 insertions(+), 2 deletions(-)
 create mode 100644 ARMeilleure/Decoders/IOpCode32AluImm.cs
 create mode 100644 ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs

diff --git a/ARMeilleure/Decoders/IOpCode32AluImm.cs b/ARMeilleure/Decoders/IOpCode32AluImm.cs
new file mode 100644
index 000000000..9d49a440d
--- /dev/null
+++ b/ARMeilleure/Decoders/IOpCode32AluImm.cs
@@ -0,0 +1,9 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluImm : IOpCode32Alu
+    {
+        int Immediate { get; }
+
+        bool IsRotated { get; }
+    }
+}
diff --git a/ARMeilleure/Decoders/OpCode32AluImm.cs b/ARMeilleure/Decoders/OpCode32AluImm.cs
index befbdcdb9..d8ea9ed28 100644
--- a/ARMeilleure/Decoders/OpCode32AluImm.cs
+++ b/ARMeilleure/Decoders/OpCode32AluImm.cs
@@ -2,7 +2,7 @@ using ARMeilleure.Common;
 
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluImm : OpCode32Alu
+    class OpCode32AluImm : OpCode32Alu, IOpCode32AluImm
     {
         public int Immediate { get; }
 
diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
new file mode 100644
index 000000000..18afa76ab
--- /dev/null
+++ b/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
@@ -0,0 +1,26 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
+    {
+        public int Rd { get; }
+        public int Rn { get; }
+
+        public bool SetFlags { get; }
+
+        public int Immediate { get; }
+
+        public bool IsRotated { get; }
+
+        public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubImm3(inst, address, opCode, inITBlock);
+
+        public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
+        {
+            Rd        = (opCode >> 0) & 0x7;
+            Rn        = (opCode >> 3) & 0x7;
+            Immediate = (opCode >> 6) & 0x7;
+            IsRotated = false;
+
+            SetFlags = !inITBlock;
+        }
+    }
+}
\ No newline at end of file
diff --git a/ARMeilleure/Decoders/OpCodeTable.cs b/ARMeilleure/Decoders/OpCodeTable.cs
index bfb249ac9..797ab85c5 100644
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -977,6 +977,8 @@ namespace ARMeilleure.Decoders
             SetT16("000<<xxxxxxxxxxx", InstName.Mov,    InstEmit32.Mov,     OpCodeT16ShiftImm.Create);
             SetT16("0001100xxxxxxxxx", InstName.Add,    InstEmit32.Add,     OpCodeT16AddSubReg.Create);
             SetT16("0001101xxxxxxxxx", InstName.Sub,    InstEmit32.Sub,     OpCodeT16AddSubReg.Create);
+            SetT16("0001110xxxxxxxxx", InstName.Add,    InstEmit32.Add,     OpCodeT16AddSubImm3.Create);
+            SetT16("0001111xxxxxxxxx", InstName.Sub,    InstEmit32.Sub,     OpCodeT16AddSubImm3.Create);
             SetT16("010001110xxxx000", InstName.Bx,     InstEmit32.Bx,      OpCodeT16BReg.Create);
 #endregion
 
diff --git a/ARMeilleure/Instructions/InstEmitAluHelper.cs b/ARMeilleure/Instructions/InstEmitAluHelper.cs
index 9dda15789..ac7b16187 100644
--- a/ARMeilleure/Instructions/InstEmitAluHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs
@@ -183,7 +183,7 @@ namespace ARMeilleure.Instructions
             switch (context.CurrOp)
             {
                 // ARM32.
-                case OpCode32AluImm op:
+                case IOpCode32AluImm op:
                 {
                     if (op.SetFlags && op.IsRotated)
                     {
diff --git a/Ryujinx.Tests/Cpu/CpuTestThumb.cs b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
index 92c8ccd24..285f3cb9a 100644
--- a/Ryujinx.Tests/Cpu/CpuTestThumb.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestThumb.cs
@@ -55,5 +55,27 @@ namespace Ryujinx.Tests.Cpu
                     break;
             }
         }
+
+        [Test, Pairwise]
+        public void AddSubImm3([Range(0u, 1u)] uint op, [Range(0u, 7u)] uint imm, [Random(RndCnt)] uint w1)
+        {
+            uint opcode = 0x1c00; // ADDS <Rd>, <Rn>, #<imm3>
+
+            uint rd = 0;
+            uint rn = 1;
+            opcode |= ((rd & 7) << 0) | ((rn & 7) << 3) | ((imm & 7) << 6) | ((op & 1) << 9);
+
+            SingleThumbOpcode((ushort)opcode, r1: w1, runUnicorn: false);
+
+            switch (op)
+            {
+                case 0:
+                    Assert.That(GetContext().GetX(0), Is.EqualTo((w1 + imm) & 0xffffffffu));
+                    break;
+                case 1:
+                    Assert.That(GetContext().GetX(0), Is.EqualTo((w1 - imm) & 0xffffffffu));
+                    break;
+            }
+        }
     }
 }