manuth/Ryujinx
1
0
Fork 0
mirror of https://git.naxdy.org/Mirror/Ryujinx.git synced 2024-11-15 01:25:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add REV64 (vector) instruction

Browse source
This commit is contained in:
gdkchan 2018-03-02 20:03:28 -03:00
parent f39a864050
commit 829b1b1cc0
2 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
ChocolArm64/AOpCodeTable.cs
View file

@ -230,6 +230,7 @@ namespace ChocolArm64
Set("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd));
Set("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
Set("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
Set("0x001110xx100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
Set("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg));
Set("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt));
Set("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd));

11
ChocolArm64/Instruction/AInstEmitSimdLogical.cs
View file

@ -1,4 +1,5 @@
using ChocolArm64.Translation;
using System;
using System.Reflection.Emit;
using static ChocolArm64.Instruction.AInstEmitSimdHelper;
@ -65,5 +66,15 @@ namespace ChocolArm64.Instruction
{
EmitVectorImmBinaryOp(Context, () => Context.Emit(OpCodes.Or));
}
public static void Rev64_V(AILEmitterCtx Context)
{
Action Emit = () =>
{
ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits64));
};
EmitVectorUnaryOpZx(Context, Emit);
}
}
}