From 8e40b7ba801ee240175f882ef6fe5122732b2a0a Mon Sep 17 00:00:00 2001
From: TSR Berry <20988865+TSRBerry@users.noreply.github.com>
Date: Sat, 8 Jul 2023 23:59:56 +0200
Subject: [PATCH] Convert ALU imm CPU tests to xUnit
---
src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs | 294 +++++++++++------------
src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs | 33 ++-
2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
index f77eab171..d57f20277 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm.cs
@@ -1,5 +1,6 @@
-// #define AluImm
+#define AluImm
+using System;
using Xunit;
namespace Ryujinx.Tests.Cpu
@@ -9,13 +10,39 @@ namespace Ryujinx.Tests.Cpu
{
#if AluImm
- [Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
- public void Add_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ private static readonly uint[] _testData_rd =
+ {
+ 0u, 31u,
+ };
+ private static readonly uint[] _testData_rn =
+ {
+ 1u, 31u,
+ };
+ private static readonly ulong[] _testData_xnSp =
+ {
+ 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+ 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+ };
+ private static readonly uint[] _testData_imm =
+ {
+ 0u, 4095u,
+ };
+ private static readonly uint[] _testData_shift =
+ {
+ 0b00u, 0b01u, // <LSL #0, LSL #12>
+ };
+ private static readonly uint[] _testData_wnWsp =
+ {
+ 0x00000000u, 0x7FFFFFFFu,
+ 0x80000000u, 0xFFFFFFFFu,
+ };
+
+ public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_64 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_imm, _testData_shift);
+ public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_32 = new(_testData_rd, _testData_rn, _testData_wnWsp, _testData_imm, _testData_shift);
+
+ [Theory(DisplayName = "ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_64))]
+ public void Add_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
{
uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -33,13 +60,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
- public void Add_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ [Theory(DisplayName = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_32))]
+ public void Add_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
{
uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -57,13 +80,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
- public void Adds_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ [Theory(DisplayName = "ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_64))]
+ public void Adds_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
{
uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -81,13 +100,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
- public void Adds_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ [Theory(DisplayName = "ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_32))]
+ public void Adds_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
{
uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -105,241 +120,224 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
- public void And_N1_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
- [Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
+ private static readonly uint[] _testData_N1_imms =
+ {
+ 0u, 31u, 32u, 62u, // <imm>
+ };
+ private static readonly uint[] _testData_N1_immr =
+ {
+ 0u, 31u, 32u, 63u, // <imm>
+ };
+
+ public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_N1 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_N1_imms, _testData_N1_immr);
+
+ [Theory(DisplayName = "AND <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N1))]
+ public void And_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0x92400000; // AND X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
- public void And_N0_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ private static uint[] _testData_N0_imms =
+ {
+ 0u, 15u, 16u, 30u, // <imm>
+ };
+ private static uint[] _testData_N0_immr =
+ {
+ 0u, 15u, 16u, 31u, // <imm>
+ };
+
+ public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_N0 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_N0_imms, _testData_N0_immr);
+
+ [Theory(DisplayName = "AND <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N0))]
+ public void And_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0x92000000; // AND X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("AND <Wd|WSP>, <Wn>, #<imm>")]
- public void And_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_Add32 = new(_testData_rd, _testData_rd, _testData_wnWsp, _testData_N0_imms, _testData_N0_immr);
+
+ [Theory(DisplayName = "AND <Wd|WSP>, <Wn>, #<imm>")]
+ [MemberData(nameof(TestData_Add32))]
+ public void And_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
{
uint opcode = 0x12000000; // AND W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ uint w31 = Random.Shared.NextUInt();
SingleOpcode(opcode, x1: wn, x31: w31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
- public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
- [Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
+ [Theory(DisplayName = "ANDS <Xd>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N1))]
+ public void Ands_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
- public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "ANDS <Xd>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N1))]
+ public void Ands_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ANDS <Wd>, <Wn>, #<imm>")]
- public void Ands_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "ANDS <Wd>, <Wn>, #<imm>")]
+ [MemberData(nameof(TestData_Add32))]
+ public void Ands_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
{
uint opcode = 0x72000000; // ANDS W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ uint w31 = Random.Shared.NextUInt();
SingleOpcode(opcode, x1: wn, x31: w31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
- public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
- [Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
+ [Theory(DisplayName = "EOR <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N1))]
+ public void Eor_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xD2400000; // EOR X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
- public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "EOR <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N0))]
+ public void Eor_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("EOR <Wd>, <Wn>, #<imm>")]
- public void Eor_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "EOR <Wd>, <Wn>, #<imm>")]
+ [MemberData(nameof(TestData_Add32))]
+ public void Eor_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
{
uint opcode = 0x52000000; // EOR W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ uint w31 = Random.Shared.NextUInt();
SingleOpcode(opcode, x1: wn, x31: w31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
- public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
- [Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
+ [Theory(DisplayName = "ORR <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N1))]
+ public void Orr_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xB2400000; // ORR X0, X0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
- public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "ORR <Xd|SP>, <Xn>, #<imm>")]
+ [MemberData(nameof(TestData_N0))]
+ public void Orr_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
{
uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- ulong x31 = TestContext.CurrentContext.Random.NextULong();
+ ulong x31 = Random.Shared.NextULong();
SingleOpcode(opcode, x1: xn, x31: x31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("ORR <Wd|WSP>, <Wn>, #<imm>")]
- public void Orr_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wn,
- [Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
- [Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
+ [Theory(DisplayName = "ORR <Wd|WSP>, <Wn>, #<imm>")]
+ [MemberData(nameof(TestData_Add32))]
+ public void Orr_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
{
uint opcode = 0x32000000; // ORR W0, W0, #0x1
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
- uint w31 = TestContext.CurrentContext.Random.NextUInt();
+ uint w31 = Random.Shared.NextUInt();
SingleOpcode(opcode, x1: wn, x31: w31);
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
- public void Sub_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ private static readonly uint[] _testData_Sub_imm =
+ {
+ 0u, 4095u,
+ };
+ private static readonly uint[] _testData_Sub_shift =
+ {
+ 0b00u, 0b01u, // <LSL #0, LSL #12>
+ };
+
+ public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_Sub64 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_Sub_imm, _testData_Sub_shift);
+
+ [Theory(DisplayName = "SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_Sub64))]
+ public void Sub_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
{
uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -357,13 +355,11 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
- public void Sub_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_Sub32 = new(_testData_rd, _testData_rn, _testData_wnWsp, _testData_Sub_imm, _testData_Sub_shift);
+
+ [Theory(DisplayName = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_Sub32))]
+ public void Sub_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
{
uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -381,13 +377,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
- public void Subs_64bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
- 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ [Theory(DisplayName = "SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_Sub64))]
+ public void Subs_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
{
uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -405,13 +397,9 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
- [Test, Pairwise, Description("SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
- public void Subs_32bit([Values(0u, 31u)] uint rd,
- [Values(1u, 31u)] uint rn,
- [Values(0x00000000u, 0x7FFFFFFFu,
- 0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
- [Values(0u, 4095u)] uint imm,
- [Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
+ [Theory(DisplayName = "SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
+ [MemberData(nameof(TestData_Sub32))]
+ public void Subs_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
{
uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
index 2708ba3ea..3bdf24efa 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestAluImm32.cs
@@ -1,5 +1,6 @@
-// #define AluRs32
+#define AluImm32
+using System;
using Xunit;
namespace Ryujinx.Tests.Cpu
@@ -7,7 +8,7 @@ namespace Ryujinx.Tests.Cpu
[Collection("AluImm32")]
public sealed class CpuTestAluImm32 : CpuTest32
{
-#if AluRs32
+#if AluImm32
#region "ValueSource (Opcodes)"
private static uint[] Opcodes()
@@ -34,17 +35,29 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 2;
- [Test, Pairwise]
- public void TestCpuTestAluImm32([ValueSource(nameof(Opcodes))] uint opcode,
- [Values(0u, 13u)] uint rd,
- [Values(1u, 13u)] uint rn,
- [Random(RndCnt)] uint imm,
- [Random(RndCnt)] uint wn,
- [Values(true, false)] bool carryIn)
+ private static readonly uint[] _testData_rd =
+ {
+ 0u, 13u,
+ };
+ private static readonly uint[] _testData_rn =
+ {
+ 1u, 13u,
+ };
+ private static readonly bool[] _testData_carry =
+ {
+ false,
+ true,
+ };
+
+ public static readonly MatrixTheoryData<uint, uint, uint, uint, uint, bool> TestData = new(Opcodes(), _testData_rd, _testData_rn, Random.Shared.NextUIntEnumerable(RndCnt), Random.Shared.NextUIntEnumerable(RndCnt), _testData_carry);
+
+ [Theory]
+ [MemberData(nameof(TestData))]
+ public void TestCpuTestAluImm32(uint opcode, uint rd, uint rn, uint imm, uint wn, bool carryIn)
{
opcode |= ((imm & 0xfff) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
- uint sp = TestContext.CurrentContext.Random.NextUInt();
+ uint sp = Random.Shared.NextUInt();
SingleOpcode(opcode, r1: wn, sp: sp, carry: carryIn);