From fd01259d2b43efcb67efdb32c8879c67e96ccdfe Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Sun, 25 Jun 2023 21:37:33 +0200 Subject: [PATCH 01/19] [Ryujinx.ShaderTools] Address dotnet-format issues (#5388) * dotnet format style --severity info Some changes were manually reverted. * dotnet format whitespace after rebase --- src/Ryujinx.ShaderTools/Program.cs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/Ryujinx.ShaderTools/Program.cs b/src/Ryujinx.ShaderTools/Program.cs index 3acebbda6..55ff12bea 100644 --- a/src/Ryujinx.ShaderTools/Program.cs +++ b/src/Ryujinx.ShaderTools/Program.cs @@ -20,7 +20,7 @@ namespace Ryujinx.ShaderTools public ReadOnlySpan GetCode(ulong address, int minimumSize) { - return MemoryMarshal.Cast(new ReadOnlySpan(_data).Slice((int)address)); + return MemoryMarshal.Cast(new ReadOnlySpan(_data)[(int)address..]); } } @@ -53,7 +53,7 @@ namespace Ryujinx.ShaderTools byte[] data = File.ReadAllBytes(options.InputPath); - TranslationOptions translationOptions = new TranslationOptions(options.TargetLanguage, options.TargetApi, flags); + TranslationOptions translationOptions = new(options.TargetLanguage, options.TargetApi, flags); ShaderProgram program = Translator.CreateContext(0, new GpuAccessor(data), translationOptions).Translate(); @@ -90,4 +90,4 @@ namespace Ryujinx.ShaderTools .WithNotParsed(errors => errors.Output()); } } -} \ No newline at end of file +} From 07fc3ded687fd1321f9ae73d0c72b2d7566c87d5 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Sun, 25 Jun 2023 21:44:42 +0200 Subject: [PATCH 02/19] [Ryujinx.Graphics.Nvdec] Address dotnet-format issues (#5369) * dotnet format style --severity info Some changes were manually reverted. * Restore a few unused methods and variables * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Address IDE0251 warnings * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass --- src/Ryujinx.Graphics.Nvdec/H264Decoder.cs | 10 ++--- .../Image/SurfaceReader.cs | 2 +- .../Image/SurfaceWriter.cs | 8 ++-- .../NvdecDecoderContext.cs | 2 +- src/Ryujinx.Graphics.Nvdec/NvdecDevice.cs | 2 +- src/Ryujinx.Graphics.Nvdec/NvdecRegisters.cs | 2 +- src/Ryujinx.Graphics.Nvdec/NvdecStatus.cs | 4 +- .../Types/H264/PictureInfo.cs | 39 ++++++++++--------- .../Types/H264/ReferenceFrame.cs | 4 +- .../Types/Vp8/PictureInfo.cs | 2 +- .../Types/Vp9/EntropyProbs.cs | 2 +- .../Types/Vp9/FrameSize.cs | 2 +- .../Types/Vp9/FrameStats.cs | 2 +- .../Types/Vp9/LoopFilter.cs | 2 +- .../Types/Vp9/PictureInfo.cs | 4 +- .../Types/Vp9/Segmentation.cs | 2 +- src/Ryujinx.Graphics.Nvdec/Vp8Decoder.cs | 2 +- src/Ryujinx.Graphics.Nvdec/Vp9Decoder.cs | 10 ++--- 18 files changed, 51 insertions(+), 50 deletions(-) diff --git a/src/Ryujinx.Graphics.Nvdec/H264Decoder.cs b/src/Ryujinx.Graphics.Nvdec/H264Decoder.cs index ecc7dbc79..c99d4a176 100644 --- a/src/Ryujinx.Graphics.Nvdec/H264Decoder.cs +++ b/src/Ryujinx.Graphics.Nvdec/H264Decoder.cs @@ -17,12 +17,12 @@ namespace Ryujinx.Graphics.Nvdec ReadOnlySpan bitstream = rm.Gmm.DeviceGetSpan(state.SetInBufBaseOffset, (int)pictureInfo.BitstreamSize); - int width = (int)pictureInfo.PicWidthInMbs * MbSizeInPixels; + int width = (int)pictureInfo.PicWidthInMbs * MbSizeInPixels; int height = (int)pictureInfo.PicHeightInMbs * MbSizeInPixels; int surfaceIndex = (int)pictureInfo.OutputSurfaceIndex; - uint lumaOffset = state.SetPictureLumaOffset[surfaceIndex]; + uint lumaOffset = state.SetPictureLumaOffset[surfaceIndex]; uint chromaOffset = state.SetPictureChromaOffset[surfaceIndex]; Decoder decoder = context.GetH264Decoder(); @@ -36,7 +36,7 @@ namespace Ryujinx.Graphics.Nvdec SurfaceWriter.Write( rm.Gmm, outputSurface, - lumaOffset + pictureInfo.LumaFrameOffset, + lumaOffset + pictureInfo.LumaFrameOffset, chromaOffset + pictureInfo.ChromaFrameOffset); } else @@ -44,9 +44,9 @@ namespace Ryujinx.Graphics.Nvdec SurfaceWriter.WriteInterlaced( rm.Gmm, outputSurface, - lumaOffset + pictureInfo.LumaTopFieldOffset, + lumaOffset + pictureInfo.LumaTopFieldOffset, chromaOffset + pictureInfo.ChromaTopFieldOffset, - lumaOffset + pictureInfo.LumaBottomFieldOffset, + lumaOffset + pictureInfo.LumaBottomFieldOffset, chromaOffset + pictureInfo.ChromaBottomFieldOffset); } } diff --git a/src/Ryujinx.Graphics.Nvdec/Image/SurfaceReader.cs b/src/Ryujinx.Graphics.Nvdec/Image/SurfaceReader.cs index 039a25832..598b71992 100644 --- a/src/Ryujinx.Graphics.Nvdec/Image/SurfaceReader.cs +++ b/src/Ryujinx.Graphics.Nvdec/Image/SurfaceReader.cs @@ -43,7 +43,7 @@ namespace Ryujinx.Graphics.Nvdec.Image int width, int height) { - OffsetCalculator calc = new OffsetCalculator(width, height, 0, false, 2, 2); + OffsetCalculator calc = new(width, height, 0, false, 2, 2); if (Sse2.IsSupported) { diff --git a/src/Ryujinx.Graphics.Nvdec/Image/SurfaceWriter.cs b/src/Ryujinx.Graphics.Nvdec/Image/SurfaceWriter.cs index cc5c251be..dd67252af 100644 --- a/src/Ryujinx.Graphics.Nvdec/Image/SurfaceWriter.cs +++ b/src/Ryujinx.Graphics.Nvdec/Image/SurfaceWriter.cs @@ -60,7 +60,7 @@ namespace Ryujinx.Graphics.Nvdec.Image WriteLuma( lumaBottom.Memory.Span, - surface.YPlane.AsSpan().Slice(surface.Stride), + surface.YPlane.AsSpan()[surface.Stride..], surface.Stride * 2, surface.Width, surface.Height / 2); @@ -80,8 +80,8 @@ namespace Ryujinx.Graphics.Nvdec.Image WriteChroma( chromaBottom.Memory.Span, - surface.UPlane.AsSpan().Slice(surface.UvStride), - surface.VPlane.AsSpan().Slice(surface.UvStride), + surface.UPlane.AsSpan()[surface.UvStride..], + surface.VPlane.AsSpan()[surface.UvStride..], surface.UvStride * 2, surface.UvWidth, surface.UvHeight / 2); @@ -100,7 +100,7 @@ namespace Ryujinx.Graphics.Nvdec.Image int width, int height) { - OffsetCalculator calc = new OffsetCalculator(width, height, 0, false, 2, 2); + OffsetCalculator calc = new(width, height, 0, false, 2, 2); if (Sse2.IsSupported) { diff --git a/src/Ryujinx.Graphics.Nvdec/NvdecDecoderContext.cs b/src/Ryujinx.Graphics.Nvdec/NvdecDecoderContext.cs index 54934bc5a..aaa734a88 100644 --- a/src/Ryujinx.Graphics.Nvdec/NvdecDecoderContext.cs +++ b/src/Ryujinx.Graphics.Nvdec/NvdecDecoderContext.cs @@ -26,4 +26,4 @@ namespace Ryujinx.Graphics.Nvdec _vp8Decoder = null; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Nvdec/NvdecDevice.cs b/src/Ryujinx.Graphics.Nvdec/NvdecDevice.cs index ef8185f4d..4ab7886d0 100644 --- a/src/Ryujinx.Graphics.Nvdec/NvdecDevice.cs +++ b/src/Ryujinx.Graphics.Nvdec/NvdecDevice.cs @@ -14,7 +14,7 @@ namespace Ryujinx.Graphics.Nvdec private readonly DeviceState _state; private long _currentId; - private ConcurrentDictionary _contexts; + private readonly ConcurrentDictionary _contexts; private NvdecDecoderContext _currentContext; public NvdecDevice(MemoryManager gmm) diff --git a/src/Ryujinx.Graphics.Nvdec/NvdecRegisters.cs b/src/Ryujinx.Graphics.Nvdec/NvdecRegisters.cs index cf8677838..5effcb498 100644 --- a/src/Ryujinx.Graphics.Nvdec/NvdecRegisters.cs +++ b/src/Ryujinx.Graphics.Nvdec/NvdecRegisters.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Nvdec { struct NvdecRegisters { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public Array64 Reserved0; public uint Nop; public Array63 Reserved104; diff --git a/src/Ryujinx.Graphics.Nvdec/NvdecStatus.cs b/src/Ryujinx.Graphics.Nvdec/NvdecStatus.cs index 0712af88b..1d6b4a60d 100644 --- a/src/Ryujinx.Graphics.Nvdec/NvdecStatus.cs +++ b/src/Ryujinx.Graphics.Nvdec/NvdecStatus.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Nvdec { struct NvdecStatus { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public uint MbsCorrectlyDecoded; public uint MbsInError; public uint Reserved; @@ -13,4 +13,4 @@ namespace Ryujinx.Graphics.Nvdec public uint SliceHeaderErrorCode; #pragma warning restore CS0649 } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Nvdec/Types/H264/PictureInfo.cs b/src/Ryujinx.Graphics.Nvdec/Types/H264/PictureInfo.cs index 7c779dff3..c0e0a463d 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/H264/PictureInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/H264/PictureInfo.cs @@ -5,8 +5,9 @@ namespace Ryujinx.Graphics.Nvdec.Types.H264 { struct PictureInfo { -#pragma warning disable CS0169, CS0649 +#pragma warning disable IDE0051, CS0169, CS0649 // Remove unused private member Array18 Unknown0; +#pragma warning restore IDE0051 public uint BitstreamSize; public uint NumSlices; public uint Unknown50; @@ -50,24 +51,24 @@ namespace Ryujinx.Graphics.Nvdec.Types.H264 public Array10 Unknown2D4; #pragma warning restore CS0169, CS0649 - public bool MbAdaptiveFrameFieldFlag => (Flags & (1 << 0)) != 0; - public bool Direct8x8InferenceFlag => (Flags & (1 << 1)) != 0; - public bool WeightedPredFlag => (Flags & (1 << 2)) != 0; - public bool ConstrainedIntraPredFlag => (Flags & (1 << 3)) != 0; - public bool IsReference => (Flags & (1 << 4)) != 0; - public bool FieldPicFlag => (Flags & (1 << 5)) != 0; - public bool BottomFieldFlag => (Flags & (1 << 6)) != 0; - public uint Log2MaxFrameNumMinus4 => (uint)(Flags >> 8) & 0xf; - public ushort ChromaFormatIdc => (ushort)((Flags >> 12) & 3); - public uint PicOrderCntType => (uint)(Flags >> 14) & 3; - public int PicInitQpMinus26 => ExtractSx(Flags, 16, 6); - public int ChromaQpIndexOffset => ExtractSx(Flags, 22, 5); - public int SecondChromaQpIndexOffset => ExtractSx(Flags, 27, 5); - public uint WeightedBipredIdc => (uint)(Flags >> 32) & 3; - public uint OutputSurfaceIndex => (uint)(Flags >> 34) & 0x7f; - public uint ColIndex => (uint)(Flags >> 41) & 0x1f; - public ushort FrameNum => (ushort)(Flags >> 46); - public bool QpprimeYZeroTransformBypassFlag => (Flags2 & (1 << 1)) != 0; + public readonly bool MbAdaptiveFrameFieldFlag => (Flags & (1 << 0)) != 0; + public readonly bool Direct8x8InferenceFlag => (Flags & (1 << 1)) != 0; + public readonly bool WeightedPredFlag => (Flags & (1 << 2)) != 0; + public readonly bool ConstrainedIntraPredFlag => (Flags & (1 << 3)) != 0; + public readonly bool IsReference => (Flags & (1 << 4)) != 0; + public readonly bool FieldPicFlag => (Flags & (1 << 5)) != 0; + public readonly bool BottomFieldFlag => (Flags & (1 << 6)) != 0; + public readonly uint Log2MaxFrameNumMinus4 => (uint)(Flags >> 8) & 0xf; + public readonly ushort ChromaFormatIdc => (ushort)((Flags >> 12) & 3); + public readonly uint PicOrderCntType => (uint)(Flags >> 14) & 3; + public readonly int PicInitQpMinus26 => ExtractSx(Flags, 16, 6); + public readonly int ChromaQpIndexOffset => ExtractSx(Flags, 22, 5); + public readonly int SecondChromaQpIndexOffset => ExtractSx(Flags, 27, 5); + public readonly uint WeightedBipredIdc => (uint)(Flags >> 32) & 3; + public readonly uint OutputSurfaceIndex => (uint)(Flags >> 34) & 0x7f; + public readonly uint ColIndex => (uint)(Flags >> 41) & 0x1f; + public readonly ushort FrameNum => (ushort)(Flags >> 46); + public readonly bool QpprimeYZeroTransformBypassFlag => (Flags2 & (1 << 1)) != 0; private static int ExtractSx(ulong packed, int lsb, int length) { diff --git a/src/Ryujinx.Graphics.Nvdec/Types/H264/ReferenceFrame.cs b/src/Ryujinx.Graphics.Nvdec/Types/H264/ReferenceFrame.cs index d205a47a4..9ab9d1320 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/H264/ReferenceFrame.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/H264/ReferenceFrame.cs @@ -4,12 +4,12 @@ namespace Ryujinx.Graphics.Nvdec.Types.H264 { struct ReferenceFrame { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public uint Flags; public Array2 FieldOrderCnt; public uint FrameNum; #pragma warning restore CS0649 - public uint OutputSurfaceIndex => (uint)Flags & 0x7f; + public readonly uint OutputSurfaceIndex => (uint)Flags & 0x7f; } } diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp8/PictureInfo.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp8/PictureInfo.cs index 844f21030..76e07a3ff 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp8/PictureInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp8/PictureInfo.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp8 { struct PictureInfo { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public Array13 Unknown0; public uint GpTimerTimeoutValue; public ushort FrameWidth; diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/EntropyProbs.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/EntropyProbs.cs index b2858d2d8..dd5221b18 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/EntropyProbs.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/EntropyProbs.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp9 { struct EntropyProbs { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public Array10>> KfYModeProbE0ToE7; public Array10> KfYModeProbE8; public Array3 Padding384; diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameSize.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameSize.cs index d449ec4d6..31c08a529 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameSize.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameSize.cs @@ -2,7 +2,7 @@ { struct FrameSize { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public ushort Width; public ushort Height; public ushort LumaPitch; diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameStats.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameStats.cs index 26aab5060..9b0325cf0 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameStats.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/FrameStats.cs @@ -2,7 +2,7 @@ { struct FrameStats { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public uint Unknown0; public uint Unknown4; public uint Pass2CycleCount; diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/LoopFilter.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/LoopFilter.cs index 7cb0fd7a8..ebef7f677 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/LoopFilter.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/LoopFilter.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp9 { struct LoopFilter { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public byte ModeRefDeltaEnabled; public Array4 RefDeltas; public Array2 ModeDeltas; diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/PictureInfo.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/PictureInfo.cs index 7d06f7474..50569dbff 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/PictureInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/PictureInfo.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp9 { struct PictureInfo { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public Array12 Unknown0; public uint BitstreamSize; public uint IsEncrypted; @@ -44,7 +44,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp9 public uint UnknownFC; #pragma warning restore CS0649 - public uint BitDepth => (SurfaceParams >> 1) & 0xf; + public readonly uint BitDepth => (SurfaceParams >> 1) & 0xf; public Vp9PictureInfo Convert() { diff --git a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/Segmentation.cs b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/Segmentation.cs index f6c4f0b17..ab9954c68 100644 --- a/src/Ryujinx.Graphics.Nvdec/Types/Vp9/Segmentation.cs +++ b/src/Ryujinx.Graphics.Nvdec/Types/Vp9/Segmentation.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Nvdec.Types.Vp9 { struct Segmentation { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public byte Enabled; public byte UpdateMap; public byte TemporalUpdate; diff --git a/src/Ryujinx.Graphics.Nvdec/Vp8Decoder.cs b/src/Ryujinx.Graphics.Nvdec/Vp8Decoder.cs index cce9a5744..e56b23d73 100644 --- a/src/Ryujinx.Graphics.Nvdec/Vp8Decoder.cs +++ b/src/Ryujinx.Graphics.Nvdec/Vp8Decoder.cs @@ -30,4 +30,4 @@ namespace Ryujinx.Graphics.Nvdec rm.Cache.Put(outputSurface); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Nvdec/Vp9Decoder.cs b/src/Ryujinx.Graphics.Nvdec/Vp9Decoder.cs index 9bb3529e8..f78bb7028 100644 --- a/src/Ryujinx.Graphics.Nvdec/Vp9Decoder.cs +++ b/src/Ryujinx.Graphics.Nvdec/Vp9Decoder.cs @@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Nvdec { static class Vp9Decoder { - private static Decoder _decoder = new Decoder(); + private static readonly Decoder _decoder = new(); public unsafe static void Decode(ResourceManager rm, ref NvdecRegisters state) { @@ -25,9 +25,9 @@ namespace Ryujinx.Graphics.Nvdec return rm.Cache.Get(_decoder, lumaOffset, chromaOffset, size.Width, size.Height); } - ISurface lastSurface = Rent(state.SetPictureLumaOffset[0], state.SetPictureChromaOffset[0], pictureInfo.LastFrameSize); - ISurface goldenSurface = Rent(state.SetPictureLumaOffset[1], state.SetPictureChromaOffset[1], pictureInfo.GoldenFrameSize); - ISurface altSurface = Rent(state.SetPictureLumaOffset[2], state.SetPictureChromaOffset[2], pictureInfo.AltFrameSize); + ISurface lastSurface = Rent(state.SetPictureLumaOffset[0], state.SetPictureChromaOffset[0], pictureInfo.LastFrameSize); + ISurface goldenSurface = Rent(state.SetPictureLumaOffset[1], state.SetPictureChromaOffset[1], pictureInfo.GoldenFrameSize); + ISurface altSurface = Rent(state.SetPictureLumaOffset[2], state.SetPictureChromaOffset[2], pictureInfo.AltFrameSize); ISurface currentSurface = Rent(state.SetPictureLumaOffset[3], state.SetPictureChromaOffset[3], pictureInfo.CurrentFrameSize); Vp9PictureInfo info = pictureInfo.Convert(); @@ -54,7 +54,7 @@ namespace Ryujinx.Graphics.Nvdec Span mvsOut = MemoryMarshal.Cast(mvsRegion.Memory.Span); - uint lumaOffset = state.SetPictureLumaOffset[3]; + uint lumaOffset = state.SetPictureLumaOffset[3]; uint chromaOffset = state.SetPictureChromaOffset[3]; if (_decoder.Decode(ref info, currentSurface, bitstream, mvsIn, mvsOut)) From 42d31f646dfe2dfc8ed646102c06ca44af7b8b07 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Sun, 25 Jun 2023 22:50:59 +0200 Subject: [PATCH 03/19] [Ryujinx.Audio.Backends.SDL2] Address dotnet-format issues (#5364) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Address dotnet format CA1816 warnings * Address most dotnet format whitespace warnings * Run dotnet format style after rebase * Run dotnet format analyzers after rebase * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Update src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceDriver.cs Co-authored-by: Ac_K --------- Co-authored-by: Ac_K --- .../SDL2HardwareDeviceDriver.cs | 10 +++++---- .../SDL2HardwareDeviceSession.cs | 22 +++++++++---------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceDriver.cs b/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceDriver.cs index 7bfff5f9b..550cc3491 100644 --- a/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceDriver.cs +++ b/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceDriver.cs @@ -19,12 +19,14 @@ namespace Ryujinx.Audio.Backends.SDL2 private readonly ManualResetEvent _pauseEvent; private readonly ConcurrentDictionary _sessions; - private bool _supportSurroundConfiguration; + private readonly bool _supportSurroundConfiguration; // TODO: Add this to SDL2-CS // NOTE: We use a DllImport here because of marshaling issue for spec. +#pragma warning disable SYSLIB1054 [DllImport("SDL2")] private static extern int SDL_GetDefaultAudioInfo(IntPtr name, out SDL_AudioSpec spec, int isCapture); +#pragma warning restore SYSLIB1054 public SDL2HardwareDeviceDriver() { @@ -90,7 +92,7 @@ namespace Ryujinx.Audio.Backends.SDL2 throw new NotImplementedException("Input direction is currently not implemented on SDL2 backend!"); } - SDL2HardwareDeviceSession session = new SDL2HardwareDeviceSession(this, memoryManager, sampleFormat, sampleRate, channelCount, volume); + SDL2HardwareDeviceSession session = new(this, memoryManager, sampleFormat, sampleRate, channelCount, volume); _sessions.TryAdd(session, 0); @@ -135,8 +137,7 @@ namespace Ryujinx.Audio.Backends.SDL2 if (device == 0) { - Logger.Error?.Print(LogClass.Application, - $"SDL2 open audio device initialization failed with error \"{SDL_GetError()}\""); + Logger.Error?.Print(LogClass.Application, $"SDL2 open audio device initialization failed with error \"{SDL_GetError()}\""); return 0; } @@ -156,6 +157,7 @@ namespace Ryujinx.Audio.Backends.SDL2 public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } diff --git a/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceSession.cs b/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceSession.cs index 14310b934..0bd73f3c7 100644 --- a/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceSession.cs +++ b/src/Ryujinx.Audio.Backends.SDL2/SDL2HardwareDeviceSession.cs @@ -12,19 +12,19 @@ namespace Ryujinx.Audio.Backends.SDL2 { class SDL2HardwareDeviceSession : HardwareDeviceSessionOutputBase { - private SDL2HardwareDeviceDriver _driver; - private ConcurrentQueue _queuedBuffers; - private DynamicRingBuffer _ringBuffer; + private readonly SDL2HardwareDeviceDriver _driver; + private readonly ConcurrentQueue _queuedBuffers; + private readonly DynamicRingBuffer _ringBuffer; private ulong _playedSampleCount; - private ManualResetEvent _updateRequiredEvent; + private readonly ManualResetEvent _updateRequiredEvent; private uint _outputStream; private bool _hasSetupError; - private SDL_AudioCallback _callbackDelegate; - private int _bytesPerFrame; + private readonly SDL_AudioCallback _callbackDelegate; + private readonly int _bytesPerFrame; private uint _sampleCount; private bool _started; private float _volume; - private ushort _nativeSampleFormat; + private readonly ushort _nativeSampleFormat; public SDL2HardwareDeviceSession(SDL2HardwareDeviceDriver driver, IVirtualMemoryManager memoryManager, SampleFormat requestedSampleFormat, uint requestedSampleRate, uint requestedChannelCount, float requestedVolume) : base(memoryManager, requestedSampleFormat, requestedSampleRate, requestedChannelCount) { @@ -72,7 +72,7 @@ namespace Ryujinx.Audio.Backends.SDL2 private unsafe void Update(IntPtr userdata, IntPtr stream, int streamLength) { - Span streamSpan = new Span((void*)stream, streamLength); + Span streamSpan = new((void*)stream, streamLength); int maxFrameCount = (int)GetSampleCount(streamLength); int bufferedFrames = _ringBuffer.Length / _bytesPerFrame; @@ -82,7 +82,7 @@ namespace Ryujinx.Audio.Backends.SDL2 if (frameCount == 0) { // SDL2 left the responsibility to the user to clear the buffer. - streamSpan.Fill(0); + streamSpan.Clear(); return; } @@ -96,7 +96,7 @@ namespace Ryujinx.Audio.Backends.SDL2 IntPtr pStreamSrc = (IntPtr)p; // Zero the dest buffer - streamSpan.Fill(0); + streamSpan.Clear(); // Apply volume to written data SDL_MixAudioFormat(stream, pStreamSrc, _nativeSampleFormat, (uint)samples.Length, (int)(_volume * SDL_MIX_MAXVOLUME)); @@ -151,7 +151,7 @@ namespace Ryujinx.Audio.Backends.SDL2 if (_outputStream != 0) { - SDL2AudioBuffer driverBuffer = new SDL2AudioBuffer(buffer.DataPointer, GetSampleCount(buffer)); + SDL2AudioBuffer driverBuffer = new(buffer.DataPointer, GetSampleCount(buffer)); _ringBuffer.Write(buffer.Data, 0, buffer.Data.Length); From f6ada8d1697502a6b37192c9cf9a32acfa28b51a Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Sun, 25 Jun 2023 23:58:44 +0200 Subject: [PATCH 04/19] [Ryujinx.Graphics.Device] Address dotnet-format issues (#5363) * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Address most dotnet format whitespace warnings * dotnet format whitespace after rebase --- src/Ryujinx.Graphics.Device/DeviceState.cs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Ryujinx.Graphics.Device/DeviceState.cs b/src/Ryujinx.Graphics.Device/DeviceState.cs index a9b446e18..b07582a8a 100644 --- a/src/Ryujinx.Graphics.Device/DeviceState.cs +++ b/src/Ryujinx.Graphics.Device/DeviceState.cs @@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Device public TState State; - private uint Size => (uint)(Unsafe.SizeOf() + RegisterSize - 1) / RegisterSize; + private static uint Size => (uint)(Unsafe.SizeOf() + RegisterSize - 1) / RegisterSize; private readonly Func[] _readCallbacks; private readonly Action[] _writeCallbacks; From 9860bfb2cdb2a3f6093d936d647b1f254a23120d Mon Sep 17 00:00:00 2001 From: Mary Date: Mon, 26 Jun 2023 03:37:12 +0200 Subject: [PATCH 05/19] misc: memory: Migrate from OutOfMemoryException to SystemException entirely (#5399) Fix a regression with address space allocation while providing more information about the context of the exception. --- src/Ryujinx.Cpu/AddressSpace.cs | 2 +- src/Ryujinx.Memory/MemoryBlock.cs | 6 +++--- src/Ryujinx.Memory/MemoryManagementUnix.cs | 12 ++++++------ src/Ryujinx.Memory/MemoryManagementWindows.cs | 4 ++-- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/Ryujinx.Cpu/AddressSpace.cs b/src/Ryujinx.Cpu/AddressSpace.cs index 0e27b1582..e051244d5 100644 --- a/src/Ryujinx.Cpu/AddressSpace.cs +++ b/src/Ryujinx.Cpu/AddressSpace.cs @@ -199,7 +199,7 @@ namespace Ryujinx.Cpu break; } - catch (OutOfMemoryException) + catch (SystemException) { baseMemory?.Dispose(); mirrorMemory?.Dispose(); diff --git a/src/Ryujinx.Memory/MemoryBlock.cs b/src/Ryujinx.Memory/MemoryBlock.cs index 2cf04628a..e7fc47516 100644 --- a/src/Ryujinx.Memory/MemoryBlock.cs +++ b/src/Ryujinx.Memory/MemoryBlock.cs @@ -31,7 +31,7 @@ namespace Ryujinx.Memory /// /// Size of the memory block in bytes /// Flags that controls memory block memory allocation - /// Throw when there's no enough memory to allocate the requested size + /// Throw when there's an error while allocating the requested size /// Throw when the current platform is not supported public MemoryBlock(ulong size, MemoryAllocationFlags flags = MemoryAllocationFlags.None) { @@ -66,7 +66,7 @@ namespace Ryujinx.Memory /// /// Size of the memory block in bytes /// Shared memory to use as backing storage for this block - /// Throw when there's no enough address space left to map the shared memory + /// Throw when there's an error while mapping the shared memory /// Throw when the current platform is not supported private MemoryBlock(ulong size, IntPtr sharedMemory) { @@ -82,7 +82,7 @@ namespace Ryujinx.Memory /// /// A new memory block that shares storage with this one /// Throw when the current memory block does not support mirroring - /// Throw when there's no enough address space left to map the shared memory + /// Throw when there's an error while mapping the shared memory /// Throw when the current platform is not supported public MemoryBlock CreateMirror() { diff --git a/src/Ryujinx.Memory/MemoryManagementUnix.cs b/src/Ryujinx.Memory/MemoryManagementUnix.cs index d665b2294..4314c3928 100644 --- a/src/Ryujinx.Memory/MemoryManagementUnix.cs +++ b/src/Ryujinx.Memory/MemoryManagementUnix.cs @@ -147,12 +147,12 @@ namespace Ryujinx.Memory fd = shm_open((IntPtr)pMemName, 0x2 | 0x200 | 0x800 | 0x400, 384); // O_RDWR | O_CREAT | O_EXCL | O_TRUNC, 0600 if (fd == -1) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } if (shm_unlink((IntPtr)pMemName) != 0) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } } } @@ -165,22 +165,22 @@ namespace Ryujinx.Memory fd = mkstemp((IntPtr)pFileName); if (fd == -1) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } if (unlink((IntPtr)pFileName) != 0) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } } } if (ftruncate(fd, (IntPtr)size) != 0) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } - return (IntPtr)fd; + return fd; } public static void DestroySharedMemory(IntPtr handle) diff --git a/src/Ryujinx.Memory/MemoryManagementWindows.cs b/src/Ryujinx.Memory/MemoryManagementWindows.cs index d7d78bd86..aaed5a637 100644 --- a/src/Ryujinx.Memory/MemoryManagementWindows.cs +++ b/src/Ryujinx.Memory/MemoryManagementWindows.cs @@ -114,7 +114,7 @@ namespace Ryujinx.Memory if (handle == IntPtr.Zero) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } return handle; @@ -134,7 +134,7 @@ namespace Ryujinx.Memory if (ptr == IntPtr.Zero) { - throw new OutOfMemoryException(); + throw new SystemException(Marshal.GetLastPInvokeErrorMessage()); } return ptr; From b29ded1d6009dc6a82a0aefd594eda21b5c2d814 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Mon, 26 Jun 2023 03:51:16 +0200 Subject: [PATCH 06/19] [Ryujinx.SDL2.Common] Address dotnet-format issues (#5387) * dotnet format style --severity info Some changes were manually reverted. * Address dotnet format CA1816 warnings * Address or silence dotnet format CA1806 and a few CA1854 warnings * Address most dotnet format whitespace warnings * dotnet format whitespace after rebase --- src/Ryujinx.SDL2.Common/SDL2Driver.cs | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/Ryujinx.SDL2.Common/SDL2Driver.cs b/src/Ryujinx.SDL2.Common/SDL2Driver.cs index 5e2deb26d..2642b26fa 100644 --- a/src/Ryujinx.SDL2.Common/SDL2Driver.cs +++ b/src/Ryujinx.SDL2.Common/SDL2Driver.cs @@ -19,10 +19,7 @@ namespace Ryujinx.SDL2.Common { get { - if (_instance == null) - { - _instance = new SDL2Driver(); - } + _instance ??= new SDL2Driver(); return _instance; } @@ -43,7 +40,7 @@ namespace Ryujinx.SDL2.Common private readonly object _lock = new(); - private SDL2Driver() {} + private SDL2Driver() { } private const string SDL_HINT_JOYSTICK_HIDAPI_COMBINE_JOY_CONS = "SDL_JOYSTICK_HIDAPI_COMBINE_JOY_CONS"; @@ -80,8 +77,15 @@ namespace Ryujinx.SDL2.Common } // First ensure that we only enable joystick events (for connected/disconnected). - SDL_GameControllerEventState(SDL_DISABLE); - SDL_JoystickEventState(SDL_ENABLE); + if (SDL_GameControllerEventState(SDL_IGNORE) != SDL_IGNORE) + { + Logger.Error?.PrintMsg(LogClass.Application, "Couldn't change the state of game controller events."); + } + + if (SDL_JoystickEventState(SDL_ENABLE) < 0) + { + Logger.Error?.PrintMsg(LogClass.Application, $"Failed to enable joystick event polling: {SDL_GetError()}"); + } // Disable all joysticks information, we don't need them no need to flood the event queue for that. SDL_EventState(SDL_EventType.SDL_JOYAXISMOTION, SDL_DISABLE); @@ -153,7 +157,7 @@ namespace Ryujinx.SDL2.Common { const int WaitTimeMs = 10; - using ManualResetEventSlim waitHandle = new ManualResetEventSlim(false); + using ManualResetEventSlim waitHandle = new(false); while (_isRunning) { @@ -199,6 +203,7 @@ namespace Ryujinx.SDL2.Common public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } } From 2de78a2d55a1306761788570ab192897299c55d8 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Mon, 26 Jun 2023 03:55:25 +0200 Subject: [PATCH 07/19] [Ryujinx.Input.SDL2] Address dotnet-format issues (#5385) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0052 warnings * Address dotnet format CA1816 warnings * Address or silence dotnet format CA1806 and a few CA1854 warnings * Address most dotnet format whitespace warnings * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Add trailing commas, log errors instead of throwing and remove redundant code --- src/Ryujinx.Input.SDL2/SDL2Gamepad.cs | 44 ++++++++++++++------- src/Ryujinx.Input.SDL2/SDL2GamepadDriver.cs | 11 +++--- src/Ryujinx.Input.SDL2/SDL2Keyboard.cs | 38 +++++++----------- src/Ryujinx.Input.SDL2/SDLKeyboardDriver.cs | 3 +- 4 files changed, 52 insertions(+), 44 deletions(-) diff --git a/src/Ryujinx.Input.SDL2/SDL2Gamepad.cs b/src/Ryujinx.Input.SDL2/SDL2Gamepad.cs index 6a8c1204f..f04fdeb3c 100644 --- a/src/Ryujinx.Input.SDL2/SDL2Gamepad.cs +++ b/src/Ryujinx.Input.SDL2/SDL2Gamepad.cs @@ -57,13 +57,13 @@ namespace Ryujinx.Input.SDL2 private readonly object _userMappingLock = new(); - private List _buttonsUserMapping; + private readonly List _buttonsUserMapping; - private StickInputId[] _stickUserMapping = new StickInputId[(int)StickInputId.Count] + private readonly StickInputId[] _stickUserMapping = new StickInputId[(int)StickInputId.Count] { StickInputId.Unbound, StickInputId.Left, - StickInputId.Right + StickInputId.Right, }; public GamepadFeaturesFlag Features { get; } @@ -85,8 +85,15 @@ namespace Ryujinx.Input.SDL2 // Enable motion tracking if (Features.HasFlag(GamepadFeaturesFlag.Motion)) { - SDL_GameControllerSetSensorEnabled(_gamepadHandle, SDL_SensorType.SDL_SENSOR_ACCEL, SDL_bool.SDL_TRUE); - SDL_GameControllerSetSensorEnabled(_gamepadHandle, SDL_SensorType.SDL_SENSOR_GYRO, SDL_bool.SDL_TRUE); + if (SDL_GameControllerSetSensorEnabled(_gamepadHandle, SDL_SensorType.SDL_SENSOR_ACCEL, SDL_bool.SDL_TRUE) != 0) + { + Logger.Error?.Print(LogClass.Hid, $"Could not enable data reporting for SensorType {SDL_SensorType.SDL_SENSOR_ACCEL}."); + } + + if (SDL_GameControllerSetSensorEnabled(_gamepadHandle, SDL_SensorType.SDL_SENSOR_GYRO, SDL_bool.SDL_TRUE) != 0) + { + Logger.Error?.Print(LogClass.Hid, $"Could not enable data reporting for SensorType {SDL_SensorType.SDL_SENSOR_GYRO}."); + } } } @@ -144,7 +151,10 @@ namespace Ryujinx.Input.SDL2 if (durationMs == uint.MaxValue) { - SDL_GameControllerRumble(_gamepadHandle, lowFrequencyRaw, highFrequencyRaw, SDL_HAPTIC_INFINITY); + if (SDL_GameControllerRumble(_gamepadHandle, lowFrequencyRaw, highFrequencyRaw, SDL_HAPTIC_INFINITY) != 0) + { + Logger.Error?.Print(LogClass.Hid, "Rumble is not supported on this game controller."); + } } else if (durationMs > SDL_HAPTIC_INFINITY) { @@ -152,7 +162,10 @@ namespace Ryujinx.Input.SDL2 } else { - SDL_GameControllerRumble(_gamepadHandle, lowFrequencyRaw, highFrequencyRaw, durationMs); + if (SDL_GameControllerRumble(_gamepadHandle, lowFrequencyRaw, highFrequencyRaw, durationMs) != 0) + { + Logger.Error?.Print(LogClass.Hid, "Rumble is not supported on this game controller."); + } } } } @@ -182,13 +195,14 @@ namespace Ryujinx.Input.SDL2 if (result == 0) { - Vector3 value = new Vector3(values[0], values[1], values[2]); + Vector3 value = new(values[0], values[1], values[2]); if (inputId == MotionInputId.Gyroscope) { return RadToDegree(value); } - else if (inputId == MotionInputId.Accelerometer) + + if (inputId == MotionInputId.Accelerometer) { return GsToMs2(value); } @@ -359,18 +373,18 @@ namespace Ryujinx.Input.SDL2 { return ConvertRawStickValue(SDL_GameControllerGetAxis(_gamepadHandle, SDL_GameControllerAxis.SDL_CONTROLLER_AXIS_TRIGGERLEFT)) > _triggerThreshold; } - else if (inputId == GamepadButtonInputId.RightTrigger) + + if (inputId == GamepadButtonInputId.RightTrigger) { return ConvertRawStickValue(SDL_GameControllerGetAxis(_gamepadHandle, SDL_GameControllerAxis.SDL_CONTROLLER_AXIS_TRIGGERRIGHT)) > _triggerThreshold; } - else if (_buttonsDriverMapping[(int)inputId] == SDL_GameControllerButton.SDL_CONTROLLER_BUTTON_INVALID) + + if (_buttonsDriverMapping[(int)inputId] == SDL_GameControllerButton.SDL_CONTROLLER_BUTTON_INVALID) { return false; } - else - { - return SDL_GameControllerGetButton(_gamepadHandle, _buttonsDriverMapping[(int)inputId]) == 1; - } + + return SDL_GameControllerGetButton(_gamepadHandle, _buttonsDriverMapping[(int)inputId]) == 1; } } } diff --git a/src/Ryujinx.Input.SDL2/SDL2GamepadDriver.cs b/src/Ryujinx.Input.SDL2/SDL2GamepadDriver.cs index d4086a105..d0e793de4 100644 --- a/src/Ryujinx.Input.SDL2/SDL2GamepadDriver.cs +++ b/src/Ryujinx.Input.SDL2/SDL2GamepadDriver.cs @@ -7,8 +7,8 @@ namespace Ryujinx.Input.SDL2 { public class SDL2GamepadDriver : IGamepadDriver { - private Dictionary _gamepadsInstanceIdsMapping; - private List _gamepadsIds; + private readonly Dictionary _gamepadsInstanceIdsMapping; + private readonly List _gamepadsIds; public ReadOnlySpan GamepadsIds => _gamepadsIds.ToArray(); @@ -35,7 +35,7 @@ namespace Ryujinx.Input.SDL2 } } - private string GenerateGamepadId(int joystickIndex) + private static string GenerateGamepadId(int joystickIndex) { Guid guid = SDL_JoystickGetDeviceGUID(joystickIndex); @@ -44,10 +44,10 @@ namespace Ryujinx.Input.SDL2 return null; } - return joystickIndex + "-" + guid.ToString(); + return joystickIndex + "-" + guid; } - private int GetJoystickIndexByGamepadId(string id) + private static int GetJoystickIndexByGamepadId(string id) { string[] data = id.Split("-"); @@ -118,6 +118,7 @@ namespace Ryujinx.Input.SDL2 public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } diff --git a/src/Ryujinx.Input.SDL2/SDL2Keyboard.cs b/src/Ryujinx.Input.SDL2/SDL2Keyboard.cs index 2fe0614d8..f46930a8e 100644 --- a/src/Ryujinx.Input.SDL2/SDL2Keyboard.cs +++ b/src/Ryujinx.Input.SDL2/SDL2Keyboard.cs @@ -26,9 +26,11 @@ namespace Ryujinx.Input.SDL2 private readonly object _userMappingLock = new(); +#pragma warning disable IDE0052 // Remove unread private member private readonly SDL2KeyboardDriver _driver; +#pragma warning restore IDE0052 private StandardKeyboardInputConfig _configuration; - private List _buttonsUserMapping; + private readonly List _buttonsUserMapping; private static readonly SDL_Keycode[] _keysDriverMapping = new SDL_Keycode[(int)Key.Count] { @@ -208,29 +210,19 @@ namespace Ryujinx.Input.SDL2 private static SDL_Keymod GetKeyboardModifierMask(Key key) { - switch (key) + return key switch { - case Key.ShiftLeft: - return SDL_Keymod.KMOD_LSHIFT; - case Key.ShiftRight: - return SDL_Keymod.KMOD_RSHIFT; - case Key.ControlLeft: - return SDL_Keymod.KMOD_LCTRL; - case Key.ControlRight: - return SDL_Keymod.KMOD_RCTRL; - case Key.AltLeft: - return SDL_Keymod.KMOD_LALT; - case Key.AltRight: - return SDL_Keymod.KMOD_RALT; - case Key.WinLeft: - return SDL_Keymod.KMOD_LGUI; - case Key.WinRight: - return SDL_Keymod.KMOD_RGUI; + Key.ShiftLeft => SDL_Keymod.KMOD_LSHIFT, + Key.ShiftRight => SDL_Keymod.KMOD_RSHIFT, + Key.ControlLeft => SDL_Keymod.KMOD_LCTRL, + Key.ControlRight => SDL_Keymod.KMOD_RCTRL, + Key.AltLeft => SDL_Keymod.KMOD_LALT, + Key.AltRight => SDL_Keymod.KMOD_RALT, + Key.WinLeft => SDL_Keymod.KMOD_LGUI, + Key.WinRight => SDL_Keymod.KMOD_RGUI, // NOTE: Menu key isn't supported by SDL2. - case Key.Menu: - default: - return SDL_Keymod.KMOD_NONE; - } + _ => SDL_Keymod.KMOD_NONE, + }; } public KeyboardStateSnapshot GetKeyboardStateSnapshot() @@ -416,4 +408,4 @@ namespace Ryujinx.Input.SDL2 return Vector3.Zero; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input.SDL2/SDLKeyboardDriver.cs b/src/Ryujinx.Input.SDL2/SDLKeyboardDriver.cs index e9361c248..d0268adbb 100644 --- a/src/Ryujinx.Input.SDL2/SDLKeyboardDriver.cs +++ b/src/Ryujinx.Input.SDL2/SDLKeyboardDriver.cs @@ -38,6 +38,7 @@ namespace Ryujinx.Input.SDL2 public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } @@ -51,4 +52,4 @@ namespace Ryujinx.Input.SDL2 return new SDL2Keyboard(this, _keyboardIdentifers[0], "All keyboards"); } } -} \ No newline at end of file +} From ff53dcf5607a82ad38388502b4cf5cc8cca77733 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Mon, 26 Jun 2023 07:25:06 +0200 Subject: [PATCH 08/19] [ARMeilleure] Address dotnet-format issues (#5357) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal --- src/ARMeilleure/Allocators.cs | 5 +- .../CodeGen/Arm64/Arm64Optimizer.cs | 2 +- src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs | 28 +- .../CodeGen/Arm64/ArmExtensionType.cs | 2 +- src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs | 4 +- src/ARMeilleure/CodeGen/Arm64/Assembler.cs | 8 +- .../CodeGen/Arm64/CallingConvention.cs | 2 +- .../CodeGen/Arm64/CodeGenCommon.cs | 2 +- .../CodeGen/Arm64/CodeGenContext.cs | 14 +- .../CodeGen/Arm64/CodeGenerator.cs | 119 ++-- .../CodeGen/Arm64/CodeGeneratorIntrinsic.cs | 2 +- .../CodeGen/Arm64/HardwareCapabilities.cs | 169 +++-- .../CodeGen/Arm64/IntrinsicInfo.cs | 6 +- .../CodeGen/Arm64/IntrinsicTable.cs | 6 +- .../CodeGen/Arm64/IntrinsicType.cs | 4 +- src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs | 34 +- src/ARMeilleure/CodeGen/CompiledFunction.cs | 6 +- src/ARMeilleure/CodeGen/Linking/RelocEntry.cs | 2 +- src/ARMeilleure/CodeGen/Linking/RelocInfo.cs | 2 +- src/ARMeilleure/CodeGen/Linking/SymbolType.cs | 2 +- .../CodeGen/Optimizations/ConstantFolding.cs | 4 +- .../CodeGen/Optimizations/Optimizer.cs | 4 +- .../CodeGen/Optimizations/Simplification.cs | 13 +- .../RegisterAllocators/AllocationResult.cs | 6 +- .../RegisterAllocators/CopyResolver.cs | 42 +- .../RegisterAllocators/HybridAllocator.cs | 18 +- .../RegisterAllocators/IRegisterAllocator.cs | 2 +- .../RegisterAllocators/LinearScanAllocator.cs | 57 +- .../RegisterAllocators/LiveInterval.cs | 8 +- .../RegisterAllocators/LiveIntervalList.cs | 6 +- .../CodeGen/RegisterAllocators/LiveRange.cs | 2 +- .../RegisterAllocators/RegisterMasks.cs | 12 +- .../RegisterAllocators/StackAllocator.cs | 2 +- .../CodeGen/RegisterAllocators/UseList.cs | 36 +- .../CodeGen/Unwinding/UnwindInfo.cs | 2 +- .../CodeGen/Unwinding/UnwindPseudoOp.cs | 10 +- .../CodeGen/Unwinding/UnwindPushEntry.cs | 2 +- src/ARMeilleure/CodeGen/X86/Assembler.cs | 67 +- src/ARMeilleure/CodeGen/X86/AssemblerTable.cs | 52 +- src/ARMeilleure/CodeGen/X86/CallConvName.cs | 4 +- .../CodeGen/X86/CallingConvention.cs | 34 +- src/ARMeilleure/CodeGen/X86/CodeGenContext.cs | 4 +- src/ARMeilleure/CodeGen/X86/CodeGenerator.cs | 618 +++++++++--------- .../CodeGen/X86/HardwareCapabilities.cs | 12 +- src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs | 4 +- src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs | 6 +- src/ARMeilleure/CodeGen/X86/IntrinsicType.cs | 4 +- src/ARMeilleure/CodeGen/X86/Mxcsr.cs | 2 +- src/ARMeilleure/CodeGen/X86/PreAllocator.cs | 296 ++++----- .../CodeGen/X86/PreAllocatorSystemV.cs | 25 +- .../CodeGen/X86/PreAllocatorWindows.cs | 4 +- src/ARMeilleure/CodeGen/X86/X86Condition.cs | 36 +- src/ARMeilleure/CodeGen/X86/X86Instruction.cs | 4 +- src/ARMeilleure/CodeGen/X86/X86Optimizer.cs | 2 +- src/ARMeilleure/CodeGen/X86/X86Register.cs | 31 +- src/ARMeilleure/Common/ArenaAllocator.cs | 15 +- src/ARMeilleure/Common/BitMap.cs | 12 +- src/ARMeilleure/Decoders/Block.cs | 16 +- src/ARMeilleure/Decoders/Condition.cs | 26 +- src/ARMeilleure/Decoders/DataOp.cs | 8 +- src/ARMeilleure/Decoders/Decoder.cs | 34 +- src/ARMeilleure/Decoders/DecoderHelper.cs | 46 +- src/ARMeilleure/Decoders/DecoderMode.cs | 2 +- src/ARMeilleure/Decoders/IOpCode.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32Alu.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluImm16.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32BImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32BReg.cs | 2 +- .../Decoders/IOpCode32Exception.cs | 2 +- .../Decoders/IOpCode32HasSetFlags.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32Mem.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemMult.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemReg.cs | 2 +- src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAlu.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAluImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeAluRs.cs | 4 +- src/ARMeilleure/Decoders/IOpCodeAluRx.cs | 4 +- src/ARMeilleure/Decoders/IOpCodeBImm.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeCond.cs | 2 +- src/ARMeilleure/Decoders/IOpCodeLit.cs | 10 +- src/ARMeilleure/Decoders/IOpCodeSimd.cs | 2 +- src/ARMeilleure/Decoders/InstDescriptor.cs | 8 +- src/ARMeilleure/Decoders/InstEmitter.cs | 2 +- src/ARMeilleure/Decoders/IntType.cs | 12 +- src/ARMeilleure/Decoders/OpCode.cs | 27 +- src/ARMeilleure/Decoders/OpCode32.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Alu.cs | 2 +- src/ARMeilleure/Decoders/OpCode32AluImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32AluRsImm.cs | 6 +- src/ARMeilleure/Decoders/OpCode32BImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32BReg.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Mem.cs | 20 +- src/ARMeilleure/Decoders/OpCode32MemImm.cs | 2 +- src/ARMeilleure/Decoders/OpCode32MemImm8.cs | 2 +- src/ARMeilleure/Decoders/OpCode32MemMult.cs | 12 +- src/ARMeilleure/Decoders/OpCode32Mrs.cs | 4 +- src/ARMeilleure/Decoders/OpCode32MsrReg.cs | 8 +- src/ARMeilleure/Decoders/OpCode32Sat.cs | 2 +- src/ARMeilleure/Decoders/OpCode32Sat16.cs | 2 +- src/ARMeilleure/Decoders/OpCode32SimdBase.cs | 24 +- src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs | 6 +- src/ARMeilleure/Decoders/OpCode32SimdLong.cs | 12 +- .../Decoders/OpCode32SimdMemPair.cs | 4 +- src/ARMeilleure/Decoders/OpCode32SimdSel.cs | 2 +- src/ARMeilleure/Decoders/OpCodeAdr.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAlu.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAluBinary.cs | 2 +- src/ARMeilleure/Decoders/OpCodeAluImm.cs | 4 +- src/ARMeilleure/Decoders/OpCodeAluRs.cs | 6 +- src/ARMeilleure/Decoders/OpCodeAluRx.cs | 8 +- src/ARMeilleure/Decoders/OpCodeBImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmAl.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmCmp.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmCond.cs | 2 +- src/ARMeilleure/Decoders/OpCodeBImmTest.cs | 6 +- src/ARMeilleure/Decoders/OpCodeBReg.cs | 4 +- src/ARMeilleure/Decoders/OpCodeBfm.cs | 8 +- src/ARMeilleure/Decoders/OpCodeCcmp.cs | 10 +- src/ARMeilleure/Decoders/OpCodeCcmpImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeCcmpReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeCsel.cs | 4 +- src/ARMeilleure/Decoders/OpCodeException.cs | 2 +- src/ARMeilleure/Decoders/OpCodeMem.cs | 12 +- src/ARMeilleure/Decoders/OpCodeMemEx.cs | 6 +- src/ARMeilleure/Decoders/OpCodeMemImm.cs | 22 +- src/ARMeilleure/Decoders/OpCodeMemLit.cs | 34 +- src/ARMeilleure/Decoders/OpCodeMemPair.cs | 10 +- src/ARMeilleure/Decoders/OpCodeMemReg.cs | 12 +- src/ARMeilleure/Decoders/OpCodeMov.cs | 8 +- src/ARMeilleure/Decoders/OpCodeMul.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimd.cs | 14 +- src/ARMeilleure/Decoders/OpCodeSimdCvt.cs | 4 +- src/ARMeilleure/Decoders/OpCodeSimdExt.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdFcond.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdFmov.cs | 8 +- src/ARMeilleure/Decoders/OpCodeSimdHelper.cs | 9 +- src/ARMeilleure/Decoders/OpCodeSimdImm.cs | 21 +- src/ARMeilleure/Decoders/OpCodeSimdIns.cs | 20 +- src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs | 8 +- src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs | 51 +- src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs | 100 +-- src/ARMeilleure/Decoders/OpCodeSimdReg.cs | 12 +- src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs | 8 +- .../Decoders/OpCodeSimdRegElemF.cs | 4 +- src/ARMeilleure/Decoders/OpCodeSimdTbl.cs | 2 +- src/ARMeilleure/Decoders/OpCodeSystem.cs | 14 +- src/ARMeilleure/Decoders/OpCodeT16.cs | 2 +- .../Decoders/OpCodeT16AddSubImm3.cs | 6 +- src/ARMeilleure/Decoders/OpCodeT16BImm11.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16BImm8.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs | 22 +- src/ARMeilleure/Decoders/OpCodeT16MemMult.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32Alu.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluImm.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluReg.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs | 6 +- src/ARMeilleure/Decoders/OpCodeT32BImm20.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32BImm24.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs | 2 +- src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32MemMult.cs | 12 +- src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs | 4 +- src/ARMeilleure/Decoders/OpCodeT32Tb.cs | 2 +- src/ARMeilleure/Decoders/OpCodeTable.cs | 67 +- .../Decoders/Optimizations/TailCallRemover.cs | 12 +- src/ARMeilleure/Decoders/RegisterSize.cs | 4 +- src/ARMeilleure/Decoders/ShiftType.cs | 4 +- src/ARMeilleure/Diagnostics/IRDumper.cs | 32 +- src/ARMeilleure/Diagnostics/Logger.cs | 4 +- src/ARMeilleure/Diagnostics/PassName.cs | 4 +- src/ARMeilleure/Diagnostics/Symbols.cs | 3 +- .../Diagnostics/TranslatorEventSource.cs | 6 +- src/ARMeilleure/Instructions/CryptoHelper.cs | 38 +- src/ARMeilleure/Instructions/InstEmitAlu.cs | 19 +- src/ARMeilleure/Instructions/InstEmitAlu32.cs | 3 +- .../Instructions/InstEmitAluHelper.cs | 135 ++-- src/ARMeilleure/Instructions/InstEmitBfm.cs | 6 +- src/ARMeilleure/Instructions/InstEmitCcmp.cs | 5 +- src/ARMeilleure/Instructions/InstEmitCsel.cs | 7 +- src/ARMeilleure/Instructions/InstEmitDiv.cs | 7 +- .../Instructions/InstEmitException.cs | 2 +- src/ARMeilleure/Instructions/InstEmitFlow.cs | 6 +- .../Instructions/InstEmitFlow32.cs | 6 +- .../Instructions/InstEmitFlowHelper.cs | 76 +-- .../Instructions/InstEmitHashHelper.cs | 16 +- .../Instructions/InstEmitHelper.cs | 129 ++-- .../Instructions/InstEmitMemory.cs | 68 +- .../Instructions/InstEmitMemory32.cs | 25 +- .../Instructions/InstEmitMemoryEx.cs | 35 +- .../Instructions/InstEmitMemoryExHelper.cs | 13 +- .../Instructions/InstEmitMemoryHelper.cs | 261 +++++--- src/ARMeilleure/Instructions/InstEmitMove.cs | 2 +- src/ARMeilleure/Instructions/InstEmitMul.cs | 13 +- src/ARMeilleure/Instructions/InstEmitMul32.cs | 11 +- .../Instructions/InstEmitSimdArithmetic.cs | 116 ++-- .../Instructions/InstEmitSimdArithmetic32.cs | 9 +- .../Instructions/InstEmitSimdCmp.cs | 7 +- .../Instructions/InstEmitSimdCvt.cs | 149 +++-- .../Instructions/InstEmitSimdCvt32.cs | 55 +- .../Instructions/InstEmitSimdHash.cs | 8 +- .../Instructions/InstEmitSimdHash32.cs | 4 +- .../Instructions/InstEmitSimdHashHelper.cs | 6 +- .../Instructions/InstEmitSimdHelper.cs | 174 ++--- .../Instructions/InstEmitSimdHelper32.cs | 49 +- .../Instructions/InstEmitSimdHelper32Arm64.cs | 18 +- .../Instructions/InstEmitSimdHelperArm64.cs | 8 +- .../Instructions/InstEmitSimdLogical.cs | 21 +- .../Instructions/InstEmitSimdLogical32.cs | 24 +- .../Instructions/InstEmitSimdMemory.cs | 4 +- .../Instructions/InstEmitSimdMove.cs | 85 ++- .../Instructions/InstEmitSimdMove32.cs | 7 +- .../Instructions/InstEmitSimdShift.cs | 39 +- .../Instructions/InstEmitSimdShift32.cs | 7 +- .../Instructions/InstEmitSystem.cs | 90 ++- .../Instructions/InstEmitSystem32.cs | 55 +- .../Instructions/NativeInterface.cs | 6 +- src/ARMeilleure/Instructions/SoftFallback.cs | 94 ++- src/ARMeilleure/Instructions/SoftFloat.cs | 306 ++++----- .../IntermediateRepresentation/BasicBlock.cs | 11 +- .../BasicBlockFrequency.cs | 4 +- .../IntermediateRepresentation/Comparison.cs | 20 +- .../IntermediateRepresentation/Instruction.cs | 4 +- .../IntermediateRepresentation/Intrinsic.cs | 6 +- .../MemoryOperand.cs | 12 +- .../IntermediateRepresentation/Multiplier.cs | 4 +- .../IntermediateRepresentation/Operand.cs | 80 +-- .../IntermediateRepresentation/OperandKind.cs | 4 +- .../IntermediateRepresentation/OperandType.cs | 55 +- .../IntermediateRepresentation/Operation.cs | 64 +- .../IntermediateRepresentation/Register.cs | 6 +- .../RegisterType.cs | 4 +- src/ARMeilleure/Memory/IJitMemoryBlock.cs | 2 +- src/ARMeilleure/Memory/IMemoryManager.cs | 2 +- src/ARMeilleure/Memory/MemoryManagerType.cs | 2 +- src/ARMeilleure/Native/JitSupportDarwin.cs | 2 +- src/ARMeilleure/Optimizations.cs | 44 +- src/ARMeilleure/Signal/NativeSignalHandler.cs | 18 +- src/ARMeilleure/Signal/TestMethods.cs | 6 +- .../Signal/UnixSignalHandlerRegistration.cs | 4 +- .../Signal/WindowsPartialUnmapHandler.cs | 2 + src/ARMeilleure/State/Aarch32Mode.cs | 16 +- src/ARMeilleure/State/ExceptionCallback.cs | 2 +- src/ARMeilleure/State/ExecutionContext.cs | 6 +- src/ARMeilleure/State/ExecutionMode.cs | 4 +- src/ARMeilleure/State/FPCR.cs | 6 +- src/ARMeilleure/State/FPException.cs | 10 +- src/ARMeilleure/State/FPRoundingMode.cs | 8 +- src/ARMeilleure/State/FPSCR.cs | 2 +- src/ARMeilleure/State/FPSR.cs | 2 +- src/ARMeilleure/State/FPState.cs | 2 +- src/ARMeilleure/State/FPType.cs | 2 +- src/ARMeilleure/State/ICounter.cs | 2 +- src/ARMeilleure/State/NativeContext.cs | 4 +- src/ARMeilleure/State/PState.cs | 2 +- src/ARMeilleure/State/RegisterAlias.cs | 18 +- src/ARMeilleure/State/RegisterConsts.cs | 14 +- src/ARMeilleure/State/V128.cs | 40 +- src/ARMeilleure/Statistics.cs | 14 +- .../Translation/ArmEmitterContext.cs | 10 +- .../Translation/Cache/CacheEntry.cs | 8 +- .../Translation/Cache/CacheMemoryAllocator.cs | 2 +- src/ARMeilleure/Translation/Cache/JitCache.cs | 32 +- .../Translation/Cache/JitCacheInvalidation.cs | 8 +- .../Translation/Cache/JitUnwindWindows.cs | 113 ++-- src/ARMeilleure/Translation/Compiler.cs | 10 +- .../Translation/CompilerContext.cs | 18 +- .../Translation/CompilerOptions.cs | 12 +- .../Translation/ControlFlowGraph.cs | 4 +- src/ARMeilleure/Translation/DelegateInfo.cs | 2 + src/ARMeilleure/Translation/Dominance.cs | 4 +- src/ARMeilleure/Translation/EmitterContext.cs | 8 +- src/ARMeilleure/Translation/GuestFunction.cs | 2 +- src/ARMeilleure/Translation/IntervalTree.cs | 132 ++-- .../Translation/PTC/EncodingCache.cs | 2 +- .../Translation/PTC/IPtcLoadState.cs | 2 +- src/ARMeilleure/Translation/PTC/Ptc.cs | 405 ++++++------ .../Translation/PTC/PtcFormatter.cs | 4 +- .../Translation/PTC/PtcLoadingState.cs | 4 +- .../Translation/PTC/PtcProfiler.cs | 130 ++-- src/ARMeilleure/Translation/PTC/PtcState.cs | 4 +- .../Translation/RegisterToLocal.cs | 4 +- src/ARMeilleure/Translation/RegisterUsage.cs | 25 +- .../Translation/SsaConstruction.cs | 4 +- .../Translation/SsaDeconstruction.cs | 2 +- .../Translation/TranslatedFunction.cs | 2 +- src/ARMeilleure/Translation/Translator.cs | 16 +- .../Translation/TranslatorStubs.cs | 2 +- .../Translation/TranslatorTestMethods.cs | 5 +- 300 files changed, 3515 insertions(+), 3120 deletions(-) diff --git a/src/ARMeilleure/Allocators.cs b/src/ARMeilleure/Allocators.cs index deabf9a26..ba782b99a 100644 --- a/src/ARMeilleure/Allocators.cs +++ b/src/ARMeilleure/Allocators.cs @@ -23,10 +23,7 @@ namespace ARMeilleure [MethodImpl(MethodImplOptions.AggressiveInlining)] private static ArenaAllocator GetAllocator(ref ArenaAllocator alloc, uint pageSize, uint pageCount) { - if (alloc == null) - { - alloc = new ArenaAllocator(pageSize, pageCount); - } + alloc ??= new ArenaAllocator(pageSize, pageCount); return alloc; } diff --git a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs index fdd4d0241..00ffd1958 100644 --- a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs +++ b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs @@ -221,7 +221,7 @@ namespace ARMeilleure.CodeGen.Arm64 2 => Multiplier.x4, 3 => Multiplier.x8, 4 => Multiplier.x16, - _ => Multiplier.x1 + _ => Multiplier.x1, }; baseOp = indexOnSrc2 ? src1 : src2; diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs index db27a8104..5db898591 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs @@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.Arm64 { enum ArmCondition { - Eq = 0, - Ne = 1, + Eq = 0, + Ne = 1, GeUn = 2, LtUn = 3, - Mi = 4, - Pl = 5, - Vs = 6, - Vc = 7, + Mi = 4, + Pl = 5, + Vs = 6, + Vc = 7, GtUn = 8, LeUn = 9, - Ge = 10, - Lt = 11, - Gt = 12, - Le = 13, - Al = 14, - Nv = 15 + Ge = 10, + Lt = 11, + Gt = 12, + Le = 13, + Al = 14, + Nv = 15, } static class ComparisonArm64Extensions @@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.Arm64 { return comp switch { +#pragma warning disable IDE0055 // Disable formatting Comparison.Equal => ArmCondition.Eq, Comparison.NotEqual => ArmCondition.Ne, Comparison.Greater => ArmCondition.Gt, @@ -39,8 +40,9 @@ namespace ARMeilleure.CodeGen.Arm64 Comparison.Less => ArmCondition.Lt, Comparison.GreaterOrEqualUI => ArmCondition.GeUn, Comparison.LessUI => ArmCondition.LtUn, +#pragma warning restore IDE0055 - _ => throw new ArgumentException(null, nameof(comp)) + _ => throw new ArgumentException(null, nameof(comp)), }; } } diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs index 062a6d0b7..20ccfd4ba 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs @@ -9,6 +9,6 @@ namespace ARMeilleure.CodeGen.Arm64 Sxtb = 4, Sxth = 5, Sxtw = 6, - Sxtx = 7 + Sxtx = 7, } } diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs index d223a1464..f32407c43 100644 --- a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.CodeGen.Arm64 Lsl = 0, Lsr = 1, Asr = 2, - Ror = 3 + Ror = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs index 0ec0be7cb..41684faf2 100644 --- a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs +++ b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs @@ -188,7 +188,7 @@ namespace ARMeilleure.CodeGen.Arm64 uint rmode = topHalf ? 1u << 19 : 0u; uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u; - uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u; + uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u; WriteUInt32(0x1e260000u | (opcode << 16) | rmode | ftype | sf | EncodeReg(rd) | (EncodeReg(rn) << 5)); } @@ -992,7 +992,7 @@ namespace ARMeilleure.CodeGen.Arm64 { OperandType.FP32 => 0, OperandType.FP64 => 1, - _ => 2 + _ => 2, }; instruction = vecInst | ((uint)opc << 30); @@ -1124,10 +1124,11 @@ namespace ARMeilleure.CodeGen.Arm64 OperandType.FP32 => 2, OperandType.FP64 => 3, OperandType.V128 => 4, - _ => throw new ArgumentException($"Invalid type {type}.") + _ => throw new ArgumentException($"Invalid type {type}."), }; } +#pragma warning disable IDE0051 // Remove unused private member private void WriteInt16(short value) { WriteUInt16((ushort)value); @@ -1142,6 +1143,7 @@ namespace ARMeilleure.CodeGen.Arm64 { _stream.WriteByte(value); } +#pragma warning restore IDE0051 private void WriteUInt16(ushort value) { diff --git a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs index fda8d7867..a487c2ed3 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs @@ -93,4 +93,4 @@ namespace ARMeilleure.CodeGen.Arm64 return 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs index 8d1e597ba..1f0148d5e 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs @@ -88,4 +88,4 @@ namespace ARMeilleure.CodeGen.Arm64 return true; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs index 0dd5355f4..12ebabddd 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs @@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.Arm64 private const int CbnzInstLength = 4; private const int LdrLitInstLength = 4; - private Stream _stream; + private readonly Stream _stream; public int StreamOffset => (int)_stream.Length; @@ -32,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64 private readonly Dictionary _visitedBlocks; private readonly Dictionary> _pendingBranches; - private struct ConstantPoolEntry + private readonly struct ConstantPoolEntry { public readonly int Offset; public readonly Symbol Symbol; @@ -58,7 +58,7 @@ namespace ARMeilleure.CodeGen.Arm64 private readonly bool _relocatable; - public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksCount, bool relocatable) + public CodeGenContext(AllocationResult allocResult, int maxCallArgs, bool relocatable) { _stream = MemoryStreamManager.Shared.GetStream(); @@ -93,10 +93,10 @@ namespace ARMeilleure.CodeGen.Arm64 if (_pendingBranches.TryGetValue(block, out var list)) { - foreach (var tuple in list) + foreach ((ArmCondition condition, long branchPos) in list) { - _stream.Seek(tuple.BranchPos, SeekOrigin.Begin); - WriteBranch(tuple.Condition, target); + _stream.Seek(branchPos, SeekOrigin.Begin); + WriteBranch(condition, target); } _stream.Seek(target, SeekOrigin.Begin); @@ -284,4 +284,4 @@ namespace ARMeilleure.CodeGen.Arm64 _stream.WriteByte((byte)(value >> 56)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs index 927198505..2df86671a 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs @@ -10,7 +10,6 @@ using System; using System.Collections.Generic; using System.Diagnostics; using System.Numerics; - using static ARMeilleure.IntermediateRepresentation.Operand; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -31,15 +30,16 @@ namespace ARMeilleure.CodeGen.Arm64 { Byte, Hword, - Auto + Auto, } - private static Action[] _instTable; + private static readonly Action[] _instTable; static CodeGenerator() { _instTable = new Action[EnumUtils.GetCount(typeof(Instruction))]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.Add, GenerateAdd); Add(Instruction.BitwiseAnd, GenerateBitwiseAnd); Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr); @@ -48,7 +48,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Instruction.BranchIf, GenerateBranchIf); Add(Instruction.ByteSwap, GenerateByteSwap); Add(Instruction.Call, GenerateCall); - //Add(Instruction.Clobber, GenerateClobber); + // Add(Instruction.Clobber, GenerateClobber); Add(Instruction.Compare, GenerateCompare); Add(Instruction.CompareAndSwap, GenerateCompareAndSwap); Add(Instruction.CompareAndSwap16, GenerateCompareAndSwap16); @@ -100,6 +100,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Instruction.ZeroExtend16, GenerateZeroExtend16); Add(Instruction.ZeroExtend32, GenerateZeroExtend32); Add(Instruction.ZeroExtend8, GenerateZeroExtend8); +#pragma warning restore IDE0055 static void Add(Instruction inst, Action func) { @@ -131,7 +132,7 @@ namespace ARMeilleure.CodeGen.Arm64 StackAllocator stackAlloc = new(); - PreAllocator.RunPass(cctx, stackAlloc, out int maxCallArgs); + PreAllocator.RunPass(cctx, out int maxCallArgs); Logger.EndPass(PassName.PreAllocation, cfg); @@ -170,7 +171,7 @@ namespace ARMeilleure.CodeGen.Arm64 bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0; - CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable); + CodeGenContext context = new(allocResult, maxCallArgs, relocatable); UnwindInfo unwindInfo = WritePrologue(context); @@ -292,7 +293,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateBitwiseNot(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -330,7 +331,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateByteSwap(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -364,15 +365,15 @@ namespace ARMeilleure.CodeGen.Arm64 { if (operation.SourcesCount == 5) // CompareAndSwap128 has 5 sources, compared to CompareAndSwap64/32's 3. { - Operand actualLow = operation.GetDestination(0); - Operand actualHigh = operation.GetDestination(1); - Operand temp0 = operation.GetDestination(2); - Operand temp1 = operation.GetDestination(3); - Operand address = operation.GetSource(0); - Operand expectedLow = operation.GetSource(1); + Operand actualLow = operation.GetDestination(0); + Operand actualHigh = operation.GetDestination(1); + Operand temp0 = operation.GetDestination(2); + Operand temp1 = operation.GetDestination(3); + Operand address = operation.GetSource(0); + Operand expectedLow = operation.GetSource(1); Operand expectedHigh = operation.GetSource(2); - Operand desiredLow = operation.GetSource(3); - Operand desiredHigh = operation.GetSource(4); + Operand desiredLow = operation.GetSource(3); + Operand desiredHigh = operation.GetSource(4); GenerateAtomicDcas( context, @@ -388,11 +389,11 @@ namespace ARMeilleure.CodeGen.Arm64 } else { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Auto); } @@ -400,22 +401,22 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCompareAndSwap16(CodeGenContext context, Operation operation) { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Hword); } private static void GenerateCompareAndSwap8(CodeGenContext context, Operation operation) { - Operand actual = operation.GetDestination(0); - Operand result = operation.GetDestination(1); - Operand address = operation.GetSource(0); + Operand actual = operation.GetDestination(0); + Operand result = operation.GetDestination(1); + Operand address = operation.GetSource(0); Operand expected = operation.GetSource(1); - Operand desired = operation.GetSource(2); + Operand desired = operation.GetSource(2); GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Byte); } @@ -444,13 +445,13 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(dest.Type.IsInteger()); Debug.Assert(src1.Type == OperandType.I32); - context.Assembler.Cmp (src1, Const(src1.Type, 0)); + context.Assembler.Cmp(src1, Const(src1.Type, 0)); context.Assembler.Csel(dest, src2, src3, ArmCondition.Ne); } private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64); @@ -460,7 +461,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateConvertToFP(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -479,7 +480,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateConvertToFPUI(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -491,7 +492,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCopy(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -523,7 +524,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -535,9 +536,9 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateDivide(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); ValidateBinOp(dest, dividend, divisor); @@ -553,9 +554,9 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateDivideUI(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); ValidateBinOp(dest, dividend, divisor); @@ -564,7 +565,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); context.Assembler.Ldr(value, address); @@ -572,7 +573,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad16(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -582,7 +583,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateLoad8(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -641,7 +642,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateNegate(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -728,7 +729,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -738,7 +739,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -748,7 +749,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateSignExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -758,7 +759,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateFill(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -799,7 +800,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStackAlloc(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -811,7 +812,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); context.Assembler.Str(value, address); @@ -819,7 +820,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore16(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -829,7 +830,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateStore8(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); Debug.Assert(value.Type.IsInteger()); @@ -876,7 +877,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); if (dest != default) @@ -1022,7 +1023,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1032,7 +1033,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1042,7 +1043,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1052,7 +1053,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1068,7 +1069,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static void GenerateZeroExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1078,7 +1079,7 @@ namespace ARMeilleure.CodeGen.Arm64 private static UnwindInfo WritePrologue(CodeGenContext context) { - List pushEntries = new List(); + List pushEntries = new(); Operand rsp = Register(SpRegister); @@ -1568,11 +1569,13 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(op1.Type == op3.Type); } +#pragma warning disable IDE0051 // Remove unused private member private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operand op4) { Debug.Assert(op1.Type == op2.Type); Debug.Assert(op1.Type == op3.Type); Debug.Assert(op1.Type == op4.Type); } +#pragma warning restore IDE0051 } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs index 1309404a8..b87370557 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs @@ -688,4 +688,4 @@ namespace ARMeilleure.CodeGen.Arm64 context.Assembler.WriteInstruction(instruction, rd, rn); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs index 99ff299e9..86afc2b4d 100644 --- a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs +++ b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs @@ -1,7 +1,4 @@ using System; -using System.Linq; -using System.Reflection; -using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Runtime.Intrinsics.Arm; using System.Runtime.Versioning; @@ -35,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64 } } -#region Linux + #region Linux private const ulong AT_HWCAP = 16; private const ulong AT_HWCAP2 = 26; @@ -46,88 +43,88 @@ namespace ARMeilleure.CodeGen.Arm64 [Flags] public enum LinuxFeatureFlagsHwCap : ulong { - Fp = 1 << 0, - Asimd = 1 << 1, - Evtstrm = 1 << 2, - Aes = 1 << 3, - Pmull = 1 << 4, - Sha1 = 1 << 5, - Sha2 = 1 << 6, - Crc32 = 1 << 7, - Atomics = 1 << 8, - FpHp = 1 << 9, - AsimdHp = 1 << 10, - CpuId = 1 << 11, - AsimdRdm = 1 << 12, - Jscvt = 1 << 13, - Fcma = 1 << 14, - Lrcpc = 1 << 15, - DcpOp = 1 << 16, - Sha3 = 1 << 17, - Sm3 = 1 << 18, - Sm4 = 1 << 19, - AsimdDp = 1 << 20, - Sha512 = 1 << 21, - Sve = 1 << 22, - AsimdFhm = 1 << 23, - Dit = 1 << 24, - Uscat = 1 << 25, - Ilrcpc = 1 << 26, - FlagM = 1 << 27, - Ssbs = 1 << 28, - Sb = 1 << 29, - Paca = 1 << 30, - Pacg = 1UL << 31 + Fp = 1 << 0, + Asimd = 1 << 1, + Evtstrm = 1 << 2, + Aes = 1 << 3, + Pmull = 1 << 4, + Sha1 = 1 << 5, + Sha2 = 1 << 6, + Crc32 = 1 << 7, + Atomics = 1 << 8, + FpHp = 1 << 9, + AsimdHp = 1 << 10, + CpuId = 1 << 11, + AsimdRdm = 1 << 12, + Jscvt = 1 << 13, + Fcma = 1 << 14, + Lrcpc = 1 << 15, + DcpOp = 1 << 16, + Sha3 = 1 << 17, + Sm3 = 1 << 18, + Sm4 = 1 << 19, + AsimdDp = 1 << 20, + Sha512 = 1 << 21, + Sve = 1 << 22, + AsimdFhm = 1 << 23, + Dit = 1 << 24, + Uscat = 1 << 25, + Ilrcpc = 1 << 26, + FlagM = 1 << 27, + Ssbs = 1 << 28, + Sb = 1 << 29, + Paca = 1 << 30, + Pacg = 1UL << 31, } [Flags] public enum LinuxFeatureFlagsHwCap2 : ulong { - Dcpodp = 1 << 0, - Sve2 = 1 << 1, - SveAes = 1 << 2, - SvePmull = 1 << 3, - SveBitperm = 1 << 4, - SveSha3 = 1 << 5, - SveSm4 = 1 << 6, - FlagM2 = 1 << 7, - Frint = 1 << 8, - SveI8mm = 1 << 9, - SveF32mm = 1 << 10, - SveF64mm = 1 << 11, - SveBf16 = 1 << 12, - I8mm = 1 << 13, - Bf16 = 1 << 14, - Dgh = 1 << 15, - Rng = 1 << 16, - Bti = 1 << 17, - Mte = 1 << 18, - Ecv = 1 << 19, - Afp = 1 << 20, - Rpres = 1 << 21, - Mte3 = 1 << 22, - Sme = 1 << 23, - Sme_i16i64 = 1 << 24, - Sme_f64f64 = 1 << 25, - Sme_i8i32 = 1 << 26, - Sme_f16f32 = 1 << 27, - Sme_b16f32 = 1 << 28, - Sme_f32f32 = 1 << 29, - Sme_fa64 = 1 << 30, - Wfxt = 1UL << 31, - Ebf16 = 1UL << 32, - Sve_Ebf16 = 1UL << 33, - Cssc = 1UL << 34, - Rprfm = 1UL << 35, - Sve2p1 = 1UL << 36 + Dcpodp = 1 << 0, + Sve2 = 1 << 1, + SveAes = 1 << 2, + SvePmull = 1 << 3, + SveBitperm = 1 << 4, + SveSha3 = 1 << 5, + SveSm4 = 1 << 6, + FlagM2 = 1 << 7, + Frint = 1 << 8, + SveI8mm = 1 << 9, + SveF32mm = 1 << 10, + SveF64mm = 1 << 11, + SveBf16 = 1 << 12, + I8mm = 1 << 13, + Bf16 = 1 << 14, + Dgh = 1 << 15, + Rng = 1 << 16, + Bti = 1 << 17, + Mte = 1 << 18, + Ecv = 1 << 19, + Afp = 1 << 20, + Rpres = 1 << 21, + Mte3 = 1 << 22, + Sme = 1 << 23, + Sme_i16i64 = 1 << 24, + Sme_f64f64 = 1 << 25, + Sme_i8i32 = 1 << 26, + Sme_f16f32 = 1 << 27, + Sme_b16f32 = 1 << 28, + Sme_f32f32 = 1 << 29, + Sme_fa64 = 1 << 30, + Wfxt = 1UL << 31, + Ebf16 = 1UL << 32, + Sve_Ebf16 = 1UL << 33, + Cssc = 1UL << 34, + Rprfm = 1UL << 35, + Sve2p1 = 1UL << 36, } public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0; public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0; -#endregion + #endregion -#region macOS + #region macOS [LibraryImport("libSystem.dylib", SetLastError = true)] private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize); @@ -143,7 +140,7 @@ namespace ARMeilleure.CodeGen.Arm64 return false; } - private static string[] _sysctlNames = new string[] + private static readonly string[] _sysctlNames = new string[] { "hw.optional.floatingpoint", "hw.optional.AdvSIMD", @@ -153,26 +150,26 @@ namespace ARMeilleure.CodeGen.Arm64 "hw.optional.arm.FEAT_LSE", "hw.optional.armv8_crc32", "hw.optional.arm.FEAT_SHA1", - "hw.optional.arm.FEAT_SHA256" + "hw.optional.arm.FEAT_SHA256", }; [Flags] public enum MacOsFeatureFlags { - Fp = 1 << 0, + Fp = 1 << 0, AdvSimd = 1 << 1, - Fp16 = 1 << 2, - Aes = 1 << 3, - Pmull = 1 << 4, - Lse = 1 << 5, - Crc32 = 1 << 6, - Sha1 = 1 << 7, - Sha256 = 1 << 8 + Fp16 = 1 << 2, + Aes = 1 << 3, + Pmull = 1 << 4, + Lse = 1 << 5, + Crc32 = 1 << 6, + Sha1 = 1 << 7, + Sha256 = 1 << 8, } public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0; -#endregion + #endregion public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd); public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes); diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs index 8695db903..956fc778d 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs @@ -1,8 +1,8 @@ namespace ARMeilleure.CodeGen.Arm64 { - struct IntrinsicInfo + readonly struct IntrinsicInfo { - public uint Inst { get; } + public uint Inst { get; } public IntrinsicType Type { get; } public IntrinsicInfo(uint inst, IntrinsicType type) @@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.Arm64 Type = type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs index c2bd0bd51..dbd5bdd10 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs @@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.Arm64 { static class IntrinsicTable { - private static IntrinsicInfo[] _intrinTable; + private static readonly IntrinsicInfo[] _intrinTable; static IntrinsicTable() { _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))]; +#pragma warning disable IDE0055 // Disable formatting Add(Intrinsic.Arm64AbsS, new IntrinsicInfo(0x5e20b800u, IntrinsicType.ScalarUnary)); Add(Intrinsic.Arm64AbsV, new IntrinsicInfo(0x0e20b800u, IntrinsicType.VectorUnary)); Add(Intrinsic.Arm64AddhnV, new IntrinsicInfo(0x0e204000u, IntrinsicType.VectorTernaryRd)); @@ -448,6 +449,7 @@ namespace ARMeilleure.CodeGen.Arm64 Add(Intrinsic.Arm64XtnV, new IntrinsicInfo(0x0e212800u, IntrinsicType.VectorUnary)); Add(Intrinsic.Arm64Zip1V, new IntrinsicInfo(0x0e003800u, IntrinsicType.VectorBinary)); Add(Intrinsic.Arm64Zip2V, new IntrinsicInfo(0x0e007800u, IntrinsicType.VectorBinary)); +#pragma warning restore IDE0055 } private static void Add(Intrinsic intrin, IntrinsicInfo info) @@ -460,4 +462,4 @@ namespace ARMeilleure.CodeGen.Arm64 return _intrinTable[(int)intrin]; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs index df61ea1eb..7538575c9 100644 --- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs +++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs @@ -55,6 +55,6 @@ namespace ARMeilleure.CodeGen.Arm64 VectorTernaryShrRd, GetRegister, - SetRegister + SetRegister, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs index 74f80e0fb..f66bb66e6 100644 --- a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs @@ -1,4 +1,3 @@ -using ARMeilleure.CodeGen.RegisterAllocators; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; @@ -31,7 +30,7 @@ namespace ARMeilleure.CodeGen.Arm64 } } - public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs) + public static void RunPass(CompilerContext cctx, out int maxCallArgs) { maxCallArgs = -1; @@ -41,7 +40,7 @@ namespace ARMeilleure.CodeGen.Arm64 for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext) { - ConstantDict constants = new ConstantDict(); + ConstantDict constants = new(); Operation nextNode; @@ -92,7 +91,7 @@ namespace ARMeilleure.CodeGen.Arm64 InsertReturnCopy(block.Operations, node); break; case Instruction.Tailcall: - InsertTailcallCopies(constants, block.Operations, stackAlloc, node, node); + InsertTailcallCopies(constants, block.Operations, node, node); break; } } @@ -138,10 +137,7 @@ namespace ARMeilleure.CodeGen.Arm64 { src2 = node.GetSource(1); - Operand temp = src1; - - src1 = src2; - src2 = temp; + (src2, src1) = (src1, src2); node.SetSource(0, src1); node.SetSource(1, src2); @@ -265,9 +261,9 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; - List sources = new List + List sources = new() { - operation.GetSource(0) + operation.GetSource(0), }; int argsCount = operation.SourcesCount - 1; @@ -302,10 +298,10 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1))); continue; @@ -339,7 +335,7 @@ namespace ARMeilleure.CodeGen.Arm64 { if (dest.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, retLReg)); @@ -364,16 +360,14 @@ namespace ARMeilleure.CodeGen.Arm64 operation.SetSources(sources.ToArray()); } - private static void InsertTailcallCopies( - ConstantDict constants, + private static void InsertTailcallCopies(ConstantDict constants, IntrusiveList nodes, - StackAllocator stackAlloc, Operation node, Operation operation) { - List sources = new List + List sources = new() { - operation.GetSource(0) + operation.GetSource(0), }; int argsCount = operation.SourcesCount - 1; @@ -403,7 +397,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); @@ -519,7 +513,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (source.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0))); diff --git a/src/ARMeilleure/CodeGen/CompiledFunction.cs b/src/ARMeilleure/CodeGen/CompiledFunction.cs index 0560bf2e9..3844cbfc9 100644 --- a/src/ARMeilleure/CodeGen/CompiledFunction.cs +++ b/src/ARMeilleure/CodeGen/CompiledFunction.cs @@ -35,9 +35,9 @@ namespace ARMeilleure.CodeGen /// Relocation info internal CompiledFunction(byte[] code, UnwindInfo unwindInfo, RelocInfo relocInfo) { - Code = code; + Code = code; UnwindInfo = unwindInfo; - RelocInfo = relocInfo; + RelocInfo = relocInfo; } /// @@ -65,4 +65,4 @@ namespace ARMeilleure.CodeGen return Marshal.GetDelegateForFunctionPointer(codePointer); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs index a27bfded2..d103bc395 100644 --- a/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs +++ b/src/ARMeilleure/CodeGen/Linking/RelocEntry.cs @@ -35,4 +35,4 @@ namespace ARMeilleure.CodeGen.Linking return $"({nameof(Position)} = {Position}, {nameof(Symbol)} = {Symbol})"; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs index caaf08e3d..01ff0347b 100644 --- a/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs +++ b/src/ARMeilleure/CodeGen/Linking/RelocInfo.cs @@ -29,4 +29,4 @@ namespace ARMeilleure.CodeGen.Linking _entries = entries; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs index b05b69692..ed348751b 100644 --- a/src/ARMeilleure/CodeGen/Linking/SymbolType.cs +++ b/src/ARMeilleure/CodeGen/Linking/SymbolType.cs @@ -23,6 +23,6 @@ /// /// Refers to a special symbol which is handled by . /// - Special + Special, } } diff --git a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs index c5a22a537..be3dff58c 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs @@ -164,7 +164,7 @@ namespace ARMeilleure.CodeGen.Optimizations } break; - case Instruction.Multiply: + case Instruction.Multiply: if (type == OperandType.I32) { EvaluateBinaryI32(operation, (x, y) => x * y); @@ -343,4 +343,4 @@ namespace ARMeilleure.CodeGen.Optimizations operation.TurnIntoCopy(Const(op(x, y))); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs b/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs index a45bb4551..1afc3a782 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs @@ -182,7 +182,7 @@ namespace ARMeilleure.CodeGen.Optimizations private static void PropagateCopy(ref Span buffer, Operation copyOp) { // Propagate copy source operand to all uses of the destination operand. - Operand dest = copyOp.Destination; + Operand dest = copyOp.Destination; Operand source = copyOp.GetSource(0); Span uses = dest.GetUses(ref buffer); @@ -249,4 +249,4 @@ namespace ARMeilleure.CodeGen.Optimizations return operation.Destination.Type == operation.GetSource(0).Type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs index a439d6424..53a7f3ede 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs @@ -171,13 +171,12 @@ namespace ARMeilleure.CodeGen.Optimizations private static ulong AllOnes(OperandType type) { - switch (type) + return type switch { - case OperandType.I32: return ~0U; - case OperandType.I64: return ~0UL; - } - - throw new ArgumentException("Invalid operand type \"" + type + "\"."); + OperandType.I32 => ~0U, + OperandType.I64 => ~0UL, + _ => throw new ArgumentException("Invalid operand type \"" + type + "\"."), + }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs index 43e5c7e2c..7b9c2f77f 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs @@ -4,7 +4,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { public int IntUsedRegisters { get; } public int VecUsedRegisters { get; } - public int SpillRegionSize { get; } + public int SpillRegionSize { get; } public AllocationResult( int intUsedRegisters, @@ -13,7 +13,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { IntUsedRegisters = intUsedRegisters; VecUsedRegisters = vecUsedRegisters; - SpillRegionSize = spillRegionSize; + SpillRegionSize = spillRegionSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs index 587b1a024..af10330ba 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs @@ -1,7 +1,6 @@ using ARMeilleure.IntermediateRepresentation; using System; using System.Collections.Generic; - using static ARMeilleure.IntermediateRepresentation.Operand.Factory; using static ARMeilleure.IntermediateRepresentation.Operation.Factory; @@ -13,16 +12,16 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { private readonly struct Copy { - public Register Dest { get; } + public Register Dest { get; } public Register Source { get; } public OperandType Type { get; } public Copy(Register dest, Register source, OperandType type) { - Dest = dest; + Dest = dest; Source = source; - Type = type; + Type = type; } } @@ -42,19 +41,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public void Sequence(List sequence) { - Dictionary locations = new Dictionary(); - Dictionary sources = new Dictionary(); + Dictionary locations = new(); + Dictionary sources = new(); - Dictionary types = new Dictionary(); + Dictionary types = new(); - Queue pendingQueue = new Queue(); - Queue readyQueue = new Queue(); + Queue pendingQueue = new(); + Queue readyQueue = new(); foreach (Copy copy in _copies) { locations[copy.Source] = copy.Source; - sources[copy.Dest] = copy.Source; - types[copy.Dest] = copy.Type; + sources[copy.Dest] = copy.Source; + types[copy.Dest] = copy.Type; pendingQueue.Enqueue(copy.Dest); } @@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } - copyDest = current; + copyDest = current; origSource = sources[copyDest]; copySource = locations[origSource]; @@ -186,10 +185,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type) { - if (_fillQueue == null) - { - _fillQueue = new Queue(); - } + _fillQueue ??= new Queue(); Operand register = GetRegister(right.Register, type); Operand offset = Const(left.SpillOffset); @@ -201,10 +197,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type) { - if (_spillQueue == null) - { - _spillQueue = new Queue(); - } + _spillQueue ??= new Queue(); Operand offset = Const(right.SpillOffset); Operand register = GetRegister(left.Register, type); @@ -216,10 +209,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type) { - if (_parallelCopy == null) - { - _parallelCopy = new ParallelCopy(); - } + _parallelCopy ??= new ParallelCopy(); _parallelCopy.AddCopy(right.Register, left.Register, type); @@ -228,7 +218,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public Operation[] Sequence() { - List sequence = new List(); + List sequence = new(); if (_spillQueue != null) { @@ -256,4 +246,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return Register(reg.Index, reg.Type, type); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs index 25952c775..5f1d6ce89 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters) { - HasCall = hasCall; + HasCall = hasCall; IntFixedRegisters = intFixedRegisters; VecFixedRegisters = vecFixedRegisters; } @@ -39,7 +39,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private int _first; private int _last; - public bool IsBlockLocal => _first == _last; + public readonly bool IsBlockLocal => _first == _last; public LocalInfo(OperandType type, int uses, int blkIndex) { @@ -53,7 +53,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators SpillOffset = default; _first = -1; - _last = -1; + _last = -1; SetBlockIndex(blkIndex); } @@ -348,17 +348,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (dest.Type.IsInteger()) { intLocalFreeRegisters &= ~(1 << selectedReg); - intUsedRegisters |= 1 << selectedReg; + intUsedRegisters |= 1 << selectedReg; } else { vecLocalFreeRegisters &= ~(1 << selectedReg); - vecUsedRegisters |= 1 << selectedReg; + vecUsedRegisters |= 1 << selectedReg; } } else { - info.Register = default; + info.Register = default; info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes())); } } @@ -382,7 +382,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators : GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg); info.Sequence = sequence; - info.Temp = temp; + info.Temp = temp; } dest = temp; @@ -408,7 +408,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private static int SelectSpillTemps(int mask0, int mask1) { int selection = 0; - int count = 0; + int count = 0; while (count < MaxIROperands && mask0 != 0) { @@ -451,4 +451,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return local.AssignmentsCount + local.UsesCount; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs index 8f236c253..7d4ce2ea6 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators StackAllocator stackAlloc, RegisterMasks regMasks); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs index d80157afb..f156e0886 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs @@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // http://www.christianwimmer.at/Publications/Wimmer04a/Wimmer04a.pdf class LinearScanAllocator : IRegisterAllocator { - private const int InstructionGap = 2; + private const int InstructionGap = 2; private const int InstructionGapMask = InstructionGap - 1; private HashSet _blockEdges; @@ -33,7 +33,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public StackAllocator StackAlloc { get; } - public BitMap Active { get; } + public BitMap Active { get; } public BitMap Inactive { get; } public int IntUsedRegisters { get; set; } @@ -47,9 +47,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public AllocationContext(StackAllocator stackAlloc, RegisterMasks masks, int intervalsCount) { StackAlloc = stackAlloc; - Masks = masks; + Masks = masks; - Active = new BitMap(Allocators.Default, intervalsCount); + Active = new BitMap(Allocators.Default, intervalsCount); Inactive = new BitMap(Allocators.Default, intervalsCount); PopulateFreePositions(RegisterType.Integer, out _intFreePositions, out _intFreePositionsCount); @@ -443,7 +443,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (highest < current) { - highest = current; + highest = current; selected = index; if (current == int.MaxValue) @@ -485,9 +485,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void SplitAndSpillOverlappingInterval( AllocationContext context, - LiveInterval current, - LiveInterval interval, - int registersCount) + LiveInterval current, + LiveInterval interval, + int registersCount) { // If there's a next use after the start of the current interval, // we need to split the spilled interval twice, and re-insert it @@ -530,8 +530,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void InsertInterval(LiveInterval interval, int registersCount) { Debug.Assert(interval.UsesCount != 0, "Trying to insert a interval without uses."); - Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval."); - Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval."); + Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval."); + Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval."); int startIndex = registersCount * 2; @@ -545,9 +545,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators _intervals.Insert(insertIndex, interval); } - private void Spill(AllocationContext context, LiveInterval interval) + private static void Spill(AllocationContext context, LiveInterval interval) { - Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval."); + Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval."); Debug.Assert(interval.UsesCount == 0, "Trying to spill a interval with uses."); // We first check if any of the siblings were spilled, if so we can reuse @@ -561,7 +561,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void InsertSplitCopies() { - Dictionary copyResolvers = new Dictionary(); + Dictionary copyResolvers = new(); CopyResolver GetCopyResolver(int position) { @@ -668,18 +668,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators continue; } - int lEnd = _blockRanges[block.Index].End - 1; + int lEnd = _blockRanges[block.Index].End - 1; int rStart = _blockRanges[succIndex].Start; - LiveInterval left = interval.GetSplitChild(lEnd); + LiveInterval left = interval.GetSplitChild(lEnd); LiveInterval right = interval.GetSplitChild(rStart); if (left != default && right != default && left != right) { - if (copyResolver == null) - { - copyResolver = new CopyResolver(); - } + copyResolver ??= new CopyResolver(); copyResolver.AddSplit(left, right); } @@ -856,14 +853,14 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int mapSize = _intervals.Count; - BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count]; + BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count]; BitMap[] blkLiveKill = new BitMap[cfg.Blocks.Count]; // Compute local live sets. for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext) { - BitMap liveGen = new BitMap(Allocators.Default, mapSize); - BitMap liveKill = new BitMap(Allocators.Default, mapSize); + BitMap liveGen = new(Allocators.Default, mapSize); + BitMap liveKill = new(Allocators.Default, mapSize); for (Operation node = block.Operations.First; node != default; node = node.ListNext) { @@ -910,17 +907,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } - blkLiveGen [block.Index] = liveGen; + blkLiveGen[block.Index] = liveGen; blkLiveKill[block.Index] = liveKill; } // Compute global live sets. - BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count]; + BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count]; BitMap[] blkLiveOut = new BitMap[cfg.Blocks.Count]; for (int index = 0; index < cfg.Blocks.Count; index++) { - blkLiveIn [index] = new BitMap(Allocators.Default, mapSize); + blkLiveIn[index] = new BitMap(Allocators.Default, mapSize); blkLiveOut[index] = new BitMap(Allocators.Default, mapSize); } @@ -945,9 +942,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators BitMap liveIn = blkLiveIn[block.Index]; - liveIn.Set (liveOut); + liveIn.Set(liveOut); liveIn.Clear(blkLiveKill[block.Index]); - liveIn.Set (blkLiveGen [block.Index]); + liveIn.Set(blkLiveGen[block.Index]); } } while (modified); @@ -969,7 +966,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int instCount = Math.Max(block.Operations.Count, 1); int blockStart = operationPos - instCount * InstructionGap; - int blockEnd = operationPos; + int blockEnd = operationPos; _blockRanges[block.Index] = new LiveRange(blockStart, blockEnd); @@ -1061,7 +1058,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { int regIndex = BitOperations.TrailingZeroCount(mask); - Register callerSavedReg = new Register(regIndex, regType); + Register callerSavedReg = new(regIndex, regType); LiveInterval interval = _intervals[GetRegisterId(callerSavedReg)]; @@ -1098,4 +1095,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators kind == OperandKind.Register; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs index d739ad281..333d3951b 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs @@ -240,8 +240,10 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public LiveInterval Split(int position) { - LiveInterval result = new(Local, Parent); - result.End = End; + LiveInterval result = new(Local, Parent) + { + End = End, + }; LiveRange prev = PrevRange; LiveRange curr = CurrRange; @@ -393,4 +395,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return string.Join(", ", GetRanges()); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs index 06b979ead..d999d767b 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs @@ -8,8 +8,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private int _count; private int _capacity; - public int Count => _count; - public Span Span => new(_items, _count); + public readonly int Count => _count; + public readonly Span Span => new(_items, _count); public void Add(LiveInterval interval) { @@ -37,4 +37,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators _count++; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs index e38b5190d..412d597e8 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs @@ -71,4 +71,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return $"[{Start}, {End})"; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs index bc948f95f..e6972cf0f 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs @@ -5,8 +5,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { readonly struct RegisterMasks { - public int IntAvailableRegisters { get; } - public int VecAvailableRegisters { get; } + public int IntAvailableRegisters { get; } + public int VecAvailableRegisters { get; } public int IntCallerSavedRegisters { get; } public int VecCallerSavedRegisters { get; } public int IntCalleeSavedRegisters { get; } @@ -22,13 +22,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int vecCalleeSavedRegisters, int registersCount) { - IntAvailableRegisters = intAvailableRegisters; - VecAvailableRegisters = vecAvailableRegisters; + IntAvailableRegisters = intAvailableRegisters; + VecAvailableRegisters = vecAvailableRegisters; IntCallerSavedRegisters = intCallerSavedRegisters; VecCallerSavedRegisters = vecCallerSavedRegisters; IntCalleeSavedRegisters = intCalleeSavedRegisters; VecCalleeSavedRegisters = vecCalleeSavedRegisters; - RegistersCount = registersCount; + RegistersCount = registersCount; } public int GetAvailableRegisters(RegisterType type) @@ -47,4 +47,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs index 038312fed..13995bc8d 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs @@ -22,4 +22,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators return offset; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs index c89f0854d..a945eccf4 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs @@ -6,15 +6,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { private int* _items; private int _capacity; - private int _count; - public int Count => _count; - public int FirstUse => _count > 0 ? _items[_count - 1] : LiveInterval.NotFound; - public Span Span => new(_items, _count); + public int Count { get; private set; } + + public readonly int FirstUse => Count > 0 ? _items[Count - 1] : LiveInterval.NotFound; + public readonly Span Span => new(_items, Count); public void Add(int position) { - if (_count + 1 > _capacity) + if (Count + 1 > _capacity) { var oldSpan = Span; @@ -28,7 +28,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // Use positions are usually inserted in descending order, so inserting in descending order is faster, // since the number of half exchanges is reduced. - int i = _count - 1; + int i = Count - 1; while (i >= 0 && _items[i] < position) { @@ -36,19 +36,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } _items[i + 1] = position; - _count++; + Count++; } - public int NextUse(int position) + public readonly int NextUse(int position) { int index = NextUseIndex(position); return index != LiveInterval.NotFound ? _items[index] : LiveInterval.NotFound; } - public int NextUseIndex(int position) + public readonly int NextUseIndex(int position) { - int i = _count - 1; + int i = Count - 1; if (i == -1 || position > _items[0]) { @@ -69,16 +69,18 @@ namespace ARMeilleure.CodeGen.RegisterAllocators // Since the list is in descending order, the new split list takes the front of the list and the current // list takes the back of the list. - UseList result = new(); - result._count = index + 1; - result._capacity = result._count; + UseList result = new() + { + Count = index + 1, + }; + result._capacity = result.Count; result._items = _items; - _count = _count - result._count; - _capacity = _count; - _items = _items + result._count; + Count -= result.Count; + _capacity = Count; + _items += result.Count; return result; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs index 3d0bc21d5..127b84231 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.CodeGen.Unwinding PrologSize = prologSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs index 4a8288a28..2045019a3 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.CodeGen.Unwinding { enum UnwindPseudoOp { - PushReg = 0, - SetFrame = 1, + PushReg = 0, + SetFrame = 1, AllocStack = 2, - SaveReg = 3, - SaveXmm128 = 4 + SaveReg = 3, + SaveXmm128 = 4, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs index fd8ea402b..507ace598 100644 --- a/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs +++ b/src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.CodeGen.Unwinding StackOffsetOrAllocSize = stackOffsetOrAllocSize; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/Assembler.cs b/src/ARMeilleure/CodeGen/X86/Assembler.cs index 67736a31f..55bf07248 100644 --- a/src/ARMeilleure/CodeGen/X86/Assembler.cs +++ b/src/ARMeilleure/CodeGen/X86/Assembler.cs @@ -15,7 +15,7 @@ namespace ARMeilleure.CodeGen.X86 private const int OpModRMBits = 24; - private const byte RexPrefix = 0x40; + private const byte RexPrefix = 0x40; private const byte RexWPrefix = 0x48; private const byte LockPrefix = 0xf0; @@ -799,7 +799,7 @@ namespace ARMeilleure.CodeGen.X86 { JumpIndex = _jumps.Count - 1, Position = (int)_stream.Position, - Symbol = source.Symbol + Symbol = source.Symbol, }); } @@ -959,7 +959,7 @@ namespace ARMeilleure.CodeGen.X86 } } - bool needsSibByte = false; + bool needsSibByte = false; bool needsDisplacement = false; int sib = 0; @@ -971,7 +971,7 @@ namespace ARMeilleure.CodeGen.X86 X86Register baseRegLow = (X86Register)(baseReg.Index & 0b111); - needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp; + needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp; needsDisplacement = memOp.Displacement != 0 || baseRegLow == X86Register.Rbp; if (needsDisplacement) @@ -1049,7 +1049,7 @@ namespace ARMeilleure.CodeGen.X86 InstructionFlags.Prefix66 => 1, InstructionFlags.PrefixF3 => 2, InstructionFlags.PrefixF2 => 3, - _ => 0 + _ => 0, }; if (src1 != default) @@ -1081,11 +1081,19 @@ namespace ARMeilleure.CodeGen.X86 switch (opCodeHigh) { - case 0xf: vexByte1 |= 1; break; - case 0xf38: vexByte1 |= 2; break; - case 0xf3a: vexByte1 |= 3; break; + case 0xf: + vexByte1 |= 1; + break; + case 0xf38: + vexByte1 |= 2; + break; + case 0xf3a: + vexByte1 |= 3; + break; - default: Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); break; + default: + Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); + break; } vexByte2 |= (rexPrefix & 8) << 4; @@ -1191,11 +1199,19 @@ namespace ARMeilleure.CodeGen.X86 switch ((ushort)(opCode >> 8)) { - case 0xf00: mm = 0b01; break; - case 0xf38: mm = 0b10; break; - case 0xf3a: mm = 0b11; break; + case 0xf00: + mm = 0b01; + break; + case 0xf38: + mm = 0b10; + break; + case 0xf3a: + mm = 0b11; + break; - default: Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); break; + default: + Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); + break; } WriteByte( @@ -1217,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86 InstructionFlags.Prefix66 => 0b01, InstructionFlags.PrefixF3 => 0b10, InstructionFlags.PrefixF2 => 0b11, - _ => 0 + _ => 0, }; WriteByte( (byte)( @@ -1233,11 +1249,19 @@ namespace ARMeilleure.CodeGen.X86 byte ll = 0b00; switch (registerWidth) { - case 128: ll = 0b00; break; - case 256: ll = 0b01; break; - case 512: ll = 0b10; break; + case 128: + ll = 0b00; + break; + case 256: + ll = 0b01; + break; + case 512: + ll = 0b10; + break; - default: Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); break; + default: + Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); + break; } // Embedded broadcast in the case of a memory operand bool bcast = broadcast; @@ -1315,10 +1339,7 @@ namespace ARMeilleure.CodeGen.X86 ref Jump jump = ref jumps[i]; // If jump target not resolved yet, resolve it. - if (jump.JumpTarget == null) - { - jump.JumpTarget = _labels[jump.JumpLabel]; - } + jump.JumpTarget ??= _labels[jump.JumpLabel]; long jumpTarget = jump.JumpTarget.Value; long offset = jumpTarget - jump.JumpPosition; @@ -1556,4 +1577,4 @@ namespace ARMeilleure.CodeGen.X86 _stream.WriteByte((byte)(value >> 56)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs index e6a2ff07f..e4114a335 100644 --- a/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs +++ b/src/ARMeilleure/CodeGen/X86/AssemblerTable.cs @@ -1,4 +1,5 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace ARMeilleure.CodeGen.X86 { @@ -12,47 +13,48 @@ namespace ARMeilleure.CodeGen.X86 private const int BadOp = 0; [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] private enum InstructionFlags { - None = 0, - RegOnly = 1 << 0, - Reg8Src = 1 << 1, + None = 0, + RegOnly = 1 << 0, + Reg8Src = 1 << 1, Reg8Dest = 1 << 2, - RexW = 1 << 3, - Vex = 1 << 4, - Evex = 1 << 5, + RexW = 1 << 3, + Vex = 1 << 4, + Evex = 1 << 5, - PrefixBit = 16, + PrefixBit = 16, PrefixMask = 7 << PrefixBit, - Prefix66 = 1 << PrefixBit, - PrefixF3 = 2 << PrefixBit, - PrefixF2 = 4 << PrefixBit + Prefix66 = 1 << PrefixBit, + PrefixF3 = 2 << PrefixBit, + PrefixF2 = 4 << PrefixBit, } private readonly struct InstructionInfo { - public int OpRMR { get; } - public int OpRMImm8 { get; } + public int OpRMR { get; } + public int OpRMImm8 { get; } public int OpRMImm32 { get; } - public int OpRImm64 { get; } - public int OpRRM { get; } + public int OpRImm64 { get; } + public int OpRRM { get; } public InstructionFlags Flags { get; } public InstructionInfo( - int opRMR, - int opRMImm8, - int opRMImm32, - int opRImm64, - int opRRM, + int opRMR, + int opRMImm8, + int opRMImm32, + int opRImm64, + int opRRM, InstructionFlags flags) { - OpRMR = opRMR; - OpRMImm8 = opRMImm8; + OpRMR = opRMR; + OpRMImm8 = opRMImm8; OpRMImm32 = opRMImm32; - OpRImm64 = opRImm64; - OpRRM = opRRM; - Flags = flags; + OpRImm64 = opRImm64; + OpRRM = opRRM; + Flags = flags; } } @@ -62,6 +64,7 @@ namespace ARMeilleure.CodeGen.X86 { _instTable = new InstructionInfo[(int)X86Instruction.Count]; +#pragma warning disable IDE0055 // Disable formatting // Name RM/R RM/I8 RM/I32 R/I64 R/RM Flags Add(X86Instruction.Add, new InstructionInfo(0x00000001, 0x00000083, 0x00000081, BadOp, 0x00000003, InstructionFlags.None)); Add(X86Instruction.Addpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f58, InstructionFlags.Vex | InstructionFlags.Prefix66)); @@ -285,6 +288,7 @@ namespace ARMeilleure.CodeGen.X86 Add(X86Instruction.Xor, new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp, 0x00000033, InstructionFlags.None)); Add(X86Instruction.Xorpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66)); Add(X86Instruction.Xorps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f57, InstructionFlags.Vex)); +#pragma warning restore IDE0055 static void Add(X86Instruction inst, in InstructionInfo info) { diff --git a/src/ARMeilleure/CodeGen/X86/CallConvName.cs b/src/ARMeilleure/CodeGen/X86/CallConvName.cs index be3676282..6208da1ec 100644 --- a/src/ARMeilleure/CodeGen/X86/CallConvName.cs +++ b/src/ARMeilleure/CodeGen/X86/CallConvName.cs @@ -3,6 +3,6 @@ namespace ARMeilleure.CodeGen.X86 enum CallConvName { SystemV, - Windows + Windows, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs index 953fef5b0..8433aaea9 100644 --- a/src/ARMeilleure/CodeGen/X86/CallingConvention.cs +++ b/src/ARMeilleure/CodeGen/X86/CallingConvention.cs @@ -20,6 +20,7 @@ namespace ARMeilleure.CodeGen.X86 { if (GetCurrentCallConv() == CallConvName.Windows) { +#pragma warning disable IDE0055 // Disable formatting return (1 << (int)X86Register.Rax) | (1 << (int)X86Register.Rcx) | (1 << (int)X86Register.Rdx) | @@ -39,6 +40,7 @@ namespace ARMeilleure.CodeGen.X86 (1 << (int)X86Register.R9) | (1 << (int)X86Register.R10) | (1 << (int)X86Register.R11); +#pragma warning restore IDE0055 } } @@ -90,22 +92,32 @@ namespace ARMeilleure.CodeGen.X86 { switch (index) { - case 0: return X86Register.Rcx; - case 1: return X86Register.Rdx; - case 2: return X86Register.R8; - case 3: return X86Register.R9; + case 0: + return X86Register.Rcx; + case 1: + return X86Register.Rdx; + case 2: + return X86Register.R8; + case 3: + return X86Register.R9; } } else /* if (GetCurrentCallConv() == CallConvName.SystemV) */ { switch (index) { - case 0: return X86Register.Rdi; - case 1: return X86Register.Rsi; - case 2: return X86Register.Rdx; - case 3: return X86Register.Rcx; - case 4: return X86Register.R8; - case 5: return X86Register.R9; + case 0: + return X86Register.Rdi; + case 1: + return X86Register.Rsi; + case 2: + return X86Register.Rdx; + case 3: + return X86Register.Rcx; + case 4: + return X86Register.R8; + case 5: + return X86Register.R9; } } @@ -155,4 +167,4 @@ namespace ARMeilleure.CodeGen.X86 : CallConvName.SystemV; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs index 899487241..d4d4c2058 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenContext.cs @@ -30,7 +30,7 @@ namespace ARMeilleure.CodeGen.X86 Assembler = new Assembler(_stream, relocatable); CallArgsRegionSize = GetCallArgsRegionSize(allocResult, maxCallArgs, out int xmmSaveRegionSize); - XmmSaveRegionSize = xmmSaveRegionSize; + XmmSaveRegionSize = xmmSaveRegionSize; } private static int GetCallArgsRegionSize(AllocationResult allocResult, int maxCallArgs, out int xmmSaveRegionSize) @@ -102,4 +102,4 @@ namespace ARMeilleure.CodeGen.X86 return label; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs index e7179b517..3cab0b6ce 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -17,7 +17,7 @@ namespace ARMeilleure.CodeGen.X86 static class CodeGenerator { private const int RegistersCount = 16; - private const int PageSize = 0x1000; + private const int PageSize = 0x1000; private const int StackGuardSize = 0x2000; private static readonly Action[] _instTable; @@ -26,6 +26,7 @@ namespace ARMeilleure.CodeGen.X86 { _instTable = new Action[EnumUtils.GetCount(typeof(Instruction))]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.Add, GenerateAdd); Add(Instruction.BitwiseAnd, GenerateBitwiseAnd); Add(Instruction.BitwiseExclusiveOr, GenerateBitwiseExclusiveOr); @@ -85,6 +86,7 @@ namespace ARMeilleure.CodeGen.X86 Add(Instruction.ZeroExtend16, GenerateZeroExtend16); Add(Instruction.ZeroExtend32, GenerateZeroExtend32); Add(Instruction.ZeroExtend8, GenerateZeroExtend8); +#pragma warning restore IDE0055 static void Add(Instruction inst, Action func) { @@ -203,290 +205,290 @@ namespace ARMeilleure.CodeGen.X86 switch (info.Type) { case IntrinsicType.Comis_: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - switch (operation.Intrinsic) - { - case Intrinsic.X86Comisdeq: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Equal); - break; - - case Intrinsic.X86Comisdge: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); - break; - - case Intrinsic.X86Comisdlt: - context.Assembler.Comisd(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Below); - break; - - case Intrinsic.X86Comisseq: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Equal); - break; - - case Intrinsic.X86Comissge: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); - break; - - case Intrinsic.X86Comisslt: - context.Assembler.Comiss(src1, src2); - context.Assembler.Setcc(dest, X86Condition.Below); - break; - } - - context.Assembler.Movzx8(dest, dest, OperandType.I32); - - break; - } - - case IntrinsicType.Mxcsr: - { - Operand offset = operation.GetSource(0); - - Debug.Assert(offset.Kind == OperandKind.Constant); - Debug.Assert(offset.Type == OperandType.I32); - - int offs = offset.AsInt32() + context.CallArgsRegionSize; - - Operand rsp = Register(X86Register.Rsp); - Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs); - - Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding); - - if (operation.Intrinsic == Intrinsic.X86Ldmxcsr) - { - Operand bits = operation.GetSource(1); - Debug.Assert(bits.Type == OperandType.I32); - - context.Assembler.Mov(memOp, bits, OperandType.I32); - context.Assembler.Ldmxcsr(memOp); - } - else if (operation.Intrinsic == Intrinsic.X86Stmxcsr) { Operand dest = operation.Destination; - Debug.Assert(dest.Type == OperandType.I32); + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); - context.Assembler.Stmxcsr(memOp); - context.Assembler.Mov(dest, memOp, OperandType.I32); + switch (operation.Intrinsic) + { + case Intrinsic.X86Comisdeq: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Equal); + break; + + case Intrinsic.X86Comisdge: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); + break; + + case Intrinsic.X86Comisdlt: + context.Assembler.Comisd(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Below); + break; + + case Intrinsic.X86Comisseq: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Equal); + break; + + case Intrinsic.X86Comissge: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.AboveOrEqual); + break; + + case Intrinsic.X86Comisslt: + context.Assembler.Comiss(src1, src2); + context.Assembler.Setcc(dest, X86Condition.Below); + break; + } + + context.Assembler.Movzx8(dest, dest, OperandType.I32); + + break; } - break; - } + case IntrinsicType.Mxcsr: + { + Operand offset = operation.GetSource(0); + + Debug.Assert(offset.Kind == OperandKind.Constant); + Debug.Assert(offset.Type == OperandType.I32); + + int offs = offset.AsInt32() + context.CallArgsRegionSize; + + Operand rsp = Register(X86Register.Rsp); + Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs); + + Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding); + + if (operation.Intrinsic == Intrinsic.X86Ldmxcsr) + { + Operand bits = operation.GetSource(1); + Debug.Assert(bits.Type == OperandType.I32); + + context.Assembler.Mov(memOp, bits, OperandType.I32); + context.Assembler.Ldmxcsr(memOp); + } + else if (operation.Intrinsic == Intrinsic.X86Stmxcsr) + { + Operand dest = operation.Destination; + Debug.Assert(dest.Type == OperandType.I32); + + context.Assembler.Stmxcsr(memOp); + context.Assembler.Mov(dest, memOp, OperandType.I32); + } + + break; + } case IntrinsicType.PopCount: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); + { + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - EnsureSameType(dest, source); + EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger()); - context.Assembler.Popcnt(dest, source, dest.Type); + context.Assembler.Popcnt(dest, source, dest.Type); - break; - } + break; + } case IntrinsicType.Unary: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); + { + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - EnsureSameType(dest, source); + EnsureSameType(dest, source); - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger()); - context.Assembler.WriteInstruction(info.Inst, dest, source); + context.Assembler.WriteInstruction(info.Inst, dest, source); - break; - } + break; + } case IntrinsicType.UnaryToGpr: - { - Operand dest = operation.Destination; - Operand source = operation.GetSource(0); - - Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger()); - - if (operation.Intrinsic == Intrinsic.X86Cvtsi2si) { - if (dest.Type == OperandType.I32) - { - context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a) - } - else /* if (dest.Type == OperandType.I64) */ - { - context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a) - } - } - else - { - context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type); - } + Operand dest = operation.Destination; + Operand source = operation.GetSource(0); - break; - } + Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger()); + + if (operation.Intrinsic == Intrinsic.X86Cvtsi2si) + { + if (dest.Type == OperandType.I32) + { + context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a) + } + else /* if (dest.Type == OperandType.I64) */ + { + context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a) + } + } + else + { + context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type); + } + + break; + } case IntrinsicType.Binary: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) { - EnsureSameReg(dest, src1); - } + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); - Debug.Assert(!dest.Type.IsInteger()); - Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant); + EnsureSameType(dest, src1); - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } - break; - } - - case IntrinsicType.BinaryGpr: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) - { - EnsureSameReg(dest, src1); - } - - Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger()); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type); - - break; - } - - case IntrinsicType.Crc32: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameReg(dest, src1); - - Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger()); - - context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type); - - break; - } - - case IntrinsicType.BinaryImm: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - - EnsureSameType(dest, src1); - - if (!HardwareCapabilities.SupportsVexEncoding) - { - EnsureSameReg(dest, src1); - } - - Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte()); - - break; - } - - case IntrinsicType.Ternary: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); - - EnsureSameType(dest, src1, src2, src3); - - Debug.Assert(!dest.Type.IsInteger()); - - if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3); - } - else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3); - } - else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding) - { - context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3); - } - else - { - EnsureSameReg(dest, src1); - - Debug.Assert(src3.GetRegister().Index == 0); + Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + + break; } - break; - } + case IntrinsicType.BinaryGpr: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameType(dest, src1); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger()); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type); + + break; + } + + case IntrinsicType.Crc32: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameReg(dest, src1); + + Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger()); + + context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type); + + break; + } + + case IntrinsicType.BinaryImm: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + + EnsureSameType(dest, src1); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte()); + + break; + } + + case IntrinsicType.Ternary: + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); + + EnsureSameType(dest, src1, src2, src3); + + Debug.Assert(!dest.Type.IsInteger()); + + if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3); + } + else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3); + } + else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding) + { + context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3); + } + else + { + EnsureSameReg(dest, src1); + + Debug.Assert(src3.GetRegister().Index == 0); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); + } + + break; + } case IntrinsicType.TernaryImm: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); - - EnsureSameType(dest, src1, src2); - - if (!HardwareCapabilities.SupportsVexEncoding) { - EnsureSameReg(dest, src1); + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); + + EnsureSameType(dest, src1, src2); + + if (!HardwareCapabilities.SupportsVexEncoding) + { + EnsureSameReg(dest, src1); + } + + Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant); + + context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte()); + + break; } - Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant); - - context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte()); - - break; - } - case IntrinsicType.Fma: - { - Operand dest = operation.Destination; - Operand src1 = operation.GetSource(0); - Operand src2 = operation.GetSource(1); - Operand src3 = operation.GetSource(2); + { + Operand dest = operation.Destination; + Operand src1 = operation.GetSource(0); + Operand src2 = operation.GetSource(1); + Operand src3 = operation.GetSource(2); - Debug.Assert(HardwareCapabilities.SupportsVexEncoding); + Debug.Assert(HardwareCapabilities.SupportsVexEncoding); - Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register); - Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory); + Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register); + Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory); - EnsureSameType(dest, src1, src2, src3); - Debug.Assert(dest.Type == OperandType.V128); + EnsureSameType(dest, src1, src2, src3); + Debug.Assert(dest.Type == OperandType.V128); - Debug.Assert(dest.Value == src1.Value); + Debug.Assert(dest.Value == src1.Value); - context.Assembler.WriteInstruction(info.Inst, dest, src2, src3); + context.Assembler.WriteInstruction(info.Inst, dest, src2, src3); - break; - } + break; + } } } else @@ -592,7 +594,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateBitwiseNot(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -630,7 +632,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateByteSwap(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -761,19 +763,19 @@ namespace ARMeilleure.CodeGen.X86 Operand src2 = operation.GetSource(1); Operand src3 = operation.GetSource(2); - EnsureSameReg (dest, src3); + EnsureSameReg(dest, src3); EnsureSameType(dest, src2, src3); Debug.Assert(dest.Type.IsInteger()); Debug.Assert(src1.Type == OperandType.I32); - context.Assembler.Test (src1, src1, src1.Type); + context.Assembler.Test(src1, src1, src1.Type); context.Assembler.Cmovcc(dest, src2, dest.Type, X86Condition.NotEqual); } private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64); @@ -783,7 +785,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateConvertToFP(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64); @@ -794,7 +796,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type.IsInteger()) { - context.Assembler.Xorps (dest, dest, dest); + context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2ss(dest, dest, source, source.Type); } else /* if (source.Type == OperandType.FP64) */ @@ -810,7 +812,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type.IsInteger()) { - context.Assembler.Xorps (dest, dest, dest); + context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2sd(dest, dest, source, source.Type); } else /* if (source.Type == OperandType.FP32) */ @@ -824,7 +826,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateCopy(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -837,7 +839,7 @@ namespace ARMeilleure.CodeGen.X86 return; } - if (dest.Kind == OperandKind.Register && + if (dest.Kind == OperandKind.Register && source.Kind == OperandKind.Constant && source.Value == 0) { // Assemble "mov reg, 0" as "xor reg, reg" as the later is more efficient. @@ -855,7 +857,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); EnsureSameType(dest, source); @@ -888,9 +890,9 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateDivide(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand dividend = operation.GetSource(0); - Operand divisor = operation.GetSource(1); + Operand divisor = operation.GetSource(1); if (!dest.Type.IsInteger()) { @@ -938,7 +940,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateFill(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -954,7 +956,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); GenerateLoad(context, address, value); @@ -962,7 +964,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad16(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -972,7 +974,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateLoad8(CodeGenContext context, Operation operation) { - Operand value = operation.Destination; + Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1039,7 +1041,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateNegate(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); ValidateUnOp(dest, source); @@ -1102,7 +1104,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1112,7 +1114,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1122,7 +1124,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateSignExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1158,7 +1160,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStackAlloc(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand offset = operation.GetSource(0); Debug.Assert(offset.Kind == OperandKind.Constant); @@ -1174,7 +1176,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); GenerateStore(context, address, value); @@ -1182,7 +1184,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore16(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1192,7 +1194,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateStore8(CodeGenContext context, Operation operation) { - Operand value = operation.GetSource(1); + Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); Debug.Assert(value.Type.IsInteger()); @@ -1231,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1278,7 +1280,7 @@ namespace ARMeilleure.CodeGen.X86 mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8); context.Assembler.Pshufd(src1, src1, (byte)mask0); - context.Assembler.Movd (dest, src1); + context.Assembler.Movd(dest, src1); context.Assembler.Pshufd(src1, src1, (byte)mask1); } } @@ -1297,7 +1299,7 @@ namespace ARMeilleure.CodeGen.X86 const byte mask = 0b01_00_11_10; context.Assembler.Pshufd(src1, src1, mask); - context.Assembler.Movq (dest, src1); + context.Assembler.Movq(dest, src1); context.Assembler.Pshufd(src1, src1, mask); } } @@ -1308,7 +1310,7 @@ namespace ARMeilleure.CodeGen.X86 (index == 1 && dest.Type == OperandType.FP64)) { context.Assembler.Movhlps(dest, dest, src1); - context.Assembler.Movq (dest, dest); + context.Assembler.Movq(dest, dest); } else { @@ -1455,11 +1457,11 @@ namespace ARMeilleure.CodeGen.X86 int mask0 = 0b11_10_01_00; int mask1 = 0b11_10_01_00; - mask0 = BitUtils.RotateRight(mask0, index * 2, 8); + mask0 = BitUtils.RotateRight(mask0, index * 2, 8); mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8); context.Assembler.Pshufd(src1, src1, (byte)mask0); // Lane to be inserted in position 0. - context.Assembler.Movss (dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0] + context.Assembler.Movss(dest, src1, src2); // dest[127:0] = src1[127:32] | src2[31:0] context.Assembler.Pshufd(dest, dest, (byte)mask1); // Inserted lane in original position. if (dest.GetRegister() != src1.GetRegister()) @@ -1555,7 +1557,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1565,7 +1567,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128); @@ -1575,7 +1577,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1585,7 +1587,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend32(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1601,7 +1603,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateZeroExtend8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; + Operand dest = operation.Destination; Operand source = operation.GetSource(0); Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); @@ -1613,13 +1615,25 @@ namespace ARMeilleure.CodeGen.X86 { switch (value.Type) { - case OperandType.I32: context.Assembler.Mov (value, address, OperandType.I32); break; - case OperandType.I64: context.Assembler.Mov (value, address, OperandType.I64); break; - case OperandType.FP32: context.Assembler.Movd (value, address); break; - case OperandType.FP64: context.Assembler.Movq (value, address); break; - case OperandType.V128: context.Assembler.Movdqu(value, address); break; + case OperandType.I32: + context.Assembler.Mov(value, address, OperandType.I32); + break; + case OperandType.I64: + context.Assembler.Mov(value, address, OperandType.I64); + break; + case OperandType.FP32: + context.Assembler.Movd(value, address); + break; + case OperandType.FP64: + context.Assembler.Movq(value, address); + break; + case OperandType.V128: + context.Assembler.Movdqu(value, address); + break; - default: Debug.Assert(false); break; + default: + Debug.Assert(false); + break; } } @@ -1627,13 +1641,25 @@ namespace ARMeilleure.CodeGen.X86 { switch (value.Type) { - case OperandType.I32: context.Assembler.Mov (address, value, OperandType.I32); break; - case OperandType.I64: context.Assembler.Mov (address, value, OperandType.I64); break; - case OperandType.FP32: context.Assembler.Movd (address, value); break; - case OperandType.FP64: context.Assembler.Movq (address, value); break; - case OperandType.V128: context.Assembler.Movdqu(address, value); break; + case OperandType.I32: + context.Assembler.Mov(address, value, OperandType.I32); + break; + case OperandType.I64: + context.Assembler.Mov(address, value, OperandType.I64); + break; + case OperandType.FP32: + context.Assembler.Movd(address, value); + break; + case OperandType.FP64: + context.Assembler.Movq(address, value); + break; + case OperandType.V128: + context.Assembler.Movdqu(address, value); + break; - default: Debug.Assert(false); break; + default: + Debug.Assert(false); + break; } } @@ -1670,21 +1696,21 @@ namespace ARMeilleure.CodeGen.X86 [Conditional("DEBUG")] private static void ValidateUnOp(Operand dest, Operand source) { - EnsureSameReg (dest, source); + EnsureSameReg(dest, source); EnsureSameType(dest, source); } [Conditional("DEBUG")] private static void ValidateBinOp(Operand dest, Operand src1, Operand src2) { - EnsureSameReg (dest, src1); + EnsureSameReg(dest, src1); EnsureSameType(dest, src1, src2); } [Conditional("DEBUG")] private static void ValidateShift(Operand dest, Operand src1, Operand src2) { - EnsureSameReg (dest, src1); + EnsureSameReg(dest, src1); EnsureSameType(dest, src1); Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32); @@ -1722,7 +1748,7 @@ namespace ARMeilleure.CodeGen.X86 private static UnwindInfo WritePrologue(CodeGenContext context) { - List pushEntries = new List(); + List pushEntries = new(); Operand rsp = Register(X86Register.Rsp); @@ -1831,7 +1857,7 @@ namespace ARMeilleure.CodeGen.X86 size = (size + pageMask) & ~pageMask; - Operand rsp = Register(X86Register.Rsp); + Operand rsp = Register(X86Register.Rsp); Operand temp = Register(CallingConvention.GetIntReturnRegister()); for (int offset = PageSize; offset < size; offset += PageSize) @@ -1862,4 +1888,4 @@ namespace ARMeilleure.CodeGen.X86 return Operand.Factory.Register((int)register, RegisterType.Vector, OperandType.V128); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs index 07cdcd096..4f6f1e87b 100644 --- a/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs +++ b/src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs @@ -47,7 +47,7 @@ namespace ARMeilleure.CodeGen.X86 0xc3, // ret }; - using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length); + using MemoryBlock memGetXcr0 = new((ulong)asmGetXcr0.Length); memGetXcr0.Write(0, asmGetXcr0); @@ -62,7 +62,7 @@ namespace ARMeilleure.CodeGen.X86 public enum FeatureFlags1Edx { Sse = 1 << 25, - Sse2 = 1 << 26 + Sse2 = 1 << 26, } [Flags] @@ -79,7 +79,7 @@ namespace ARMeilleure.CodeGen.X86 Xsave = 1 << 26, Osxsave = 1 << 27, Avx = 1 << 28, - F16c = 1 << 29 + F16c = 1 << 29, } [Flags] @@ -90,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86 Avx512dq = 1 << 17, Sha = 1 << 29, Avx512bw = 1 << 30, - Avx512vl = 1 << 31 + Avx512vl = 1 << 31, } [Flags] @@ -106,7 +106,7 @@ namespace ARMeilleure.CodeGen.X86 YmmHi128 = 1 << 2, Opmask = 1 << 5, ZmmHi256 = 1 << 6, - Hi16Zmm = 1 << 7 + Hi16Zmm = 1 << 7, } public static FeatureFlags1Edx FeatureInfo1Edx { get; } @@ -141,4 +141,4 @@ namespace ARMeilleure.CodeGen.X86 public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse; public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs index 302bf4d3c..16054c616 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.CodeGen.X86 readonly struct IntrinsicInfo { public X86Instruction Inst { get; } - public IntrinsicType Type { get; } + public IntrinsicType Type { get; } public IntrinsicInfo(X86Instruction inst, IntrinsicType type) { @@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.X86 Type = type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs index e3d94b7ae..daa1f8f60 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs @@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.X86 { static class IntrinsicTable { - private static IntrinsicInfo[] _intrinTable; + private static readonly IntrinsicInfo[] _intrinTable; static IntrinsicTable() { _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))]; +#pragma warning disable IDE0055 // Disable formatting Add(Intrinsic.X86Addpd, new IntrinsicInfo(X86Instruction.Addpd, IntrinsicType.Binary)); Add(Intrinsic.X86Addps, new IntrinsicInfo(X86Instruction.Addps, IntrinsicType.Binary)); Add(Intrinsic.X86Addsd, new IntrinsicInfo(X86Instruction.Addsd, IntrinsicType.Binary)); @@ -185,6 +186,7 @@ namespace ARMeilleure.CodeGen.X86 Add(Intrinsic.X86Vpternlogd, new IntrinsicInfo(X86Instruction.Vpternlogd, IntrinsicType.TernaryImm)); Add(Intrinsic.X86Xorpd, new IntrinsicInfo(X86Instruction.Xorpd, IntrinsicType.Binary)); Add(Intrinsic.X86Xorps, new IntrinsicInfo(X86Instruction.Xorps, IntrinsicType.Binary)); +#pragma warning restore IDE0055 } private static void Add(Intrinsic intrin, IntrinsicInfo info) @@ -197,4 +199,4 @@ namespace ARMeilleure.CodeGen.X86 return _intrinTable[(int)intrin]; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs index 5a9c14afa..7c3ef354d 100644 --- a/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs +++ b/src/ARMeilleure/CodeGen/X86/IntrinsicType.cs @@ -13,6 +13,6 @@ namespace ARMeilleure.CodeGen.X86 Crc32, Ternary, TernaryImm, - Fma + Fma, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs index c61eac31a..83d7a5845 100644 --- a/src/ARMeilleure/CodeGen/X86/Mxcsr.cs +++ b/src/ARMeilleure/CodeGen/X86/Mxcsr.cs @@ -10,6 +10,6 @@ namespace ARMeilleure.CodeGen.X86 Rlo = 1 << 13, // Round Mode low bit. Um = 1 << 11, // Underflow Mask. Dm = 1 << 8, // Denormal Mask. - Daz = 1 << 6 // Denormals Are Zero. + Daz = 1 << 6, // Denormals Are Zero. } } diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs index cb742d67f..590c35c7b 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs @@ -104,11 +104,11 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.Tailcall: if (callConv == CallConvName.Windows) { - PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node); + PreAllocatorWindows.InsertTailcallCopies(block.Operations, node); } else { - PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node); + PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node); } break; @@ -177,10 +177,7 @@ namespace ARMeilleure.CodeGen.X86 { src2 = node.GetSource(1); - Operand temp = src1; - - src1 = src2; - src2 = temp; + (src2, src1) = (src1, src2); node.SetSource(0, src1); node.SetSource(1, src2); @@ -228,151 +225,151 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.CompareAndSwap: case Instruction.CompareAndSwap16: case Instruction.CompareAndSwap8: - { - OperandType type = node.GetSource(1).Type; - - if (type == OperandType.V128) { - // Handle the many restrictions of the compare and exchange (16 bytes) instruction: - // - The expected value should be in RDX:RAX. - // - The new value to be written should be in RCX:RBX. - // - The value at the memory location is loaded to RDX:RAX. - void SplitOperand(Operand source, Operand lr, Operand hr) + OperandType type = node.GetSource(1).Type; + + if (type == OperandType.V128) { - nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0))); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1))); + // Handle the many restrictions of the compare and exchange (16 bytes) instruction: + // - The expected value should be in RDX:RAX. + // - The new value to be written should be in RCX:RBX. + // - The value at the memory location is loaded to RDX:RAX. + void SplitOperand(Operand source, Operand lr, Operand hr) + { + nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1))); + } + + Operand rax = Gpr(X86Register.Rax, OperandType.I64); + Operand rbx = Gpr(X86Register.Rbx, OperandType.I64); + Operand rcx = Gpr(X86Register.Rcx, OperandType.I64); + Operand rdx = Gpr(X86Register.Rdx, OperandType.I64); + + SplitOperand(node.GetSource(1), rax, rdx); + SplitOperand(node.GetSource(2), rbx, rcx); + + Operation operation = node; + + node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax)); + nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1))); + + operation.SetDestinations(new Operand[] { rdx, rax }); + operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx }); + } + else + { + // Handle the many restrictions of the compare and exchange (32/64) instruction: + // - The expected value should be in (E/R)AX. + // - The value at the memory location is loaded to (E/R)AX. + Operand expected = node.GetSource(1); + Operand newValue = node.GetSource(2); + + Operand rax = Gpr(X86Register.Rax, expected.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected)); + + // We need to store the new value into a temp, since it may + // be a constant, and this instruction does not support immediate operands. + Operand temp = Local(newValue.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue)); + + node.SetSources(new Operand[] { node.GetSource(0), rax, temp }); + + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + + node.Destination = rax; } - Operand rax = Gpr(X86Register.Rax, OperandType.I64); - Operand rbx = Gpr(X86Register.Rbx, OperandType.I64); - Operand rcx = Gpr(X86Register.Rcx, OperandType.I64); - Operand rdx = Gpr(X86Register.Rdx, OperandType.I64); - - SplitOperand(node.GetSource(1), rax, rdx); - SplitOperand(node.GetSource(2), rbx, rcx); - - Operation operation = node; - - node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax)); - nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1))); - - operation.SetDestinations(new Operand[] { rdx, rax }); - operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx }); + break; } - else - { - // Handle the many restrictions of the compare and exchange (32/64) instruction: - // - The expected value should be in (E/R)AX. - // - The value at the memory location is loaded to (E/R)AX. - Operand expected = node.GetSource(1); - Operand newValue = node.GetSource(2); - - Operand rax = Gpr(X86Register.Rax, expected.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected)); - - // We need to store the new value into a temp, since it may - // be a constant, and this instruction does not support immediate operands. - Operand temp = Local(newValue.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue)); - - node.SetSources(new Operand[] { node.GetSource(0), rax, temp }); - - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); - - node.Destination = rax; - } - - break; - } case Instruction.Divide: case Instruction.DivideUI: - { - // Handle the many restrictions of the division instructions: - // - The dividend is always in RDX:RAX. - // - The result is always in RAX. - // - Additionally it also writes the remainder in RDX. - if (dest.Type.IsInteger()) { + // Handle the many restrictions of the division instructions: + // - The dividend is always in RDX:RAX. + // - The result is always in RAX. + // - Additionally it also writes the remainder in RDX. + if (dest.Type.IsInteger()) + { + Operand src1 = node.GetSource(0); + + Operand rax = Gpr(X86Register.Rax, src1.Type); + Operand rdx = Gpr(X86Register.Rdx, src1.Type); + + nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); + nodes.AddBefore(node, Operation(Instruction.Clobber, rdx)); + + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + + node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) }); + node.Destination = rax; + } + + break; + } + + case Instruction.Extended: + { + bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd || + node.Intrinsic == Intrinsic.X86Blendvps || + node.Intrinsic == Intrinsic.X86Pblendvb; + + // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported. + // SHA256RNDS2 always has an implied XMM0 as a last operand. + if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2) + { + Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128); + + nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2))); + + node.SetSource(2, xmm0); + } + + break; + } + + case Instruction.Multiply64HighSI: + case Instruction.Multiply64HighUI: + { + // Handle the many restrictions of the i64 * i64 = i128 multiply instructions: + // - The multiplicand is always in RAX. + // - The lower 64-bits of the result is always in RAX. + // - The higher 64-bits of the result is always in RDX. Operand src1 = node.GetSource(0); Operand rax = Gpr(X86Register.Rax, src1.Type); Operand rdx = Gpr(X86Register.Rdx, src1.Type); - nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - nodes.AddBefore(node, Operation(Instruction.Clobber, rdx)); + nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax)); + node.SetSource(0, rax); - node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) }); - node.Destination = rax; + nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx)); + + node.SetDestinations(new Operand[] { rdx, rax }); + + break; } - break; - } - - case Instruction.Extended: - { - bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd || - node.Intrinsic == Intrinsic.X86Blendvps || - node.Intrinsic == Intrinsic.X86Pblendvb; - - // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported. - // SHA256RNDS2 always has an implied XMM0 as a last operand. - if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2) - { - Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128); - - nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2))); - - node.SetSource(2, xmm0); - } - - break; - } - - case Instruction.Multiply64HighSI: - case Instruction.Multiply64HighUI: - { - // Handle the many restrictions of the i64 * i64 = i128 multiply instructions: - // - The multiplicand is always in RAX. - // - The lower 64-bits of the result is always in RAX. - // - The higher 64-bits of the result is always in RDX. - Operand src1 = node.GetSource(0); - - Operand rax = Gpr(X86Register.Rax, src1.Type); - Operand rdx = Gpr(X86Register.Rdx, src1.Type); - - nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1)); - - node.SetSource(0, rax); - - nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx)); - - node.SetDestinations(new Operand[] { rdx, rax }); - - break; - } - case Instruction.RotateRight: case Instruction.ShiftLeft: case Instruction.ShiftRightSI: case Instruction.ShiftRightUI: - { - // The shift register is always implied to be CL (low 8-bits of RCX or ECX). - if (node.GetSource(1).Kind == OperandKind.LocalVariable) { - Operand rcx = Gpr(X86Register.Rcx, OperandType.I32); + // The shift register is always implied to be CL (low 8-bits of RCX or ECX). + if (node.GetSource(1).Kind == OperandKind.LocalVariable) + { + Operand rcx = Gpr(X86Register.Rcx, OperandType.I32); - nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1))); + nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1))); - node.SetSource(1, rcx); + node.SetSource(1, rcx); + } + + break; } - - break; - } } } @@ -459,7 +456,7 @@ namespace ARMeilleure.CodeGen.X86 // Unsigned integer to FP conversions are not supported on X86. // We need to turn them into signed integer to FP conversions, and // adjust the final result. - Operand dest = node.Destination; + Operand dest = node.Destination; Operand source = node.GetSource(0); Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\"."); @@ -472,8 +469,8 @@ namespace ARMeilleure.CodeGen.X86 // and then use the 64-bits signed conversion instructions. Operand zex = Local(OperandType.I64); - node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source)); - node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex)); + node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source)); + nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex)); } else /* if (source.Type == OperandType.I64) */ { @@ -487,15 +484,15 @@ namespace ARMeilleure.CodeGen.X86 // --- This can be done efficiently by adding the result to itself. // -- Then, we need to add the least significant bit that was shifted out. // --- We can convert the least significant bit to float, and add it to the result. - Operand lsb = Local(OperandType.I64); + Operand lsb = Local(OperandType.I64); Operand half = Local(OperandType.I64); Operand lsbF = Local(dest.Type); - node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source)); + node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source)); node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source)); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L))); node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1))); node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb)); @@ -513,7 +510,7 @@ namespace ARMeilleure.CodeGen.X86 // There's no SSE FP negate instruction, so we need to transform that into // a XOR of the value to be negated with a mask with the highest bit set. // This also produces -0 for a negation of the value 0. - Operand dest = node.Destination; + Operand dest = node.Destination; Operand source = node.GetSource(0); Debug.Assert(dest.Type == OperandType.FP32 || @@ -569,14 +566,14 @@ namespace ARMeilleure.CodeGen.X86 if ((index & 1) != 0) { node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1)); - node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8))); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); + node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); } else { node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2)); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00))); - node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00))); + node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2)); } Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1)); @@ -709,16 +706,11 @@ namespace ARMeilleure.CodeGen.X86 private static bool HasConstSrc1(Instruction inst) { - switch (inst) + return inst switch { - case Instruction.Copy: - case Instruction.LoadArgument: - case Instruction.Spill: - case Instruction.SpillArg: - return true; - } - - return false; + Instruction.Copy or Instruction.LoadArgument or Instruction.Spill or Instruction.SpillArg => true, + _ => false, + }; } private static bool HasConstSrc2(Instruction inst) @@ -762,15 +754,15 @@ namespace ARMeilleure.CodeGen.X86 case Instruction.BranchIf: case Instruction.Compare: - { - Operand comp = operation.GetSource(2); + { + Operand comp = operation.GetSource(2); - Debug.Assert(comp.Kind == OperandKind.Constant); + Debug.Assert(comp.Kind == OperandKind.Constant); - var compType = (Comparison)comp.AsInt32(); + var compType = (Comparison)comp.AsInt32(); - return compType == Comparison.Equal || compType == Comparison.NotEqual; - } + return compType == Comparison.Equal || compType == Comparison.NotEqual; + } } return false; @@ -793,4 +785,4 @@ namespace ARMeilleure.CodeGen.X86 return info.Type != IntrinsicType.Crc32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs index a84d5050d..e754cb09b 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs @@ -1,4 +1,3 @@ -using ARMeilleure.CodeGen.RegisterAllocators; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; @@ -15,9 +14,9 @@ namespace ARMeilleure.CodeGen.X86 { Operand dest = node.Destination; - List sources = new List + List sources = new() { - node.GetSource(0) + node.GetSource(0), }; int argsCount = node.SourcesCount - 1; @@ -52,10 +51,10 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type == OperandType.V128 && passOnReg) { // V128 is a struct, we pass each half on a GPR if possible. - Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); + Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64); - nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); + nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0))); nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1))); continue; @@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86 { if (dest.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); Operation operation = node; @@ -116,11 +115,11 @@ namespace ARMeilleure.CodeGen.X86 } } - public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node) + public static void InsertTailcallCopies(IntrusiveList nodes, Operation node) { - List sources = new List + List sources = new() { - node.GetSource(0) + node.GetSource(0), }; int argsCount = node.SourcesCount - 1; @@ -251,11 +250,11 @@ namespace ARMeilleure.CodeGen.X86 // V128 is a struct, we pass each half on a GPR if possible. Operand pArg = Local(OperandType.V128); - Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64); + Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64); Operand argHReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount + 1), OperandType.I64); Operation copyL = Operation(Instruction.VectorCreateScalar, pArg, argLReg); - Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1)); + Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1)); cctx.Cfg.Entry.Operations.AddFirst(copyH); cctx.Cfg.Entry.Operations.AddFirst(copyL); @@ -313,7 +312,7 @@ namespace ARMeilleure.CodeGen.X86 if (source.Type == OperandType.V128) { - Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); + Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64); Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64); nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0))); @@ -331,4 +330,4 @@ namespace ARMeilleure.CodeGen.X86 } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs index 45319e6a5..10a2bd129 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs @@ -155,7 +155,7 @@ namespace ARMeilleure.CodeGen.X86 node.SetSources(sources); } - public static void InsertTailcallCopies(IntrusiveList nodes, StackAllocator stackAlloc, Operation node) + public static void InsertTailcallCopies(IntrusiveList nodes, Operation node) { int argsCount = node.SourcesCount - 1; int maxArgs = CallingConvention.GetArgumentsOnRegsCount(); @@ -324,4 +324,4 @@ namespace ARMeilleure.CodeGen.X86 node.SetSources(Array.Empty()); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Condition.cs b/src/ARMeilleure/CodeGen/X86/X86Condition.cs index c82cbdec5..70699a207 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Condition.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Condition.cs @@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.X86 { enum X86Condition { - Overflow = 0x0, - NotOverflow = 0x1, - Below = 0x2, - AboveOrEqual = 0x3, - Equal = 0x4, - NotEqual = 0x5, - BelowOrEqual = 0x6, - Above = 0x7, - Sign = 0x8, - NotSign = 0x9, - ParityEven = 0xa, - ParityOdd = 0xb, - Less = 0xc, + Overflow = 0x0, + NotOverflow = 0x1, + Below = 0x2, + AboveOrEqual = 0x3, + Equal = 0x4, + NotEqual = 0x5, + BelowOrEqual = 0x6, + Above = 0x7, + Sign = 0x8, + NotSign = 0x9, + ParityEven = 0xa, + ParityOdd = 0xb, + Less = 0xc, GreaterOrEqual = 0xd, - LessOrEqual = 0xe, - Greater = 0xf + LessOrEqual = 0xe, + Greater = 0xf, } static class ComparisonX86Extensions @@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.X86 { return comp switch { +#pragma warning disable IDE0055 // Disable formatting Comparison.Equal => X86Condition.Equal, Comparison.NotEqual => X86Condition.NotEqual, Comparison.Greater => X86Condition.Greater, @@ -39,9 +40,10 @@ namespace ARMeilleure.CodeGen.X86 Comparison.Less => X86Condition.Less, Comparison.GreaterOrEqualUI => X86Condition.AboveOrEqual, Comparison.LessUI => X86Condition.Below, +#pragma warning restore IDE0055 - _ => throw new ArgumentException(null, nameof(comp)) + _ => throw new ArgumentException(null, nameof(comp)), }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs index 9a85c516f..e1979011d 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Instruction.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Instruction.cs @@ -226,6 +226,6 @@ namespace ARMeilleure.CodeGen.X86 Xorpd, Xorps, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs index 98a19b9a2..9d23f9ada 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Optimizer.cs @@ -215,7 +215,7 @@ namespace ARMeilleure.CodeGen.X86 1 => Multiplier.x2, 2 => Multiplier.x4, 3 => Multiplier.x8, - _ => Multiplier.x1 + _ => Multiplier.x1, }; baseOp = indexOnSrc2 ? src1 : src2; diff --git a/src/ARMeilleure/CodeGen/X86/X86Register.cs b/src/ARMeilleure/CodeGen/X86/X86Register.cs index 01f63e311..0a6563663 100644 --- a/src/ARMeilleure/CodeGen/X86/X86Register.cs +++ b/src/ARMeilleure/CodeGen/X86/X86Register.cs @@ -1,5 +1,8 @@ +using System.Diagnostics.CodeAnalysis; + namespace ARMeilleure.CodeGen.X86 { + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum X86Register { Invalid = -1, @@ -12,8 +15,8 @@ namespace ARMeilleure.CodeGen.X86 Rbp = 5, Rsi = 6, Rdi = 7, - R8 = 8, - R9 = 9, + R8 = 8, + R9 = 9, R10 = 10, R11 = 11, R12 = 12, @@ -21,21 +24,21 @@ namespace ARMeilleure.CodeGen.X86 R14 = 14, R15 = 15, - Xmm0 = 0, - Xmm1 = 1, - Xmm2 = 2, - Xmm3 = 3, - Xmm4 = 4, - Xmm5 = 5, - Xmm6 = 6, - Xmm7 = 7, - Xmm8 = 8, - Xmm9 = 9, + Xmm0 = 0, + Xmm1 = 1, + Xmm2 = 2, + Xmm3 = 3, + Xmm4 = 4, + Xmm5 = 5, + Xmm6 = 6, + Xmm7 = 7, + Xmm8 = 8, + Xmm9 = 9, Xmm10 = 10, Xmm11 = 11, Xmm12 = 12, Xmm13 = 13, Xmm14 = 14, - Xmm15 = 15 + Xmm15 = 15, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Common/ArenaAllocator.cs b/src/ARMeilleure/Common/ArenaAllocator.cs index bce6794ad..f810c2abd 100644 --- a/src/ARMeilleure/Common/ArenaAllocator.cs +++ b/src/ARMeilleure/Common/ArenaAllocator.cs @@ -82,8 +82,10 @@ namespace ARMeilleure.Common } else { - _page = new PageInfo(); - _page.Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize); + _page = new PageInfo + { + Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize), + }; _pages.Add(_page); } @@ -106,7 +108,7 @@ namespace ARMeilleure.Common // Free excess pages that was allocated. while (_pages.Count > _pageCount) { - NativeAllocator.Instance.Free(_pages[_pages.Count - 1].Pointer); + NativeAllocator.Instance.Free(_pages[^1].Pointer); _pages.RemoveAt(_pages.Count - 1); } @@ -125,12 +127,13 @@ namespace ARMeilleure.Common // If arena is used frequently, keep pages for longer. Otherwise keep pages for a shorter amount of time. int now = Environment.TickCount; - int count = (now - _lastReset) switch { + int count = (now - _lastReset) switch + { >= 5000 => 0, >= 2500 => 50, >= 1000 => 100, - >= 10 => 1500, - _ => 5000 + >= 10 => 1500, + _ => 5000, }; for (int i = _pages.Count - 1; i >= 0; i--) diff --git a/src/ARMeilleure/Common/BitMap.cs b/src/ARMeilleure/Common/BitMap.cs index 27ef031f3..94d47ea59 100644 --- a/src/ARMeilleure/Common/BitMap.cs +++ b/src/ARMeilleure/Common/BitMap.cs @@ -138,7 +138,7 @@ namespace ARMeilleure.Common var newSpan = new Span(_masks, _count); oldSpan.CopyTo(newSpan); - newSpan.Slice(oldSpan.Length).Clear(); + newSpan[oldSpan.Length..].Clear(); _allocator.Free(oldMask); } @@ -176,8 +176,8 @@ namespace ARMeilleure.Common private int _bit; private readonly BitMap _map; - public int Current => (int)_index * IntSize + _bit; - object IEnumerator.Current => Current; + public readonly int Current => (int)_index * IntSize + _bit; + readonly object IEnumerator.Current => Current; public Enumerator(BitMap map) { @@ -214,9 +214,9 @@ namespace ARMeilleure.Common return true; } - public void Reset() { } + public readonly void Reset() { } - public void Dispose() { } + public readonly void Dispose() { } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Block.cs b/src/ARMeilleure/Decoders/Block.cs index f296d299d..bb88170da 100644 --- a/src/ARMeilleure/Decoders/Block.cs +++ b/src/ARMeilleure/Decoders/Block.cs @@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders { class Block { - public ulong Address { get; set; } + public ulong Address { get; set; } public ulong EndAddress { get; set; } - public Block Next { get; set; } + public Block Next { get; set; } public Block Branch { get; set; } public bool Exit { get; set; } @@ -43,14 +43,14 @@ namespace ARMeilleure.Decoders rightBlock.EndAddress = EndAddress; - rightBlock.Next = Next; + rightBlock.Next = Next; rightBlock.Branch = Branch; rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount)); EndAddress = rightBlock.Address; - Next = rightBlock; + Next = rightBlock; Branch = null; OpCodes.RemoveRange(splitIndex, splitCount); @@ -58,9 +58,9 @@ namespace ARMeilleure.Decoders private static int BinarySearch(List opCodes, ulong address) { - int left = 0; + int left = 0; int middle = 0; - int right = opCodes.Count - 1; + int right = opCodes.Count - 1; while (left <= right) { @@ -92,10 +92,10 @@ namespace ARMeilleure.Decoders { if (OpCodes.Count > 0) { - return OpCodes[OpCodes.Count - 1]; + return OpCodes[^1]; } return null; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Condition.cs b/src/ARMeilleure/Decoders/Condition.cs index 727f897da..961825a10 100644 --- a/src/ARMeilleure/Decoders/Condition.cs +++ b/src/ARMeilleure/Decoders/Condition.cs @@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders { enum Condition { - Eq = 0, - Ne = 1, + Eq = 0, + Ne = 1, GeUn = 2, LtUn = 3, - Mi = 4, - Pl = 5, - Vs = 6, - Vc = 7, + Mi = 4, + Pl = 5, + Vs = 6, + Vc = 7, GtUn = 8, LeUn = 9, - Ge = 10, - Lt = 11, - Gt = 12, - Le = 13, - Al = 14, - Nv = 15 + Ge = 10, + Lt = 11, + Gt = 12, + Le = 13, + Al = 14, + Nv = 15, } static class ConditionExtensions @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders return (Condition)((int)cond ^ 1); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DataOp.cs b/src/ARMeilleure/Decoders/DataOp.cs index 464d00898..f99fd5e70 100644 --- a/src/ARMeilleure/Decoders/DataOp.cs +++ b/src/ARMeilleure/Decoders/DataOp.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { enum DataOp { - Adr = 0, + Adr = 0, Arithmetic = 1, - Logical = 2, - BitField = 3 + Logical = 2, + BitField = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Decoder.cs b/src/ARMeilleure/Decoders/Decoder.cs index 426465aaa..d8abeb9c8 100644 --- a/src/ARMeilleure/Decoders/Decoder.cs +++ b/src/ARMeilleure/Decoders/Decoder.cs @@ -20,11 +20,11 @@ namespace ARMeilleure.Decoders public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode) { - List blocks = new List(); + List blocks = new(); - Queue workQueue = new Queue(); + Queue workQueue = new(); - Dictionary visited = new Dictionary(); + Dictionary visited = new(); Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction); @@ -163,7 +163,7 @@ namespace ARMeilleure.Decoders { index = 0; - int left = 0; + int left = 0; int right = blocks.Count - 1; while (left <= right) @@ -196,9 +196,9 @@ namespace ARMeilleure.Decoders private static void FillBlock( IMemoryManager memory, - ExecutionMode mode, - Block block, - ulong limitAddress) + ExecutionMode mode, + Block block, + ulong limitAddress) { ulong address = block.Address; int itBlockSize = 0; @@ -241,12 +241,12 @@ namespace ARMeilleure.Decoders private static bool IsUnconditionalBranch(OpCode opCode) { return opCode is OpCodeBImmAl || - opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); + opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); } private static bool IsAarch32UnconditionalBranch(OpCode opCode) { - if (!(opCode is OpCode32 op)) + if (opCode is not OpCode32 op) { return false; } @@ -290,9 +290,9 @@ namespace ARMeilleure.Decoders if (opCode is IOpCode32Mem opMem) { - rt = opMem.Rt; - rn = opMem.Rn; - wBack = opMem.WBack; + rt = opMem.Rt; + rn = opMem.Rn; + wBack = opMem.WBack; isLoad = opMem.IsLoad; // For the dual load, we also need to take into account the @@ -306,10 +306,10 @@ namespace ARMeilleure.Decoders { const int pcMask = 1 << RegisterAlias.Aarch32Pc; - rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; - rn = opMemMult.Rn; - wBack = opMemMult.PostOffset != 0; - isLoad = opMemMult.IsLoad; + rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; + rn = opMemMult.Rn; + wBack = opMemMult.PostOffset != 0; + isLoad = opMemMult.IsLoad; } else { @@ -388,4 +388,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderHelper.cs b/src/ARMeilleure/Decoders/DecoderHelper.cs index 5227e6a19..35e573955 100644 --- a/src/ARMeilleure/Decoders/DecoderHelper.cs +++ b/src/ARMeilleure/Decoders/DecoderHelper.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders Imm8ToFP64Table = BuildImm8ToFP64Table(); } - public static readonly uint[] Imm8ToFP32Table; + public static readonly uint[] Imm8ToFP32Table; public static readonly ulong[] Imm8ToFP64Table; private static uint[] BuildImm8ToFP32Table() @@ -40,47 +40,47 @@ namespace ARMeilleure.Decoders // abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b) private static uint ExpandImm8ToFP32(uint imm) { - uint MoveBit(uint bits, int from, int to) + static uint MoveBit(uint bits, int from, int to) { return ((bits >> from) & 1U) << to; } return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) | - MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) | - MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) | - MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) | - MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) | - MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) | + MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) | + MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) | + MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) | + MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) | + MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) | MoveBit(imm, 0, 19); } // abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b) private static ulong ExpandImm8ToFP64(ulong imm) { - ulong MoveBit(ulong bits, int from, int to) + static ulong MoveBit(ulong bits, int from, int to) { return ((bits >> from) & 1UL) << to; } return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) | - MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) | - MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) | - MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) | - MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) | - MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) | - MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) | - MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48); + MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) | + MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) | + MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) | + MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) | + MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) | + MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) | + MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48); } public struct BitMask { public long WMask; public long TMask; - public int Pos; - public int Shift; + public int Pos; + public int Shift; public bool IsUndefined; - public static BitMask Invalid => new BitMask { IsUndefined = true }; + public static BitMask Invalid => new() { IsUndefined = true }; } public static BitMask DecodeBitMask(int opCode, bool immediate) @@ -88,7 +88,7 @@ namespace ARMeilleure.Decoders int immS = (opCode >> 10) & 0x3f; int immR = (opCode >> 16) & 0x3f; - int n = (opCode >> 22) & 1; + int n = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6)); @@ -115,7 +115,7 @@ namespace ARMeilleure.Decoders if (r > 0) { - wMask = BitUtils.RotateRight(wMask, r, size); + wMask = BitUtils.RotateRight(wMask, r, size); wMask &= BitUtils.FillWithOnes(size); } @@ -124,8 +124,8 @@ namespace ARMeilleure.Decoders WMask = BitUtils.Replicate(wMask, size), TMask = BitUtils.Replicate(tMask, size), - Pos = immS, - Shift = immR + Pos = immS, + Shift = immR, }; } @@ -164,4 +164,4 @@ namespace ARMeilleure.Decoders return false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderMode.cs b/src/ARMeilleure/Decoders/DecoderMode.cs index 553620847..280ebb649 100644 --- a/src/ARMeilleure/Decoders/DecoderMode.cs +++ b/src/ARMeilleure/Decoders/DecoderMode.cs @@ -6,4 +6,4 @@ SingleBlock, SingleInstruction, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode.cs b/src/ARMeilleure/Decoders/IOpCode.cs index 37ba7a4c6..9d5e3bf7a 100644 --- a/src/ARMeilleure/Decoders/IOpCode.cs +++ b/src/ARMeilleure/Decoders/IOpCode.cs @@ -14,4 +14,4 @@ namespace ARMeilleure.Decoders OperandType GetOperandType(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32.cs b/src/ARMeilleure/Decoders/IOpCode32.cs index 126c10690..578925dee 100644 --- a/src/ARMeilleure/Decoders/IOpCode32.cs +++ b/src/ARMeilleure/Decoders/IOpCode32.cs @@ -6,4 +6,4 @@ namespace ARMeilleure.Decoders uint GetPc(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Alu.cs b/src/ARMeilleure/Decoders/IOpCode32Alu.cs index 69fee164c..a85ef44ad 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Alu.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rd { get; } int Rn { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs index 342fb8f6c..9d49a440d 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs @@ -6,4 +6,4 @@ bool IsRotated { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs index cd128f657..dd42a70b1 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs index e899a6592..8b976b58f 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs index 879db0593..e8c33c2b1 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BImm.cs b/src/ARMeilleure/Decoders/IOpCode32BImm.cs index ec7db2c26..8d22d5c40 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BImm.cs @@ -1,4 +1,4 @@ namespace ARMeilleure.Decoders { interface IOpCode32BImm : IOpCode32, IOpCodeBImm { } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BReg.cs b/src/ARMeilleure/Decoders/IOpCode32BReg.cs index 097ab4275..9badc9858 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BReg.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Rm { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Exception.cs b/src/ARMeilleure/Decoders/IOpCode32Exception.cs index 8f0fb81a0..4c1fc231c 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Exception.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Exception.cs @@ -4,4 +4,4 @@ { int Id { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs index 71ca6d19c..772e1080f 100644 --- a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs +++ b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs @@ -4,4 +4,4 @@ { bool? SetFlags { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Mem.cs b/src/ARMeilleure/Decoders/IOpCode32Mem.cs index 6664ddffd..a34bc0e2a 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Mem.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders int Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs index 4b891bc1b..0c5e48f22 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders int Offset { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs index 7fe1b0229..f356e4d7c 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs @@ -4,4 +4,4 @@ { int Rm { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs index 65b7ee0b4..3407e98ac 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rm { get; } ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAlu.cs b/src/ARMeilleure/Decoders/IOpCodeAlu.cs index b8c28513d..059769ba9 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAlu.cs @@ -7,4 +7,4 @@ namespace ARMeilleure.Decoders DataOp DataOp { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs index 02f4c997b..40a69cc90 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs index 22540b11a..eec956982 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRs : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } ShiftType ShiftType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs index 9d16be787..e5a8559d8 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRx : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } IntType IntType { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeBImm.cs b/src/ARMeilleure/Decoders/IOpCodeBImm.cs index 958bff28d..9ce7512a1 100644 --- a/src/ARMeilleure/Decoders/IOpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeBImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeCond.cs b/src/ARMeilleure/Decoders/IOpCodeCond.cs index 9808f7c08..6604f19a2 100644 --- a/src/ARMeilleure/Decoders/IOpCodeCond.cs +++ b/src/ARMeilleure/Decoders/IOpCodeCond.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { Condition Cond { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeLit.cs b/src/ARMeilleure/Decoders/IOpCodeLit.cs index 74084a457..434e4da88 100644 --- a/src/ARMeilleure/Decoders/IOpCodeLit.cs +++ b/src/ARMeilleure/Decoders/IOpCodeLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { interface IOpCodeLit : IOpCode { - int Rt { get; } + int Rt { get; } long Immediate { get; } - int Size { get; } - bool Signed { get; } - bool Prefetch { get; } + int Size { get; } + bool Signed { get; } + bool Prefetch { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeSimd.cs b/src/ARMeilleure/Decoders/IOpCodeSimd.cs index 056ef045c..598d9d7f8 100644 --- a/src/ARMeilleure/Decoders/IOpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/IOpCodeSimd.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Size { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstDescriptor.cs b/src/ARMeilleure/Decoders/InstDescriptor.cs index 577ff3946..c35c754a9 100644 --- a/src/ARMeilleure/Decoders/InstDescriptor.cs +++ b/src/ARMeilleure/Decoders/InstDescriptor.cs @@ -4,15 +4,15 @@ namespace ARMeilleure.Decoders { readonly struct InstDescriptor { - public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, InstEmit.Und); + public static InstDescriptor Undefined => new(InstName.Und, InstEmit.Und); - public InstName Name { get; } + public InstName Name { get; } public InstEmitter Emitter { get; } public InstDescriptor(InstName name, InstEmitter emitter) { - Name = name; + Name = name; Emitter = emitter; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstEmitter.cs b/src/ARMeilleure/Decoders/InstEmitter.cs index a8b526569..43bfcdca3 100644 --- a/src/ARMeilleure/Decoders/InstEmitter.cs +++ b/src/ARMeilleure/Decoders/InstEmitter.cs @@ -3,4 +3,4 @@ using ARMeilleure.Translation; namespace ARMeilleure.Decoders { delegate void InstEmitter(ArmEmitterContext context); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IntType.cs b/src/ARMeilleure/Decoders/IntType.cs index 244e96805..937a569aa 100644 --- a/src/ARMeilleure/Decoders/IntType.cs +++ b/src/ARMeilleure/Decoders/IntType.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders { enum IntType { - UInt8 = 0, + UInt8 = 0, UInt16 = 1, UInt32 = 2, UInt64 = 3, - Int8 = 4, - Int16 = 5, - Int32 = 6, - Int64 = 7 + Int8 = 4, + Int16 = 5, + Int32 = 6, + Int64 = 7, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode.cs b/src/ARMeilleure/Decoders/OpCode.cs index f9aed7924..c8123308b 100644 --- a/src/ARMeilleure/Decoders/OpCode.cs +++ b/src/ARMeilleure/Decoders/OpCode.cs @@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders { class OpCode : IOpCode { - public ulong Address { get; } - public int RawOpCode { get; } + public ulong Address { get; } + public int RawOpCode { get; } public int OpCodeSizeInBytes { get; protected set; } = 4; @@ -14,13 +14,13 @@ namespace ARMeilleure.Decoders public RegisterSize RegisterSize { get; protected set; } - public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode); + public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new(inst, address, opCode); public OpCode(InstDescriptor inst, ulong address, int opCode) { Instruction = inst; - Address = address; - RawOpCode = opCode; + Address = address; + RawOpCode = opCode; RegisterSize = RegisterSize.Int64; } @@ -30,15 +30,14 @@ namespace ARMeilleure.Decoders public int GetBitsCount() { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Int32: return 32; - case RegisterSize.Int64: return 64; - case RegisterSize.Simd64: return 64; - case RegisterSize.Simd128: return 128; - } - - throw new InvalidOperationException(); + RegisterSize.Int32 => 32, + RegisterSize.Int64 => 64, + RegisterSize.Simd64 => 64, + RegisterSize.Simd128 => 128, + _ => throw new InvalidOperationException(), + }; } public OperandType GetOperandType() @@ -46,4 +45,4 @@ namespace ARMeilleure.Decoders return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32.cs b/src/ARMeilleure/Decoders/OpCode32.cs index c2f14145b..a2be01e9a 100644 --- a/src/ARMeilleure/Decoders/OpCode32.cs +++ b/src/ARMeilleure/Decoders/OpCode32.cs @@ -31,4 +31,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Alu.cs b/src/ARMeilleure/Decoders/OpCode32Alu.cs index 1625aee0a..8634f5ce9 100644 --- a/src/ARMeilleure/Decoders/OpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCode32Alu.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders SetFlags = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluImm.cs b/src/ARMeilleure/Decoders/OpCode32AluImm.cs index b5435aaf1..c8b05e6bc 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluImm.cs @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders IsRotated = shift != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs index c2dee6c9a..4b2c5897a 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; ShiftType = (ShiftType)((opCode >> 5) & 3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BImm.cs b/src/ARMeilleure/Decoders/OpCode32BImm.cs index f2959b331..e7f5d6db1 100644 --- a/src/ARMeilleure/Decoders/OpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32BImm.cs @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BReg.cs b/src/ARMeilleure/Decoders/OpCode32BReg.cs index d4f5f7601..8939c0de3 100644 --- a/src/ARMeilleure/Decoders/OpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32BReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = opCode & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mem.cs b/src/ARMeilleure/Decoders/OpCode32Mem.cs index ceb1e49f5..8a2421996 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mem.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public int Immediate { get; protected set; } - public bool Index { get; } - public bool Add { get; } - public bool WBack { get; } + public bool Index { get; } + public bool Add { get; } + public bool WBack { get; } public bool Unprivileged { get; } public bool IsLoad { get; } @@ -24,16 +24,16 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; - Index = p; - Add = u; - WBack = !p || w; + Index = p; + Add = u; + WBack = !p || w; Unprivileged = !p && w; IsLoad = isLoad || inst.Name == InstName.Ldrd; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm.cs b/src/ARMeilleure/Decoders/OpCode32MemImm.cs index 3af4b6f7c..fa10e04ee 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = opCode & 0xfff; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs index 1b8a57de4..248ee8e65 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders Immediate = imm4L | (imm4H << 4); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemMult.cs b/src/ARMeilleure/Decoders/OpCode32MemMult.cs index 522b96bb9..6e39e3479 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mrs.cs b/src/ARMeilleure/Decoders/OpCode32Mrs.cs index c34a8b997..b681b54c0 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mrs.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mrs.cs @@ -2,8 +2,8 @@ namespace ARMeilleure.Decoders { class OpCode32Mrs : OpCode32 { - public bool R { get; } - public int Rd { get; } + public bool R { get; } + public int Rd { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mrs(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs index d897ffd80..7186ebf74 100644 --- a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { class OpCode32MsrReg : OpCode32 { - public bool R { get; } - public int Mask { get; } - public int Rd { get; } + public bool R { get; } + public int Mask { get; } + public int Rd { get; } public bool Banked { get; } - public int Rn { get; } + public int Rn { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32Sat.cs b/src/ARMeilleure/Decoders/OpCode32Sat.cs index 621def27c..35c5cf47a 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat.cs @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 5) & 2); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Sat16.cs b/src/ARMeilleure/Decoders/OpCode32Sat16.cs index 51061b079..01f4d3b23 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat16.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat16.cs @@ -15,4 +15,4 @@ namespace ARMeilleure.Decoders SatImm = (opCode >> 16) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs index 4382fc2aa..2361ac1eb 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs @@ -24,27 +24,21 @@ namespace ARMeilleure.Decoders protected int GetQuadwordIndex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - case RegisterSize.Simd64: - return index >> 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 or RegisterSize.Simd64 => index >> 1, + _ => throw new InvalidOperationException(), + }; } protected int GetQuadwordSubindex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - return 0; - case RegisterSize.Simd64: - return index & 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 => 0, + RegisterSize.Simd64 => index & 1, + _ => throw new InvalidOperationException(), + }; } protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode) diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs index a95b32ab0..d3beb4bfd 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs @@ -15,8 +15,8 @@ namespace ARMeilleure.Decoders { IsThumb = isThumb; - Op = ((opCode >> 16) & 0x1) != 0; - T = ((opCode >> 7) & 0x1) != 0; + Op = ((opCode >> 16) & 0x1) != 0; + T = ((opCode >> 7) & 0x1) != 0; Size = ((opCode >> 8) & 0x1); RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32; @@ -41,4 +41,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs index 8d64d673a..558771a38 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs @@ -14,9 +14,15 @@ // The value must be a power of 2, otherwise it is the encoding of another instruction. switch (imm3h) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; } U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0; diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs index da88eed27..325be4ece 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs @@ -4,12 +4,12 @@ namespace ARMeilleure.Decoders { class OpCode32SimdMemPair : OpCode32, IOpCode32Simd { - private static int[] _regsMap = + private static readonly int[] _regsMap = { 1, 1, 4, 2, 1, 1, 3, 1, 1, 1, 2, 1, - 1, 1, 1, 1 + 1, 1, 1, 1, }; public int Vd { get; } diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs index bd4865ea5..cb28418c3 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs @@ -18,6 +18,6 @@ Eq = 0, Vs, Ge, - Gt + Gt, } } diff --git a/src/ARMeilleure/Decoders/OpCodeAdr.cs b/src/ARMeilleure/Decoders/OpCodeAdr.cs index 9655c766c..080280404 100644 --- a/src/ARMeilleure/Decoders/OpCodeAdr.cs +++ b/src/ARMeilleure/Decoders/OpCodeAdr.cs @@ -6,14 +6,14 @@ namespace ARMeilleure.Decoders public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; - Immediate = DecoderHelper.DecodeImmS19_2(opCode); + Immediate = DecoderHelper.DecodeImmS19_2(opCode); Immediate |= ((long)opCode >> 29) & 3; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAlu.cs b/src/ARMeilleure/Decoders/OpCodeAlu.cs index 4d7f03a71..1619ecd8e 100644 --- a/src/ARMeilleure/Decoders/OpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/OpCodeAlu.cs @@ -11,8 +11,8 @@ namespace ARMeilleure.Decoders public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; DataOp = (DataOp)((opCode >> 24) & 0x3); RegisterSize = (opCode >> 31) != 0 @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs index e8b10656a..4413581ca 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluImm.cs b/src/ARMeilleure/Decoders/OpCodeAluImm.cs index 91aa95531..0d2f7202f 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluImm.cs @@ -33,8 +33,8 @@ namespace ARMeilleure.Decoders } else { - throw new ArgumentException(nameof(opCode)); + throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode)); } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRs.cs b/src/ARMeilleure/Decoders/OpCodeAluRs.cs index 949833363..47a47e7d0 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRs.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public ShiftType ShiftType { get; } @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders Shift = shift; - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; ShiftType = (ShiftType)((opCode >> 22) & 0x3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRx.cs b/src/ARMeilleure/Decoders/OpCodeAluRx.cs index d39da9e74..c21486788 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRx.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,9 +11,9 @@ namespace ARMeilleure.Decoders public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = (opCode >> 10) & 0x7; + Shift = (opCode >> 10) & 0x7; IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImm.cs b/src/ARMeilleure/Decoders/OpCodeBImm.cs index e302516e2..2848c1409 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs index 47ae5f562..6c4b28c6c 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs index a52465699..c477ddecf 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs index b57a7ea85..7a51a0720 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs index bad984055..f989e59e4 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeBImmTest : OpCodeBImm { - public int Rt { get; } + public int Rt { get; } public int Bit { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode); @@ -13,8 +13,8 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode); - Bit = (opCode >> 19) & 0x1f; + Bit = (opCode >> 19) & 0x1f; Bit |= (opCode >> 26) & 0x20; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBReg.cs b/src/ARMeilleure/Decoders/OpCodeBReg.cs index b5dcbfd8e..3b84cf5c0 100644 --- a/src/ARMeilleure/Decoders/OpCodeBReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeBReg.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Decoders public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int op4 = (opCode >> 0) & 0x1f; + int op4 = (opCode >> 0) & 0x1f; int op2 = (opCode >> 16) & 0x1f; if (op2 != 0b11111 || op4 != 0b00000) @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 5) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBfm.cs b/src/ARMeilleure/Decoders/OpCodeBfm.cs index 8e1c78361..d51efade2 100644 --- a/src/ARMeilleure/Decoders/OpCodeBfm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBfm.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { public long WMask { get; } public long TMask { get; } - public int Pos { get; } - public int Shift { get; } + public int Pos { get; } + public int Shift { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode); @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders WMask = bm.WMask; TMask = bm.TMask; - Pos = bm.Pos; + Pos = bm.Pos; Shift = bm.Shift; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmp.cs b/src/ARMeilleure/Decoders/OpCodeCcmp.cs index aa47146f8..d40353486 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmp.cs @@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders { class OpCodeCcmp : OpCodeAlu, IOpCodeCond { - public int Nzcv { get; } + public int Nzcv { get; } protected int RmImm; public Condition Cond { get; } @@ -22,11 +22,11 @@ namespace ARMeilleure.Decoders return; } - Nzcv = (opCode >> 0) & 0xf; - Cond = (Condition)((opCode >> 12) & 0xf); - RmImm = (opCode >> 16) & 0x1f; + Nzcv = (opCode >> 0) & 0xf; + Cond = (Condition)((opCode >> 12) & 0xf); + RmImm = (opCode >> 16) & 0x1f; Rd = RegisterAlias.Zr; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs index 3548f2da8..9d6acf196 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs index d5df3b102..349afa120 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCsel.cs b/src/ARMeilleure/Decoders/OpCodeCsel.cs index 4b8dc7fdd..418962e08 100644 --- a/src/ARMeilleure/Decoders/OpCodeCsel.cs +++ b/src/ARMeilleure/Decoders/OpCodeCsel.cs @@ -10,8 +10,8 @@ namespace ARMeilleure.Decoders public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; Cond = (Condition)((opCode >> 12) & 0xf); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeException.cs b/src/ARMeilleure/Decoders/OpCodeException.cs index 6b72138ee..eee636405 100644 --- a/src/ARMeilleure/Decoders/OpCodeException.cs +++ b/src/ARMeilleure/Decoders/OpCodeException.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Id = (opCode >> 5) & 0xffff; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMem.cs b/src/ARMeilleure/Decoders/OpCodeMem.cs index 0ba2bcd18..9b4e5ff3e 100644 --- a/src/ARMeilleure/Decoders/OpCodeMem.cs +++ b/src/ARMeilleure/Decoders/OpCodeMem.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMem : OpCode { - public int Rt { get; protected set; } - public int Rn { get; protected set; } - public int Size { get; protected set; } + public int Rt { get; protected set; } + public int Rn { get; protected set; } + public int Size { get; protected set; } public bool Extend64 { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode); public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rt = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; Size = (opCode >> 30) & 0x3; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemEx.cs b/src/ARMeilleure/Decoders/OpCodeMemEx.cs index 899024853..1dc73140f 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemEx.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemEx.cs @@ -3,14 +3,14 @@ namespace ARMeilleure.Decoders class OpCodeMemEx : OpCodeMem { public int Rt2 { get; } - public int Rs { get; } + public int Rs { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode); public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt2 = (opCode >> 10) & 0x1f; - Rs = (opCode >> 16) & 0x1f; + Rs = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemImm.cs b/src/ARMeilleure/Decoders/OpCodeMemImm.cs index d6ed2282f..4d5eeb1ed 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemImm.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMemImm : OpCodeMem { - public long Immediate { get; protected set; } - public bool WBack { get; protected set; } - public bool PostIdx { get; protected set; } - protected bool Unscaled { get; } + public long Immediate { get; protected set; } + public bool WBack { get; protected set; } + public bool PostIdx { get; protected set; } + protected bool Unscaled { get; } private enum MemOp { - Unscaled = 0, - PostIndexed = 1, + Unscaled = 0, + PostIndexed = 1, Unprivileged = 2, - PreIndexed = 3, - Unsigned + PreIndexed = 3, + Unsigned, } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode); @@ -21,13 +21,13 @@ namespace ARMeilleure.Decoders public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; - WBack = ((opCode >> 24) & 1) == 0; + WBack = ((opCode >> 24) & 1) == 0; // The type is not valid for the Unsigned Immediate 12-bits encoding, // because the bits 11:10 are used for the larger Immediate offset. MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned; - PostIdx = type == MemOp.PostIndexed; + PostIdx = type == MemOp.PostIndexed; Unscaled = type == MemOp.Unscaled || type == MemOp.Unprivileged; @@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemLit.cs b/src/ARMeilleure/Decoders/OpCodeMemLit.cs index 986d66340..8712a78e3 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemLit.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeMemLit : OpCode, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed { get; } - public bool Prefetch { get; } + public int Size { get; } + public bool Signed { get; } + public bool Prefetch { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode); @@ -18,11 +18,27 @@ namespace ARMeilleure.Decoders switch ((opCode >> 30) & 3) { - case 0: Size = 2; Signed = false; Prefetch = false; break; - case 1: Size = 3; Signed = false; Prefetch = false; break; - case 2: Size = 2; Signed = true; Prefetch = false; break; - case 3: Size = 0; Signed = false; Prefetch = true; break; + case 0: + Size = 2; + Signed = false; + Prefetch = false; + break; + case 1: + Size = 3; + Signed = false; + Prefetch = false; + break; + case 2: + Size = 2; + Signed = true; + Prefetch = false; + break; + case 3: + Size = 0; + Signed = false; + Prefetch = true; + break; } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemPair.cs b/src/ARMeilleure/Decoders/OpCodeMemPair.cs index 21018033d..eb696cfeb 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemPair.cs @@ -8,11 +8,11 @@ namespace ARMeilleure.Decoders public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt2 = (opCode >> 10) & 0x1f; - WBack = ((opCode >> 23) & 0x1) != 0; - PostIdx = ((opCode >> 23) & 0x3) == 1; + Rt2 = (opCode >> 10) & 0x1f; + WBack = ((opCode >> 23) & 0x1) != 0; + PostIdx = ((opCode >> 23) & 0x3) == 1; Extend64 = ((opCode >> 30) & 0x3) == 1; - Size = ((opCode >> 31) & 0x1) | 2; + Size = ((opCode >> 31) & 0x1) | 2; DecodeImm(opCode); } @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemReg.cs b/src/ARMeilleure/Decoders/OpCodeMemReg.cs index 73d6c5d2c..9b0d15959 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemReg.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeMemReg : OpCodeMem { public bool Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = ((opCode >> 12) & 0x1) != 0; - IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; - Extend64 = ((opCode >> 22) & 0x3) == 2; + Shift = ((opCode >> 12) & 0x1) != 0; + IntType = (IntType)((opCode >> 13) & 0x7); + Rm = (opCode >> 16) & 0x1f; + Extend64 = ((opCode >> 22) & 0x3) == 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMov.cs b/src/ARMeilleure/Decoders/OpCodeMov.cs index 50af88cb9..a2914b71c 100644 --- a/src/ARMeilleure/Decoders/OpCodeMov.cs +++ b/src/ARMeilleure/Decoders/OpCodeMov.cs @@ -22,9 +22,9 @@ namespace ARMeilleure.Decoders return; } - Rd = (opCode >> 0) & 0x1f; - Immediate = (opCode >> 5) & 0xffff; - Bit = (opCode >> 21) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Immediate = (opCode >> 5) & 0xffff; + Bit = (opCode >> 21) & 0x3; Bit <<= 4; @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMul.cs b/src/ARMeilleure/Decoders/OpCodeMul.cs index 31d140a65..9b1dd37b8 100644 --- a/src/ARMeilleure/Decoders/OpCodeMul.cs +++ b/src/ARMeilleure/Decoders/OpCodeMul.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimd.cs b/src/ARMeilleure/Decoders/OpCodeSimd.cs index 85713690a..bd34d74d9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimd.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeSimd : OpCode, IOpCodeSimd { - public int Rd { get; } - public int Rn { get; } - public int Opc { get; } + public int Rd { get; } + public int Rn { get; } + public int Opc { get; } public int Size { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode); public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; - Opc = (opCode >> 15) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; + Opc = (opCode >> 15) & 0x3; Size = (opCode >> 22) & 0x3; RegisterSize = ((opCode >> 30) & 1) != 0 @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs index 05b32941a..e50cf12e6 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int scale = (opCode >> 10) & 0x3f; - int sf = (opCode >> 31) & 0x1; + int sf = (opCode >> 31) & 0x1; FBits = 64 - scale; @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs index a0e264d9d..0a3359e13 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Imm4 = (opCode >> 11) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs index aa16e0c19..510cd3101 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs index 9f9062b8d..662abe284 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdFmov : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode); @@ -16,7 +16,7 @@ namespace ARMeilleure.Decoders long imm; - Rd = (opCode >> 0) & 0x1f; + Rd = (opCode >> 0) & 0x1f; imm = (opCode >> 13) & 0xff; if (type == 0) @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs index 02f74d030..d900ed9ba 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs @@ -52,17 +52,20 @@ else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - size = 1; imm <<= (modeHigh & 1) << 3; + size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - size = 2; imm <<= modeHigh << 3; + size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - size = 2; imm = ShlOnes(imm, 8 << modeLow); + size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { diff --git a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs index eeca77096..3f4bad7f7 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdImm : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode); @@ -13,14 +13,14 @@ namespace ARMeilleure.Decoders Rd = opCode & 0x1f; int cMode = (opCode >> 12) & 0xf; - int op = (opCode >> 29) & 0x1; + int op = (opCode >> 29) & 0x1; - int modeLow = cMode & 1; + int modeLow = cMode & 1; int modeHigh = cMode >> 1; long imm; - imm = ((uint)opCode >> 5) & 0x1f; + imm = ((uint)opCode >> 5) & 0x1f; imm |= ((uint)opCode >> 11) & 0xe0; if (modeHigh == 0b111) @@ -67,17 +67,20 @@ namespace ARMeilleure.Decoders else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - Size = 1; imm <<= (modeHigh & 1) << 3; + Size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - Size = 2; imm <<= modeHigh << 3; + Size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - Size = 2; imm = ShlOnes(imm, 8 << modeLow); + Size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { @@ -104,4 +107,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs index f6f9249d1..95436879c 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs @@ -23,14 +23,22 @@ namespace ARMeilleure.Decoders switch (Size) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; - case 8: Size = 3; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; + case 8: + Size = 3; + break; } - SrcIndex = imm4 >> Size; + SrcIndex = imm4 >> Size; DstIndex = imm5 >> (Size + 1); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs index c11594cb0..14a9d7c9c 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs @@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs index 8e2129661..efa558bf9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed => false; + public int Size { get; } + public bool Signed => false; public bool Prefetch => false; public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode); @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders Size = opc + 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs index 8922c18f6..c05b52494 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd { - public int Reps { get; } - public int SElems { get; } - public int Elems { get; } - public bool WBack { get; } + public int Reps { get; } + public int SElems { get; } + public int Elems { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode); @@ -13,18 +13,41 @@ namespace ARMeilleure.Decoders { switch ((opCode >> 12) & 0xf) { - case 0b0000: Reps = 1; SElems = 4; break; - case 0b0010: Reps = 4; SElems = 1; break; - case 0b0100: Reps = 1; SElems = 3; break; - case 0b0110: Reps = 3; SElems = 1; break; - case 0b0111: Reps = 1; SElems = 1; break; - case 0b1000: Reps = 1; SElems = 2; break; - case 0b1010: Reps = 2; SElems = 1; break; + case 0b0000: + Reps = 1; + SElems = 4; + break; + case 0b0010: + Reps = 4; + SElems = 1; + break; + case 0b0100: + Reps = 1; + SElems = 3; + break; + case 0b0110: + Reps = 3; + SElems = 1; + break; + case 0b0111: + Reps = 1; + SElems = 1; + break; + case 0b1000: + Reps = 1; + SElems = 2; + break; + case 0b1010: + Reps = 2; + SElems = 1; + break; - default: Instruction = InstDescriptor.Undefined; return; + default: + Instruction = InstDescriptor.Undefined; + return; } - Size = (opCode >> 10) & 3; + Size = (opCode >> 10) & 3; WBack = ((opCode >> 23) & 1) != 0; bool q = ((opCode >> 30) & 1) != 0; @@ -45,4 +68,4 @@ namespace ARMeilleure.Decoders Elems = (GetBitsCount() >> 3) >> Size; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs index 1ab953679..697163896 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders DecodeImm(opCode); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs index 9ea6dda37..be7b25b9d 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs index 44abdd389..5bc614e19 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs @@ -2,21 +2,21 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd { - public int SElems { get; } - public int Index { get; } + public int SElems { get; } + public int Index { get; } public bool Replicate { get; } - public bool WBack { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode); public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int size = (opCode >> 10) & 3; - int s = (opCode >> 12) & 1; + int size = (opCode >> 10) & 3; + int s = (opCode >> 12) & 1; int sElems = (opCode >> 12) & 2; - int scale = (opCode >> 14) & 3; - int l = (opCode >> 22) & 1; - int q = (opCode >> 30) & 1; + int scale = (opCode >> 14) & 3; + int l = (opCode >> 22) & 1; + int q = (opCode >> 30) & 1; sElems |= (opCode >> 21) & 1; @@ -27,63 +27,63 @@ namespace ARMeilleure.Decoders switch (scale) { case 1: - { - if ((size & 1) != 0) { - Instruction = InstDescriptor.Undefined; + if ((size & 1) != 0) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + index >>= 1; + + break; } - index >>= 1; - - break; - } - case 2: - { - if ((size & 2) != 0 || - ((size & 1) != 0 && s != 0)) { - Instruction = InstDescriptor.Undefined; + if ((size & 2) != 0 || + ((size & 1) != 0 && s != 0)) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + if ((size & 1) != 0) + { + index >>= 3; + + scale = 3; + } + else + { + index >>= 2; + } + + break; } - if ((size & 1) != 0) - { - index >>= 3; - - scale = 3; - } - else - { - index >>= 2; - } - - break; - } - case 3: - { - if (l == 0 || s != 0) { - Instruction = InstDescriptor.Undefined; + if (l == 0 || s != 0) + { + Instruction = InstDescriptor.Undefined; - return; + return; + } + + scale = size; + + Replicate = true; + + break; } - - scale = size; - - Replicate = true; - - break; - } } - Index = index; + Index = index; SElems = sElems; - Size = scale; + Size = scale; Extend64 = false; @@ -94,4 +94,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs index ac4f71dae..40f9b1c53 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs @@ -3,16 +3,16 @@ namespace ARMeilleure.Decoders class OpCodeSimdReg : OpCodeSimd { public bool Bit3 { get; } - public int Ra { get; } - public int Rm { get; protected set; } + public int Ra { get; } + public int Rm { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode); public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Bit3 = ((opCode >> 3) & 0x1) != 0; - Ra = (opCode >> 10) & 0x1f; - Rm = (opCode >> 16) & 0x1f; + Bit3 = ((opCode >> 3) & 0x1) != 0; + Ra = (opCode >> 10) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs index 92368deea..bb248ab6b 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Decoders { case 1: Index = (opCode >> 20) & 3 | - (opCode >> 9) & 4; + (opCode >> 9) & 4; Rm &= 0xf; @@ -24,8 +24,10 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs index d46dd57ed..c97bd787e 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs @@ -26,7 +26,9 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs index 9c631e485..3a7ef6aba 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Size = ((opCode >> 13) & 3) + 1; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSystem.cs b/src/ARMeilleure/Decoders/OpCodeSystem.cs index 4d79421a8..215134153 100644 --- a/src/ARMeilleure/Decoders/OpCodeSystem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSystem.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeSystem : OpCode { - public int Rt { get; } + public int Rt { get; } public int Op2 { get; } public int CRm { get; } public int CRn { get; } @@ -13,12 +13,12 @@ namespace ARMeilleure.Decoders public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Op2 = (opCode >> 5) & 0x7; - CRm = (opCode >> 8) & 0xf; - CRn = (opCode >> 12) & 0xf; - Op1 = (opCode >> 16) & 0x7; + Rt = (opCode >> 0) & 0x1f; + Op2 = (opCode >> 5) & 0x7; + CRm = (opCode >> 8) & 0xf; + CRn = (opCode >> 12) & 0xf; + Op1 = (opCode >> 16) & 0x7; Op0 = ((opCode >> 19) & 0x1) | 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16.cs b/src/ARMeilleure/Decoders/OpCodeT16.cs index 9c3d6b006..de946b961 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders OpCodeSizeInBytes = 2; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs index 95f180548..cefb50e4a 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs @@ -1,6 +1,6 @@ namespace ARMeilleure.Decoders { - class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm + class OpCodeT16AddSubImm3 : OpCodeT16, IOpCode32AluImm { public int Rd { get; } public int Rn { get; } @@ -15,8 +15,8 @@ public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rn = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rn = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x7; IsRotated = false; } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs index f230b20e2..fab098a8f 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs @@ -8,7 +8,7 @@ public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int imm = (opCode << 21) >> 20; + int imm = (opCode << 21) >> 20; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs index 5f6842983..edfa86ba5 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs @@ -10,7 +10,7 @@ { Cond = (Condition)((opCode >> 8) & 0xf); - int imm = (opCode << 24) >> 23; + int imm = (opCode << 24) >> 23; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs index 20ef31e27..873c63b93 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs @@ -36,23 +36,13 @@ namespace ARMeilleure.Decoders break; } - switch (inst.Name) + Immediate = inst.Name switch { - case InstName.Str: - case InstName.Ldr: - Immediate = ((opCode >> 6) & 0x1f) << 2; - break; - case InstName.Strb: - case InstName.Ldrb: - Immediate = ((opCode >> 6) & 0x1f); - break; - case InstName.Strh: - case InstName.Ldrh: - Immediate = ((opCode >> 6) & 0x1f) << 1; - break; - default: - throw new InvalidOperationException(); - } + InstName.Str or InstName.Ldr => ((opCode >> 6) & 0x1f) << 2, + InstName.Strb or InstName.Ldrb => ((opCode >> 6) & 0x1f), + InstName.Strh or InstName.Ldrh => ((opCode >> 6) & 0x1f) << 1, + _ => throw new InvalidOperationException(), + }; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs index f4185cfcb..3f3057acd 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs @@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders { InstName.Ldm => true, InstName.Stm => false, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs index a540026ec..8f35e4391 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs @@ -15,8 +15,8 @@ public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rm = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rm = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x1F; ShiftType = (ShiftType)((opCode >> 11) & 3); } diff --git a/src/ARMeilleure/Decoders/OpCodeT32.cs b/src/ARMeilleure/Decoders/OpCodeT32.cs index cf43d4298..5ccbd6a27 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32.cs @@ -12,4 +12,4 @@ OpCodeSizeInBytes = 4; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs index a81b3b3dc..1f92f7558 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs @@ -17,4 +17,4 @@ SetFlags = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs index 0895c29b4..863d14bda 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs index 31de63dd3..12b65a100 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs index a487f55a6..4ac983470 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 0) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs index 1c9ba7a2c..edf0298df 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs @@ -2,7 +2,7 @@ { class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); ShiftType = (ShiftType)((opCode >> 4) & 3); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs index b6da8abdb..13256ee54 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs @@ -24,4 +24,4 @@ Cond = (Condition)((opCode >> 22) & 0xf); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs index 774ec3a64..d7c606619 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs @@ -32,4 +32,4 @@ namespace ARMeilleure.Decoders Immediate = pc + imm32; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs index 7838604b2..4977cdf50 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs @@ -22,4 +22,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs index d8b7763cb..f84e41400 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs @@ -18,7 +18,7 @@ Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 10) & 1) != 0; - Add = ((opCode >> 9) & 1) != 0; + Add = ((opCode >> 9) & 1) != 0; WBack = ((opCode >> 8) & 1) != 0; Immediate = opCode & 0xff; @@ -26,4 +26,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs index 7a078c489..51f5042f2 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 24) & 1) != 0; - Add = ((opCode >> 23) & 1) != 0; + Add = ((opCode >> 23) & 1) != 0; WBack = ((opCode >> 21) & 1) != 0; Immediate = (opCode & 0xff) << 2; @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders IsLoad = ((opCode >> 20) & 1) != 0; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs index a9ba306dc..d155842a6 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs index 5161892bb..2f871c740 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs @@ -4,8 +4,6 @@ namespace ARMeilleure.Decoders { public int Immediate { get; } - public bool IsRotated => false; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode); public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) @@ -13,4 +11,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs index 527754b1f..0a4d2a6c4 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeTable.cs b/src/ARMeilleure/Decoders/OpCodeTable.cs index 4f3599583..d3fc4ca08 100644 --- a/src/ARMeilleure/Decoders/OpCodeTable.cs +++ b/src/ARMeilleure/Decoders/OpCodeTable.cs @@ -13,7 +13,7 @@ namespace ARMeilleure.Decoders private readonly struct InstInfo { - public int Mask { get; } + public int Mask { get; } public int Value { get; } public InstDescriptor Inst { get; } @@ -22,24 +22,25 @@ namespace ARMeilleure.Decoders public InstInfo(int mask, int value, InstDescriptor inst, MakeOp makeOp) { - Mask = mask; - Value = value; - Inst = inst; + Mask = mask; + Value = value; + Inst = inst; MakeOp = makeOp; } } - private static List AllInstA32 = new(); - private static List AllInstT32 = new(); - private static List AllInstA64 = new(); + private static readonly List _allInstA32 = new(); + private static readonly List _allInstT32 = new(); + private static readonly List _allInstA64 = new(); - private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstA64FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instT32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA64FastLookup = new InstInfo[FastLookupSize][]; static OpCodeTable() { -#region "OpCode Table (AArch64)" +#pragma warning disable IDE0055 // Disable formatting + #region "OpCode Table (AArch64)" // Base SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc, InstEmit.Adc, OpCodeAluRs.Create); SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs, InstEmit.Adcs, OpCodeAluRs.Create); @@ -638,9 +639,9 @@ namespace ARMeilleure.Decoders SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V, InstEmit.Xtn_V, OpCodeSimd.Create); SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V, InstEmit.Zip1_V, OpCodeSimdReg.Create); SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create); -#endregion + #endregion -#region "OpCode Table (AArch32, A32)" + #region "OpCode Table (AArch32, A32)" // Base SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create); SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create); @@ -1050,9 +1051,9 @@ namespace ARMeilleure.Decoders SetAsimd("111100100x< allInsts, Func ToFastLookupIndex) + private static void FillFastLookupTable(InstInfo[][] table, List allInsts, Func toFastLookupIndex) { List[] temp = new List[FastLookupSize]; @@ -1315,8 +1317,8 @@ namespace ARMeilleure.Decoders foreach (InstInfo inst in allInsts) { - int mask = ToFastLookupIndex(inst.Mask); - int value = ToFastLookupIndex(inst.Value); + int mask = toFastLookupIndex(inst.Mask); + int value = toFastLookupIndex(inst.Value); for (int index = 0; index < temp.Length; index++) { @@ -1335,22 +1337,21 @@ namespace ARMeilleure.Decoders private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA32, new InstDescriptor(name, emitter), makeOp); } private static void SetT16(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { encoding = "xxxxxxxxxxxxxxxx" + encoding; - Set(encoding, AllInstT32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstT32, new InstDescriptor(name, emitter), makeOp); } private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { string reversedEncoding = $"{encoding.AsSpan(16)}{encoding.AsSpan(0, 16)}"; - MakeOp reversedMakeOp = - (inst, address, opCode) + OpCode ReversedMakeOp(InstDescriptor inst, ulong address, int opCode) => makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16)); - Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp); + Set(reversedEncoding, _allInstT32, new InstDescriptor(name, emitter), ReversedMakeOp); } private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32) @@ -1395,12 +1396,12 @@ namespace ARMeilleure.Decoders private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA64, new InstDescriptor(name, emitter), makeOp); } private static void Set(string encoding, List list, InstDescriptor inst, MakeOp makeOp) { - int bit = encoding.Length - 1; + int bit = encoding.Length - 1; int value = 0; int xMask = 0; int xBits = 0; @@ -1439,7 +1440,7 @@ namespace ARMeilleure.Decoders } else if (chr != '0') { - throw new ArgumentException(nameof(encoding)); + throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding)); } } @@ -1470,17 +1471,17 @@ namespace ARMeilleure.Decoders public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode) { - return GetInstFromList(InstA32FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA32FastLookup[ToFastLookupIndexA(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode) { - return GetInstFromList(InstT32FastLookup[ToFastLookupIndexT(opCode)], opCode); + return GetInstFromList(_instT32FastLookup[ToFastLookupIndexT(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode) { - return GetInstFromList(InstA64FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA64FastLookup[ToFastLookupIndexA(opCode)], opCode); } private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode) diff --git a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs index 17c17812d..ff9a6f271 100644 --- a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs +++ b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs @@ -22,10 +22,10 @@ namespace ARMeilleure.Decoders.Optimizations Block entryBlock = blocks[entryBlockId]; Block startBlock = entryBlock; - Block endBlock = entryBlock; + Block endBlock = entryBlock; int startBlockIndex = entryBlockId; - int endBlockIndex = entryBlockId; + int endBlockIndex = entryBlockId; for (int i = entryBlockId + 1; i < blocks.Count; i++) // Search forwards. { @@ -36,7 +36,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - endBlock = block; + endBlock = block; endBlockIndex = i; } @@ -49,7 +49,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - startBlock = block; + startBlock = block; startBlockIndex = i; } @@ -57,7 +57,7 @@ namespace ARMeilleure.Decoders.Optimizations { return blocks.ToArray(); // Nothing to do here. } - + // Mark branches whose target is outside of the contiguous region as an exit block. for (int i = startBlockIndex; i <= endBlockIndex; i++) { @@ -69,7 +69,7 @@ namespace ARMeilleure.Decoders.Optimizations } } - var newBlocks = new List(blocks.Count); + var newBlocks = new List(blocks.Count); // Finally, rebuild decoded block list, ignoring blocks outside the contiguous range. for (int i = 0; i < blocks.Count; i++) diff --git a/src/ARMeilleure/Decoders/RegisterSize.cs b/src/ARMeilleure/Decoders/RegisterSize.cs index c9cea03ed..7c00984e8 100644 --- a/src/ARMeilleure/Decoders/RegisterSize.cs +++ b/src/ARMeilleure/Decoders/RegisterSize.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Int32, Int64, Simd64, - Simd128 + Simd128, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/ShiftType.cs b/src/ARMeilleure/Decoders/ShiftType.cs index 8583f16ad..43b738f3f 100644 --- a/src/ARMeilleure/Decoders/ShiftType.cs +++ b/src/ARMeilleure/Decoders/ShiftType.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Lsl = 0, Lsr = 1, Asr = 2, - Ror = 3 + Ror = 3, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/IRDumper.cs b/src/ARMeilleure/Diagnostics/IRDumper.cs index 3d1a60e58..16833d085 100644 --- a/src/ARMeilleure/Diagnostics/IRDumper.cs +++ b/src/ARMeilleure/Diagnostics/IRDumper.cs @@ -34,7 +34,9 @@ namespace ARMeilleure.Diagnostics for (int index = 0; index < _indentLevel; index++) { +#pragma warning disable CA1834 // Use StringBuilder.Append(char) for single character strings _builder.Append(Indentation); +#pragma warning restore CA1834 } } @@ -110,10 +112,18 @@ namespace ARMeilleure.Diagnostics switch (reg.Type) { - case RegisterType.Flag: _builder.Append('b'); break; - case RegisterType.FpFlag: _builder.Append('f'); break; - case RegisterType.Integer: _builder.Append('r'); break; - case RegisterType.Vector: _builder.Append('v'); break; + case RegisterType.Flag: + _builder.Append('b'); + break; + case RegisterType.FpFlag: + _builder.Append('f'); + break; + case RegisterType.Integer: + _builder.Append('r'); + break; + case RegisterType.Vector: + _builder.Append('v'); + break; } _builder.Append(reg.Index); @@ -145,9 +155,15 @@ namespace ARMeilleure.Diagnostics switch (memOp.Scale) { - case Multiplier.x2: _builder.Append("*2"); break; - case Multiplier.x4: _builder.Append("*4"); break; - case Multiplier.x8: _builder.Append("*8"); break; + case Multiplier.x2: + _builder.Append("*2"); + break; + case Multiplier.x4: + _builder.Append("*4"); + break; + case Multiplier.x8: + _builder.Append("*8"); + break; } } @@ -308,4 +324,4 @@ namespace ARMeilleure.Diagnostics }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/Logger.cs b/src/ARMeilleure/Diagnostics/Logger.cs index 07a60667e..d7f61230c 100644 --- a/src/ARMeilleure/Diagnostics/Logger.cs +++ b/src/ARMeilleure/Diagnostics/Logger.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Diagnostics { private static long _startTime; - private static long[] _accumulatedTime; + private static readonly long[] _accumulatedTime; static Logger() { @@ -53,4 +53,4 @@ namespace ARMeilleure.Diagnostics Console.WriteLine(text); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/PassName.cs b/src/ARMeilleure/Diagnostics/PassName.cs index e34bf0d2f..2d87659f0 100644 --- a/src/ARMeilleure/Diagnostics/PassName.cs +++ b/src/ARMeilleure/Diagnostics/PassName.cs @@ -14,6 +14,6 @@ namespace ARMeilleure.Diagnostics RegisterAllocation, CodeGeneration, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Diagnostics/Symbols.cs b/src/ARMeilleure/Diagnostics/Symbols.cs index 6bde62f56..86469d8bb 100644 --- a/src/ARMeilleure/Diagnostics/Symbols.cs +++ b/src/ARMeilleure/Diagnostics/Symbols.cs @@ -33,9 +33,8 @@ namespace ARMeilleure.Diagnostics public static string Get(ulong address) { - string result; - if (_symbols.TryGetValue(address, out result)) + if (_symbols.TryGetValue(address, out string result)) { return result; } diff --git a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs index a4f17844d..6452bf0af 100644 --- a/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs +++ b/src/ARMeilleure/Diagnostics/TranslatorEventSource.cs @@ -19,19 +19,19 @@ namespace ARMeilleure.Diagnostics { _rejitQueueCounter = new PollingCounter("rejit-queue-length", this, () => _rejitQueue) { - DisplayName = "Rejit Queue Length" + DisplayName = "Rejit Queue Length", }; _funcTabSizeCounter = new PollingCounter("addr-tab-alloc", this, () => _funcTabSize / 1024d / 1024d) { DisplayName = "AddressTable Total Bytes Allocated", - DisplayUnits = "MiB" + DisplayUnits = "MiB", }; _funcTabLeafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _funcTabLeafSize / 1024d / 1024d) { DisplayName = "AddressTable Total Leaf Bytes Allocated", - DisplayUnits = "MiB" + DisplayUnits = "MiB", }; } diff --git a/src/ARMeilleure/Instructions/CryptoHelper.cs b/src/ARMeilleure/Instructions/CryptoHelper.cs index e517c75d2..ba68cebb3 100644 --- a/src/ARMeilleure/Instructions/CryptoHelper.cs +++ b/src/ARMeilleure/Instructions/CryptoHelper.cs @@ -7,7 +7,8 @@ namespace ARMeilleure.Instructions { static class CryptoHelper { -#region "LookUp Tables" + #region "LookUp Tables" +#pragma warning disable IDE1006 // Naming rule violation private static ReadOnlySpan _sBox => new byte[] { 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, @@ -25,7 +26,7 @@ namespace ARMeilleure.Instructions 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, - 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16, }; private static ReadOnlySpan _invSBox => new byte[] @@ -45,7 +46,7 @@ namespace ARMeilleure.Instructions 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, - 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d, }; private static ReadOnlySpan _gfMul02 => new byte[] @@ -65,7 +66,7 @@ namespace ARMeilleure.Instructions 0x9b, 0x99, 0x9f, 0x9d, 0x93, 0x91, 0x97, 0x95, 0x8b, 0x89, 0x8f, 0x8d, 0x83, 0x81, 0x87, 0x85, 0xbb, 0xb9, 0xbf, 0xbd, 0xb3, 0xb1, 0xb7, 0xb5, 0xab, 0xa9, 0xaf, 0xad, 0xa3, 0xa1, 0xa7, 0xa5, 0xdb, 0xd9, 0xdf, 0xdd, 0xd3, 0xd1, 0xd7, 0xd5, 0xcb, 0xc9, 0xcf, 0xcd, 0xc3, 0xc1, 0xc7, 0xc5, - 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5 + 0xfb, 0xf9, 0xff, 0xfd, 0xf3, 0xf1, 0xf7, 0xf5, 0xeb, 0xe9, 0xef, 0xed, 0xe3, 0xe1, 0xe7, 0xe5, }; private static ReadOnlySpan _gfMul03 => new byte[] @@ -85,7 +86,7 @@ namespace ARMeilleure.Instructions 0x5b, 0x58, 0x5d, 0x5e, 0x57, 0x54, 0x51, 0x52, 0x43, 0x40, 0x45, 0x46, 0x4f, 0x4c, 0x49, 0x4a, 0x6b, 0x68, 0x6d, 0x6e, 0x67, 0x64, 0x61, 0x62, 0x73, 0x70, 0x75, 0x76, 0x7f, 0x7c, 0x79, 0x7a, 0x3b, 0x38, 0x3d, 0x3e, 0x37, 0x34, 0x31, 0x32, 0x23, 0x20, 0x25, 0x26, 0x2f, 0x2c, 0x29, 0x2a, - 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a + 0x0b, 0x08, 0x0d, 0x0e, 0x07, 0x04, 0x01, 0x02, 0x13, 0x10, 0x15, 0x16, 0x1f, 0x1c, 0x19, 0x1a, }; private static ReadOnlySpan _gfMul09 => new byte[] @@ -105,7 +106,7 @@ namespace ARMeilleure.Instructions 0x9a, 0x93, 0x88, 0x81, 0xbe, 0xb7, 0xac, 0xa5, 0xd2, 0xdb, 0xc0, 0xc9, 0xf6, 0xff, 0xe4, 0xed, 0x0a, 0x03, 0x18, 0x11, 0x2e, 0x27, 0x3c, 0x35, 0x42, 0x4b, 0x50, 0x59, 0x66, 0x6f, 0x74, 0x7d, 0xa1, 0xa8, 0xb3, 0xba, 0x85, 0x8c, 0x97, 0x9e, 0xe9, 0xe0, 0xfb, 0xf2, 0xcd, 0xc4, 0xdf, 0xd6, - 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46 + 0x31, 0x38, 0x23, 0x2a, 0x15, 0x1c, 0x07, 0x0e, 0x79, 0x70, 0x6b, 0x62, 0x5d, 0x54, 0x4f, 0x46, }; private static ReadOnlySpan _gfMul0B => new byte[] @@ -125,7 +126,7 @@ namespace ARMeilleure.Instructions 0x01, 0x0a, 0x17, 0x1c, 0x2d, 0x26, 0x3b, 0x30, 0x59, 0x52, 0x4f, 0x44, 0x75, 0x7e, 0x63, 0x68, 0xb1, 0xba, 0xa7, 0xac, 0x9d, 0x96, 0x8b, 0x80, 0xe9, 0xe2, 0xff, 0xf4, 0xc5, 0xce, 0xd3, 0xd8, 0x7a, 0x71, 0x6c, 0x67, 0x56, 0x5d, 0x40, 0x4b, 0x22, 0x29, 0x34, 0x3f, 0x0e, 0x05, 0x18, 0x13, - 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3 + 0xca, 0xc1, 0xdc, 0xd7, 0xe6, 0xed, 0xf0, 0xfb, 0x92, 0x99, 0x84, 0x8f, 0xbe, 0xb5, 0xa8, 0xa3, }; private static ReadOnlySpan _gfMul0D => new byte[] @@ -145,7 +146,7 @@ namespace ARMeilleure.Instructions 0xb7, 0xba, 0xad, 0xa0, 0x83, 0x8e, 0x99, 0x94, 0xdf, 0xd2, 0xc5, 0xc8, 0xeb, 0xe6, 0xf1, 0xfc, 0x67, 0x6a, 0x7d, 0x70, 0x53, 0x5e, 0x49, 0x44, 0x0f, 0x02, 0x15, 0x18, 0x3b, 0x36, 0x21, 0x2c, 0x0c, 0x01, 0x16, 0x1b, 0x38, 0x35, 0x22, 0x2f, 0x64, 0x69, 0x7e, 0x73, 0x50, 0x5d, 0x4a, 0x47, - 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97 + 0xdc, 0xd1, 0xc6, 0xcb, 0xe8, 0xe5, 0xf2, 0xff, 0xb4, 0xb9, 0xae, 0xa3, 0x80, 0x8d, 0x9a, 0x97, }; private static ReadOnlySpan _gfMul0E => new byte[] @@ -165,23 +166,24 @@ namespace ARMeilleure.Instructions 0xec, 0xe2, 0xf0, 0xfe, 0xd4, 0xda, 0xc8, 0xc6, 0x9c, 0x92, 0x80, 0x8e, 0xa4, 0xaa, 0xb8, 0xb6, 0x0c, 0x02, 0x10, 0x1e, 0x34, 0x3a, 0x28, 0x26, 0x7c, 0x72, 0x60, 0x6e, 0x44, 0x4a, 0x58, 0x56, 0x37, 0x39, 0x2b, 0x25, 0x0f, 0x01, 0x13, 0x1d, 0x47, 0x49, 0x5b, 0x55, 0x7f, 0x71, 0x63, 0x6d, - 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d + 0xd7, 0xd9, 0xcb, 0xc5, 0xef, 0xe1, 0xf3, 0xfd, 0xa7, 0xa9, 0xbb, 0xb5, 0x9f, 0x91, 0x83, 0x8d, }; private static ReadOnlySpan _srPerm => new byte[] { - 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3 + 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3, }; private static ReadOnlySpan _isrPerm => new byte[] { - 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11 + 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11, }; -#endregion +#pragma warning restore IDE1006 + #endregion public static V128 AesInvMixColumns(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int columns = 0; columns <= 3; columns++) @@ -204,7 +206,7 @@ namespace ARMeilleure.Instructions public static V128 AesInvShiftRows(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -217,7 +219,7 @@ namespace ARMeilleure.Instructions public static V128 AesInvSubBytes(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -230,7 +232,7 @@ namespace ARMeilleure.Instructions public static V128 AesMixColumns(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int columns = 0; columns <= 3; columns++) @@ -253,7 +255,7 @@ namespace ARMeilleure.Instructions public static V128 AesShiftRows(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) @@ -266,7 +268,7 @@ namespace ARMeilleure.Instructions public static V128 AesSubBytes(V128 op) { - byte[] inState = op.ToArray(); + byte[] inState = op.ToArray(); byte[] outState = new byte[16]; for (int idx = 0; idx <= 15; idx++) diff --git a/src/ARMeilleure/Instructions/InstEmitAlu.cs b/src/ARMeilleure/Instructions/InstEmitAlu.cs index e0d10e77d..ac17c32a7 100644 --- a/src/ARMeilleure/Instructions/InstEmitAlu.cs +++ b/src/ARMeilleure/Instructions/InstEmitAlu.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,7 +11,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { - public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false); + public static void Adc(ArmEmitterContext context) => EmitAdc(context, setFlags: false); public static void Adcs(ArmEmitterContext context) => EmitAdc(context, setFlags: true); private static void EmitAdc(ArmEmitterContext context, bool setFlags) @@ -87,7 +86,7 @@ namespace ARMeilleure.Instructions SetAluDOrZR(context, context.ShiftRightSI(GetAluN(context), GetAluMShift(context))); } - public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false); + public static void Bic(ArmEmitterContext context) => EmitBic(context, setFlags: false); public static void Bics(ArmEmitterContext context) => EmitBic(context, setFlags: true); private static void EmitBic(ArmEmitterContext context, bool setFlags) @@ -190,7 +189,7 @@ namespace ARMeilleure.Instructions SetAluDOrZR(context, context.ShiftRightUI(GetAluN(context), GetAluMShift(context))); } - public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false); + public static void Sbc(ArmEmitterContext context) => EmitSbc(context, setFlags: false); public static void Sbcs(ArmEmitterContext context) => EmitSbc(context, setFlags: true); private static void EmitSbc(ArmEmitterContext context, bool setFlags) @@ -281,16 +280,16 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.I64); Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaaaaaaaaaaaaaaaul)), Const(1)), - context.ShiftLeft (context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1))); + context.ShiftLeft(context.BitwiseAnd(op, Const(0x5555555555555555ul)), Const(1))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccccccccccccccccul)), Const(2)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x3333333333333333ul)), Const(2))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xf0f0f0f0f0f0f0f0ul)), Const(4)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0f0f0f0f0f0f0f0ful)), Const(4))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xff00ff00ff00ff00ul)), Const(8)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x00ff00ff00ff00fful)), Const(8))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); return context.BitwiseOr(context.ShiftRightUI(val, Const(32)), context.ShiftLeft(val, Const(32))); } @@ -340,7 +339,7 @@ namespace ARMeilleure.Instructions Operand val = EmitReverseBytes16_64Op(context, op); return context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xffff0000ffff0000ul)), Const(16)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0000ffff0000fffful)), Const(16))); } public static void Rev64(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitAlu32.cs b/src/ARMeilleure/Instructions/InstEmitAlu32.cs index 584ada7e0..3a5e71bcc 100644 --- a/src/ARMeilleure/Instructions/InstEmitAlu32.cs +++ b/src/ARMeilleure/Instructions/InstEmitAlu32.cs @@ -2,13 +2,14 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - +using System.Diagnostics.CodeAnalysis; using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; namespace ARMeilleure.Instructions { + [SuppressMessage("Style", "IDE0059: Remove unnecessary value assignment")] static partial class InstEmit32 { public static void Add(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs index 994878ad7..4d4a31f7b 100644 --- a/src/ARMeilleure/Instructions/InstEmitAluHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitAluHelper.cs @@ -26,7 +26,7 @@ namespace ARMeilleure.Instructions public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d) { - SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0))); + SetFlag(context, PState.NFlag, context.ICompareLess(d, Const(d.Type, 0))); SetFlag(context, PState.ZFlag, context.ICompareEqual(d, Const(d.Type, 0))); } @@ -196,60 +196,73 @@ namespace ARMeilleure.Instructions { // ARM32. case IOpCode32AluImm op: - { - if (ShouldSetFlags(context) && op.IsRotated && setCarry) { - SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31)); + if (ShouldSetFlags(context) && op.IsRotated && setCarry) + { + SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31)); + } + + return Const(op.Immediate); } + case IOpCode32AluImm16 op: return Const(op.Immediate); - } - case IOpCode32AluImm16 op: return Const(op.Immediate); + case IOpCode32AluRsImm op: + return GetMShiftedByImmediate(context, op, setCarry); + case IOpCode32AluRsReg op: + return GetMShiftedByReg(context, op, setCarry); - case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry); - case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry); - - case IOpCode32AluReg op: return GetIntA32(context, op.Rm); + case IOpCode32AluReg op: + return GetIntA32(context, op.Rm); // ARM64. case IOpCodeAluImm op: - { - if (op.GetOperandType() == OperandType.I32) { - return Const((int)op.Immediate); + if (op.GetOperandType() == OperandType.I32) + { + return Const((int)op.Immediate); + } + else + { + return Const(op.Immediate); + } } - else - { - return Const(op.Immediate); - } - } case IOpCodeAluRs op: - { - Operand value = GetIntOrZR(context, op.Rm); - - switch (op.ShiftType) { - case ShiftType.Lsl: value = context.ShiftLeft (value, Const(op.Shift)); break; - case ShiftType.Lsr: value = context.ShiftRightUI(value, Const(op.Shift)); break; - case ShiftType.Asr: value = context.ShiftRightSI(value, Const(op.Shift)); break; - case ShiftType.Ror: value = context.RotateRight (value, Const(op.Shift)); break; + Operand value = GetIntOrZR(context, op.Rm); + + switch (op.ShiftType) + { + case ShiftType.Lsl: + value = context.ShiftLeft(value, Const(op.Shift)); + break; + case ShiftType.Lsr: + value = context.ShiftRightUI(value, Const(op.Shift)); + break; + case ShiftType.Asr: + value = context.ShiftRightSI(value, Const(op.Shift)); + break; + case ShiftType.Ror: + value = context.RotateRight(value, Const(op.Shift)); + break; + } + + return value; } - return value; - } - case IOpCodeAluRx op: - { - Operand value = GetExtendedM(context, op.Rm, op.IntType); + { + Operand value = GetExtendedM(context, op.Rm, op.IntType); - value = context.ShiftLeft(value, Const(op.Shift)); + value = context.ShiftLeft(value, Const(op.Shift)); - return value; - } + return value; + } - default: throw InvalidOpCodeType(context.CurrOp); + default: + throw InvalidOpCodeType(context.CurrOp); } } @@ -269,9 +282,15 @@ namespace ARMeilleure.Instructions { switch (op.ShiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -281,9 +300,15 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: m = GetLslC(context, m, setCarry, shift); break; - case ShiftType.Lsr: m = GetLsrC(context, m, setCarry, shift); break; - case ShiftType.Asr: m = GetAsrC(context, m, setCarry, shift); break; + case ShiftType.Lsl: + m = GetLslC(context, m, setCarry, shift); + break; + case ShiftType.Lsr: + m = GetLsrC(context, m, setCarry, shift); + break; + case ShiftType.Asr: + m = GetAsrC(context, m, setCarry, shift); + break; case ShiftType.Ror: if (op.Immediate != 0) { @@ -306,9 +331,15 @@ namespace ARMeilleure.Instructions { switch (shiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -328,10 +359,18 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Lsr: shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Asr: shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); break; - case ShiftType.Ror: shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); break; + case ShiftType.Lsl: + shiftResult = EmitLslC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Lsr: + shiftResult = EmitLsrC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Asr: + shiftResult = EmitAsrC(context, m, setCarry, s, shiftIsZero); + break; + case ShiftType.Ror: + shiftResult = EmitRorC(context, m, setCarry, s, shiftIsZero); + break; } return context.ConditionalSelect(shiftIsZero, zeroResult, shiftResult); diff --git a/src/ARMeilleure/Instructions/InstEmitBfm.cs b/src/ARMeilleure/Instructions/InstEmitBfm.cs index 46a7ddddd..aaf228756 100644 --- a/src/ARMeilleure/Instructions/InstEmitBfm.cs +++ b/src/ARMeilleure/Instructions/InstEmitBfm.cs @@ -84,9 +84,9 @@ namespace ARMeilleure.Instructions { Operand res = GetIntOrZR(context, op.Rn); - res = context.ShiftLeft (res, Const(bitsCount - 1 - op.Pos)); + res = context.ShiftLeft(res, Const(bitsCount - 1 - op.Pos)); res = context.ShiftRightSI(res, Const(bitsCount - 1)); - res = context.BitwiseAnd (res, Const(res.Type, ~op.TMask)); + res = context.BitwiseAnd(res, Const(res.Type, ~op.TMask)); Operand n2 = GetBfmN(context); @@ -193,4 +193,4 @@ namespace ARMeilleure.Instructions return context.BitwiseAnd(context.RotateRight(res, Const(op.Shift)), Const(res.Type, mask)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitCcmp.cs b/src/ARMeilleure/Instructions/InstEmitCcmp.cs index 7f0beb6cb..a71fc2689 100644 --- a/src/ARMeilleure/Instructions/InstEmitCcmp.cs +++ b/src/ARMeilleure/Instructions/InstEmitCcmp.cs @@ -2,7 +2,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions OpCodeCcmp op = (OpCodeCcmp)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); EmitCondBranch(context, lblTrue, op.Cond); @@ -58,4 +57,4 @@ namespace ARMeilleure.Instructions context.MarkLabel(lblEnd); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitCsel.cs b/src/ARMeilleure/Instructions/InstEmitCsel.cs index 926b9a9ed..1cd936b31 100644 --- a/src/ARMeilleure/Instructions/InstEmitCsel.cs +++ b/src/ARMeilleure/Instructions/InstEmitCsel.cs @@ -1,7 +1,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -15,10 +14,10 @@ namespace ARMeilleure.Instructions None, Increment, Invert, - Negate + Negate, } - public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None); + public static void Csel(ArmEmitterContext context) => EmitCsel(context, CselOperation.None); public static void Csinc(ArmEmitterContext context) => EmitCsel(context, CselOperation.Increment); public static void Csinv(ArmEmitterContext context) => EmitCsel(context, CselOperation.Invert); public static void Csneg(ArmEmitterContext context) => EmitCsel(context, CselOperation.Negate); @@ -50,4 +49,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, d); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitDiv.cs b/src/ARMeilleure/Instructions/InstEmitDiv.cs index 39a5c32e6..728462ed4 100644 --- a/src/ARMeilleure/Instructions/InstEmitDiv.cs +++ b/src/ARMeilleure/Instructions/InstEmitDiv.cs @@ -1,7 +1,6 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -23,7 +22,7 @@ namespace ARMeilleure.Instructions Operand divisorIsZero = context.ICompareEqual(m, Const(m.Type, 0)); Operand lblBadDiv = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBadDiv, divisorIsZero); @@ -33,7 +32,7 @@ namespace ARMeilleure.Instructions bool is32Bits = op.RegisterSize == RegisterSize.Int32; Operand intMin = is32Bits ? Const(int.MinValue) : Const(long.MinValue); - Operand minus1 = is32Bits ? Const(-1) : Const(-1L); + Operand minus1 = is32Bits ? Const(-1) : Const(-1L); Operand nIsIntMin = context.ICompareEqual(n, intMin); Operand mIsMinus1 = context.ICompareEqual(m, minus1); @@ -51,7 +50,7 @@ namespace ARMeilleure.Instructions Operand d = unsigned ? context.DivideUI(n, m) - : context.Divide (n, m); + : context.Divide(n, m); SetAluDOrZR(context, d); diff --git a/src/ARMeilleure/Instructions/InstEmitException.cs b/src/ARMeilleure/Instructions/InstEmitException.cs index 0baaa87d7..d30fb2fbd 100644 --- a/src/ARMeilleure/Instructions/InstEmitException.cs +++ b/src/ARMeilleure/Instructions/InstEmitException.cs @@ -52,4 +52,4 @@ namespace ARMeilleure.Instructions context.Return(Const(op.Address)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlow.cs b/src/ARMeilleure/Instructions/InstEmitFlow.cs index c40eb55cf..a986bf66f 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlow.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlow.cs @@ -53,7 +53,7 @@ namespace ARMeilleure.Instructions } public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true); - public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); + public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); private static void EmitCb(ArmEmitterContext context, bool onNotZero) { @@ -70,7 +70,7 @@ namespace ARMeilleure.Instructions } public static void Tbnz(ArmEmitterContext context) => EmitTb(context, onNotZero: true); - public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false); + public static void Tbz(ArmEmitterContext context) => EmitTb(context, onNotZero: false); private static void EmitTb(ArmEmitterContext context, bool onNotZero) { @@ -104,4 +104,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlow32.cs b/src/ARMeilleure/Instructions/InstEmitFlow32.cs index 3a7707ee9..289d3f483 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlow32.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlow32.cs @@ -82,7 +82,7 @@ namespace ARMeilleure.Instructions } public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true); - public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); + public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false); private static void EmitCb(ArmEmitterContext context, bool onNotZero) { @@ -109,7 +109,7 @@ namespace ARMeilleure.Instructions } public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false); - public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true); + public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true); private static void EmitTb(ArmEmitterContext context, bool halfword) { @@ -133,4 +133,4 @@ namespace ARMeilleure.Instructions EmitVirtualJump(context, targetAddress, isReturn: false); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs index 6ac329085..2009bafda 100644 --- a/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitFlowHelper.cs @@ -75,66 +75,66 @@ namespace ARMeilleure.Instructions break; case Condition.GtUn: - { - Operand c = GetFlag(PState.CFlag); - Operand z = GetFlag(PState.ZFlag); + { + Operand c = GetFlag(PState.CFlag); + Operand z = GetFlag(PState.ZFlag); - value = context.BitwiseAnd(c, Inverse(z)); + value = context.BitwiseAnd(c, Inverse(z)); - break; - } + break; + } case Condition.LeUn: - { - Operand c = GetFlag(PState.CFlag); - Operand z = GetFlag(PState.ZFlag); + { + Operand c = GetFlag(PState.CFlag); + Operand z = GetFlag(PState.ZFlag); - value = context.BitwiseOr(Inverse(c), z); + value = context.BitwiseOr(Inverse(c), z); - break; - } + break; + } case Condition.Ge: - { - Operand n = GetFlag(PState.NFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand v = GetFlag(PState.VFlag); - value = context.ICompareEqual(n, v); + value = context.ICompareEqual(n, v); - break; - } + break; + } case Condition.Lt: - { - Operand n = GetFlag(PState.NFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand v = GetFlag(PState.VFlag); - value = context.ICompareNotEqual(n, v); + value = context.ICompareNotEqual(n, v); - break; - } + break; + } case Condition.Gt: - { - Operand n = GetFlag(PState.NFlag); - Operand z = GetFlag(PState.ZFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand z = GetFlag(PState.ZFlag); + Operand v = GetFlag(PState.VFlag); - value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v)); + value = context.BitwiseAnd(Inverse(z), context.ICompareEqual(n, v)); - break; - } + break; + } case Condition.Le: - { - Operand n = GetFlag(PState.NFlag); - Operand z = GetFlag(PState.ZFlag); - Operand v = GetFlag(PState.VFlag); + { + Operand n = GetFlag(PState.NFlag); + Operand z = GetFlag(PState.ZFlag); + Operand v = GetFlag(PState.VFlag); - value = context.BitwiseOr(z, context.ICompareNotEqual(n, v)); + value = context.BitwiseOr(z, context.ICompareNotEqual(n, v)); - break; - } + break; + } } return value; diff --git a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs index 55a03a4f6..9218e1ae0 100644 --- a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs @@ -45,7 +45,7 @@ namespace ARMeilleure.Instructions } else { - string name = (size, castagnoli) switch + string name = (size, castagnoli) switch { (0, false) => nameof(SoftFallback.Crc32b), (1, false) => nameof(SoftFallback.Crc32h), @@ -55,7 +55,7 @@ namespace ARMeilleure.Instructions (1, true) => nameof(SoftFallback.Crc32ch), (2, true) => nameof(SoftFallback.Crc32cw), (3, true) => nameof(SoftFallback.Crc32cx), - _ => throw new ArgumentOutOfRangeException(nameof(size)) + _ => throw new ArgumentOutOfRangeException(nameof(size)), }; return context.Call(typeof(SoftFallback).GetMethod(name), crc, value); @@ -71,9 +71,15 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: data = context.VectorInsert8(context.VectorZero(), data, 0); break; - case 1: data = context.VectorInsert16(context.VectorZero(), data, 0); break; - case 2: data = context.VectorInsert(context.VectorZero(), data, 0); break; + case 0: + data = context.VectorInsert8(context.VectorZero(), data, 0); + break; + case 1: + data = context.VectorInsert16(context.VectorZero(), data, 0); + break; + case 2: + data = context.VectorInsert(context.VectorZero(), data, 0); + break; } int bitsize = 8 << size; diff --git a/src/ARMeilleure/Instructions/InstEmitHelper.cs b/src/ARMeilleure/Instructions/InstEmitHelper.cs index a22bb3fb7..7a515f94f 100644 --- a/src/ARMeilleure/Instructions/InstEmitHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitHelper.cs @@ -16,13 +16,25 @@ namespace ARMeilleure.Instructions switch (type) { - case IntType.UInt8: value = context.ZeroExtend8 (value.Type, value); break; - case IntType.UInt16: value = context.ZeroExtend16(value.Type, value); break; - case IntType.UInt32: value = context.ZeroExtend32(value.Type, value); break; + case IntType.UInt8: + value = context.ZeroExtend8(value.Type, value); + break; + case IntType.UInt16: + value = context.ZeroExtend16(value.Type, value); + break; + case IntType.UInt32: + value = context.ZeroExtend32(value.Type, value); + break; - case IntType.Int8: value = context.SignExtend8 (value.Type, value); break; - case IntType.Int16: value = context.SignExtend16(value.Type, value); break; - case IntType.Int32: value = context.SignExtend32(value.Type, value); break; + case IntType.Int8: + value = context.SignExtend8(value.Type, value); + break; + case IntType.Int16: + value = context.SignExtend16(value.Type, value); + break; + case IntType.Int32: + value = context.SignExtend32(value.Type, value); + break; } return value; @@ -100,78 +112,51 @@ namespace ARMeilleure.Instructions public static int GetBankedRegisterAlias(Aarch32Mode mode, int regIndex) { - switch (regIndex) + return regIndex switch { - case 8: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R8Fiq - : RegisterAlias.R8Usr; - - case 9: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R9Fiq - : RegisterAlias.R9Usr; - - case 10: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R10Fiq - : RegisterAlias.R10Usr; - - case 11: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R11Fiq - : RegisterAlias.R11Usr; - - case 12: return mode == Aarch32Mode.Fiq - ? RegisterAlias.R12Fiq - : RegisterAlias.R12Usr; - - case 13: - switch (mode) - { - case Aarch32Mode.User: - case Aarch32Mode.System: return RegisterAlias.SpUsr; - case Aarch32Mode.Fiq: return RegisterAlias.SpFiq; - case Aarch32Mode.Irq: return RegisterAlias.SpIrq; - case Aarch32Mode.Supervisor: return RegisterAlias.SpSvc; - case Aarch32Mode.Abort: return RegisterAlias.SpAbt; - case Aarch32Mode.Hypervisor: return RegisterAlias.SpHyp; - case Aarch32Mode.Undefined: return RegisterAlias.SpUnd; - - default: throw new ArgumentException(nameof(mode)); - } - - case 14: - switch (mode) - { - case Aarch32Mode.User: - case Aarch32Mode.Hypervisor: - case Aarch32Mode.System: return RegisterAlias.LrUsr; - case Aarch32Mode.Fiq: return RegisterAlias.LrFiq; - case Aarch32Mode.Irq: return RegisterAlias.LrIrq; - case Aarch32Mode.Supervisor: return RegisterAlias.LrSvc; - case Aarch32Mode.Abort: return RegisterAlias.LrAbt; - case Aarch32Mode.Undefined: return RegisterAlias.LrUnd; - - default: throw new ArgumentException(nameof(mode)); - } - - default: throw new ArgumentOutOfRangeException(nameof(regIndex)); - } +#pragma warning disable IDE0055 // Disable formatting + 8 => mode == Aarch32Mode.Fiq ? RegisterAlias.R8Fiq : RegisterAlias.R8Usr, + 9 => mode == Aarch32Mode.Fiq ? RegisterAlias.R9Fiq : RegisterAlias.R9Usr, + 10 => mode == Aarch32Mode.Fiq ? RegisterAlias.R10Fiq : RegisterAlias.R10Usr, + 11 => mode == Aarch32Mode.Fiq ? RegisterAlias.R11Fiq : RegisterAlias.R11Usr, + 12 => mode == Aarch32Mode.Fiq ? RegisterAlias.R12Fiq : RegisterAlias.R12Usr, + 13 => mode switch + { + Aarch32Mode.User or Aarch32Mode.System => RegisterAlias.SpUsr, + Aarch32Mode.Fiq => RegisterAlias.SpFiq, + Aarch32Mode.Irq => RegisterAlias.SpIrq, + Aarch32Mode.Supervisor => RegisterAlias.SpSvc, + Aarch32Mode.Abort => RegisterAlias.SpAbt, + Aarch32Mode.Hypervisor => RegisterAlias.SpHyp, + Aarch32Mode.Undefined => RegisterAlias.SpUnd, + _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)), + }, + 14 => mode switch + { + Aarch32Mode.User or Aarch32Mode.Hypervisor or Aarch32Mode.System => RegisterAlias.LrUsr, + Aarch32Mode.Fiq => RegisterAlias.LrFiq, + Aarch32Mode.Irq => RegisterAlias.LrIrq, + Aarch32Mode.Supervisor => RegisterAlias.LrSvc, + Aarch32Mode.Abort => RegisterAlias.LrAbt, + Aarch32Mode.Undefined => RegisterAlias.LrUnd, + _ => throw new ArgumentException($"No such AArch32Mode: {mode}", nameof(mode)), + }, + _ => throw new ArgumentOutOfRangeException(nameof(regIndex), regIndex, null), +#pragma warning restore IDE0055 + }; } public static bool IsA32Return(ArmEmitterContext context) { - switch (context.CurrOp) + return context.CurrOp switch { - case IOpCode32MemMult op: - return true; // Setting PC using LDM is nearly always a return. - case OpCode32AluRsImm op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32AluRsReg op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32AluReg op: - return op.Rm == RegisterAlias.Aarch32Lr; - case OpCode32Mem op: - return op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index; // Setting PC to an address stored on the stack is nearly always a return. - } - return false; + IOpCode32MemMult => true, // Setting PC using LDM is nearly always a return. + OpCode32AluRsImm op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32AluRsReg op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32AluReg op => op.Rm == RegisterAlias.Aarch32Lr, + OpCode32Mem op => op.Rn == RegisterAlias.Aarch32Sp && op.WBack && !op.Index, // Setting PC to an address stored on the stack is nearly always a return. + _ => false, + }; } public static void EmitBxWritePc(ArmEmitterContext context, Operand pc, int sourceRegister = 0) diff --git a/src/ARMeilleure/Instructions/InstEmitMemory.cs b/src/ARMeilleure/Instructions/InstEmitMemory.cs index 7baed14c8..840099f9c 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemory.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemory.cs @@ -26,7 +26,7 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, Const(address)); } - public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false); + public static void Ldr(ArmEmitterContext context) => EmitLdr(context, signed: false); public static void Ldrs(ArmEmitterContext context) => EmitLdr(context, signed: true); private static void EmitLdr(ArmEmitterContext context, bool signed) @@ -89,7 +89,7 @@ namespace ARMeilleure.Instructions Operand address = GetAddress(context); Operand address2 = GetAddress(context, 1L << op.Size); - EmitLoad(op.Rt, address); + EmitLoad(op.Rt, address); EmitLoad(op.Rt2, address2); EmitWBackIfNeeded(context, address); @@ -113,7 +113,7 @@ namespace ARMeilleure.Instructions Operand address = GetAddress(context); Operand address2 = GetAddress(context, 1L << op.Size); - EmitStore(context, address, op.Rt, op.Size); + EmitStore(context, address, op.Rt, op.Size); EmitStore(context, address2, op.Rt2, op.Size); EmitWBackIfNeeded(context, address); @@ -126,42 +126,42 @@ namespace ARMeilleure.Instructions switch (context.CurrOp) { case OpCodeMemImm op: - { - address = context.Copy(GetIntOrSP(context, op.Rn)); - - // Pre-indexing. - if (!op.PostIdx) { - address = context.Add(address, Const(op.Immediate + addend)); - } - else if (addend != 0) - { - address = context.Add(address, Const(addend)); - } + address = context.Copy(GetIntOrSP(context, op.Rn)); - break; - } + // Pre-indexing. + if (!op.PostIdx) + { + address = context.Add(address, Const(op.Immediate + addend)); + } + else if (addend != 0) + { + address = context.Add(address, Const(addend)); + } + + break; + } case OpCodeMemReg op: - { - Operand n = GetIntOrSP(context, op.Rn); - - Operand m = GetExtendedM(context, op.Rm, op.IntType); - - if (op.Shift) { - m = context.ShiftLeft(m, Const(op.Size)); + Operand n = GetIntOrSP(context, op.Rn); + + Operand m = GetExtendedM(context, op.Rm, op.IntType); + + if (op.Shift) + { + m = context.ShiftLeft(m, Const(op.Size)); + } + + address = context.Add(n, m); + + if (addend != 0) + { + address = context.Add(address, Const(addend)); + } + + break; } - - address = context.Add(n, m); - - if (addend != 0) - { - address = context.Add(address, Const(addend)); - } - - break; - } } return address; @@ -181,4 +181,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemory32.cs b/src/ARMeilleure/Instructions/InstEmitMemory32.cs index 17ec97aa6..cee06700d 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemory32.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemory32.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitMemoryHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,18 +11,18 @@ namespace ARMeilleure.Instructions { static partial class InstEmit32 { - private const int ByteSizeLog2 = 0; + private const int ByteSizeLog2 = 0; private const int HWordSizeLog2 = 1; - private const int WordSizeLog2 = 2; + private const int WordSizeLog2 = 2; private const int DWordSizeLog2 = 3; [Flags] enum AccessType { - Store = 0, - Signed = 1, - Load = 2, - Ordered = 4, + Store = 0, + Signed = 1, + Load = 2, + Ordered = 4, Exclusive = 8, LoadZx = Load, @@ -47,7 +46,7 @@ namespace ARMeilleure.Instructions SetIntA32(context, op.Rn, context.Add(n, Const(op.PostOffset))); } - int mask = op.RegisterMask; + int mask = op.RegisterMask; int offset = 0; for (int register = 0; mask != 0; mask >>= 1, register++) @@ -101,7 +100,7 @@ namespace ARMeilleure.Instructions Operand baseAddress = context.Add(n, Const(op.Offset)); - int mask = op.RegisterMask; + int mask = op.RegisterMask; int offset = 0; for (int register = 0; mask != 0; mask >>= 1, register++) @@ -161,7 +160,7 @@ namespace ARMeilleure.Instructions if (op.Index || op.WBack) { temp = op.Add - ? context.Add (n, m) + ? context.Add(n, m) : context.Subtract(n, m); } @@ -200,7 +199,7 @@ namespace ARMeilleure.Instructions if (size == DWordSizeLog2) { Operand lblBigEndian = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag)); @@ -233,7 +232,7 @@ namespace ARMeilleure.Instructions if (size == DWordSizeLog2) { Operand lblBigEndian = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag)); @@ -262,4 +261,4 @@ namespace ARMeilleure.Instructions SetIntA32(context, op.Rd, Const(op.Immediate)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs index c7ed01e34..8c95b33c5 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryEx.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitMemoryExHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -15,10 +14,10 @@ namespace ARMeilleure.Instructions [Flags] private enum AccessType { - None = 0, - Ordered = 1, + None = 0, + Ordered = 1, Exclusive = 2, - OrderedEx = Ordered | Exclusive + OrderedEx = Ordered | Exclusive, } public static void Clrex(ArmEmitterContext context) @@ -34,10 +33,10 @@ namespace ARMeilleure.Instructions public static void Dmb(ArmEmitterContext context) => EmitBarrier(context); public static void Dsb(ArmEmitterContext context) => EmitBarrier(context); - public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered); + public static void Ldar(ArmEmitterContext context) => EmitLdr(context, AccessType.Ordered); public static void Ldaxr(ArmEmitterContext context) => EmitLdr(context, AccessType.OrderedEx); - public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive); - public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive); + public static void Ldxr(ArmEmitterContext context) => EmitLdr(context, AccessType.Exclusive); + public static void Ldxp(ArmEmitterContext context) => EmitLdp(context, AccessType.Exclusive); public static void Ldaxp(ArmEmitterContext context) => EmitLdp(context, AccessType.OrderedEx); private static void EmitLdr(ArmEmitterContext context, AccessType accType) @@ -54,7 +53,7 @@ namespace ARMeilleure.Instructions { OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; - bool ordered = (accType & AccessType.Ordered) != 0; + bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; if (ordered) @@ -80,17 +79,17 @@ namespace ARMeilleure.Instructions Operand valueHigh = context.ShiftRightUI(value, Const(32)); - SetIntOrZR(context, op.Rt, valueLow); + SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt2, valueHigh); } else if (op.Size == 3) { Operand value = EmitLoadExclusive(context, address, exclusive, 4); - Operand valueLow = context.VectorExtract(OperandType.I64, value, 0); + Operand valueLow = context.VectorExtract(OperandType.I64, value, 0); Operand valueHigh = context.VectorExtract(OperandType.I64, value, 1); - SetIntOrZR(context, op.Rt, valueLow); + SetIntOrZR(context, op.Rt, valueLow); SetIntOrZR(context, op.Rt2, valueHigh); } else @@ -112,10 +111,10 @@ namespace ARMeilleure.Instructions // Memory Prefetch, execute as no-op. } - public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered); + public static void Stlr(ArmEmitterContext context) => EmitStr(context, AccessType.Ordered); public static void Stlxr(ArmEmitterContext context) => EmitStr(context, AccessType.OrderedEx); - public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive); - public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive); + public static void Stxr(ArmEmitterContext context) => EmitStr(context, AccessType.Exclusive); + public static void Stxp(ArmEmitterContext context) => EmitStp(context, AccessType.Exclusive); public static void Stlxp(ArmEmitterContext context) => EmitStp(context, AccessType.OrderedEx); private static void EmitStr(ArmEmitterContext context, AccessType accType) @@ -132,7 +131,7 @@ namespace ARMeilleure.Instructions { OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; - bool ordered = (accType & AccessType.Ordered) != 0; + bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; Operand address = context.Copy(GetIntOrSP(context, op.Rn)); @@ -153,8 +152,8 @@ namespace ARMeilleure.Instructions } else /* if (op.Size == 3) */ { - value = context.VectorInsert(context.VectorZero(), t, 0); - value = context.VectorInsert(value, t2, 1); + value = context.VectorInsert(context.VectorZero(), t, 0); + value = context.VectorInsert(value, t2, 1); } EmitStoreExclusive(context, address, value, exclusive, op.Size + 1, op.Rs, a32: false); @@ -175,4 +174,4 @@ namespace ARMeilleure.Instructions context.MemoryBarrier(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs index 9a69442a6..c9a99a3b5 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs @@ -1,7 +1,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -33,7 +32,7 @@ namespace ARMeilleure.Instructions Operand arg0 = context.LoadArgument(OperandType.I64, 0); - Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset())); + Operand exAddrPtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveAddressOffset())); Operand exValuePtr = context.Add(arg0, Const((long)NativeContext.GetExclusiveValueOffset())); context.Store(exAddrPtr, context.BitwiseAnd(address, Const(address.Type, GetExclusiveAddressMask()))); @@ -118,14 +117,14 @@ namespace ARMeilleure.Instructions 1 => context.Load16(exValuePtr), 2 => context.Load(OperandType.I32, exValuePtr), 3 => context.Load(OperandType.I64, exValuePtr), - _ => context.Load(OperandType.V128, exValuePtr) + _ => context.Load(OperandType.V128, exValuePtr), }; Operand currValue = size switch { 0 => context.CompareAndSwap8(physAddr, exValue, value), 1 => context.CompareAndSwap16(physAddr, exValue, value), - _ => context.CompareAndSwap(physAddr, exValue, value) + _ => context.CompareAndSwap(physAddr, exValue, value), }; // STEP 3: Check if we succeeded by comparing expected and in-memory values. @@ -133,14 +132,14 @@ namespace ARMeilleure.Instructions if (size == 4) { - Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0); + Operand currValueLow = context.VectorExtract(OperandType.I64, currValue, 0); Operand currValueHigh = context.VectorExtract(OperandType.I64, currValue, 1); - Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0); + Operand exValueLow = context.VectorExtract(OperandType.I64, exValue, 0); Operand exValueHigh = context.VectorExtract(OperandType.I64, exValue, 1); storeFailed = context.BitwiseOr( - context.ICompareNotEqual(currValueLow, exValueLow), + context.ICompareNotEqual(currValueLow, exValueLow), context.ICompareNotEqual(currValueHigh, exValueHigh)); } else diff --git a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs index f97e395ce..a807eed51 100644 --- a/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using ARMeilleure.Translation.PTC; using System; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions { Zx, Sx32, - Sx64 + Sx64, } public static void EmitLoadZx(ArmEmitterContext context, Operand address, int rt, int size) @@ -66,9 +65,15 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.SignExtend8 (destType, value); break; - case 1: value = context.SignExtend16(destType, value); break; - case 2: value = context.SignExtend32(destType, value); break; + case 0: + value = context.SignExtend8(destType, value); + break; + case 1: + value = context.SignExtend16(destType, value); + break; + case 2: + value = context.SignExtend32(destType, value); + break; } } @@ -128,7 +133,7 @@ namespace ARMeilleure.Instructions Operand temp = context.AllocateLocal(size == 3 ? OperandType.I64 : OperandType.I32); Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -136,10 +141,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.Load8 (physAddr); break; - case 1: value = context.Load16(physAddr); break; - case 2: value = context.Load (OperandType.I32, physAddr); break; - case 3: value = context.Load (OperandType.I64, physAddr); break; + case 0: + value = context.Load8(physAddr); + break; + case 1: + value = context.Load16(physAddr); + break; + case 2: + value = context.Load(OperandType.I32, physAddr); + break; + case 3: + value = context.Load(OperandType.I64, physAddr); + break; } context.Copy(temp, value); @@ -161,7 +174,7 @@ namespace ARMeilleure.Instructions private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -169,10 +182,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.Load8 (physAddr); break; - case 1: value = context.Load16(physAddr); break; - case 2: value = context.Load (OperandType.I32, physAddr); break; - case 3: value = context.Load (OperandType.I64, physAddr); break; + case 0: + value = context.Load8(physAddr); + break; + case 1: + value = context.Load16(physAddr); + break; + case 2: + value = context.Load(OperandType.I32, physAddr); + break; + case 3: + value = context.Load(OperandType.I64, physAddr); + break; } SetInt(context, rt, value); @@ -204,7 +225,7 @@ namespace ARMeilleure.Instructions 1 => context.Load16(physAddr), 2 => context.Load(OperandType.I32, physAddr), 3 => context.Load(OperandType.I64, physAddr), - _ => context.Load(OperandType.V128, physAddr) + _ => context.Load(OperandType.V128, physAddr), }; } @@ -217,7 +238,7 @@ namespace ARMeilleure.Instructions int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size); @@ -225,11 +246,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: value = context.VectorInsert8 (vector, context.Load8(physAddr), elem); break; - case 1: value = context.VectorInsert16(vector, context.Load16(physAddr), elem); break; - case 2: value = context.VectorInsert (vector, context.Load(OperandType.I32, physAddr), elem); break; - case 3: value = context.VectorInsert (vector, context.Load(OperandType.I64, physAddr), elem); break; - case 4: value = context.Load (OperandType.V128, physAddr); break; + case 0: + value = context.VectorInsert8(vector, context.Load8(physAddr), elem); + break; + case 1: + value = context.VectorInsert16(vector, context.Load16(physAddr), elem); + break; + case 2: + value = context.VectorInsert(vector, context.Load(OperandType.I32, physAddr), elem); + break; + case 3: + value = context.VectorInsert(vector, context.Load(OperandType.I64, physAddr), elem); + break; + case 4: + value = context.Load(OperandType.V128, physAddr); + break; } context.Copy(GetVec(rt), value); @@ -254,7 +285,7 @@ namespace ARMeilleure.Instructions private static void EmitWriteInt(ArmEmitterContext context, Operand address, int rt, int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size); @@ -267,10 +298,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: context.Store8 (physAddr, value); break; - case 1: context.Store16(physAddr, value); break; - case 2: context.Store (physAddr, value); break; - case 3: context.Store (physAddr, value); break; + case 0: + context.Store8(physAddr, value); + break; + case 1: + context.Store16(physAddr, value); + break; + case 2: + context.Store(physAddr, value); + break; + case 3: + context.Store(physAddr, value); + break; } if (!context.Memory.Type.IsHostMapped()) @@ -321,7 +360,7 @@ namespace ARMeilleure.Instructions int size) { Operand lblSlowPath = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: true, size); @@ -329,11 +368,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: context.Store8 (physAddr, context.VectorExtract8(value, elem)); break; - case 1: context.Store16(physAddr, context.VectorExtract16(value, elem)); break; - case 2: context.Store (physAddr, context.VectorExtract(OperandType.I32, value, elem)); break; - case 3: context.Store (physAddr, context.VectorExtract(OperandType.I64, value, elem)); break; - case 4: context.Store (physAddr, value); break; + case 0: + context.Store8(physAddr, context.VectorExtract8(value, elem)); + break; + case 1: + context.Store16(physAddr, context.VectorExtract16(value, elem)); + break; + case 2: + context.Store(physAddr, context.VectorExtract(OperandType.I32, value, elem)); + break; + case 3: + context.Store(physAddr, context.VectorExtract(OperandType.I64, value, elem)); + break; + case 4: + context.Store(physAddr, value); + break; } if (!context.Memory.Type.IsHostMapped()) @@ -464,10 +513,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); + break; } return context.Call(info, address); @@ -485,21 +542,39 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break; - case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); + break; + case 4: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadVector128)); + break; } Operand value = context.Call(info, address); switch (size) { - case 0: value = context.VectorInsert8 (vector, value, elem); break; - case 1: value = context.VectorInsert16(vector, value, elem); break; - case 2: value = context.VectorInsert (vector, value, elem); break; - case 3: value = context.VectorInsert (vector, value, elem); break; + case 0: + value = context.VectorInsert8(vector, value, elem); + break; + case 1: + value = context.VectorInsert16(vector, value, elem); + break; + case 2: + value = context.VectorInsert(vector, value, elem); + break; + case 3: + value = context.VectorInsert(vector, value, elem); + break; } context.Copy(GetVec(rt), value); @@ -511,10 +586,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); + break; } Operand value = GetInt(context, rt); @@ -538,11 +621,21 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); break; - case 1: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); break; - case 2: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); break; - case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); break; - case 4: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); break; + case 0: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteByte)); + break; + case 1: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt16)); + break; + case 2: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt32)); + break; + case 3: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)); + break; + case 4: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)); + break; } Operand value = default; @@ -551,10 +644,18 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: value = context.VectorExtract8 (GetVec(rt), elem); break; - case 1: value = context.VectorExtract16(GetVec(rt), elem); break; - case 2: value = context.VectorExtract (OperandType.I32, GetVec(rt), elem); break; - case 3: value = context.VectorExtract (OperandType.I64, GetVec(rt), elem); break; + case 0: + value = context.VectorExtract8(GetVec(rt), elem); + break; + case 1: + value = context.VectorExtract16(GetVec(rt), elem); + break; + case 2: + value = context.VectorExtract(OperandType.I32, GetVec(rt), elem); + break; + case 3: + value = context.VectorExtract(OperandType.I64, GetVec(rt), elem); + break; } } else @@ -585,18 +686,14 @@ namespace ARMeilleure.Instructions // ARM32 helpers. public static Operand GetMemM(ArmEmitterContext context, bool setCarry = true) { - switch (context.CurrOp) + return context.CurrOp switch { - case IOpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry); - - case IOpCode32MemReg op: return GetIntA32(context, op.Rm); - - case IOpCode32Mem op: return Const(op.Immediate); - - case OpCode32SimdMemImm op: return Const(op.Immediate); - - default: throw InvalidOpCodeType(context.CurrOp); - } + IOpCode32MemRsImm op => GetMShiftedByImmediate(context, op, setCarry), + IOpCode32MemReg op => GetIntA32(context, op.Rm), + IOpCode32Mem op => Const(op.Immediate), + OpCode32SimdMemImm op => Const(op.Immediate), + _ => throw InvalidOpCodeType(context.CurrOp), + }; } private static Exception InvalidOpCodeType(OpCode opCode) @@ -614,9 +711,15 @@ namespace ARMeilleure.Instructions { switch (op.ShiftType) { - case ShiftType.Lsr: shift = 32; break; - case ShiftType.Asr: shift = 32; break; - case ShiftType.Ror: shift = 1; break; + case ShiftType.Lsr: + shift = 32; + break; + case ShiftType.Asr: + shift = 32; + break; + case ShiftType.Ror: + shift = 1; + break; } } @@ -626,9 +729,15 @@ namespace ARMeilleure.Instructions switch (op.ShiftType) { - case ShiftType.Lsl: m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); break; - case ShiftType.Lsr: m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); break; - case ShiftType.Asr: m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); break; + case ShiftType.Lsl: + m = InstEmitAluHelper.GetLslC(context, m, setCarry, shift); + break; + case ShiftType.Lsr: + m = InstEmitAluHelper.GetLsrC(context, m, setCarry, shift); + break; + case ShiftType.Asr: + m = InstEmitAluHelper.GetAsrC(context, m, setCarry, shift); + break; case ShiftType.Ror: if (op.Immediate != 0) { diff --git a/src/ARMeilleure/Instructions/InstEmitMove.cs b/src/ARMeilleure/Instructions/InstEmitMove.cs index d551bf2da..f23ac333b 100644 --- a/src/ARMeilleure/Instructions/InstEmitMove.cs +++ b/src/ARMeilleure/Instructions/InstEmitMove.cs @@ -38,4 +38,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, Const(op.GetOperandType(), op.Immediate)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMul.cs b/src/ARMeilleure/Instructions/InstEmitMul.cs index 65d11b30d..89dc09938 100644 --- a/src/ARMeilleure/Instructions/InstEmitMul.cs +++ b/src/ARMeilleure/Instructions/InstEmitMul.cs @@ -2,7 +2,7 @@ using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - +using System.Diagnostics.CodeAnalysis; using static ARMeilleure.Instructions.InstEmitHelper; namespace ARMeilleure.Instructions @@ -33,14 +33,15 @@ namespace ARMeilleure.Instructions public static void Umsubl(ArmEmitterContext context) => EmitMull(context, MullFlags.Subtract); [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] private enum MullFlags { Subtract = 0, - Add = 1 << 0, - Signed = 1 << 1, + Add = 1 << 0, + Signed = 1 << 1, - SignedAdd = Signed | Add, - SignedSubtract = Signed | Subtract + SignedAdd = Signed | Add, + SignedSubtract = Signed | Subtract, } private static void EmitMull(ArmEmitterContext context, MullFlags flags) @@ -97,4 +98,4 @@ namespace ARMeilleure.Instructions SetIntOrZR(context, op.Rd, d); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitMul32.cs b/src/ARMeilleure/Instructions/InstEmitMul32.cs index 0822f92c3..b9680fb69 100644 --- a/src/ARMeilleure/Instructions/InstEmitMul32.cs +++ b/src/ARMeilleure/Instructions/InstEmitMul32.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitAluHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -20,7 +19,7 @@ namespace ARMeilleure.Instructions Signed = 1 << 2, SignedAdd = Signed | Add, - SignedSubtract = Signed | Subtract + SignedSubtract = Signed | Subtract, } public static void Mla(ArmEmitterContext context) @@ -287,14 +286,14 @@ namespace ARMeilleure.Instructions { IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp; - Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn)); - Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm)); + Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn)); + Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm)); Operand dHi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdHi)); Operand dLo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.RdLo)); Operand res = context.Multiply(n, m); - res = context.Add(res, dHi); - res = context.Add(res, dLo); + res = context.Add(res, dHi); + res = context.Add(res, dLo); Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32))); Operand lo = context.ConvertI64ToI32(res); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs index 7e7f26b1a..7b308fa96 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs @@ -7,7 +7,6 @@ using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -185,11 +184,12 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; - Operand res = eSize switch { - 8 => Clz_V_I8 (context, GetVec(op.Rn)), + Operand res = eSize switch + { + 8 => Clz_V_I8(context, GetVec(op.Rn)), 16 => Clz_V_I16(context, GetVec(op.Rn)), 32 => Clz_V_I32(context, GetVec(op.Rn)), - _ => default + _ => default, }; if (res != default) @@ -230,14 +230,14 @@ namespace ARMeilleure.Instructions Operand clzTable = X86GetScalar(context, 0x01_01_01_01_02_02_03_04); Operand maskLow = X86GetAllElements(context, 0x0f_0f_0f_0f); - Operand c04 = X86GetAllElements(context, 0x04_04_04_04); + Operand c04 = X86GetAllElements(context, 0x04_04_04_04); // CLZ of low 4 bits of elements in arg. Operand loClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, arg); // Get the high 4 bits of elements in arg. Operand hiArg = context.AddIntrinsic(Intrinsic.X86Psrlw, arg, Const(4)); - hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow); + hiArg = context.AddIntrinsic(Intrinsic.X86Pand, hiArg, maskLow); // CLZ of high 4 bits of elements in arg. Operand hiClz = context.AddIntrinsic(Intrinsic.X86Pshufb, clzTable, hiArg); @@ -257,8 +257,8 @@ namespace ARMeilleure.Instructions } Operand maskSwap = X86GetElements(context, 0x80_0f_80_0d_80_0b_80_09, 0x80_07_80_05_80_03_80_01); - Operand maskLow = X86GetAllElements(context, 0x00ff_00ff); - Operand c0008 = X86GetAllElements(context, 0x0008_0008); + Operand maskLow = X86GetAllElements(context, 0x00ff_00ff); + Operand c0008 = X86GetAllElements(context, 0x0008_0008); // CLZ pair of high 8 and low 8 bits of elements in arg. Operand hiloClz = Clz_V_I8(context, arg); @@ -282,12 +282,14 @@ namespace ARMeilleure.Instructions return default; } +#pragma warning disable IDE0055 // Disable formatting Operand AddVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Paddd, op0, op1); Operand SubVectorI32(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Psubd, op0, op1); Operand ShiftRightVectorUI32(Operand op0, int imm8) => context.AddIntrinsic(Intrinsic.X86Psrld, op0, Const(imm8)); Operand OrVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Por, op0, op1); Operand AndVector(Operand op0, Operand op1) => context.AddIntrinsic(Intrinsic.X86Pand, op0, op1); Operand NotVector(Operand op0) => context.AddIntrinsic(Intrinsic.X86Pandn, op0, context.VectorOne()); +#pragma warning restore IDE0055 Operand c55555555 = X86GetAllElements(context, 0x55555555); Operand c33333333 = X86GetAllElements(context, 0x33333333); @@ -311,24 +313,24 @@ namespace ARMeilleure.Instructions // Count leading 1s, which is the population count. tmp0 = ShiftRightVectorUI32(res, 1); tmp0 = AndVector(tmp0, c55555555); - res = SubVectorI32(res, tmp0); + res = SubVectorI32(res, tmp0); tmp0 = ShiftRightVectorUI32(res, 2); tmp0 = AndVector(tmp0, c33333333); tmp1 = AndVector(res, c33333333); - res = AddVectorI32(tmp0, tmp1); + res = AddVectorI32(tmp0, tmp1); tmp0 = ShiftRightVectorUI32(res, 4); tmp0 = AddVectorI32(tmp0, res); - res = AndVector(tmp0, c0f0f0f0f); + res = AndVector(tmp0, c0f0f0f0f); tmp0 = ShiftRightVectorUI32(res, 8); - res = AddVectorI32(tmp0, res); + res = AddVectorI32(tmp0, res); tmp0 = ShiftRightVectorUI32(res, 16); - res = AddVectorI32(tmp0, res); + res = AddVectorI32(tmp0, res); - res = AndVector(res, c0000003f); + res = AndVector(res, c0000003f); return res; } @@ -2436,8 +2438,8 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { - Operand maskHalf = X86GetScalar(context, 0.5f); - Operand maskThree = X86GetScalar(context, 3f); + Operand maskHalf = X86GetScalar(context, 0.5f); + Operand maskThree = X86GetScalar(context, 3f); Operand maskOneHalf = X86GetScalar(context, 1.5f); if (Optimizations.UseFma) @@ -2457,8 +2459,8 @@ namespace ARMeilleure.Instructions } else /* if (sizeF == 1) */ { - Operand maskHalf = X86GetScalar(context, 0.5d); - Operand maskThree = X86GetScalar(context, 3d); + Operand maskHalf = X86GetScalar(context, 0.5d); + Operand maskThree = X86GetScalar(context, 3d); Operand maskOneHalf = X86GetScalar(context, 1.5d); if (Optimizations.UseFma) @@ -2505,8 +2507,8 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { - Operand maskHalf = X86GetAllElements(context, 0.5f); - Operand maskThree = X86GetAllElements(context, 3f); + Operand maskHalf = X86GetAllElements(context, 0.5f); + Operand maskThree = X86GetAllElements(context, 3f); Operand maskOneHalf = X86GetAllElements(context, 1.5f); if (Optimizations.UseFma) @@ -2519,7 +2521,7 @@ namespace ARMeilleure.Instructions res = context.AddIntrinsic(Intrinsic.X86Subps, maskThree, res); } - res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res); + res = context.AddIntrinsic(Intrinsic.X86Mulps, maskHalf, res); res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF); if (op.RegisterSize == RegisterSize.Simd64) @@ -2531,8 +2533,8 @@ namespace ARMeilleure.Instructions } else /* if (sizeF == 1) */ { - Operand maskHalf = X86GetAllElements(context, 0.5d); - Operand maskThree = X86GetAllElements(context, 3d); + Operand maskHalf = X86GetAllElements(context, 0.5d); + Operand maskThree = X86GetAllElements(context, 3d); Operand maskOneHalf = X86GetAllElements(context, 1.5d); if (Optimizations.UseFma) @@ -2545,7 +2547,7 @@ namespace ARMeilleure.Instructions res = context.AddIntrinsic(Intrinsic.X86Subpd, maskThree, res); } - res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res); + res = context.AddIntrinsic(Intrinsic.X86Mulpd, maskHalf, res); res = EmitSse41RecipStepSelectOpF(context, n, m, res, maskOneHalf, scalar: false, sizeF); context.Copy(GetVec(op.Rd), res); @@ -2824,10 +2826,10 @@ namespace ARMeilleure.Instructions for (int i = 0; i < 8; i++) { Operand mask = context.AddIntrinsic(Intrinsic.X86Psllw, n, Const(15 - i)); - mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15)); + mask = context.AddIntrinsic(Intrinsic.X86Psraw, mask, Const(15)); Operand tmp = context.AddIntrinsic(Intrinsic.X86Psllw, m, Const(i)); - tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); + tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp); } @@ -2839,12 +2841,12 @@ namespace ARMeilleure.Instructions for (int i = 0; i < 64; i++) { Operand mask = context.AddIntrinsic(Intrinsic.X86Movlhps, n, n); - mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i)); - mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63)); - mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask); + mask = context.AddIntrinsic(Intrinsic.X86Psllq, mask, Const(63 - i)); + mask = context.AddIntrinsic(Intrinsic.X86Psrlq, mask, Const(63)); + mask = context.AddIntrinsic(Intrinsic.X86Psubq, zero, mask); Operand tmp = EmitSse2Sll_128(context, m, i); - tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); + tmp = context.AddIntrinsic(Intrinsic.X86Pand, tmp, mask); res = context.AddIntrinsic(Intrinsic.X86Pxor, res, tmp); } @@ -3119,7 +3121,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand m = GetVec(op.Rm); - Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); + Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m); Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psraw : Intrinsic.X86Psrad; @@ -4058,7 +4060,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand m = GetVec(op.Rm); - Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); + Operand res = context.AddIntrinsic(Intrinsic.X86Pand, n, m); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pxor, n, m); Intrinsic shiftInst = op.Size == 1 ? Intrinsic.X86Psrlw : Intrinsic.X86Psrld; @@ -4594,7 +4596,7 @@ namespace ARMeilleure.Instructions { int pairIndex = index << 1; - Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); + Operand ne0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); Operand ne1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed); Operand e = context.Add(ne0, ne1); @@ -4686,7 +4688,7 @@ namespace ARMeilleure.Instructions Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64); Operand cmp = signed - ? context.ICompareGreaterOrEqual (op1, op2) + ? context.ICompareGreaterOrEqual(op1, op2) : context.ICompareGreaterOrEqualUI(op1, op2); return context.ConditionalSelect(cmp, op1, op2); @@ -4697,7 +4699,7 @@ namespace ARMeilleure.Instructions Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64); Operand cmp = signed - ? context.ICompareLessOrEqual (op1, op2) + ? context.ICompareLessOrEqual(op1, op2) : context.ICompareLessOrEqualUI(op1, op2); return context.ConditionalSelect(cmp, op1, op2); @@ -4852,10 +4854,10 @@ namespace ARMeilleure.Instructions Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmpps, opF, opF, Const((int)CmpCondition.UnorderedQ)); - Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); - mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal)); + Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); + mask2 = context.AddIntrinsic(Intrinsic.X86Cmpps, mask2, qMask, Const((int)CmpCondition.Equal)); - qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default; + qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andps, mask2, mask1) : default; sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnps, mask2, mask1) : default; } else /* if ((op.Size & 1) == 1) */ @@ -4866,10 +4868,10 @@ namespace ARMeilleure.Instructions Operand mask1 = context.AddIntrinsic(Intrinsic.X86Cmppd, opF, opF, Const((int)CmpCondition.UnorderedQ)); - Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); - mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal)); + Operand mask2 = context.AddIntrinsic(Intrinsic.X86Pand, opF, qMask); + mask2 = context.AddIntrinsic(Intrinsic.X86Cmppd, mask2, qMask, Const((int)CmpCondition.Equal)); - qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default; + qNaNMask = isQNaN == null || (bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andpd, mask2, mask1) : default; sNaNMask = isQNaN == null || !(bool)isQNaN ? context.AddIntrinsic(Intrinsic.X86Andnpd, mask2, mask1) : default; } } @@ -4895,11 +4897,11 @@ namespace ARMeilleure.Instructions Operand qMask = scalar ? X86GetScalar(context, 1 << QBit) : X86GetAllElements(context, 1 << QBit); - Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); - resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); + Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); + resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvps, mCopy, nCopy, resNaNMask); - resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); + resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmpps, nCopy, mCopy, Const((int)CmpCondition.OrderedQ)); @@ -4929,11 +4931,11 @@ namespace ARMeilleure.Instructions Operand qMask = scalar ? X86GetScalar(context, 1L << QBit) : X86GetAllElements(context, 1L << QBit); - Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); - resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); + Operand resNaNMask = context.AddIntrinsic(Intrinsic.X86Pandn, mSNaNMask, nQNaNMask); + resNaNMask = context.AddIntrinsic(Intrinsic.X86Por, resNaNMask, nSNaNMask); Operand resNaN = context.AddIntrinsic(Intrinsic.X86Blendvpd, mCopy, nCopy, resNaNMask); - resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); + resNaN = context.AddIntrinsic(Intrinsic.X86Por, resNaN, qMask); Operand resMask = context.AddIntrinsic(Intrinsic.X86Cmppd, nCopy, mCopy, Const((int)CmpCondition.OrderedQ)); @@ -4964,10 +4966,10 @@ namespace ARMeilleure.Instructions Operand mask = X86GetAllElements(context, -0f); Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxps : Intrinsic.X86Minps, n, m); - res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res); + res = context.AddIntrinsic(Intrinsic.X86Andnps, mask, res); Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m); - resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign); + resSign = context.AddIntrinsic(Intrinsic.X86Andps, mask, resSign); return context.AddIntrinsic(Intrinsic.X86Por, res, resSign); } @@ -4976,10 +4978,10 @@ namespace ARMeilleure.Instructions Operand mask = X86GetAllElements(context, -0d); Operand res = context.AddIntrinsic(isMax ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, n, m); - res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res); + res = context.AddIntrinsic(Intrinsic.X86Andnpd, mask, res); Operand resSign = context.AddIntrinsic(isMax ? Intrinsic.X86Pand : Intrinsic.X86Por, n, m); - resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign); + resSign = context.AddIntrinsic(Intrinsic.X86Andpd, mask, resSign); return context.AddIntrinsic(Intrinsic.X86Por, res, resSign); } @@ -5003,7 +5005,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand negInfMask = scalar - ? X86GetScalar (context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity) + ? X86GetScalar(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity) : X86GetAllElements(context, isMaxNum ? float.NegativeInfinity : float.PositiveInfinity); Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnps, mQNaNMask, nQNaNMask); @@ -5038,7 +5040,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand negInfMask = scalar - ? X86GetScalar (context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity) + ? X86GetScalar(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity) : X86GetAllElements(context, isMaxNum ? double.NegativeInfinity : double.PositiveInfinity); Operand nMask = context.AddIntrinsic(Intrinsic.X86Andnpd, mQNaNMask, nQNaNMask); @@ -5072,7 +5074,7 @@ namespace ARMeilleure.Instructions { None, Add, - Subtract + Subtract, } private static void EmitSse41VectorMul_AddSub(ArmEmitterContext context, AddSub addSub) @@ -5187,10 +5189,10 @@ namespace ARMeilleure.Instructions Intrinsic subInst = X86PsubInstruction[size]; - Operand res = context.AddIntrinsic(subInst, n, m); + Operand res = context.AddIntrinsic(subInst, n, m); Operand res2 = context.AddIntrinsic(subInst, m, n); - res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res); + res = context.AddIntrinsic(Intrinsic.X86Pand, cmpMask, res); res2 = context.AddIntrinsic(Intrinsic.X86Pandn, cmpMask, res2); res = context.AddIntrinsic(Intrinsic.X86Por, res, res2); @@ -5214,7 +5216,7 @@ namespace ARMeilleure.Instructions } Operand high = context.AddIntrinsic(Intrinsic.X86Pslldq, op, Const(8)); - high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift)); + high = context.AddIntrinsic(Intrinsic.X86Psrlq, high, Const(64 - shift)); Operand low = context.AddIntrinsic(Intrinsic.X86Psllq, op, Const(shift)); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index a9994e412..1d99cbc3d 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -2,7 +2,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitFlowHelper; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; @@ -190,7 +189,7 @@ namespace ARMeilleure.Instructions 2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)), 1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)), 0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)), - _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".") + _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."), }; InsertScalar(context, op.Vd, insert); @@ -212,7 +211,7 @@ namespace ARMeilleure.Instructions 2 => context.Multiply(context.ZeroExtend32(OperandType.I64, insert), Const(0x0000000100000001u)), 1 => context.Multiply(context.ZeroExtend16(OperandType.I64, insert), Const(0x0001000100010001u)), 0 => context.Multiply(context.ZeroExtend8(OperandType.I64, insert), Const(0x0101010101010101u)), - _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\".") + _ => throw new InvalidOperationException($"Invalid Vdup size \"{op.Size}\"."), }; InsertScalar(context, op.Vd, insert); @@ -1654,7 +1653,7 @@ namespace ARMeilleure.Instructions { IOpCode32Simd op = (IOpCode32Simd)context.CurrOp; - Func genericEmit = (n, m) => + Operand genericEmit(Operand n, Operand m) { Operand nNum = context.Copy(n); Operand mNum = context.Copy(m); @@ -1688,7 +1687,7 @@ namespace ARMeilleure.Instructions return context.AddIntrinsic(isMaxNum ? Intrinsic.X86Maxpd : Intrinsic.X86Minpd, nNum, mNum); } - }; + } if (scalar) { diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs index c32b64ba1..aab677869 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCmp.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -493,7 +492,7 @@ namespace ARMeilleure.Instructions OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); context.BranchIfTrue(lblTrue, InstEmitFlowHelper.GetCondTrue(context, op.Cond)); @@ -510,7 +509,7 @@ namespace ARMeilleure.Instructions private static void EmitSetNzcv(ArmEmitterContext context, int nzcv) { - Operand Extract(int value, int bit) + static Operand Extract(int value, int bit) { if (bit != 0) { @@ -532,7 +531,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; + bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3; if (Optimizations.FastFP && (signalNaNs ? Optimizations.UseAvx : Optimizations.UseSse2)) { diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs index 652ad397c..3363a7c77 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -67,8 +66,8 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); - res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112() - res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14)); + res = context.AddIntrinsic(Intrinsic.X86Pslldq, res, Const(14)); // VectorZeroUpper112() + res = context.AddIntrinsic(Intrinsic.X86Psrldq, res, Const(14)); context.Copy(GetVec(op.Rd), res); } @@ -92,7 +91,7 @@ namespace ARMeilleure.Instructions Debug.Assert(!Optimizations.ForceLegacySse); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn)); - res = context.VectorZeroUpper96(res); + res = context.VectorZeroUpper96(res); context.Copy(GetVec(op.Rd), res); } @@ -116,7 +115,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), n); - res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); + res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); context.Copy(GetVec(op.Rd), res); } @@ -140,8 +139,8 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, GetVec(op.Rn)); - res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res); - res = context.VectorZeroUpper64(res); + res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res); + res = context.VectorZeroUpper64(res); context.Copy(GetVec(op.Rd), res); } @@ -273,7 +272,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n; - res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res); + res = context.AddIntrinsic(Intrinsic.X86Cvtps2pd, res); context.Copy(GetVec(op.Rd), res); } @@ -284,7 +283,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand res = op.RegisterSize == RegisterSize.Simd128 ? context.AddIntrinsic(Intrinsic.X86Movhlps, n, n) : n; - res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res); + res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res); context.Copy(GetVec(op.Rd), res); } @@ -387,10 +386,10 @@ namespace ARMeilleure.Instructions Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps; Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtpd2ps, GetVec(op.Rn)); - nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); + nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); Operand res = context.VectorZeroUpper64(d); - res = context.AddIntrinsic(movInst, res, nInt); + res = context.AddIntrinsic(movInst, res, nInt); context.Copy(d, res); } @@ -404,10 +403,10 @@ namespace ARMeilleure.Instructions Intrinsic movInst = op.RegisterSize == RegisterSize.Simd128 ? Intrinsic.X86Movlhps : Intrinsic.X86Movhlps; Operand nInt = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, n, Const(X86GetRoundControl(FPRoundingMode.ToNearest))); - nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); + nInt = context.AddIntrinsic(Intrinsic.X86Movlhps, nInt, nInt); Operand res = context.VectorZeroUpper64(d); - res = context.AddIntrinsic(movInst, res, nInt); + res = context.AddIntrinsic(movInst, res, nInt); context.Copy(d, res); } @@ -1225,15 +1224,15 @@ namespace ARMeilleure.Instructions { Debug.Assert(opF.Type == OperandType.V128); - Operand longL = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opF); // opFL - Operand res = context.VectorCreateScalar(longL); + Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opF); // opFL + Operand res = context.VectorCreateScalar(longL); if (!scalar) { - Operand opFH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, opF); // res doesn't matter. - Operand longH = context.AddIntrinsicLong (Intrinsic.X86Cvtsd2si, opFH); - Operand resH = context.VectorCreateScalar(longH); - res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH); + Operand opFH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, opF); // res doesn't matter. + Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, opFH); + Operand resH = context.VectorCreateScalar(longH); + res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH); } return res; @@ -1244,14 +1243,14 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.V128); Operand longL = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, op); // opL - Operand res = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL); + Operand res = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, context.VectorZero(), longL); if (!scalar) { - Operand opH = context.AddIntrinsic (Intrinsic.X86Movhlps, res, op); // res doesn't matter. + Operand opH = context.AddIntrinsic(Intrinsic.X86Movhlps, res, op); // res doesn't matter. Operand longH = context.AddIntrinsicLong(Intrinsic.X86Cvtsi2si, opH); - Operand resH = context.AddIntrinsic (Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter. - res = context.AddIntrinsic (Intrinsic.X86Movlhps, res, resH); + Operand resH = context.AddIntrinsic(Intrinsic.X86Cvtsi2sd, res, longH); // res doesn't matter. + res = context.AddIntrinsic(Intrinsic.X86Movlhps, res, resH); } return res; @@ -1278,7 +1277,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 - fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask); @@ -1307,7 +1306,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask); @@ -1334,16 +1333,16 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand mask = scalar // 65536.000f (1 << 16) - ? X86GetScalar (context, 0x47800000) + ? X86GetScalar(context, 0x47800000) : X86GetAllElements(context, 0x47800000); Operand res = context.AddIntrinsic(Intrinsic.X86Psrld, n, Const(16)); - res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res); - res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask); + res = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res); + res = context.AddIntrinsic(Intrinsic.X86Mulps, res, mask); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pslld, n, Const(16)); - res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16)); - res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2); + res2 = context.AddIntrinsic(Intrinsic.X86Psrld, res2, Const(16)); + res2 = context.AddIntrinsic(Intrinsic.X86Cvtdq2ps, res2); res = context.AddIntrinsic(Intrinsic.X86Addps, res, res2); @@ -1355,7 +1354,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 - fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulps, res, fpScaledMask); @@ -1375,16 +1374,16 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand mask = scalar // 4294967296.0000000d (1L << 32) - ? X86GetScalar (context, 0x41F0000000000000L) + ? X86GetScalar(context, 0x41F0000000000000L) : X86GetAllElements(context, 0x41F0000000000000L); - Operand res = context.AddIntrinsic (Intrinsic.X86Psrlq, n, Const(32)); - res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar); - res = context.AddIntrinsic (Intrinsic.X86Mulpd, res, mask); + Operand res = context.AddIntrinsic(Intrinsic.X86Psrlq, n, Const(32)); + res = EmitSse2CvtInt64ToDoubleOp(context, res, scalar); + res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, mask); - Operand res2 = context.AddIntrinsic (Intrinsic.X86Psllq, n, Const(32)); - res2 = context.AddIntrinsic (Intrinsic.X86Psrlq, res2, Const(32)); - res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar); + Operand res2 = context.AddIntrinsic(Intrinsic.X86Psllq, n, Const(32)); + res2 = context.AddIntrinsic(Intrinsic.X86Psrlq, res2, Const(32)); + res2 = EmitSse2CvtInt64ToDoubleOp(context, res2, scalar); res = context.AddIntrinsic(Intrinsic.X86Addpd, res, res2); @@ -1396,7 +1395,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L - fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); res = context.AddIntrinsic(Intrinsic.X86Mulpd, res, fpScaledMask); @@ -1423,7 +1422,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1433,7 +1432,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 + fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask); @@ -1451,7 +1450,7 @@ namespace ARMeilleure.Instructions Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648) - ? X86GetScalar (context, 0x4F000000) + ? X86GetScalar(context, 0x4F000000) : X86GetAllElements(context, 0x4F000000); nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1472,7 +1471,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1482,7 +1481,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask); @@ -1500,7 +1499,7 @@ namespace ARMeilleure.Instructions Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808) - ? X86GetScalar (context, 0x43E0000000000000L) + ? X86GetScalar(context, 0x43E0000000000000L) : X86GetAllElements(context, 0x43E0000000000000L); nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1528,7 +1527,7 @@ namespace ARMeilleure.Instructions if (sizeF == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1538,7 +1537,7 @@ namespace ARMeilleure.Instructions int fpScaled = 0x3F800000 + fBits * 0x800000; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulps, nRes, fpScaledMask); @@ -1556,10 +1555,10 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand fpMaxValMask = scalar // 2.14748365E9f (2147483648) - ? X86GetScalar (context, 0x4F000000) + ? X86GetScalar(context, 0x4F000000) : X86GetAllElements(context, 0x4F000000); Operand nInt = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); @@ -1567,14 +1566,14 @@ namespace ARMeilleure.Instructions nRes = context.AddIntrinsic(Intrinsic.X86Subps, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nInt2 = context.AddIntrinsic(Intrinsic.X86Cvtps2dq, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpps, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); - Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes); - dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt); + Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nInt2, nRes); + dRes = context.AddIntrinsic(Intrinsic.X86Paddd, dRes, nInt); if (scalar) { @@ -1590,7 +1589,7 @@ namespace ARMeilleure.Instructions else /* if (sizeF == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (op is OpCodeSimdShImm fixedOp) { @@ -1600,7 +1599,7 @@ namespace ARMeilleure.Instructions long fpScaled = 0x3FF0000000000000L + fBits * 0x10000000000000L; Operand fpScaledMask = scalar - ? X86GetScalar (context, fpScaled) + ? X86GetScalar(context, fpScaled) : X86GetAllElements(context, fpScaled); nRes = context.AddIntrinsic(Intrinsic.X86Mulpd, nRes, fpScaledMask); @@ -1618,10 +1617,10 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand fpMaxValMask = scalar // 9.2233720368547760E18d (9223372036854775808) - ? X86GetScalar (context, 0x43E0000000000000L) + ? X86GetScalar(context, 0x43E0000000000000L) : X86GetAllElements(context, 0x43E0000000000000L); Operand nLong = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); @@ -1629,14 +1628,14 @@ namespace ARMeilleure.Instructions nRes = context.AddIntrinsic(Intrinsic.X86Subpd, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nLong2 = EmitSse2CvtDoubleToInt64OpF(context, nRes, scalar); nRes = context.AddIntrinsic(Intrinsic.X86Cmppd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); - Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes); - dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong); + Operand dRes = context.AddIntrinsic(Intrinsic.X86Pxor, nLong2, nRes); + dRes = context.AddIntrinsic(Intrinsic.X86Paddq, dRes, nLong); if (scalar) { @@ -1656,7 +1655,7 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1678,7 +1677,7 @@ namespace ARMeilleure.Instructions } Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); int fpMaxVal = op.RegisterSize == RegisterSize.Int32 @@ -1703,7 +1702,7 @@ namespace ARMeilleure.Instructions else /* if (op.Size == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1725,7 +1724,7 @@ namespace ARMeilleure.Instructions } Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); long fpMaxVal = op.RegisterSize == RegisterSize.Int32 @@ -1758,7 +1757,7 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1782,7 +1781,7 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); int fpMaxVal = op.RegisterSize == RegisterSize.Int32 ? 0x4F000000 // 2.14748365E9f (2147483648) @@ -1791,16 +1790,16 @@ namespace ARMeilleure.Instructions Operand fpMaxValMask = X86GetScalar(context, fpMaxVal); Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Subss, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtss2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtss2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtss2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpss, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1813,14 +1812,14 @@ namespace ARMeilleure.Instructions } Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nInt); - dRes = context.Add(dRes, nIntOrLong); + dRes = context.Add(dRes, nIntOrLong); SetIntOrZR(context, op.Rd, dRes); } else /* if (op.Size == 1) */ { Operand nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, n, n, Const((int)CmpCondition.OrderedQ)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, n); if (isFixed) { @@ -1844,7 +1843,7 @@ namespace ARMeilleure.Instructions Operand zero = context.VectorZero(); Operand nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); long fpMaxVal = op.RegisterSize == RegisterSize.Int32 ? 0x41E0000000000000L // 2147483648.0000000d (2147483648) @@ -1853,16 +1852,16 @@ namespace ARMeilleure.Instructions Operand fpMaxValMask = X86GetScalar(context, fpMaxVal); Operand nIntOrLong = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Subsd, nRes, fpMaxValMask); nCmp = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, zero, Const((int)CmpCondition.NotLessThanOrEqual)); - nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); + nRes = context.AddIntrinsic(Intrinsic.X86Pand, nRes, nCmp); Operand nIntOrLong2 = op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (Intrinsic.X86Cvtsd2si, nRes) + ? context.AddIntrinsicInt(Intrinsic.X86Cvtsd2si, nRes) : context.AddIntrinsicLong(Intrinsic.X86Cvtsd2si, nRes); nRes = context.AddIntrinsic(Intrinsic.X86Cmpsd, nRes, fpMaxValMask, Const((int)CmpCondition.NotLessThan)); @@ -1875,7 +1874,7 @@ namespace ARMeilleure.Instructions } Operand dRes = context.BitwiseExclusiveOr(nIntOrLong2, nLong); - dRes = context.Add(dRes, nIntOrLong); + dRes = context.Add(dRes, nIntOrLong); SetIntOrZR(context, op.Rd, dRes); } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs index bec36e2d6..dcdcc65de 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -217,33 +216,22 @@ namespace ARMeilleure.Instructions string name = nameof(Math.Round); MethodInfo info = (op.Size & 1) == 0 - ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); + ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) + : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); return context.Call(info, n, Const((int)roundMode)); } private static FPRoundingMode RMToRoundMode(int rm) { - FPRoundingMode roundMode; - switch (rm) + return rm switch { - case 0b00: - roundMode = FPRoundingMode.ToNearestAway; - break; - case 0b01: - roundMode = FPRoundingMode.ToNearest; - break; - case 0b10: - roundMode = FPRoundingMode.TowardsPlusInfinity; - break; - case 0b11: - roundMode = FPRoundingMode.TowardsMinusInfinity; - break; - default: - throw new ArgumentOutOfRangeException(nameof(rm)); - } - return roundMode; + 0b00 => FPRoundingMode.ToNearestAway, + 0b01 => FPRoundingMode.ToNearest, + 0b10 => FPRoundingMode.TowardsPlusInfinity, + 0b11 => FPRoundingMode.TowardsMinusInfinity, + _ => throw new ArgumentOutOfRangeException(nameof(rm)), + }; } // VCVTA/M/N/P (floating-point). @@ -270,22 +258,24 @@ namespace ARMeilleure.Instructions if (unsigned) { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtauGp, 0b01 => Intrinsic.Arm64FcvtnuGp, 0b10 => Intrinsic.Arm64FcvtpuGp, 0b11 => Intrinsic.Arm64FcvtmuGp, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } else { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtasGp, 0b01 => Intrinsic.Arm64FcvtnsGp, 0b10 => Intrinsic.Arm64FcvtpsGp, 0b11 => Intrinsic.Arm64FcvtmsGp, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } @@ -297,22 +287,24 @@ namespace ARMeilleure.Instructions { if (unsigned) { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtauS, 0b01 => Intrinsic.Arm64FcvtnuS, 0b10 => Intrinsic.Arm64FcvtpuS, 0b11 => Intrinsic.Arm64FcvtmuS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } else { - inst = rm switch { + inst = rm switch + { 0b00 => Intrinsic.Arm64FcvtasS, 0b01 => Intrinsic.Arm64FcvtnsS, 0b10 => Intrinsic.Arm64FcvtpsS, 0b11 => Intrinsic.Arm64FcvtmsS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; } @@ -432,12 +424,13 @@ namespace ARMeilleure.Instructions if (Optimizations.UseAdvSimd) { - Intrinsic inst = rm switch { + Intrinsic inst = rm switch + { 0b00 => Intrinsic.Arm64FrintaS, 0b01 => Intrinsic.Arm64FrintnS, 0b10 => Intrinsic.Arm64FrintpS, 0b11 => Intrinsic.Arm64FrintmS, - _ => throw new ArgumentOutOfRangeException(nameof(rm)) + _ => throw new InvalidOperationException($"{nameof(rm)} contains an invalid value: {rm}"), }; InstEmitSimdHelper32Arm64.EmitScalarUnaryOpF32(context, inst); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs index 4fb048eed..aee12d7dc 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHash.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHash.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { -#region "Sha1" + #region "Sha1" public static void Sha1c_V(ArmEmitterContext context) { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; @@ -89,9 +89,9 @@ namespace ARMeilleure.Instructions context.Copy(GetVec(op.Rd), res); } -#endregion + #endregion -#region "Sha256" + #region "Sha256" public static void Sha256h_V(ArmEmitterContext context) { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; @@ -142,6 +142,6 @@ namespace ARMeilleure.Instructions context.Copy(GetVec(op.Rd), res); } -#endregion + #endregion } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs index 51334608d..c2bb951ab 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHash32.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static partial class InstEmit32 { -#region "Sha256" + #region "Sha256" public static void Sha256h_V(ArmEmitterContext context) { OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; @@ -59,6 +59,6 @@ namespace ARMeilleure.Instructions context.Copy(GetVecA32(op.Qd), res); } -#endregion + #endregion } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs index 23e4948d9..a672b159f 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHashHelper.cs @@ -18,9 +18,9 @@ namespace ARMeilleure.Instructions Operand round2 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src1, src2, w); Operand round4 = context.AddIntrinsic(Intrinsic.X86Sha256Rnds2, src2, round2, w2); - + Operand res = context.AddIntrinsic(Intrinsic.X86Shufps, round4, round2, Const(part2 ? 0x11 : 0xbb)); - + return res; } @@ -53,4 +53,4 @@ namespace ARMeilleure.Instructions return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)), x, y, z); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs index c44c9b4d9..35052ad11 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs @@ -6,7 +6,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -18,19 +17,19 @@ namespace ARMeilleure.Instructions static class InstEmitSimdHelper { -#region "Masks" + #region "Masks" public static readonly long[] EvenMasks = new long[] { 14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B 13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H - 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S + 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0, // S }; public static readonly long[] OddMasks = new long[] { 15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B 15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H - 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S + 15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0, // S }; public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0; @@ -38,19 +37,19 @@ namespace ARMeilleure.Instructions public static ulong X86GetGf2p8LogicalShiftLeft(int shift) { ulong identity = (0b00000001UL << 56) | (0b00000010UL << 48) | (0b00000100UL << 40) | (0b00001000UL << 32) | - (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0); + (0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0); return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8); } -#endregion + #endregion -#region "X86 SSE Intrinsics" + #region "X86 SSE Intrinsics" public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[] { Intrinsic.X86Paddb, Intrinsic.X86Paddw, Intrinsic.X86Paddd, - Intrinsic.X86Paddq + Intrinsic.X86Paddq, }; public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[] @@ -58,7 +57,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Pcmpeqb, Intrinsic.X86Pcmpeqw, Intrinsic.X86Pcmpeqd, - Intrinsic.X86Pcmpeqq + Intrinsic.X86Pcmpeqq, }; public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[] @@ -66,49 +65,49 @@ namespace ARMeilleure.Instructions Intrinsic.X86Pcmpgtb, Intrinsic.X86Pcmpgtw, Intrinsic.X86Pcmpgtd, - Intrinsic.X86Pcmpgtq + Intrinsic.X86Pcmpgtq, }; public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[] { Intrinsic.X86Pmaxsb, Intrinsic.X86Pmaxsw, - Intrinsic.X86Pmaxsd + Intrinsic.X86Pmaxsd, }; public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[] { Intrinsic.X86Pmaxub, Intrinsic.X86Pmaxuw, - Intrinsic.X86Pmaxud + Intrinsic.X86Pmaxud, }; public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[] { Intrinsic.X86Pminsb, Intrinsic.X86Pminsw, - Intrinsic.X86Pminsd + Intrinsic.X86Pminsd, }; public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[] { Intrinsic.X86Pminub, Intrinsic.X86Pminuw, - Intrinsic.X86Pminud + Intrinsic.X86Pminud, }; public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[] { Intrinsic.X86Pmovsxbw, Intrinsic.X86Pmovsxwd, - Intrinsic.X86Pmovsxdq + Intrinsic.X86Pmovsxdq, }; public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[] { Intrinsic.X86Pmovzxbw, Intrinsic.X86Pmovzxwd, - Intrinsic.X86Pmovzxdq + Intrinsic.X86Pmovzxdq, }; public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[] @@ -116,14 +115,14 @@ namespace ARMeilleure.Instructions 0, Intrinsic.X86Psllw, Intrinsic.X86Pslld, - Intrinsic.X86Psllq + Intrinsic.X86Psllq, }; public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[] { 0, Intrinsic.X86Psraw, - Intrinsic.X86Psrad + Intrinsic.X86Psrad, }; public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[] @@ -131,7 +130,7 @@ namespace ARMeilleure.Instructions 0, Intrinsic.X86Psrlw, Intrinsic.X86Psrld, - Intrinsic.X86Psrlq + Intrinsic.X86Psrlq, }; public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[] @@ -139,7 +138,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Psubb, Intrinsic.X86Psubw, Intrinsic.X86Psubd, - Intrinsic.X86Psubq + Intrinsic.X86Psubq, }; public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[] @@ -147,7 +146,7 @@ namespace ARMeilleure.Instructions Intrinsic.X86Punpckhbw, Intrinsic.X86Punpckhwd, Intrinsic.X86Punpckhdq, - Intrinsic.X86Punpckhqdq + Intrinsic.X86Punpckhqdq, }; public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[] @@ -155,9 +154,9 @@ namespace ARMeilleure.Instructions Intrinsic.X86Punpcklbw, Intrinsic.X86Punpcklwd, Intrinsic.X86Punpckldq, - Intrinsic.X86Punpcklqdq + Intrinsic.X86Punpcklqdq, }; -#endregion + #endregion public static void EnterArmFpMode(EmitterContext context, Func getFpFlag) { @@ -310,15 +309,16 @@ namespace ARMeilleure.Instructions public static int X86GetRoundControl(FPRoundingMode roundMode) { - switch (roundMode) + return roundMode switch { - case FPRoundingMode.ToNearest: return 8 | 0; // even - case FPRoundingMode.TowardsPlusInfinity: return 8 | 2; - case FPRoundingMode.TowardsMinusInfinity: return 8 | 1; - case FPRoundingMode.TowardsZero: return 8 | 3; - } - - throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."); +#pragma warning disable IDE0055 // Disable formatting + FPRoundingMode.ToNearest => 8 | 0, // even + FPRoundingMode.TowardsPlusInfinity => 8 | 2, + FPRoundingMode.TowardsMinusInfinity => 8 | 1, + FPRoundingMode.TowardsZero => 8 | 3, + _ => throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."), +#pragma warning restore IDE0055 + }; } public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext context, Operand n, bool scalar) @@ -334,11 +334,11 @@ namespace ARMeilleure.Instructions if ((op.Size & 1) == 0) { Operand signMask = scalar ? X86GetScalar(context, int.MinValue) : X86GetAllElements(context, int.MinValue); - signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); + signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); // 0x3EFFFFFF == BitConverter.SingleToInt32Bits(0.5f) - 1 Operand valueMask = scalar ? X86GetScalar(context, 0x3EFFFFFF) : X86GetAllElements(context, 0x3EFFFFFF); - valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); + valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addss : Intrinsic.X86Addps, nCopy, valueMask); @@ -347,11 +347,11 @@ namespace ARMeilleure.Instructions else { Operand signMask = scalar ? X86GetScalar(context, long.MinValue) : X86GetAllElements(context, long.MinValue); - signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); + signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy); // 0x3FDFFFFFFFFFFFFFL == BitConverter.DoubleToInt64Bits(0.5d) - 1L Operand valueMask = scalar ? X86GetScalar(context, 0x3FDFFFFFFFFFFFFFL) : X86GetAllElements(context, 0x3FDFFFFFFFFFFFFFL); - valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); + valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask); nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addsd : Intrinsic.X86Addpd, nCopy, valueMask); @@ -461,7 +461,7 @@ namespace ARMeilleure.Instructions MethodInfo info = (op.Size & 1) == 0 ? typeof(MathF).GetMethod(name, new Type[] { typeof(float) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double) }); + : typeof(Math).GetMethod(name, new Type[] { typeof(double) }); return context.Call(info, n); } @@ -473,8 +473,8 @@ namespace ARMeilleure.Instructions string name = nameof(Math.Round); MethodInfo info = (op.Size & 1) == 0 - ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) - : typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); + ? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) }) + : typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) }); return context.Call(info, n, Const((int)roundMode)); } @@ -482,7 +482,7 @@ namespace ARMeilleure.Instructions public static Operand EmitGetRoundingMode(ArmEmitterContext context) { Operand rMode = context.ShiftLeft(GetFpFlag(FPState.RMode1Flag), Const(1)); - rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag)); + rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag)); return rMode; } @@ -1015,8 +1015,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed); - Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); + Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed); + Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1); } @@ -1077,9 +1077,9 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); - Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); - Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); + Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); + Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); + Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1); } @@ -1143,8 +1143,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { - Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); - Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); + Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed); + Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed); res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1); } @@ -1174,13 +1174,13 @@ namespace ARMeilleure.Instructions { int pairIndex = index << 1; - Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); + Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed); Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed); - Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed); + Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed); Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed); - res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size); + res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size); res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size); } @@ -1197,11 +1197,11 @@ namespace ARMeilleure.Instructions if (op.RegisterSize == RegisterSize.Simd64) { Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]); - Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]); + Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks[op.Size]); Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n - Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n + Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right)); @@ -1213,14 +1213,14 @@ namespace ARMeilleure.Instructions Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m - Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM); + Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM); Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM); context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right)); } else { - Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); + Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m); context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right)); @@ -1381,7 +1381,7 @@ namespace ARMeilleure.Instructions Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex); Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1); - res = context.VectorInsert(res, emit(n0, n1), index); + res = context.VectorInsert(res, emit(n0, n1), index); res = context.VectorInsert(res, emit(m0, m1), pairs + index); } @@ -1433,18 +1433,18 @@ namespace ARMeilleure.Instructions public enum CmpCondition { // Legacy Sse. - Equal = 0, // Ordered, non-signaling. - LessThan = 1, // Ordered, signaling. - LessThanOrEqual = 2, // Ordered, signaling. - UnorderedQ = 3, // Non-signaling. - NotLessThan = 5, // Unordered, signaling. + Equal = 0, // Ordered, non-signaling. + LessThan = 1, // Ordered, signaling. + LessThanOrEqual = 2, // Ordered, signaling. + UnorderedQ = 3, // Non-signaling. + NotLessThan = 5, // Unordered, signaling. NotLessThanOrEqual = 6, // Unordered, signaling. - OrderedQ = 7, // Non-signaling. + OrderedQ = 7, // Non-signaling. // Vex. GreaterThanOrEqual = 13, // Ordered, signaling. - GreaterThan = 14, // Ordered, signaling. - OrderedS = 23 // Signaling. + GreaterThan = 14, // Ordered, signaling. + OrderedS = 23, // Signaling. } [Flags] @@ -1459,7 +1459,7 @@ namespace ARMeilleure.Instructions Add = 1 << 3, Sub = 1 << 4, - Accumulate = 1 << 5 + Accumulate = 1 << 5, } public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit) @@ -1579,7 +1579,7 @@ namespace ARMeilleure.Instructions { Operand de; Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed); - Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed); + Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed); if (op.Size <= 2) { @@ -1627,7 +1627,7 @@ namespace ARMeilleure.Instructions [Flags] public enum SaturatingNarrowFlags { - Scalar = 1 << 0, + Scalar = 1 << 0, SignedSrc = 1 << 1, SignedDst = 1 << 2, @@ -1637,14 +1637,14 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags) { OpCodeSimd op = (OpCodeSimd)context.CurrOp; - bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0; @@ -2034,18 +2034,30 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: res = context.SignExtend8 (OperandType.I64, res); break; - case 1: res = context.SignExtend16(OperandType.I64, res); break; - case 2: res = context.SignExtend32(OperandType.I64, res); break; + case 0: + res = context.SignExtend8(OperandType.I64, res); + break; + case 1: + res = context.SignExtend16(OperandType.I64, res); + break; + case 2: + res = context.SignExtend32(OperandType.I64, res); + break; } } else { switch (size) { - case 0: res = context.ZeroExtend8 (OperandType.I64, res); break; - case 1: res = context.ZeroExtend16(OperandType.I64, res); break; - case 2: res = context.ZeroExtend32(OperandType.I64, res); break; + case 0: + res = context.ZeroExtend8(OperandType.I64, res); + break; + case 1: + res = context.ZeroExtend16(OperandType.I64, res); + break; + case 2: + res = context.ZeroExtend32(OperandType.I64, res); + break; } } @@ -2063,10 +2075,18 @@ namespace ARMeilleure.Instructions switch (size) { - case 0: vector = context.VectorInsert8 (vector, value, index); break; - case 1: vector = context.VectorInsert16(vector, value, index); break; - case 2: vector = context.VectorInsert (vector, value, index); break; - case 3: vector = context.VectorInsert (vector, value, index); break; + case 0: + vector = context.VectorInsert8(vector, value, index); + break; + case 1: + vector = context.VectorInsert16(vector, value, index); + break; + case 2: + vector = context.VectorInsert(vector, value, index); + break; + case 3: + vector = context.VectorInsert(vector, value, index); + break; } return vector; diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs index 36d27d425..c1c59b87b 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs @@ -4,7 +4,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -19,18 +18,13 @@ namespace ARMeilleure.Instructions { public static (int, int) GetQuadwordAndSubindex(int index, RegisterSize size) { - switch (size) + return size switch { - case RegisterSize.Simd128: - return (index >> 1, 0); - case RegisterSize.Simd64: - case RegisterSize.Int64: - return (index >> 1, index & 1); - case RegisterSize.Int32: - return (index >> 2, index & 3); - } - - throw new ArgumentException("Unrecognized Vector Register Size."); + RegisterSize.Simd128 => (index >> 1, 0), + RegisterSize.Simd64 or RegisterSize.Int64 => (index >> 1, index & 1), + RegisterSize.Int32 => (index >> 2, index & 3), + _ => throw new ArgumentException("Unrecognized Vector Register Size."), + }; } public static Operand ExtractScalar(ArmEmitterContext context, OperandType type, int reg) @@ -327,7 +321,7 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size + 1, signed); - Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); + Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); if (op.Size == 2) { @@ -380,8 +374,8 @@ namespace ARMeilleure.Instructions for (int index = 0; index < elems; index++) { Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size + 1, signed); - Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed); - Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); + Operand ne = EmitVectorExtract32(context, op.Qn, op.In + index, op.Size, signed); + Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed); if (op.Size == 2) { @@ -778,7 +772,10 @@ namespace ARMeilleure.Instructions { // Index into 0, 0 into index. This swap happens at the start of an A32 scalar op if required. int index = reg & (doubleWidth ? 1 : 3); - if (index == 0) return target; + if (index == 0) + { + return target; + } if (doubleWidth) { @@ -974,7 +971,7 @@ namespace ARMeilleure.Instructions Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32; - EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); + EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); } public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc) @@ -1195,7 +1192,7 @@ namespace ARMeilleure.Instructions : typeof(SoftFloat64).GetMethod(name); Array.Resize(ref callArgs, callArgs.Length + 1); - callArgs[callArgs.Length - 1] = Const(1); + callArgs[^1] = Const(1); context.ExitArmFpMode(); context.StoreToContext(); @@ -1245,16 +1242,24 @@ namespace ARMeilleure.Instructions { switch (size) { - case 0: res = context.SignExtend8(OperandType.I32, res); break; - case 1: res = context.SignExtend16(OperandType.I32, res); break; + case 0: + res = context.SignExtend8(OperandType.I32, res); + break; + case 1: + res = context.SignExtend16(OperandType.I32, res); + break; } } else { switch (size) { - case 0: res = context.ZeroExtend8(OperandType.I32, res); break; - case 1: res = context.ZeroExtend16(OperandType.I32, res); break; + case 0: + res = context.ZeroExtend8(OperandType.I32, res); + break; + case 1: + res = context.ZeroExtend16(OperandType.I32, res); + break; } } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs index 804d915c4..568c07122 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs @@ -1,11 +1,9 @@ - using ARMeilleure.Decoders; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -74,7 +72,10 @@ namespace ARMeilleure.Instructions public static Operand EmitExtractScalar(ArmEmitterContext context, Operand target, int reg, bool doubleWidth) { int index = reg & (doubleWidth ? 1 : 3); - if (index == 0) return target; // Element is already at index 0, so just return the vector directly. + if (index == 0) + { + return target; // Element is already at index 0, so just return the vector directly. + } if (doubleWidth) { @@ -249,7 +250,7 @@ namespace ARMeilleure.Instructions OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp; inst |= ((op.Size & 1) != 0 ? Intrinsic.Arm64VDouble : Intrinsic.Arm64VFloat) | Intrinsic.Arm64V128; - EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); + EmitScalarBinaryOpSimd32(context, (n, m) => context.AddIntrinsic(inst, n, m)); } public static void EmitScalarTernaryOpSimd32(ArmEmitterContext context, Func3I scalarFunc) @@ -336,16 +337,17 @@ namespace ARMeilleure.Instructions CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeVz, CmpCondition.LessThan => Intrinsic.Arm64FcmltVz, CmpCondition.LessThanOrEqual => Intrinsic.Arm64FcmleVz, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } - else { + else + { inst = cond switch { CmpCondition.Equal => Intrinsic.Arm64FcmeqV, CmpCondition.GreaterThan => Intrinsic.Arm64FcmgtV, CmpCondition.GreaterThanOrEqual => Intrinsic.Arm64FcmgeV, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } @@ -367,4 +369,4 @@ namespace ARMeilleure.Instructions } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs index f0d242ae2..70dfc0fbd 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelperArm64.cs @@ -50,7 +50,7 @@ namespace ARMeilleure.Instructions } SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (inst, n) + ? context.AddIntrinsicInt(inst, n) : context.AddIntrinsicLong(inst, n)); } @@ -288,7 +288,7 @@ namespace ARMeilleure.Instructions } SetIntOrZR(context, op.Rd, op.RegisterSize == RegisterSize.Int32 - ? context.AddIntrinsicInt (inst, n, Const(fBits)) + ? context.AddIntrinsicInt(inst, n, Const(fBits)) : context.AddIntrinsicLong(inst, n, Const(fBits))); } @@ -695,7 +695,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; + bool cmpWithZero = op is not OpCodeSimdFcond && op.Bit3; Intrinsic inst = signalNaNs ? Intrinsic.Arm64FcmpeS : Intrinsic.Arm64FcmpS; @@ -717,4 +717,4 @@ namespace ARMeilleure.Instructions SetFlag(context, PState.NFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const(31)), one)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs index 2bf531e6c..97e3da67e 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; using System.Diagnostics; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -80,10 +79,11 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; Operand d = GetVec(op.Rd); - Operand imm = eSize switch { + Operand imm = eSize switch + { 16 => X86GetAllElements(context, (short)~op.Immediate), 32 => X86GetAllElements(context, (int)~op.Immediate), - _ => throw new InvalidOperationException($"Invalid element size {eSize}.") + _ => throw new InvalidOperationException($"Invalid element size {eSize}."), }; Operand res = context.AddIntrinsic(Intrinsic.X86Pand, d, imm); @@ -380,10 +380,11 @@ namespace ARMeilleure.Instructions int eSize = 8 << op.Size; Operand d = GetVec(op.Rd); - Operand imm = eSize switch { + Operand imm = eSize switch + { 16 => X86GetAllElements(context, (short)op.Immediate), 32 => X86GetAllElements(context, (int)op.Immediate), - _ => throw new InvalidOperationException($"Invalid element size {eSize}.") + _ => throw new InvalidOperationException($"Invalid element size {eSize}."), }; Operand res = context.AddIntrinsic(Intrinsic.X86Por, d, imm); @@ -414,8 +415,8 @@ namespace ARMeilleure.Instructions (0b00010000L << 32) | (0b00001000L << 24) | (0b00000100L << 16) | - (0b00000010L << 8) | - (0b00000001L << 0); + (0b00000010L << 8) | + (0b00000001L << 0); Operand vBitMatrix = X86GetAllElements(context, bitMatrix); @@ -451,13 +452,13 @@ namespace ARMeilleure.Instructions Debug.Assert(op.Type == OperandType.I64); Operand val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op, Const(0xaaul)), Const(1)), - context.ShiftLeft (context.BitwiseAnd(op, Const(0x55ul)), Const(1))); + context.ShiftLeft(context.BitwiseAnd(op, Const(0x55ul)), Const(1))); val = context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(val, Const(0xccul)), Const(2)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x33ul)), Const(2))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x33ul)), Const(2))); return context.BitwiseOr(context.ShiftRightUI(val, Const(4)), - context.ShiftLeft (context.BitwiseAnd(val, Const(0x0ful)), Const(4))); + context.ShiftLeft(context.BitwiseAnd(val, Const(0x0ful)), Const(4))); } public static void Rev16_V(ArmEmitterContext context) diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs index 68ef4ed17..747acb101 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs @@ -52,9 +52,15 @@ namespace ARMeilleure.Instructions // Replicate fields to fill the 64-bits, if size is < 64-bits. switch (op.Size) { - case 0: immediate *= 0x0101010101010101L; break; - case 1: immediate *= 0x0001000100010001L; break; - case 2: immediate *= 0x0000000100000001L; break; + case 0: + immediate *= 0x0101010101010101L; + break; + case 1: + immediate *= 0x0001000100010001L; + break; + case 2: + immediate *= 0x0000000100000001L; + break; } Operand imm = Const(immediate); @@ -199,9 +205,15 @@ namespace ARMeilleure.Instructions // Replicate fields to fill the 64-bits, if size is < 64-bits. switch (op.Size) { - case 0: immediate *= 0x0101010101010101L; break; - case 1: immediate *= 0x0001000100010001L; break; - case 2: immediate *= 0x0000000100000001L; break; + case 0: + immediate *= 0x0101010101010101L; + break; + case 1: + immediate *= 0x0001000100010001L; + break; + case 2: + immediate *= 0x0000000100000001L; + break; } Operand imm = Const(immediate); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs index 9b19872af..dedf0fa05 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMemory.cs @@ -40,6 +40,7 @@ namespace ARMeilleure.Instructions long offset = 0; +#pragma warning disable IDE0055 // Disable formatting for (int rep = 0; rep < op.Reps; rep++) for (int elem = 0; elem < op.Elems; elem++) for (int sElem = 0; sElem < op.SElems; sElem++) @@ -66,6 +67,7 @@ namespace ARMeilleure.Instructions offset += 1 << op.Size; } +#pragma warning restore IDE0055 if (op.WBack) { @@ -157,4 +159,4 @@ namespace ARMeilleure.Instructions context.Copy(n, context.Add(n, m)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs index b58a32f69..85c98fe3a 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMove.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMove.cs @@ -3,7 +3,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System.Collections.Generic; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -12,19 +11,19 @@ namespace ARMeilleure.Instructions { static partial class InstEmit { -#region "Masks" + #region "Masks" private static readonly long[] _masksE0_Uzp = new long[] { 13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0, - 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0 + 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0, }; private static readonly long[] _masksE1_Uzp = new long[] { 15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0, - 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0 + 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0, }; -#endregion + #endregion public static void Dup_Gp(ArmEmitterContext context) { @@ -36,9 +35,17 @@ namespace ARMeilleure.Instructions { switch (op.Size) { - case 0: n = context.ZeroExtend8 (n.Type, n); n = context.Multiply(n, Const(n.Type, 0x01010101)); break; - case 1: n = context.ZeroExtend16(n.Type, n); n = context.Multiply(n, Const(n.Type, 0x00010001)); break; - case 2: n = context.ZeroExtend32(n.Type, n); break; + case 0: + n = context.ZeroExtend8(n.Type, n); + n = context.Multiply(n, Const(n.Type, 0x01010101)); + break; + case 1: + n = context.ZeroExtend16(n.Type, n); + n = context.Multiply(n, Const(n.Type, 0x00010001)); + break; + case 2: + n = context.ZeroExtend32(n.Type, n); + break; } Operand res = context.VectorInsert(context.VectorZero(), n, 0); @@ -209,7 +216,7 @@ namespace ARMeilleure.Instructions OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; Operand lblTrue = Label(); - Operand lblEnd = Label(); + Operand lblEnd = Label(); Operand isTrue = InstEmitFlowHelper.GetCondTrue(context, op.Cond); @@ -353,7 +360,7 @@ namespace ARMeilleure.Instructions { OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; - Operand d = GetVec(op.Rd); + Operand d = GetVec(op.Rd); Operand ne = EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size); context.Copy(d, EmitVectorInsert(context, d, ne, op.DstIndex, op.Size)); @@ -497,8 +504,12 @@ namespace ARMeilleure.Instructions switch (op.Size) { - case 0: imm *= 0x01010101; break; - case 1: imm *= 0x00010001; break; + case 0: + imm *= 0x01010101; + break; + case 1: + imm *= 0x00010001; + break; } if (not) @@ -543,7 +554,7 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, mask); - mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m); + mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, m); res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mMask); } @@ -557,7 +568,7 @@ namespace ARMeilleure.Instructions Operand mSubMask = context.AddIntrinsic(Intrinsic.X86Psubb, m, idxMask); Operand mMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, mSubMask, mask); - mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask); + mMask = context.AddIntrinsic(Intrinsic.X86Por, mMask, mSubMask); Operand res2 = context.AddIntrinsic(Intrinsic.X86Pshufb, ni, mMask); @@ -566,7 +577,7 @@ namespace ARMeilleure.Instructions if (!isTbl) { - Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L); + Operand idxMask = X86GetAllElements(context, (0x1010101010101010L * op.Size) - 0x0101010101010101L); Operand zeroMask = context.VectorZero(); Operand mPosMask = context.AddIntrinsic(Intrinsic.X86Pcmpgtb, m, idxMask); @@ -590,7 +601,7 @@ namespace ARMeilleure.Instructions { Operand d = GetVec(op.Rd); - List args = new List(); + List args = new(); if (!isTbl) { @@ -612,20 +623,36 @@ namespace ARMeilleure.Instructions { switch (op.Size) { - case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); break; - case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); break; - case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); break; - case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); break; + case 1: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)); + break; + case 2: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)); + break; + case 3: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)); + break; + case 4: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl4)); + break; } } else { switch (op.Size) { - case 1: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); break; - case 2: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); break; - case 3: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); break; - case 4: info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); break; + case 1: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx1)); + break; + case 2: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)); + break; + case 3: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)); + break; + case 4: + info = typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)); + break; } } @@ -644,7 +671,7 @@ namespace ARMeilleure.Instructions if (op.Size < 3) { long maskE0 = EvenMasks[op.Size]; - long maskE1 = OddMasks [op.Size]; + long maskE1 = OddMasks[op.Size]; mask = X86GetScalar(context, maskE0); @@ -691,7 +718,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, pairIndex + part, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, pairIndex + part, op.Size); - res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); + res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size); } @@ -712,7 +739,7 @@ namespace ARMeilleure.Instructions if (op.Size < 3) { long maskE0 = EvenMasks[op.Size]; - long maskE1 = OddMasks [op.Size]; + long maskE1 = OddMasks[op.Size]; mask = X86GetScalar(context, maskE0); @@ -784,7 +811,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, idx + part, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, idx + part, op.Size); - res = EmitVectorInsert(context, res, ne, index, op.Size); + res = EmitVectorInsert(context, res, ne, index, op.Size); res = EmitVectorInsert(context, res, me, pairs + index, op.Size); } @@ -839,7 +866,7 @@ namespace ARMeilleure.Instructions Operand ne = EmitVectorExtractZx(context, op.Rn, baseIndex + index, op.Size); Operand me = EmitVectorExtractZx(context, op.Rm, baseIndex + index, op.Size); - res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); + res = EmitVectorInsert(context, res, ne, pairIndex, op.Size); res = EmitVectorInsert(context, res, me, pairIndex + 1, op.Size); } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs index b8b91b31d..050d35e9d 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs @@ -2,7 +2,6 @@ using ARMeilleure.IntermediateRepresentation; using ARMeilleure.Translation; using System; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -17,13 +16,13 @@ namespace ARMeilleure.Instructions private static readonly long[] _masksE0_Uzp = new long[] { 13L << 56 | 09L << 48 | 05L << 40 | 01L << 32 | 12L << 24 | 08L << 16 | 04L << 8 | 00L << 0, - 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0 + 11L << 56 | 10L << 48 | 03L << 40 | 02L << 32 | 09L << 24 | 08L << 16 | 01L << 8 | 00L << 0, }; private static readonly long[] _masksE1_Uzp = new long[] { 15L << 56 | 11L << 48 | 07L << 40 | 03L << 32 | 14L << 24 | 10L << 16 | 06L << 8 | 02L << 0, - 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0 + 15L << 56 | 14L << 48 | 07L << 40 | 06L << 32 | 13L << 24 | 12L << 16 | 05L << 8 | 04L << 0, }; #endregion @@ -220,7 +219,7 @@ namespace ARMeilleure.Instructions for (int index = 1; index < length; index++) { int newVn = (op.Vn + index) & 0x1F; - (int qn, int ind) = GetQuadwordAndSubindex(newVn, op.RegisterSize); + (int qn, _) = GetQuadwordAndSubindex(newVn, op.RegisterSize); Operand ni = EmitMoveDoubleWordToSide(context, GetVecA32(qn), newVn, 0); Operand idxMask = X86GetAllElements(context, 0x0808080808080808L * index); diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs index 19e41119b..be0670645 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdShift.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdShift.cs @@ -6,7 +6,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -17,12 +16,12 @@ namespace ARMeilleure.Instructions static partial class InstEmit { -#region "Masks" + #region "Masks" private static readonly long[] _masks_SliSri = new long[] // Replication masks. { - 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L + 0x0101010101010101L, 0x0001000100010001L, 0x0000000100000001L, 0x0000000000000001L, }; -#endregion + #endregion public static void Rshrn_V(ArmEmitterContext context) { @@ -51,9 +50,15 @@ namespace ARMeilleure.Instructions switch (op.Size + 1) { - case 1: mask = X86GetAllElements(context, (int)roundConst * 0x00010001); break; - case 2: mask = X86GetAllElements(context, (int)roundConst); break; - case 3: mask = X86GetAllElements(context, roundConst); break; + case 1: + mask = X86GetAllElements(context, (int)roundConst * 0x00010001); + break; + case 2: + mask = X86GetAllElements(context, (int)roundConst); + break; + case 3: + mask = X86GetAllElements(context, roundConst); + break; } Intrinsic addInst = X86PaddInstruction[op.Size + 1]; @@ -1174,14 +1179,14 @@ namespace ARMeilleure.Instructions Scalar = 1 << 0, Signed = 1 << 1, - Round = 1 << 2, + Round = 1 << 2, Accumulate = 1 << 3, ScalarSx = Scalar | Signed, ScalarZx = Scalar, VectorSx = Signed, - VectorZx = 0 + VectorZx = 0, } private static void EmitScalarShrImmOpSx(ArmEmitterContext context, ShrImmFlags flags) @@ -1210,9 +1215,9 @@ namespace ARMeilleure.Instructions Operand res = context.VectorZero(); - bool scalar = (flags & ShrImmFlags.Scalar) != 0; - bool signed = (flags & ShrImmFlags.Signed) != 0; - bool round = (flags & ShrImmFlags.Round) != 0; + bool scalar = (flags & ShrImmFlags.Scalar) != 0; + bool signed = (flags & ShrImmFlags.Signed) != 0; + bool round = (flags & ShrImmFlags.Round) != 0; bool accumulate = (flags & ShrImmFlags.Accumulate) != 0; int shift = GetImmShr(op); @@ -1288,7 +1293,7 @@ namespace ARMeilleure.Instructions [Flags] private enum ShrImmSaturatingNarrowFlags { - Scalar = 1 << 0, + Scalar = 1 << 0, SignedSrc = 1 << 1, SignedDst = 1 << 2, @@ -1300,7 +1305,7 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags) @@ -1312,10 +1317,10 @@ namespace ARMeilleure.Instructions { OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0; - bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; + bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; int shift = GetImmShr(op); @@ -1585,7 +1590,7 @@ namespace ARMeilleure.Instructions Scalar = 1 << 0, Signed = 1 << 1, Round = 1 << 2, - Saturating = 1 << 3 + Saturating = 1 << 3, } private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None) diff --git a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs index 9ac680884..5c7d48287 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdShift32.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation; using System; using System.Diagnostics; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; @@ -291,7 +290,7 @@ namespace ARMeilleure.Instructions VectorSxSx = SignedSrc | SignedDst, VectorSxZx = SignedSrc, - VectorZxZx = 0 + VectorZxZx = 0, } private static void EmitRoundShrImmSaturatingNarrowOp(ArmEmitterContext context, ShrImmSaturatingNarrowFlags flags) @@ -303,10 +302,10 @@ namespace ARMeilleure.Instructions { OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp; - bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; + bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; bool signedDst = (flags & ShrImmSaturatingNarrowFlags.SignedDst) != 0; - bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; + bool round = (flags & ShrImmSaturatingNarrowFlags.Round) != 0; if (scalar) { diff --git a/src/ARMeilleure/Instructions/InstEmitSystem.cs b/src/ARMeilleure/Instructions/InstEmitSystem.cs index f84829aa1..8c430fc23 100644 --- a/src/ARMeilleure/Instructions/InstEmitSystem.cs +++ b/src/ARMeilleure/Instructions/InstEmitSystem.cs @@ -28,18 +28,39 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { - case 0b11_011_0000_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); break; - case 0b11_011_0000_0000_111: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); break; - case 0b11_011_0100_0010_000: EmitGetNzcv(context); return; - case 0b11_011_0100_0100_000: EmitGetFpcr(context); return; - case 0b11_011_0100_0100_001: EmitGetFpsr(context); return; - case 0b11_011_1101_0000_010: EmitGetTpidrEl0(context); return; - case 0b11_011_1101_0000_011: EmitGetTpidrroEl0(context); return; - case 0b11_011_1110_0000_000: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); break; - case 0b11_011_1110_0000_001: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break; - case 0b11_011_1110_0000_010: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); break; + case 0b11_011_0000_0000_001: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCtrEl0)); + break; + case 0b11_011_0000_0000_111: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetDczidEl0)); + break; + case 0b11_011_0100_0010_000: + EmitGetNzcv(context); + return; + case 0b11_011_0100_0100_000: + EmitGetFpcr(context); + return; + case 0b11_011_0100_0100_001: + EmitGetFpsr(context); + return; + case 0b11_011_1101_0000_010: + EmitGetTpidrEl0(context); + return; + case 0b11_011_1101_0000_011: + EmitGetTpidrroEl0(context); + return; + case 0b11_011_1110_0000_000: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntfrqEl0)); + break; + case 0b11_011_1110_0000_001: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); + break; + case 0b11_011_1110_0000_010: + info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntvctEl0)); + break; - default: throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); + default: + throw new NotImplementedException($"Unknown MRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); } SetIntOrZR(context, op.Rt, context.Call(info)); @@ -51,12 +72,21 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { - case 0b11_011_0100_0010_000: EmitSetNzcv(context); return; - case 0b11_011_0100_0100_000: EmitSetFpcr(context); return; - case 0b11_011_0100_0100_001: EmitSetFpsr(context); return; - case 0b11_011_1101_0000_010: EmitSetTpidrEl0(context); return; + case 0b11_011_0100_0010_000: + EmitSetNzcv(context); + return; + case 0b11_011_0100_0100_000: + EmitSetFpcr(context); + return; + case 0b11_011_0100_0100_001: + EmitSetFpsr(context); + return; + case 0b11_011_1101_0000_010: + EmitSetTpidrEl0(context); + return; - default: throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); + default: + throw new NotImplementedException($"Unknown MSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}."); } } @@ -75,20 +105,20 @@ namespace ARMeilleure.Instructions switch (GetPackedId(op)) { case 0b11_011_0111_0100_001: - { - // DC ZVA - Operand t = GetIntOrZR(context, op.Rt); - - for (long offset = 0; offset < DczSizeInBytes; offset += 8) { - Operand address = context.Add(t, Const(offset)); + // DC ZVA + Operand t = GetIntOrZR(context, op.Rt); - InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3); + for (long offset = 0; offset < DczSizeInBytes; offset += 8) + { + Operand address = context.Add(t, Const(offset)); + + InstEmitMemoryHelper.EmitStore(context, address, RegisterConsts.ZeroIndex, 3); + } + + break; } - break; - } - // No-op case 0b11_011_0111_1110_001: // DC CIVAC break; @@ -104,7 +134,7 @@ namespace ARMeilleure.Instructions { int id; - id = op.Op2 << 0; + id = op.Op2 << 0; id |= op.CRm << 3; id |= op.CRn << 7; id |= op.Op1 << 11; @@ -188,7 +218,7 @@ namespace ARMeilleure.Instructions OpCodeSystem op = (OpCodeSystem)context.CurrOp; Operand nzcv = GetIntOrZR(context, op.Rt); - nzcv = context.ConvertI64ToI32(nzcv); + nzcv = context.ConvertI64ToI32(nzcv); SetFlag(context, PState.VFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.VFlag)), Const(1))); SetFlag(context, PState.CFlag, context.BitwiseAnd(context.ShiftRightUI(nzcv, Const((int)PState.CFlag)), Const(1))); @@ -201,7 +231,7 @@ namespace ARMeilleure.Instructions OpCodeSystem op = (OpCodeSystem)context.CurrOp; Operand fpcr = GetIntOrZR(context, op.Rt); - fpcr = context.ConvertI64ToI32(fpcr); + fpcr = context.ConvertI64ToI32(fpcr); for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++) { @@ -221,7 +251,7 @@ namespace ARMeilleure.Instructions context.ClearQcFlagIfModified(); Operand fpsr = GetIntOrZR(context, op.Rt); - fpsr = context.ConvertI64ToI32(fpsr); + fpsr = context.ConvertI64ToI32(fpsr); for (int flag = 0; flag < RegisterConsts.FpFlagsCount; flag++) { diff --git a/src/ARMeilleure/Instructions/InstEmitSystem32.cs b/src/ARMeilleure/Instructions/InstEmitSystem32.cs index f2732c998..82e625715 100644 --- a/src/ARMeilleure/Instructions/InstEmitSystem32.cs +++ b/src/ARMeilleure/Instructions/InstEmitSystem32.cs @@ -4,7 +4,6 @@ using ARMeilleure.State; using ARMeilleure.Translation; using System; using System.Reflection; - using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -34,7 +33,8 @@ namespace ARMeilleure.Instructions switch (op.Opc2) { case 2: - EmitSetTpidrEl0(context); return; + EmitSetTpidrEl0(context); + return; default: throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); @@ -83,17 +83,13 @@ namespace ARMeilleure.Instructions throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); } - switch (op.Opc2) + result = op.Opc2 switch { - case 2: - result = EmitGetTpidrEl0(context); break; - - case 3: - result = EmitGetTpidrroEl0(context); break; - - default: - throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); - } + 2 => EmitGetTpidrEl0(context), + 3 => EmitGetTpidrroEl0(context), + _ => throw new NotImplementedException( + $"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."), + }; break; @@ -126,27 +122,16 @@ namespace ARMeilleure.Instructions } int opc = op.MrrcOp; - - MethodInfo info; - - switch (op.CRm) + MethodInfo info = op.CRm switch { - case 14: // Timer. - switch (opc) - { - case 0: - info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break; - - default: - throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."); - } - - break; - - default: - throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}."); - } - + // Timer. + 14 => opc switch + { + 0 => typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)), + _ => throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X})."), + }, + _ => throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}."), + }; Operand result = context.Call(info); SetIntA32(context, op.Rt, context.ConvertI64ToI32(result)); @@ -235,7 +220,8 @@ namespace ARMeilleure.Instructions case 0b0000: // FPSID throw new NotImplementedException("Supervisor Only"); case 0b0001: // FPSCR - EmitGetFpscr(context); return; + EmitGetFpscr(context); + return; case 0b0101: // MVFR2 throw new NotImplementedException("MVFR2"); case 0b0110: // MVFR1 @@ -258,7 +244,8 @@ namespace ARMeilleure.Instructions case 0b0000: // FPSID throw new NotImplementedException("Supervisor Only"); case 0b0001: // FPSCR - EmitSetFpscr(context); return; + EmitSetFpscr(context); + return; case 0b0101: // MVFR2 throw new NotImplementedException("MVFR2"); case 0b0110: // MVFR1 diff --git a/src/ARMeilleure/Instructions/NativeInterface.cs b/src/ARMeilleure/Instructions/NativeInterface.cs index 2c35387a6..d1b2e353c 100644 --- a/src/ARMeilleure/Instructions/NativeInterface.cs +++ b/src/ARMeilleure/Instructions/NativeInterface.cs @@ -64,12 +64,12 @@ namespace ARMeilleure.Instructions #region "System registers" public static ulong GetCtrEl0() { - return (ulong)GetContext().CtrEl0; + return GetContext().CtrEl0; } public static ulong GetDczidEl0() { - return (ulong)GetContext().DczidEl0; + return GetContext().DczidEl0; } public static ulong GetCntfrqEl0() @@ -192,4 +192,4 @@ namespace ARMeilleure.Instructions return Context.Memory; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Instructions/SoftFallback.cs b/src/ARMeilleure/Instructions/SoftFallback.cs index 06d76a67c..c4fe677bf 100644 --- a/src/ARMeilleure/Instructions/SoftFallback.cs +++ b/src/ARMeilleure/Instructions/SoftFallback.cs @@ -5,7 +5,7 @@ namespace ARMeilleure.Instructions { static class SoftFallback { -#region "ShrImm64" + #region "ShrImm64" public static long SignedShrImm64(long value, long roundConst, int shift) { if (roundConst == 0L) @@ -89,12 +89,15 @@ namespace ARMeilleure.Instructions } } } -#endregion + #endregion -#region "Saturation" + #region "Saturation" public static int SatF32ToS32(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= int.MaxValue ? int.MaxValue : value <= int.MinValue ? int.MinValue : (int)value; @@ -102,7 +105,10 @@ namespace ARMeilleure.Instructions public static long SatF32ToS64(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= long.MaxValue ? long.MaxValue : value <= long.MinValue ? long.MinValue : (long)value; @@ -110,7 +116,10 @@ namespace ARMeilleure.Instructions public static uint SatF32ToU32(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= uint.MaxValue ? uint.MaxValue : value <= uint.MinValue ? uint.MinValue : (uint)value; @@ -118,7 +127,10 @@ namespace ARMeilleure.Instructions public static ulong SatF32ToU64(float value) { - if (float.IsNaN(value)) return 0; + if (float.IsNaN(value)) + { + return 0; + } return value >= ulong.MaxValue ? ulong.MaxValue : value <= ulong.MinValue ? ulong.MinValue : (ulong)value; @@ -126,7 +138,10 @@ namespace ARMeilleure.Instructions public static int SatF64ToS32(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= int.MaxValue ? int.MaxValue : value <= int.MinValue ? int.MinValue : (int)value; @@ -134,7 +149,10 @@ namespace ARMeilleure.Instructions public static long SatF64ToS64(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= long.MaxValue ? long.MaxValue : value <= long.MinValue ? long.MinValue : (long)value; @@ -142,7 +160,10 @@ namespace ARMeilleure.Instructions public static uint SatF64ToU32(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= uint.MaxValue ? uint.MaxValue : value <= uint.MinValue ? uint.MinValue : (uint)value; @@ -150,14 +171,17 @@ namespace ARMeilleure.Instructions public static ulong SatF64ToU64(double value) { - if (double.IsNaN(value)) return 0; + if (double.IsNaN(value)) + { + return 0; + } return value >= ulong.MaxValue ? ulong.MaxValue : value <= ulong.MinValue ? ulong.MinValue : (ulong)value; } -#endregion + #endregion -#region "Count" + #region "Count" public static ulong CountLeadingSigns(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.). { value ^= value >> 1; @@ -197,9 +221,9 @@ namespace ARMeilleure.Instructions return (ulong)count; } -#endregion + #endregion -#region "Table" + #region "Table" public static V128 Tbl1(V128 vector, int bytes, V128 tb0) { return TblOrTbx(default, vector, bytes, tb0); @@ -270,21 +294,21 @@ namespace ARMeilleure.Instructions return new V128(res); } -#endregion + #endregion -#region "Crc32" - private const uint Crc32RevPoly = 0xedb88320; + #region "Crc32" + private const uint Crc32RevPoly = 0xedb88320; private const uint Crc32cRevPoly = 0x82f63b78; - public static uint Crc32b(uint crc, byte value) => Crc32 (crc, Crc32RevPoly, value); + public static uint Crc32b(uint crc, byte value) => Crc32(crc, Crc32RevPoly, value); public static uint Crc32h(uint crc, ushort value) => Crc32h(crc, Crc32RevPoly, value); - public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value); - public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value); + public static uint Crc32w(uint crc, uint value) => Crc32w(crc, Crc32RevPoly, value); + public static uint Crc32x(uint crc, ulong value) => Crc32x(crc, Crc32RevPoly, value); - public static uint Crc32cb(uint crc, byte value) => Crc32 (crc, Crc32cRevPoly, value); + public static uint Crc32cb(uint crc, byte value) => Crc32(crc, Crc32cRevPoly, value); public static uint Crc32ch(uint crc, ushort value) => Crc32h(crc, Crc32cRevPoly, value); - public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value); - public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value); + public static uint Crc32cw(uint crc, uint value) => Crc32w(crc, Crc32cRevPoly, value); + public static uint Crc32cx(uint crc, ulong value) => Crc32x(crc, Crc32cRevPoly, value); private static uint Crc32h(uint crc, uint poly, ushort val) { @@ -331,9 +355,9 @@ namespace ARMeilleure.Instructions return crc; } -#endregion + #endregion -#region "Aes" + #region "Aes" public static V128 Decrypt(V128 value, V128 roundKey) { return CryptoHelper.AesInvSubBytes(CryptoHelper.AesInvShiftRows(value ^ roundKey)); @@ -353,9 +377,9 @@ namespace ARMeilleure.Instructions { return CryptoHelper.AesMixColumns(value); } -#endregion + #endregion -#region "Sha1" + #region "Sha1" public static V128 HashChoose(V128 hash_abcd, uint hash_e, V128 wk) { for (int e = 0; e <= 3; e++) @@ -426,7 +450,7 @@ namespace ARMeilleure.Instructions ulong t2 = w4_7.Extract(0); ulong t1 = w0_3.Extract(1); - V128 result = new V128(t1, t2); + V128 result = new(t1, t2); return result ^ (w0_3 ^ w8_11); } @@ -472,9 +496,9 @@ namespace ARMeilleure.Instructions { return (value << count) | (value >> (32 - count)); } -#endregion + #endregion -#region "Sha256" + #region "Sha256" public static V128 HashLower(V128 hash_abcd, V128 hash_efgh, V128 wk) { return Sha256Hash(hash_abcd, hash_efgh, wk, part1: true); @@ -487,7 +511,7 @@ namespace ARMeilleure.Instructions public static V128 Sha256SchedulePart1(V128 w0_3, V128 w4_7) { - V128 result = new V128(); + V128 result = new(); for (int e = 0; e <= 3; e++) { @@ -505,7 +529,7 @@ namespace ARMeilleure.Instructions public static V128 Sha256SchedulePart2(V128 w0_3, V128 w8_11, V128 w12_15) { - V128 result = new V128(); + V128 result = new(); ulong t1 = w12_15.Extract(1); @@ -602,13 +626,13 @@ namespace ARMeilleure.Instructions ? (uint)(value & 0xFFFFFFFFUL) : (uint)(value >> 32); } -#endregion + #endregion public static V128 PolynomialMult64_128(ulong op1, ulong op2) { V128 result = V128.Zero; - V128 op2_128 = new V128(op2, 0); + V128 op2_128 = new(op2, 0); for (int i = 0; i < 64; i++) { diff --git a/src/ARMeilleure/Instructions/SoftFloat.cs b/src/ARMeilleure/Instructions/SoftFloat.cs index 4af73c6df..e8f44ce30 100644 --- a/src/ARMeilleure/Instructions/SoftFloat.cs +++ b/src/ARMeilleure/Instructions/SoftFloat.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Instructions { static SoftFloat() { - RecipEstimateTable = BuildRecipEstimateTable(); + RecipEstimateTable = BuildRecipEstimateTable(); RecipSqrtEstimateTable = BuildRecipSqrtEstimateTable(); } @@ -63,7 +63,7 @@ namespace ARMeilleure.Instructions while (src * (aux + 1u) * (aux + 1u) < (1u << 28)) { - aux = aux + 1u; + aux++; } uint dst = (aux + 1u) >> 1; @@ -133,8 +133,8 @@ namespace ARMeilleure.Instructions { sign = (~(uint)valueBits & 0x8000u) == 0u; - uint exp16 = ((uint)valueBits & 0x7C00u) >> 10; - uint frac16 = (uint)valueBits & 0x03FFu; + uint exp16 = ((uint)valueBits & 0x7C00u) >> 10; + uint frac16 = (uint)valueBits & 0x03FFu; double real; @@ -180,17 +180,17 @@ namespace ARMeilleure.Instructions const int e = 5; const int f = 10; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -229,22 +229,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -359,17 +359,17 @@ namespace ARMeilleure.Instructions const int e = 8; const int f = 23; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -415,22 +415,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -534,17 +534,17 @@ namespace ARMeilleure.Instructions const int e = 11; const int f = 52; - bool sign; + bool sign; double mantissa; if (real < 0d) { - sign = true; + sign = true; mantissa = -real; } else { - sign = false; + sign = false; mantissa = real; } @@ -590,22 +590,22 @@ namespace ARMeilleure.Instructions switch (context.Fpcr.GetRoundingMode()) { case FPRoundingMode.ToNearest: - roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); + roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; case FPRoundingMode.TowardsPlusInfinity: - roundUp = (error != 0d && !sign); + roundUp = (error != 0d && !sign); overflowToInf = !sign; break; case FPRoundingMode.TowardsMinusInfinity: - roundUp = (error != 0d && sign); + roundUp = (error != 0d && sign); overflowToInf = sign; break; case FPRoundingMode.TowardsZero: - roundUp = false; + roundUp = false; overflowToInf = false; break; @@ -728,8 +728,8 @@ namespace ARMeilleure.Instructions sign = (~valueBits & 0x80000000u) == 0u; - uint exp32 = (valueBits & 0x7F800000u) >> 23; - uint frac32 = valueBits & 0x007FFFFFu; + uint exp32 = (valueBits & 0x7F800000u) >> 23; + uint frac32 = valueBits & 0x007FFFFFu; double real; @@ -798,8 +798,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == !sign2) { @@ -840,8 +842,8 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.Fpcr; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr); int result; @@ -995,8 +997,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { @@ -1232,8 +1236,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1276,11 +1282,13 @@ namespace ARMeilleure.Instructions FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr; valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out uint addend, context, fpcr); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr); @@ -1293,10 +1301,11 @@ namespace ARMeilleure.Instructions if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FPType.Infinity; + bool zeroA = typeA == FPType.Zero; - bool signP = sign1 ^ sign2; - bool infP = inf1 || inf2; + bool signP = sign1 ^ sign2; + bool infP = inf1 || inf2; bool zeroP = zero1 || zero2; if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP)) @@ -1359,8 +1368,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1435,34 +1446,17 @@ namespace ARMeilleure.Instructions } else if (MathF.Abs(value) < MathF.Pow(2f, -128)) { - bool overflowToInf; - - switch (fpcr.GetRoundingMode()) + var overflowToInf = fpcr.GetRoundingMode() switch { - case FPRoundingMode.ToNearest: - overflowToInf = true; - break; - - case FPRoundingMode.TowardsPlusInfinity: - overflowToInf = !sign; - break; - - case FPRoundingMode.TowardsMinusInfinity: - overflowToInf = sign; - break; - - case FPRoundingMode.TowardsZero: - overflowToInf = false; - break; - - default: - throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."); - } - + FPRoundingMode.TowardsPlusInfinity => !sign, + FPRoundingMode.TowardsMinusInfinity => sign, + FPRoundingMode.TowardsZero => false, + _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."), + }; result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); SoftFloat.FPProcessException(FPException.Overflow, context, fpcr); - SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); + SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); } else if ((fpcr & FPCR.Fz) != 0 && (MathF.Abs(value) >= MathF.Pow(2f, 126))) { @@ -1518,15 +1512,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr); float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float product; @@ -1559,8 +1555,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1691,8 +1689,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -1733,15 +1733,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out uint op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out uint op2, context, fpcr); float result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; float product; @@ -1774,8 +1776,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1860,8 +1864,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -1958,7 +1964,7 @@ namespace ARMeilleure.Instructions { if ((valueBits & 0x007FFFFFu) == 0u || (fpcr & FPCR.Fz) != 0) { - type = FPType.Zero; + type = FPType.Zero; value = FPZero(sign); if ((valueBits & 0x007FFFFFu) != 0u) @@ -1979,7 +1985,7 @@ namespace ARMeilleure.Instructions } else { - type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN; + type = (~valueBits & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN; value = FPZero(sign); } } @@ -2153,8 +2159,8 @@ namespace ARMeilleure.Instructions sign = (~valueBits & 0x8000000000000000ul) == 0u; - ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52; - ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul; + ulong exp64 = (valueBits & 0x7FF0000000000000ul) >> 52; + ulong frac64 = valueBits & 0x000FFFFFFFFFFFFFul; double real; @@ -2223,8 +2229,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == !sign2) { @@ -2265,8 +2273,8 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.Fpcr; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out _, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out _, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out _, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out _, context, fpcr); int result; @@ -2420,8 +2428,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { @@ -2657,8 +2667,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -2701,11 +2713,13 @@ namespace ARMeilleure.Instructions FPCR fpcr = standardFpscr ? context.StandardFpcrValue : context.Fpcr; valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out ulong addend, context, fpcr); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, out bool done, context, fpcr); @@ -2718,10 +2732,11 @@ namespace ARMeilleure.Instructions if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FPType.Infinity; + bool zeroA = typeA == FPType.Zero; - bool signP = sign1 ^ sign2; - bool infP = inf1 || inf2; + bool signP = sign1 ^ sign2; + bool infP = inf1 || inf2; bool zeroP = zero1 || zero2; if ((inf1 && zero2) || (zero1 && inf2) || (infA && infP && signA != signP)) @@ -2784,8 +2799,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -2860,34 +2877,17 @@ namespace ARMeilleure.Instructions } else if (Math.Abs(value) < Math.Pow(2d, -1024)) { - bool overflowToInf; - - switch (fpcr.GetRoundingMode()) + var overflowToInf = fpcr.GetRoundingMode() switch { - case FPRoundingMode.ToNearest: - overflowToInf = true; - break; - - case FPRoundingMode.TowardsPlusInfinity: - overflowToInf = !sign; - break; - - case FPRoundingMode.TowardsMinusInfinity: - overflowToInf = sign; - break; - - case FPRoundingMode.TowardsZero: - overflowToInf = false; - break; - - default: - throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."); - } - + FPRoundingMode.TowardsPlusInfinity => !sign, + FPRoundingMode.TowardsMinusInfinity => sign, + FPRoundingMode.TowardsZero => false, + _ => throw new ArgumentException($"Invalid rounding mode \"{fpcr.GetRoundingMode()}\"."), + }; result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); SoftFloat.FPProcessException(FPException.Overflow, context, fpcr); - SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); + SoftFloat.FPProcessException(FPException.Inexact, context, fpcr); } else if ((fpcr & FPCR.Fz) != 0 && (Math.Abs(value) >= Math.Pow(2d, 1022))) { @@ -2943,15 +2943,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr); double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double product; @@ -2984,8 +2986,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -3116,8 +3120,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -3158,15 +3164,17 @@ namespace ARMeilleure.Instructions ExecutionContext context = NativeInterface.GetContext(); FPCR fpcr = context.StandardFpcrValue; - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1, context, fpcr); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2, context, fpcr); + value1 = value1.FPUnpack(out FPType type1, out _, out ulong op1, context, fpcr); + value2 = value2.FPUnpack(out FPType type2, out _, out ulong op2, context, fpcr); double result = FPProcessNaNs(type1, type2, op1, op2, out bool done, context, fpcr); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; double product; @@ -3199,8 +3207,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -3285,8 +3295,10 @@ namespace ARMeilleure.Instructions if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FPType.Infinity; + bool zero1 = type1 == FPType.Zero; + bool inf2 = type2 == FPType.Infinity; + bool zero2 = type2 == FPType.Zero; if (inf1 && inf2 && sign1 == sign2) { @@ -3383,7 +3395,7 @@ namespace ARMeilleure.Instructions { if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul || (fpcr & FPCR.Fz) != 0) { - type = FPType.Zero; + type = FPType.Zero; value = FPZero(sign); if ((valueBits & 0x000FFFFFFFFFFFFFul) != 0ul) @@ -3404,7 +3416,7 @@ namespace ARMeilleure.Instructions } else { - type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN; + type = (~valueBits & 0x0008000000000000ul) == 0ul ? FPType.QNaN : FPType.SNaN; value = FPZero(sign); } } diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs index 07bd8b672..810461d7c 100644 --- a/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs +++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlock.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.IntermediateRepresentation private int _succCount; private BasicBlock _succ0; - private BasicBlock _succ1; + private readonly BasicBlock _succ1; private HashSet _domFrontiers; public int Index { get; set; } @@ -27,10 +27,7 @@ namespace ARMeilleure.IntermediateRepresentation { get { - if (_domFrontiers == null) - { - _domFrontiers = new HashSet(); - } + _domFrontiers ??= new HashSet(); return _domFrontiers; } @@ -108,7 +105,7 @@ namespace ARMeilleure.IntermediateRepresentation oldBlock.Predecessors.Remove(this); block.Predecessors.Add(this); - + oldBlock = block; } @@ -156,4 +153,4 @@ namespace ARMeilleure.IntermediateRepresentation return base.GetHashCode(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs index 96cfee35a..74aaea6b1 100644 --- a/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs +++ b/src/ARMeilleure/IntermediateRepresentation/BasicBlockFrequency.cs @@ -3,6 +3,6 @@ enum BasicBlockFrequency { Default, - Cold + Cold, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs index 628ce1051..e3a68b49d 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Comparison.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Comparison.cs @@ -2,16 +2,16 @@ { enum Comparison { - Equal = 0, - NotEqual = 1, - Greater = 2, - LessOrEqual = 3, - GreaterUI = 4, - LessOrEqualUI = 5, - GreaterOrEqual = 6, - Less = 7, - GreaterOrEqualUI = 8, - LessUI = 9 + Equal = 0, + NotEqual = 1, + Greater = 2, + LessOrEqual = 3, + GreaterUI = 4, + LessOrEqualUI = 5, + GreaterOrEqual = 6, + Less = 7, + GreaterOrEqualUI = 8, + LessUI = 9, } static class ComparisonExtensions diff --git a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs index b55fe1dac..9bae8d1fb 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Instruction.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Instruction.cs @@ -67,6 +67,6 @@ namespace ARMeilleure.IntermediateRepresentation Phi, Spill, SpillArg, - StoreToContext + StoreToContext, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs index df5d39ae4..b9cab6674 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Intrinsic.cs @@ -1,8 +1,10 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace ARMeilleure.IntermediateRepresentation { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum Intrinsic : ushort { // X86 (SSE and AVX) @@ -634,6 +636,6 @@ namespace ARMeilleure.IntermediateRepresentation Arm64VByte = 0 << Arm64VSizeShift, Arm64VHWord = 1 << Arm64VSizeShift, Arm64VWord = 2 << Arm64VSizeShift, - Arm64VDWord = 3 << Arm64VSizeShift + Arm64VDWord = 3 << Arm64VSizeShift, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs index 07d2633b4..9b3df8ca4 100644 --- a/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs +++ b/src/ARMeilleure/IntermediateRepresentation/MemoryOperand.cs @@ -4,11 +4,11 @@ using System.Runtime.CompilerServices; namespace ARMeilleure.IntermediateRepresentation { - unsafe struct MemoryOperand + readonly unsafe struct MemoryOperand { private struct Data { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public byte Kind; public byte Type; #pragma warning restore CS0649 @@ -18,7 +18,7 @@ namespace ARMeilleure.IntermediateRepresentation public int Displacement; } - private Data* _data; + private readonly Data* _data; public MemoryOperand(Operand operand) { @@ -30,13 +30,13 @@ namespace ARMeilleure.IntermediateRepresentation public Operand BaseAddress { get => _data->BaseAddress; - set => _data->BaseAddress = value; + set => _data->BaseAddress = value; } public Operand Index { get => _data->Index; - set => _data->Index = value; + set => _data->Index = value; } public Multiplier Scale @@ -51,4 +51,4 @@ namespace ARMeilleure.IntermediateRepresentation set => _data->Displacement = value; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs index d6bc7d994..6bcdda014 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Multiplier.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.IntermediateRepresentation x2 = 1, x4 = 2, x8 = 3, - x16 = 4 + x16 = 4, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Operand.cs b/src/ARMeilleure/IntermediateRepresentation/Operand.cs index 9e8de3ba4..89aefacb1 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Operand.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Operand.cs @@ -27,25 +27,25 @@ namespace ARMeilleure.IntermediateRepresentation private Data* _data; - public OperandKind Kind + public readonly OperandKind Kind { get => (OperandKind)_data->Kind; private set => _data->Kind = (byte)value; } - public OperandType Type + public readonly OperandType Type { get => (OperandType)_data->Type; private set => _data->Type = (byte)value; } - public ulong Value + public readonly ulong Value { get => _data->Value; private set => _data->Value = value; } - public Symbol Symbol + public readonly Symbol Symbol { get { @@ -69,7 +69,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public ReadOnlySpan Assignments + public readonly ReadOnlySpan Assignments { get { @@ -79,7 +79,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public ReadOnlySpan Uses + public readonly ReadOnlySpan Uses { get { @@ -89,13 +89,13 @@ namespace ARMeilleure.IntermediateRepresentation } } - public int UsesCount => (int)_data->UsesCount; - public int AssignmentsCount => _data->AssignmentsCount; + public readonly int UsesCount => (int)_data->UsesCount; + public readonly int AssignmentsCount => _data->AssignmentsCount; - public bool Relocatable => Symbol.Type != SymbolType.None; + public readonly bool Relocatable => Symbol.Type != SymbolType.None; [MethodImpl(MethodImplOptions.AggressiveInlining)] - public Register GetRegister() + public readonly Register GetRegister() { Debug.Assert(Kind == OperandKind.Register); @@ -103,52 +103,52 @@ namespace ARMeilleure.IntermediateRepresentation } [MethodImpl(MethodImplOptions.AggressiveInlining)] - public MemoryOperand GetMemory() + public readonly MemoryOperand GetMemory() { Debug.Assert(Kind == OperandKind.Memory); return new MemoryOperand(this); } - public int GetLocalNumber() + public readonly int GetLocalNumber() { Debug.Assert(Kind == OperandKind.LocalVariable); return (int)Value; } - public byte AsByte() + public readonly byte AsByte() { return (byte)Value; } - public short AsInt16() + public readonly short AsInt16() { return (short)Value; } - public int AsInt32() + public readonly int AsInt32() { return (int)Value; } - public long AsInt64() + public readonly long AsInt64() { return (long)Value; } - public float AsFloat() + public readonly float AsFloat() { return BitConverter.Int32BitsToSingle((int)Value); } - public double AsDouble() + public readonly double AsDouble() { return BitConverter.Int64BitsToDouble((long)Value); } [MethodImpl(MethodImplOptions.AggressiveInlining)] - internal ref ulong GetValueUnsafe() + internal readonly ref ulong GetValueUnsafe() { return ref _data->Value; } @@ -163,7 +163,7 @@ namespace ARMeilleure.IntermediateRepresentation Value = (ulong)number; } - public void AddAssignment(Operation operation) + public readonly void AddAssignment(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -187,7 +187,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void RemoveAssignment(Operation operation) + public readonly void RemoveAssignment(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -211,7 +211,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void AddUse(Operation operation) + public readonly void AddUse(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -235,7 +235,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void RemoveUse(Operation operation) + public readonly void RemoveUse(Operation operation) { if (Kind == OperandKind.LocalVariable) { @@ -259,7 +259,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public Span GetUses(ref Span buffer) + public readonly Span GetUses(ref Span buffer) { ReadOnlySpan uses = Uses; @@ -270,7 +270,7 @@ namespace ARMeilleure.IntermediateRepresentation uses.CopyTo(buffer); - return buffer.Slice(0, uses.Length); + return buffer[..uses.Length]; } private static void New(ref T* data, ref ushort count, ref ushort capacity, ushort initialCapacity) where T : unmanaged @@ -360,7 +360,7 @@ namespace ARMeilleure.IntermediateRepresentation { if (i + 1 < count) { - span.Slice(i + 1).CopyTo(span.Slice(i)); + span[(i + 1)..].CopyTo(span[i..]); } count--; @@ -380,7 +380,7 @@ namespace ARMeilleure.IntermediateRepresentation { if (i + 1 < count) { - span.Slice(i + 1).CopyTo(span.Slice(i)); + span[(i + 1)..].CopyTo(span[i..]); } count--; @@ -390,17 +390,17 @@ namespace ARMeilleure.IntermediateRepresentation } } - public override int GetHashCode() + public readonly override int GetHashCode() { return ((ulong)_data).GetHashCode(); } - public bool Equals(Operand operand) + public readonly bool Equals(Operand operand) { return operand._data == _data; } - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is Operand operand && Equals(operand); } @@ -453,8 +453,10 @@ namespace ARMeilleure.IntermediateRepresentation // Look in the next InternTableProbeLength slots for a match. for (uint i = 0; i < InternTableProbeLength; i++) { - Operand interned = new(); - interned._data = &InternTable[(hash + i) % InternTableSize]; + Operand interned = new() + { + _data = &InternTable[(hash + i) % InternTableSize], + }; // If slot matches the allocation request then return that slot. if (interned.Kind == kind && interned.Type == type && interned.Value == value && interned.Symbol == symbol) @@ -479,11 +481,13 @@ namespace ARMeilleure.IntermediateRepresentation *data = default; - Operand result = new(); - result._data = data; - result.Value = value; - result.Kind = kind; - result.Type = type; + Operand result = new() + { + _data = data, + Value = value, + Kind = kind, + Type = type, + }; if (kind != OperandKind.Memory) { @@ -591,4 +595,4 @@ namespace ARMeilleure.IntermediateRepresentation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs index adb835614..2b973f006 100644 --- a/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs +++ b/src/ARMeilleure/IntermediateRepresentation/OperandKind.cs @@ -8,6 +8,6 @@ namespace ARMeilleure.IntermediateRepresentation LocalVariable, Memory, Register, - Undefined + Undefined, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs index 81b22cf56..67ebdcde4 100644 --- a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs +++ b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.IntermediateRepresentation I64, FP32, FP64, - V128 + V128, } static class OperandTypeExtensions @@ -22,44 +22,41 @@ namespace ARMeilleure.IntermediateRepresentation public static RegisterType ToRegisterType(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return RegisterType.Vector; - case OperandType.FP64: return RegisterType.Vector; - case OperandType.I32: return RegisterType.Integer; - case OperandType.I64: return RegisterType.Integer; - case OperandType.V128: return RegisterType.Vector; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => RegisterType.Vector, + OperandType.FP64 => RegisterType.Vector, + OperandType.I32 => RegisterType.Integer, + OperandType.I64 => RegisterType.Integer, + OperandType.V128 => RegisterType.Vector, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } public static int GetSizeInBytes(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return 4; - case OperandType.FP64: return 8; - case OperandType.I32: return 4; - case OperandType.I64: return 8; - case OperandType.V128: return 16; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => 4, + OperandType.FP64 => 8, + OperandType.I32 => 4, + OperandType.I64 => 8, + OperandType.V128 => 16, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } public static int GetSizeInBytesLog2(this OperandType type) { - switch (type) + return type switch { - case OperandType.FP32: return 2; - case OperandType.FP64: return 3; - case OperandType.I32: return 2; - case OperandType.I64: return 3; - case OperandType.V128: return 4; - } - - throw new InvalidOperationException($"Invalid operand type \"{type}\"."); + OperandType.FP32 => 2, + OperandType.FP64 => 3, + OperandType.I32 => 2, + OperandType.I64 => 3, + OperandType.V128 => 4, + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + }; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Operation.cs b/src/ARMeilleure/IntermediateRepresentation/Operation.cs index c71e143c3..bc3a71b31 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Operation.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Operation.cs @@ -20,60 +20,60 @@ namespace ARMeilleure.IntermediateRepresentation private Data* _data; - public Instruction Instruction + public readonly Instruction Instruction { get => (Instruction)_data->Instruction; private set => _data->Instruction = (ushort)value; } - public Intrinsic Intrinsic + public readonly Intrinsic Intrinsic { get => (Intrinsic)_data->Intrinsic; private set => _data->Intrinsic = (ushort)value; } - public Operation ListPrevious + public readonly Operation ListPrevious { get => _data->ListPrevious; set => _data->ListPrevious = value; } - public Operation ListNext + public readonly Operation ListNext { get => _data->ListNext; set => _data->ListNext = value; } - public Operand Destination + public readonly Operand Destination { get => _data->DestinationsCount != 0 ? GetDestination(0) : default; set => SetDestination(value); } - public int DestinationsCount => _data->DestinationsCount; - public int SourcesCount => _data->SourcesCount; + public readonly int DestinationsCount => _data->DestinationsCount; + public readonly int SourcesCount => _data->SourcesCount; - internal Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount); - internal Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount); + internal readonly Span DestinationsUnsafe => new(_data->Destinations, _data->DestinationsCount); + internal readonly Span SourcesUnsafe => new(_data->Sources, _data->SourcesCount); - public PhiOperation AsPhi() + public readonly PhiOperation AsPhi() { Debug.Assert(Instruction == Instruction.Phi); return new PhiOperation(this); } - public Operand GetDestination(int index) + public readonly Operand GetDestination(int index) { return DestinationsUnsafe[index]; } - public Operand GetSource(int index) + public readonly Operand GetSource(int index) { return SourcesUnsafe[index]; } - public void SetDestination(int index, Operand dest) + public readonly void SetDestination(int index, Operand dest) { ref Operand curDest = ref DestinationsUnsafe[index]; @@ -83,7 +83,7 @@ namespace ARMeilleure.IntermediateRepresentation curDest = dest; } - public void SetSource(int index, Operand src) + public readonly void SetSource(int index, Operand src) { ref Operand curSrc = ref SourcesUnsafe[index]; @@ -93,7 +93,7 @@ namespace ARMeilleure.IntermediateRepresentation curSrc = src; } - private void RemoveOldDestinations() + private readonly void RemoveOldDestinations() { for (int i = 0; i < _data->DestinationsCount; i++) { @@ -101,7 +101,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetDestination(Operand dest) + public readonly void SetDestination(Operand dest) { RemoveOldDestinations(); @@ -119,7 +119,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetDestinations(Operand[] dests) + public readonly void SetDestinations(Operand[] dests) { RemoveOldDestinations(); @@ -135,7 +135,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveOldSources() + private readonly void RemoveOldSources() { for (int index = 0; index < _data->SourcesCount; index++) { @@ -143,7 +143,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetSource(Operand src) + public readonly void SetSource(Operand src) { RemoveOldSources(); @@ -161,7 +161,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - public void SetSources(Operand[] srcs) + public readonly void SetSources(Operand[] srcs) { RemoveOldSources(); @@ -184,7 +184,7 @@ namespace ARMeilleure.IntermediateRepresentation SetSource(source); } - private void AddAssignment(Operand op) + private readonly void AddAssignment(Operand op) { if (op != default) { @@ -192,7 +192,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveAssignment(Operand op) + private readonly void RemoveAssignment(Operand op) { if (op != default) { @@ -200,7 +200,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void AddUse(Operand op) + private readonly void AddUse(Operand op) { if (op != default) { @@ -208,7 +208,7 @@ namespace ARMeilleure.IntermediateRepresentation } } - private void RemoveUse(Operand op) + private readonly void RemoveUse(Operand op) { if (op != default) { @@ -216,17 +216,17 @@ namespace ARMeilleure.IntermediateRepresentation } } - public bool Equals(Operation operation) + public readonly bool Equals(Operation operation) { return operation._data == _data; } - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is Operation operation && Equals(operation); } - public override int GetHashCode() + public readonly override int GetHashCode() { return HashCode.Combine((IntPtr)_data); } @@ -267,9 +267,11 @@ namespace ARMeilleure.IntermediateRepresentation Data* data = Allocators.Operations.Allocate(); *data = default; - Operation result = new(); - result._data = data; - result.Instruction = inst; + Operation result = new() + { + _data = data, + Instruction = inst, + }; EnsureCapacity(ref result._data->Destinations, ref result._data->DestinationsCount, destCount); EnsureCapacity(ref result._data->Sources, ref result._data->SourcesCount, srcCount); @@ -373,4 +375,4 @@ namespace ARMeilleure.IntermediateRepresentation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/Register.cs b/src/ARMeilleure/IntermediateRepresentation/Register.cs index 241e4d13d..208f94be1 100644 --- a/src/ARMeilleure/IntermediateRepresentation/Register.cs +++ b/src/ARMeilleure/IntermediateRepresentation/Register.cs @@ -11,7 +11,7 @@ namespace ARMeilleure.IntermediateRepresentation public Register(int index, RegisterType type) { Index = index; - Type = type; + Type = type; } public override int GetHashCode() @@ -37,7 +37,7 @@ namespace ARMeilleure.IntermediateRepresentation public bool Equals(Register other) { return other.Index == Index && - other.Type == Type; + other.Type == Type; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs index 88ac6c124..2b4c9068c 100644 --- a/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs +++ b/src/ARMeilleure/IntermediateRepresentation/RegisterType.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.IntermediateRepresentation Integer, Vector, Flag, - FpFlag + FpFlag, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/IJitMemoryBlock.cs b/src/ARMeilleure/Memory/IJitMemoryBlock.cs index 9b11e07ff..e94b0a60d 100644 --- a/src/ARMeilleure/Memory/IJitMemoryBlock.cs +++ b/src/ARMeilleure/Memory/IJitMemoryBlock.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Memory void MapAsRx(ulong offset, ulong size); void MapAsRwx(ulong offset, ulong size); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/IMemoryManager.cs b/src/ARMeilleure/Memory/IMemoryManager.cs index 5eb1fadd6..ec5b81ebe 100644 --- a/src/ARMeilleure/Memory/IMemoryManager.cs +++ b/src/ARMeilleure/Memory/IMemoryManager.cs @@ -74,4 +74,4 @@ namespace ARMeilleure.Memory /// Optional ID of the handles that should not be signalled void SignalMemoryTracking(ulong va, ulong size, bool write, bool precise = false, int? exemptId = null); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Memory/MemoryManagerType.cs b/src/ARMeilleure/Memory/MemoryManagerType.cs index ce84ccaf3..e897a038f 100644 --- a/src/ARMeilleure/Memory/MemoryManagerType.cs +++ b/src/ARMeilleure/Memory/MemoryManagerType.cs @@ -28,7 +28,7 @@ /// Same as the host mapped memory manager type, but without masking the address within the address space. /// Allows invalid access from JIT code to the rest of the program, but is faster. /// - HostMappedUnsafe + HostMappedUnsafe, } static class MemoryManagerTypeExtensions diff --git a/src/ARMeilleure/Native/JitSupportDarwin.cs b/src/ARMeilleure/Native/JitSupportDarwin.cs index 7d6a8634a..ed347b9cf 100644 --- a/src/ARMeilleure/Native/JitSupportDarwin.cs +++ b/src/ARMeilleure/Native/JitSupportDarwin.cs @@ -5,7 +5,7 @@ using System.Runtime.Versioning; namespace ARMeilleure.Native { [SupportedOSPlatform("macos")] - public static partial class JitSupportDarwin + internal static partial class JitSupportDarwin { [LibraryImport("libarmeilleure-jitsupport", EntryPoint = "armeilleure_jit_memcpy")] public static partial void Copy(IntPtr dst, IntPtr src, ulong n); diff --git a/src/ARMeilleure/Optimizations.cs b/src/ARMeilleure/Optimizations.cs index 13348cec2..8fe478e47 100644 --- a/src/ARMeilleure/Optimizations.cs +++ b/src/ARMeilleure/Optimizations.cs @@ -1,5 +1,3 @@ -using System.Runtime.Intrinsics.Arm; - namespace ARMeilleure { using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities; @@ -9,31 +7,31 @@ namespace ARMeilleure { public static bool FastFP { get; set; } = true; - public static bool AllowLcqInFunctionTable { get; set; } = true; + public static bool AllowLcqInFunctionTable { get; set; } = true; public static bool UseUnmanagedDispatchLoop { get; set; } = true; - public static bool UseAdvSimdIfAvailable { get; set; } = true; - public static bool UseArm64AesIfAvailable { get; set; } = true; + public static bool UseAdvSimdIfAvailable { get; set; } = true; + public static bool UseArm64AesIfAvailable { get; set; } = true; public static bool UseArm64PmullIfAvailable { get; set; } = true; - public static bool UseSseIfAvailable { get; set; } = true; - public static bool UseSse2IfAvailable { get; set; } = true; - public static bool UseSse3IfAvailable { get; set; } = true; - public static bool UseSsse3IfAvailable { get; set; } = true; - public static bool UseSse41IfAvailable { get; set; } = true; - public static bool UseSse42IfAvailable { get; set; } = true; - public static bool UsePopCntIfAvailable { get; set; } = true; - public static bool UseAvxIfAvailable { get; set; } = true; - public static bool UseAvx512FIfAvailable { get; set; } = true; - public static bool UseAvx512VlIfAvailable { get; set; } = true; - public static bool UseAvx512BwIfAvailable { get; set; } = true; - public static bool UseAvx512DqIfAvailable { get; set; } = true; - public static bool UseF16cIfAvailable { get; set; } = true; - public static bool UseFmaIfAvailable { get; set; } = true; - public static bool UseAesniIfAvailable { get; set; } = true; + public static bool UseSseIfAvailable { get; set; } = true; + public static bool UseSse2IfAvailable { get; set; } = true; + public static bool UseSse3IfAvailable { get; set; } = true; + public static bool UseSsse3IfAvailable { get; set; } = true; + public static bool UseSse41IfAvailable { get; set; } = true; + public static bool UseSse42IfAvailable { get; set; } = true; + public static bool UsePopCntIfAvailable { get; set; } = true; + public static bool UseAvxIfAvailable { get; set; } = true; + public static bool UseAvx512FIfAvailable { get; set; } = true; + public static bool UseAvx512VlIfAvailable { get; set; } = true; + public static bool UseAvx512BwIfAvailable { get; set; } = true; + public static bool UseAvx512DqIfAvailable { get; set; } = true; + public static bool UseF16cIfAvailable { get; set; } = true; + public static bool UseFmaIfAvailable { get; set; } = true; + public static bool UseAesniIfAvailable { get; set; } = true; public static bool UsePclmulqdqIfAvailable { get; set; } = true; - public static bool UseShaIfAvailable { get; set; } = true; - public static bool UseGfniIfAvailable { get; set; } = true; + public static bool UseShaIfAvailable { get; set; } = true; + public static bool UseGfniIfAvailable { get; set; } = true; public static bool ForceLegacySse { @@ -41,6 +39,7 @@ namespace ARMeilleure set => X86HardwareCapabilities.ForceLegacySse = value; } +#pragma warning disable IDE0055 // Disable formatting internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd; internal static bool UseArm64Aes => UseArm64AesIfAvailable && Arm64HardwareCapabilities.SupportsAes; internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull; @@ -63,6 +62,7 @@ namespace ARMeilleure internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && X86HardwareCapabilities.SupportsPclmulqdq; internal static bool UseSha => UseShaIfAvailable && X86HardwareCapabilities.SupportsSha; internal static bool UseGfni => UseGfniIfAvailable && X86HardwareCapabilities.SupportsGfni; +#pragma warning restore IDE0055 internal static bool UseAvx512Ortho => UseAvx512F && UseAvx512Vl; internal static bool UseAvx512OrthoFloat => UseAvx512Ortho && UseAvx512Dq; diff --git a/src/ARMeilleure/Signal/NativeSignalHandler.cs b/src/ARMeilleure/Signal/NativeSignalHandler.cs index 5da0c7726..ed284677d 100644 --- a/src/ARMeilleure/Signal/NativeSignalHandler.cs +++ b/src/ARMeilleure/Signal/NativeSignalHandler.cs @@ -74,7 +74,7 @@ namespace ARMeilleure.Signal private static ulong _pageSize; private static ulong _pageMask; - private static IntPtr _handlerConfig; + private static readonly IntPtr _handlerConfig; private static IntPtr _signalHandlerPtr; private static IntPtr _signalHandlerHandle; @@ -96,11 +96,17 @@ namespace ARMeilleure.Signal public static void InitializeSignalHandler(ulong pageSize, Func customSignalHandlerFactory = null) { - if (_initialized) return; + if (_initialized) + { + return; + } lock (_lock) { - if (_initialized) return; + if (_initialized) + { + return; + } _pageSize = pageSize; _pageMask = pageSize - 1; @@ -284,7 +290,7 @@ namespace ARMeilleure.Signal const ulong auxOffset = 464; // uc_mcontext.__reserved const uint esrMagic = 0x45535201; - context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset))); + context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset))); context.MarkLabel(loopLabel); @@ -319,7 +325,7 @@ namespace ARMeilleure.Signal private static UnixExceptionHandler GenerateUnixSignalHandler(IntPtr signalStructPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // (int sig, SigInfo* sigInfo, void* ucontext) Operand sigInfoPtr = context.LoadArgument(OperandType.I64, 1); @@ -367,7 +373,7 @@ namespace ARMeilleure.Signal private static VectoredExceptionHandler GenerateWindowsSignalHandler(IntPtr signalStructPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // (ExceptionPointers* exceptionInfo) Operand exceptionInfoPtr = context.LoadArgument(OperandType.I64, 0); diff --git a/src/ARMeilleure/Signal/TestMethods.cs b/src/ARMeilleure/Signal/TestMethods.cs index e2ecad242..ec228c850 100644 --- a/src/ARMeilleure/Signal/TestMethods.cs +++ b/src/ARMeilleure/Signal/TestMethods.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Signal public static DebugPartialUnmap GenerateDebugPartialUnmap() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); var result = WindowsPartialUnmapHandler.EmitRetryFromAccessViolation(context); @@ -37,7 +37,7 @@ namespace ARMeilleure.Signal public static DebugThreadLocalMapGetOrReserve GenerateDebugThreadLocalMapGetOrReserve(IntPtr structPtr) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); var result = WindowsPartialUnmapHandler.EmitThreadLocalMapIntGetOrReserve(context, structPtr, context.LoadArgument(OperandType.I32, 0), context.LoadArgument(OperandType.I32, 1)); @@ -54,7 +54,7 @@ namespace ARMeilleure.Signal public static DebugNativeWriteLoop GenerateDebugNativeWriteLoop() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); // Loop a write to the target address until "running" is false. diff --git a/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs b/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs index 22009240b..79a8f803d 100644 --- a/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs +++ b/src/ARMeilleure/Signal/UnixSignalHandlerRegistration.cs @@ -47,10 +47,10 @@ namespace ARMeilleure.Signal public static SigAction RegisterExceptionHandler(IntPtr action) { - SigAction sig = new SigAction + SigAction sig = new() { sa_handler = action, - sa_flags = SA_SIGINFO + sa_flags = SA_SIGINFO, }; sigemptyset(ref sig.sa_mask); diff --git a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs index 941e36e58..4da1b32dc 100644 --- a/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs +++ b/src/ARMeilleure/Signal/WindowsPartialUnmapHandler.cs @@ -137,6 +137,7 @@ namespace ARMeilleure.Signal return context.Add(structsPtr, context.SignExtend32(OperandType.I64, offset)); } +#pragma warning disable IDE0051 // Remove unused private member private static void EmitThreadLocalMapIntRelease(EmitterContext context, IntPtr threadLocalMapPtr, Operand threadId, Operand index) { Operand offset = context.Multiply(index, Const(sizeof(int))); @@ -145,6 +146,7 @@ namespace ARMeilleure.Signal context.CompareAndSwap(idPtr, threadId, Const(0)); } +#pragma warning restore IDE0051 private static void EmitAtomicAddI32(EmitterContext context, Operand ptr, Operand additive) { diff --git a/src/ARMeilleure/State/Aarch32Mode.cs b/src/ARMeilleure/State/Aarch32Mode.cs index 395e288aa..add1cd26f 100644 --- a/src/ARMeilleure/State/Aarch32Mode.cs +++ b/src/ARMeilleure/State/Aarch32Mode.cs @@ -2,14 +2,14 @@ namespace ARMeilleure.State { enum Aarch32Mode { - User = 0b10000, - Fiq = 0b10001, - Irq = 0b10010, + User = 0b10000, + Fiq = 0b10001, + Irq = 0b10010, Supervisor = 0b10011, - Monitor = 0b10110, - Abort = 0b10111, + Monitor = 0b10110, + Abort = 0b10111, Hypervisor = 0b11010, - Undefined = 0b11011, - System = 0b11111 + Undefined = 0b11011, + System = 0b11111, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExceptionCallback.cs b/src/ARMeilleure/State/ExceptionCallback.cs index 38d6eef78..2a4e9656a 100644 --- a/src/ARMeilleure/State/ExceptionCallback.cs +++ b/src/ARMeilleure/State/ExceptionCallback.cs @@ -2,4 +2,4 @@ namespace ARMeilleure.State { public delegate void ExceptionCallbackNoArgs(ExecutionContext context); public delegate void ExceptionCallback(ExecutionContext context, ulong address, int id); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExecutionContext.cs b/src/ARMeilleure/State/ExecutionContext.cs index 859fb3a5d..ce10a591c 100644 --- a/src/ARMeilleure/State/ExecutionContext.cs +++ b/src/ARMeilleure/State/ExecutionContext.cs @@ -7,7 +7,7 @@ namespace ARMeilleure.State { private const int MinCountForCheck = 4000; - private NativeContext _nativeContext; + private readonly NativeContext _nativeContext; internal IntPtr NativeContextPtr => _nativeContext.BasePtr; @@ -17,8 +17,10 @@ namespace ARMeilleure.State public ulong Pc => _nativeContext.GetPc(); +#pragma warning disable CA1822 // Mark member as static public uint CtrEl0 => 0x8444c004; public uint DczidEl0 => 0x00000004; +#pragma warning restore CA1822 public ulong CntfrqEl0 => _counter.Frequency; public ulong CntpctEl0 => _counter.Counter; @@ -170,4 +172,4 @@ namespace ARMeilleure.State _nativeContext.Dispose(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/ExecutionMode.cs b/src/ARMeilleure/State/ExecutionMode.cs index f43c5569f..e1fb722bd 100644 --- a/src/ARMeilleure/State/ExecutionMode.cs +++ b/src/ARMeilleure/State/ExecutionMode.cs @@ -4,6 +4,6 @@ namespace ARMeilleure.State { Aarch32Arm = 0, Aarch32Thumb = 1, - Aarch64 = 2 + Aarch64 = 2, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/FPCR.cs b/src/ARMeilleure/State/FPCR.cs index 6f707de7d..427300add 100644 --- a/src/ARMeilleure/State/FPCR.cs +++ b/src/ARMeilleure/State/FPCR.cs @@ -13,10 +13,10 @@ namespace ARMeilleure.State Ide = 1u << 15, RMode0 = 1u << 22, RMode1 = 1u << 23, - Fz = 1u << 24, - Dn = 1u << 25, + Fz = 1u << 24, + Dn = 1u << 25, Ahp = 1u << 26, - Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe // 0x07C09F00u + Mask = Ahp | Dn | Fz | RMode1 | RMode0 | Ide | Ixe | Ufe | Ofe | Dze | Ioe, // 0x07C09F00u } } diff --git a/src/ARMeilleure/State/FPException.cs b/src/ARMeilleure/State/FPException.cs index e24e07af1..5b13659ab 100644 --- a/src/ARMeilleure/State/FPException.cs +++ b/src/ARMeilleure/State/FPException.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.State { enum FPException { - InvalidOp = 0, + InvalidOp = 0, DivideByZero = 1, - Overflow = 2, - Underflow = 3, - Inexact = 4, - InputDenorm = 7 + Overflow = 2, + Underflow = 3, + Inexact = 4, + InputDenorm = 7, } } diff --git a/src/ARMeilleure/State/FPRoundingMode.cs b/src/ARMeilleure/State/FPRoundingMode.cs index 8d757a151..0913175e7 100644 --- a/src/ARMeilleure/State/FPRoundingMode.cs +++ b/src/ARMeilleure/State/FPRoundingMode.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.State { public enum FPRoundingMode { - ToNearest = 0, // With ties to even. - TowardsPlusInfinity = 1, + ToNearest = 0, // With ties to even. + TowardsPlusInfinity = 1, TowardsMinusInfinity = 2, - TowardsZero = 3, - ToNearestAway = 4 // With ties to away. + TowardsZero = 3, + ToNearestAway = 4, // With ties to away. } } diff --git a/src/ARMeilleure/State/FPSCR.cs b/src/ARMeilleure/State/FPSCR.cs index d6d2fc26a..65a060ebd 100644 --- a/src/ARMeilleure/State/FPSCR.cs +++ b/src/ARMeilleure/State/FPSCR.cs @@ -10,6 +10,6 @@ namespace ARMeilleure.State Z = 1u << 30, N = 1u << 31, - Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask // 0xFFC09F9Fu + Mask = N | Z | C | V | FPSR.Mask | FPCR.Mask, // 0xFFC09F9Fu } } diff --git a/src/ARMeilleure/State/FPSR.cs b/src/ARMeilleure/State/FPSR.cs index 5e66d5ce1..915b2fb31 100644 --- a/src/ARMeilleure/State/FPSR.cs +++ b/src/ARMeilleure/State/FPSR.cs @@ -13,6 +13,6 @@ namespace ARMeilleure.State Idc = 1u << 7, Qc = 1u << 27, - Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc // 0x0800009Fu + Mask = Qc | Idc | Ixc | Ufc | Ofc | Dzc | Ioc, // 0x0800009Fu } } diff --git a/src/ARMeilleure/State/FPState.cs b/src/ARMeilleure/State/FPState.cs index fa6ab9d46..027272eee 100644 --- a/src/ARMeilleure/State/FPState.cs +++ b/src/ARMeilleure/State/FPState.cs @@ -26,6 +26,6 @@ RMode1Flag = 23, FzFlag = 24, DnFlag = 25, - AhpFlag = 26 + AhpFlag = 26, } } diff --git a/src/ARMeilleure/State/FPType.cs b/src/ARMeilleure/State/FPType.cs index 84e0db8da..367082ffc 100644 --- a/src/ARMeilleure/State/FPType.cs +++ b/src/ARMeilleure/State/FPType.cs @@ -6,6 +6,6 @@ namespace ARMeilleure.State Zero, Infinity, QNaN, - SNaN + SNaN, } } diff --git a/src/ARMeilleure/State/ICounter.cs b/src/ARMeilleure/State/ICounter.cs index 93e721ea3..7aa1cce73 100644 --- a/src/ARMeilleure/State/ICounter.cs +++ b/src/ARMeilleure/State/ICounter.cs @@ -15,4 +15,4 @@ namespace ARMeilleure.State /// ulong Counter { get; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/NativeContext.cs b/src/ARMeilleure/State/NativeContext.cs index 3189bdd8a..5403042ea 100644 --- a/src/ARMeilleure/State/NativeContext.cs +++ b/src/ARMeilleure/State/NativeContext.cs @@ -23,7 +23,7 @@ namespace ARMeilleure.State public int Running; } - private static NativeCtxStorage _dummyStorage = new NativeCtxStorage(); + private static NativeCtxStorage _dummyStorage = new(); private readonly IJitMemoryBlock _block; @@ -266,4 +266,4 @@ namespace ARMeilleure.State public void Dispose() => _block.Dispose(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/PState.cs b/src/ARMeilleure/State/PState.cs index 9a80bc570..d4ddc8656 100644 --- a/src/ARMeilleure/State/PState.cs +++ b/src/ARMeilleure/State/PState.cs @@ -12,6 +12,6 @@ namespace ARMeilleure.State VFlag = 28, CFlag = 29, ZFlag = 30, - NFlag = 31 + NFlag = 31, } } diff --git a/src/ARMeilleure/State/RegisterAlias.cs b/src/ARMeilleure/State/RegisterAlias.cs index 7ebfa2753..a95740891 100644 --- a/src/ARMeilleure/State/RegisterAlias.cs +++ b/src/ARMeilleure/State/RegisterAlias.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.State { static class RegisterAlias { - public const int R8Usr = 8; - public const int R9Usr = 9; + public const int R8Usr = 8; + public const int R9Usr = 9; public const int R10Usr = 10; public const int R11Usr = 11; public const int R12Usr = 12; - public const int SpUsr = 13; - public const int LrUsr = 14; + public const int SpUsr = 13; + public const int LrUsr = 14; public const int SpHyp = 15; @@ -24,13 +24,13 @@ namespace ARMeilleure.State public const int LrUnd = 22; public const int SpUnd = 23; - public const int R8Fiq = 24; - public const int R9Fiq = 25; + public const int R8Fiq = 24; + public const int R9Fiq = 25; public const int R10Fiq = 26; public const int R11Fiq = 27; public const int R12Fiq = 28; - public const int SpFiq = 29; - public const int LrFiq = 30; + public const int SpFiq = 29; + public const int LrFiq = 30; public const int Aarch32Sp = 13; public const int Aarch32Lr = 14; @@ -39,4 +39,4 @@ namespace ARMeilleure.State public const int Lr = 30; public const int Zr = 31; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/RegisterConsts.cs b/src/ARMeilleure/State/RegisterConsts.cs index d62940808..b43f8d646 100644 --- a/src/ARMeilleure/State/RegisterConsts.cs +++ b/src/ARMeilleure/State/RegisterConsts.cs @@ -2,14 +2,14 @@ namespace ARMeilleure.State { static class RegisterConsts { - public const int IntRegsCount = 32; - public const int VecRegsCount = 32; - public const int FlagsCount = 32; - public const int FpFlagsCount = 32; + public const int IntRegsCount = 32; + public const int VecRegsCount = 32; + public const int FlagsCount = 32; + public const int FpFlagsCount = 32; public const int IntAndVecRegsCount = IntRegsCount + VecRegsCount; - public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount; - public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount; + public const int FpFlagsOffset = IntRegsCount + VecRegsCount + FlagsCount; + public const int TotalCount = IntRegsCount + VecRegsCount + FlagsCount + FpFlagsCount; public const int ZeroIndex = 31; } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/State/V128.cs b/src/ARMeilleure/State/V128.cs index 441bbfa6d..cbcaddfc2 100644 --- a/src/ARMeilleure/State/V128.cs +++ b/src/ARMeilleure/State/V128.cs @@ -19,7 +19,7 @@ namespace ARMeilleure.State /// /// Gets a new with all bits set to zero. /// - public static V128 Zero => new V128(0, 0); + public static V128 Zero => new(0, 0); /// /// Initializes a new instance of the struct with the specified value @@ -55,9 +55,9 @@ namespace ARMeilleure.State /// Element 3 public V128(float e0, float e1, float e2, float e3) { - _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0; + _e0 = (ulong)(uint)BitConverter.SingleToInt32Bits(e0) << 0; _e0 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e1) << 32; - _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0; + _e1 = (ulong)(uint)BitConverter.SingleToInt32Bits(e2) << 0; _e1 |= (ulong)(uint)BitConverter.SingleToInt32Bits(e3) << 32; } @@ -98,9 +98,9 @@ namespace ARMeilleure.State /// Element 3 public V128(uint e0, uint e1, uint e2, uint e3) { - _e0 = (ulong)e0 << 0; + _e0 = (ulong)e0 << 0; _e0 |= (ulong)e1 << 32; - _e1 = (ulong)e2 << 0; + _e1 = (ulong)e2 << 0; _e1 |= (ulong)e3 << 32; } @@ -137,7 +137,9 @@ namespace ARMeilleure.State public T Extract(int index) where T : unmanaged { if ((uint)index >= GetElementCount()) + { ThrowIndexOutOfRange(); + } // Performs: // return *((*T)this + index); @@ -156,7 +158,9 @@ namespace ARMeilleure.State public void Insert(int index, T value) where T : unmanaged { if ((uint)index >= GetElementCount()) + { ThrowIndexOutOfRange(); + } // Performs: // *((*T)this + index) = value; @@ -167,13 +171,13 @@ namespace ARMeilleure.State /// Returns a new array which represents the . /// /// A new array which represents the - public byte[] ToArray() + public readonly byte[] ToArray() { - byte[] data = new byte[16]; + byte[] data = new byte[16]; Span span = data; BitConverter.TryWriteBytes(span, _e0); - BitConverter.TryWriteBytes(span.Slice(8), _e1); + BitConverter.TryWriteBytes(span[8..], _e1); return data; } @@ -225,7 +229,7 @@ namespace ARMeilleure.State /// /// Target /// Result of not operation - public static V128 operator ~(V128 x) => new V128(~x._e0, ~x._e1); + public static V128 operator ~(V128 x) => new(~x._e0, ~x._e1); /// /// Performs a bitwise and on the specified instances. @@ -233,7 +237,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of and operation - public static V128 operator &(V128 x, V128 y) => new V128(x._e0 & y._e0, x._e1 & y._e1); + public static V128 operator &(V128 x, V128 y) => new(x._e0 & y._e0, x._e1 & y._e1); /// /// Performs a bitwise or on the specified instances. @@ -241,7 +245,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of or operation - public static V128 operator |(V128 x, V128 y) => new V128(x._e0 | y._e0, x._e1 | y._e1); + public static V128 operator |(V128 x, V128 y) => new(x._e0 | y._e0, x._e1 | y._e1); /// /// Performs a bitwise exlusive or on the specified instances. @@ -249,7 +253,7 @@ namespace ARMeilleure.State /// First instance /// Second instance /// Result of exclusive or operation - public static V128 operator ^(V128 x, V128 y) => new V128(x._e0 ^ y._e0, x._e1 ^ y._e1); + public static V128 operator ^(V128 x, V128 y) => new(x._e0 ^ y._e0, x._e1 ^ y._e1); /// /// Determines if the specified instances are equal. @@ -272,7 +276,7 @@ namespace ARMeilleure.State /// /// Other instance /// true if equal; otherwise false - public bool Equals(V128 other) + public readonly bool Equals(V128 other) { return other._e0 == _e0 && other._e1 == _e1; } @@ -282,24 +286,24 @@ namespace ARMeilleure.State /// /// Other instance /// true if equal; otherwise false - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is V128 vector && Equals(vector); } /// - public override int GetHashCode() + public readonly override int GetHashCode() { return HashCode.Combine(_e0, _e1); } /// - public override string ToString() + public readonly override string ToString() { return $"0x{_e1:X16}{_e0:X16}"; } - private uint GetElementCount() where T : unmanaged + private static uint GetElementCount() where T : unmanaged { return (uint)(Unsafe.SizeOf() / Unsafe.SizeOf()); } @@ -309,4 +313,4 @@ namespace ARMeilleure.State throw new ArgumentOutOfRangeException("index"); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Statistics.cs b/src/ARMeilleure/Statistics.cs index fbc647082..2f873bcfa 100644 --- a/src/ARMeilleure/Statistics.cs +++ b/src/ARMeilleure/Statistics.cs @@ -1,4 +1,6 @@ +#if M_PROFILE using System; +#endif using System.Collections.Concurrent; using System.Collections.Generic; using System.Diagnostics; @@ -11,12 +13,12 @@ namespace ARMeilleure { private const int ReportMaxFunctions = 100; -#pragma warning disable CS0169 +#if M_PROFILE [ThreadStatic] private static Stopwatch _executionTimer; -#pragma warning restore CS0169 +#endif - private static ConcurrentDictionary _ticksPerFunction; + private static readonly ConcurrentDictionary _ticksPerFunction; static Statistics() { @@ -47,7 +49,7 @@ namespace ARMeilleure long ticks = _executionTimer.ElapsedTicks; - _ticksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks); + TicksPerFunction.AddOrUpdate(funcAddr, ticks, (key, oldTicks) => oldTicks + ticks); #endif } @@ -69,7 +71,7 @@ namespace ARMeilleure { int count = 0; - StringBuilder sb = new StringBuilder(); + StringBuilder sb = new(); sb.AppendLine(" Function address | Time"); sb.AppendLine("--------------------------"); @@ -91,4 +93,4 @@ namespace ARMeilleure return sb.ToString(); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/ArmEmitterContext.cs b/src/ARMeilleure/Translation/ArmEmitterContext.cs index 565d2aada..e24074739 100644 --- a/src/ARMeilleure/Translation/ArmEmitterContext.cs +++ b/src/ARMeilleure/Translation/ArmEmitterContext.cs @@ -55,7 +55,7 @@ namespace ARMeilleure.Translation public Aarch32Mode Mode { get; } private int _ifThenBlockStateIndex = 0; - private Condition[] _ifThenBlockState = { }; + private Condition[] _ifThenBlockState = Array.Empty(); public bool IsInIfThenBlock => _ifThenBlockStateIndex < _ifThenBlockState.Length; public Condition CurrentIfThenBlockCond => _ifThenBlockState[_ifThenBlockStateIndex]; @@ -96,7 +96,7 @@ namespace ARMeilleure.Translation OperandType returnType = GetOperandType(info.ReturnType); - Symbol symbol = new Symbol(SymbolType.DelegateTable, (ulong)index); + Symbol symbol = new(SymbolType.DelegateTable, (ulong)index); Symbols.Add((ulong)funcPtr.ToInt64(), info.Name); @@ -219,6 +219,7 @@ namespace ARMeilleure.Translation { switch (condition) { +#pragma warning disable IDE0055 // Disable formatting case Condition.Eq: return ICompareEqual (n, m); case Condition.Ne: return ICompareNotEqual (n, m); case Condition.GeUn: return ICompareGreaterOrEqualUI(n, m); @@ -229,6 +230,7 @@ namespace ARMeilleure.Translation case Condition.Lt: return ICompareLess (n, m); case Condition.Gt: return ICompareGreater (n, m); case Condition.Le: return ICompareLessOrEqual (n, m); +#pragma warning restore IDE0055 } } else if (cmpName == InstName.Adds && _optOpLastCompare is IOpCodeAluImm op) @@ -253,12 +255,14 @@ namespace ARMeilleure.Translation switch (condition) { +#pragma warning disable IDE0055 // Disable formatting case Condition.Eq: return ICompareEqual (n, m); case Condition.Ne: return ICompareNotEqual (n, m); case Condition.Ge: return ICompareGreaterOrEqual(n, m); case Condition.Lt: return ICompareLess (n, m); case Condition.Gt: return ICompareGreater (n, m); case Condition.Le: return ICompareLessOrEqual (n, m); +#pragma warning restore IDE0055 } } @@ -279,4 +283,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/CacheEntry.cs b/src/ARMeilleure/Translation/Cache/CacheEntry.cs index dc5503b18..25b06f781 100644 --- a/src/ARMeilleure/Translation/Cache/CacheEntry.cs +++ b/src/ARMeilleure/Translation/Cache/CacheEntry.cs @@ -7,14 +7,14 @@ namespace ARMeilleure.Translation.Cache readonly struct CacheEntry : IComparable { public int Offset { get; } - public int Size { get; } + public int Size { get; } public UnwindInfo UnwindInfo { get; } public CacheEntry(int offset, int size, UnwindInfo unwindInfo) { - Offset = offset; - Size = size; + Offset = offset; + Size = size; UnwindInfo = unwindInfo; } @@ -23,4 +23,4 @@ namespace ARMeilleure.Translation.Cache return Offset.CompareTo(other.Offset); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs index 4c22de40e..dd67e4201 100644 --- a/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs +++ b/src/ARMeilleure/Translation/Cache/CacheMemoryAllocator.cs @@ -23,7 +23,7 @@ namespace ARMeilleure.Translation.Cache } } - private readonly List _blocks = new List(); + private readonly List _blocks = new(); public CacheMemoryAllocator(int capacity) { diff --git a/src/ARMeilleure/Translation/Cache/JitCache.cs b/src/ARMeilleure/Translation/Cache/JitCache.cs index 03cba5ade..91a054123 100644 --- a/src/ARMeilleure/Translation/Cache/JitCache.cs +++ b/src/ARMeilleure/Translation/Cache/JitCache.cs @@ -13,8 +13,8 @@ namespace ARMeilleure.Translation.Cache { static partial class JitCache { - private static readonly int PageSize = (int)MemoryBlock.GetPageSize(); - private static readonly int PageMask = PageSize - 1; + private static readonly int _pageSize = (int)MemoryBlock.GetPageSize(); + private static readonly int _pageMask = _pageSize - 1; private const int CodeAlignment = 4; // Bytes. private const int CacheSize = 2047 * 1024 * 1024; @@ -24,7 +24,7 @@ namespace ARMeilleure.Translation.Cache private static CacheMemoryAllocator _cacheAllocator; - private static readonly List _cacheEntries = new List(); + private static readonly List _cacheEntries = new(); private static readonly object _lock = new(); private static bool _initialized; @@ -35,11 +35,17 @@ namespace ARMeilleure.Translation.Cache public static void Initialize(IJitMemoryAllocator allocator) { - if (_initialized) return; + if (_initialized) + { + return; + } lock (_lock) { - if (_initialized) return; + if (_initialized) + { + return; + } _jitRegion = new ReservedRegion(allocator, CacheSize); @@ -52,7 +58,7 @@ namespace ARMeilleure.Translation.Cache if (OperatingSystem.IsWindows()) { - JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(PageSize)); + JitUnwindWindows.InstallFunctionTableHandler(_jitRegion.Pointer, CacheSize, _jitRegion.Pointer + Allocate(_pageSize)); } _initialized = true; @@ -75,7 +81,7 @@ namespace ARMeilleure.Translation.Cache { unsafe { - fixed (byte *codePtr = code) + fixed (byte* codePtr = code) { JitSupportDarwin.Copy(funcPtr, (IntPtr)codePtr, (ulong)code.Length); } @@ -124,8 +130,8 @@ namespace ARMeilleure.Translation.Cache { int endOffs = offset + size; - int regionStart = offset & ~PageMask; - int regionEnd = (endOffs + PageMask) & ~PageMask; + int regionStart = offset & ~_pageMask; + int regionEnd = (endOffs + _pageMask) & ~_pageMask; _jitRegion.Block.MapAsRwx((ulong)regionStart, (ulong)(regionEnd - regionStart)); } @@ -134,8 +140,8 @@ namespace ARMeilleure.Translation.Cache { int endOffs = offset + size; - int regionStart = offset & ~PageMask; - int regionEnd = (endOffs + PageMask) & ~PageMask; + int regionStart = offset & ~_pageMask; + int regionEnd = (endOffs + _pageMask) & ~_pageMask; _jitRegion.Block.MapAsRx((ulong)regionStart, (ulong)(regionEnd - regionStart)); } @@ -163,7 +169,7 @@ namespace ARMeilleure.Translation.Cache private static void Add(int offset, int size, UnwindInfo unwindInfo) { - CacheEntry entry = new CacheEntry(offset, size, unwindInfo); + CacheEntry entry = new(offset, size, unwindInfo); int index = _cacheEntries.BinarySearch(entry); @@ -212,4 +218,4 @@ namespace ARMeilleure.Translation.Cache return false; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs index 57f7bf121..3aa2e19f1 100644 --- a/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs +++ b/src/ARMeilleure/Translation/Cache/JitCacheInvalidation.cs @@ -6,7 +6,7 @@ namespace ARMeilleure.Translation.Cache { class JitCacheInvalidation { - private static int[] _invalidationCode = new int[] + private static readonly int[] _invalidationCode = new int[] { unchecked((int)0xd53b0022), // mrs x2, ctr_el0 unchecked((int)0xd3504c44), // ubfx x4, x2, #16, #4 @@ -40,8 +40,8 @@ namespace ARMeilleure.Translation.Cache private delegate void InvalidateCache(ulong start, ulong end); - private InvalidateCache _invalidateCache; - private ReservedRegion _invalidateCacheCodeRegion; + private readonly InvalidateCache _invalidateCache; + private readonly ReservedRegion _invalidateCacheCodeRegion; private readonly bool _needsInvalidation; @@ -76,4 +76,4 @@ namespace ARMeilleure.Translation.Cache } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs index 77727bf16..91fd19c25 100644 --- a/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs +++ b/src/ARMeilleure/Translation/Cache/JitUnwindWindows.cs @@ -29,15 +29,15 @@ namespace ARMeilleure.Translation.Cache private enum UnwindOp { - PushNonvol = 0, - AllocLarge = 1, - AllocSmall = 2, - SetFpreg = 3, - SaveNonvol = 4, + PushNonvol = 0, + AllocLarge = 1, + AllocSmall = 2, + SetFpreg = 3, + SaveNonvol = 4, SaveNonvolFar = 5, - SaveXmm128 = 8, + SaveXmm128 = 8, SaveXmm128Far = 9, - PushMachframe = 10 + PushMachframe = 10, } private unsafe delegate RuntimeFunction* GetRuntimeFunctionCallback(ulong controlPc, IntPtr context); @@ -111,72 +111,73 @@ namespace ARMeilleure.Translation.Cache switch (entry.PseudoOp) { case UnwindPseudoOp.SaveXmm128: - { - int stackOffset = entry.StackOffsetOrAllocSize; - - Debug.Assert(stackOffset % 16 == 0); - - if (stackOffset <= 0xFFFF0) { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16); - } - else - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16); - } + int stackOffset = entry.StackOffsetOrAllocSize; - break; - } + Debug.Assert(stackOffset % 16 == 0); + + if (stackOffset <= 0xFFFF0) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128, entry.PrologOffset, entry.RegIndex); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset / 16); + } + else + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.SaveXmm128Far, entry.PrologOffset, entry.RegIndex); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(stackOffset >> 16); + } + + break; + } case UnwindPseudoOp.AllocStack: - { - int allocSize = entry.StackOffsetOrAllocSize; - - Debug.Assert(allocSize % 8 == 0); - - if (allocSize <= 128) { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1); - } - else if (allocSize <= 0x7FFF8) - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8); - } - else - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0); - _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16); - } + int allocSize = entry.StackOffsetOrAllocSize; - break; - } + Debug.Assert(allocSize % 8 == 0); + + if (allocSize <= 128) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocSmall, entry.PrologOffset, (allocSize / 8) - 1); + } + else if (allocSize <= 0x7FFF8) + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize / 8); + } + else + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.AllocLarge, entry.PrologOffset, 1); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 0); + _unwindInfo->UnwindCodes[codeIndex++] = (ushort)(allocSize >> 16); + } + + break; + } case UnwindPseudoOp.PushReg: - { - _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex); + { + _unwindInfo->UnwindCodes[codeIndex++] = PackUnwindOp(UnwindOp.PushNonvol, entry.PrologOffset, entry.RegIndex); - break; - } + break; + } - default: throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})"); + default: + throw new NotImplementedException($"({nameof(entry.PseudoOp)} = {entry.PseudoOp})"); } } Debug.Assert(codeIndex <= MaxUnwindCodesArraySize); - _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler. - _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize; + _unwindInfo->VersionAndFlags = 1; // Flags: The function has no handler. + _unwindInfo->SizeOfProlog = (byte)unwindInfo.PrologSize; _unwindInfo->CountOfUnwindCodes = (byte)codeIndex; - _unwindInfo->FrameRegister = 0; + _unwindInfo->FrameRegister = 0; _runtimeFunction->BeginAddress = (uint)funcEntry.Offset; - _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size); - _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction; + _runtimeFunction->EndAddress = (uint)(funcEntry.Offset + funcEntry.Size); + _runtimeFunction->UnwindData = (uint)_sizeOfRuntimeFunction; return _runtimeFunction; } @@ -186,4 +187,4 @@ namespace ARMeilleure.Translation.Cache return (ushort)(prologOffset | ((int)op << 8) | (opInfo << 12)); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Compiler.cs b/src/ARMeilleure/Translation/Compiler.cs index d4aa5cd96..293e63496 100644 --- a/src/ARMeilleure/Translation/Compiler.cs +++ b/src/ARMeilleure/Translation/Compiler.cs @@ -11,10 +11,10 @@ namespace ARMeilleure.Translation { public static CompiledFunction Compile( ControlFlowGraph cfg, - OperandType[] argTypes, - OperandType retType, - CompilerOptions options, - Architecture target) + OperandType[] argTypes, + OperandType retType, + CompilerOptions options, + Architecture target) { CompilerContext cctx = new(cfg, argTypes, retType, options); @@ -65,4 +65,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/CompilerContext.cs b/src/ARMeilleure/Translation/CompilerContext.cs index 510dec58f..5b10686b3 100644 --- a/src/ARMeilleure/Translation/CompilerContext.cs +++ b/src/ARMeilleure/Translation/CompilerContext.cs @@ -6,21 +6,21 @@ namespace ARMeilleure.Translation { public ControlFlowGraph Cfg { get; } - public OperandType[] FuncArgTypes { get; } - public OperandType FuncReturnType { get; } + public OperandType[] FuncArgTypes { get; } + public OperandType FuncReturnType { get; } public CompilerOptions Options { get; } public CompilerContext( ControlFlowGraph cfg, - OperandType[] funcArgTypes, - OperandType funcReturnType, - CompilerOptions options) + OperandType[] funcArgTypes, + OperandType funcReturnType, + CompilerOptions options) { - Cfg = cfg; - FuncArgTypes = funcArgTypes; + Cfg = cfg; + FuncArgTypes = funcArgTypes; FuncReturnType = funcReturnType; - Options = options; + Options = options; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/CompilerOptions.cs b/src/ARMeilleure/Translation/CompilerOptions.cs index 0a07ed4ab..d454de7f2 100644 --- a/src/ARMeilleure/Translation/CompilerOptions.cs +++ b/src/ARMeilleure/Translation/CompilerOptions.cs @@ -5,13 +5,13 @@ namespace ARMeilleure.Translation [Flags] enum CompilerOptions { - None = 0, - SsaForm = 1 << 0, - Optimize = 1 << 1, - Lsra = 1 << 2, + None = 0, + SsaForm = 1 << 0, + Optimize = 1 << 1, + Lsra = 1 << 2, Relocatable = 1 << 3, MediumCq = SsaForm | Optimize, - HighCq = SsaForm | Optimize | Lsra + HighCq = SsaForm | Optimize | Lsra, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/ControlFlowGraph.cs b/src/ARMeilleure/Translation/ControlFlowGraph.cs index c935f1521..3ead49c93 100644 --- a/src/ARMeilleure/Translation/ControlFlowGraph.cs +++ b/src/ARMeilleure/Translation/ControlFlowGraph.cs @@ -130,7 +130,7 @@ namespace ARMeilleure.Translation public BasicBlock SplitEdge(BasicBlock predecessor, BasicBlock successor) { - BasicBlock splitBlock = new BasicBlock(Blocks.Count); + BasicBlock splitBlock = new(Blocks.Count); for (int i = 0; i < predecessor.SuccessorsCount; i++) { @@ -152,4 +152,4 @@ namespace ARMeilleure.Translation return splitBlock; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/DelegateInfo.cs b/src/ARMeilleure/Translation/DelegateInfo.cs index 36320ac31..27479a003 100644 --- a/src/ARMeilleure/Translation/DelegateInfo.cs +++ b/src/ARMeilleure/Translation/DelegateInfo.cs @@ -5,7 +5,9 @@ namespace ARMeilleure.Translation { class DelegateInfo { +#pragma warning disable IDE0052 // Remove unread private member private readonly Delegate _dlg; // Ensure that this delegate will not be garbage collected. +#pragma warning restore IDE0052 public IntPtr FuncPtr { get; } diff --git a/src/ARMeilleure/Translation/Dominance.cs b/src/ARMeilleure/Translation/Dominance.cs index b9b961d15..e2185bd85 100644 --- a/src/ARMeilleure/Translation/Dominance.cs +++ b/src/ARMeilleure/Translation/Dominance.cs @@ -29,7 +29,7 @@ namespace ARMeilleure.Translation cfg.Entry.ImmediateDominator = cfg.Entry; - Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[cfg.PostOrderBlocks.Length - 1]); + Debug.Assert(cfg.Entry == cfg.PostOrderBlocks[^1]); bool modified; @@ -92,4 +92,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/EmitterContext.cs b/src/ARMeilleure/Translation/EmitterContext.cs index 8fcb4deec..88bfe1335 100644 --- a/src/ARMeilleure/Translation/EmitterContext.cs +++ b/src/ARMeilleure/Translation/EmitterContext.cs @@ -108,9 +108,9 @@ namespace ARMeilleure.Translation protected static OperandType GetOperandType(Type type) { - if (type == typeof(bool) || type == typeof(byte) || - type == typeof(char) || type == typeof(short) || - type == typeof(int) || type == typeof(sbyte) || + if (type == typeof(bool) || type == typeof(byte) || + type == typeof(char) || type == typeof(short) || + type == typeof(int) || type == typeof(sbyte) || type == typeof(ushort) || type == typeof(uint)) { return OperandType.I32; @@ -635,7 +635,7 @@ namespace ARMeilleure.Translation private void NewNextBlock() { - BasicBlock block = new BasicBlock(_irBlocks.Count); + BasicBlock block = new(_irBlocks.Count); _irBlocks.AddLast(block); diff --git a/src/ARMeilleure/Translation/GuestFunction.cs b/src/ARMeilleure/Translation/GuestFunction.cs index ac131a0d1..6414d6bd0 100644 --- a/src/ARMeilleure/Translation/GuestFunction.cs +++ b/src/ARMeilleure/Translation/GuestFunction.cs @@ -3,4 +3,4 @@ using System; namespace ARMeilleure.Translation { delegate ulong GuestFunction(IntPtr nativeContextPtr); -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/IntervalTree.cs b/src/ARMeilleure/Translation/IntervalTree.cs index 9af01bea0..afd89b930 100644 --- a/src/ARMeilleure/Translation/IntervalTree.cs +++ b/src/ARMeilleure/Translation/IntervalTree.cs @@ -6,15 +6,15 @@ namespace ARMeilleure.Translation /// /// An Augmented Interval Tree based off of the "TreeDictionary"'s Red-Black Tree. Allows fast overlap checking of ranges. /// - /// Key - /// Value - class IntervalTree where K : IComparable + /// Key + /// Value + class IntervalTree where TK : IComparable { private const int ArrayGrowthSize = 32; private const bool Black = true; private const bool Red = false; - private IntervalTreeNode _root = null; + private IntervalTreeNode _root = null; private int _count = 0; public int Count => _count; @@ -27,9 +27,9 @@ namespace ARMeilleure.Translation /// Key of the node value to get /// Value with the given /// True if the key is on the dictionary, false otherwise - public bool TryGet(K key, out V value) + public bool TryGet(TK key, out TV value) { - IntervalTreeNode node = GetNode(key); + IntervalTreeNode node = GetNode(key); if (node == null) { @@ -49,7 +49,7 @@ namespace ARMeilleure.Translation /// Overlaps array to place results in /// Index to start writing results into the array. Defaults to 0 /// Number of intervals found - public int Get(K start, K end, ref K[] overlaps, int overlapCount = 0) + public int Get(TK start, TK end, ref TK[] overlaps, int overlapCount = 0) { GetKeys(_root, start, end, ref overlaps, ref overlapCount); @@ -65,11 +65,11 @@ namespace ARMeilleure.Translation /// Optional factory used to create a new value if is already on the tree /// is null /// True if the value was added, false if the start key was already in the dictionary - public bool AddOrUpdate(K start, K end, V value, Func updateFactoryCallback) + public bool AddOrUpdate(TK start, TK end, TV value, Func updateFactoryCallback) { ArgumentNullException.ThrowIfNull(value); - return BSTInsert(start, end, value, updateFactoryCallback, out IntervalTreeNode node); + return BSTInsert(start, end, value, updateFactoryCallback, out _); } /// @@ -80,11 +80,11 @@ namespace ARMeilleure.Translation /// Value to add /// is null /// if is not yet on the tree, or the existing value otherwise - public V GetOrAdd(K start, K end, V value) + public TV GetOrAdd(TK start, TK end, TV value) { ArgumentNullException.ThrowIfNull(value); - BSTInsert(start, end, value, null, out IntervalTreeNode node); + BSTInsert(start, end, value, null, out IntervalTreeNode node); return node.Value; } @@ -93,7 +93,7 @@ namespace ARMeilleure.Translation /// /// Key of the node to remove /// Number of deleted values - public int Remove(K key) + public int Remove(TK key) { int removed = Delete(key); @@ -106,9 +106,9 @@ namespace ARMeilleure.Translation /// Adds all the nodes in the dictionary into . /// /// A list of all values sorted by Key Order - public List AsList() + public List AsList() { - List list = new List(); + List list = new(); AddToList(_root, list); @@ -124,7 +124,7 @@ namespace ARMeilleure.Translation /// /// The node to search for values within /// The list to add values to - private void AddToList(IntervalTreeNode node, List list) + private void AddToList(IntervalTreeNode node, List list) { if (node == null) { @@ -144,11 +144,11 @@ namespace ARMeilleure.Translation /// Key of the node to get /// is null /// Node reference in the tree - private IntervalTreeNode GetNode(K key) + private IntervalTreeNode GetNode(TK key) { ArgumentNullException.ThrowIfNull(key); - IntervalTreeNode node = _root; + IntervalTreeNode node = _root; while (node != null) { int cmp = key.CompareTo(node.Start); @@ -175,7 +175,7 @@ namespace ARMeilleure.Translation /// End of the range /// Overlaps array to place results in /// Overlaps count to update - private void GetKeys(IntervalTreeNode node, K start, K end, ref K[] overlaps, ref int overlapCount) + private void GetKeys(IntervalTreeNode node, TK start, TK end, ref TK[] overlaps, ref int overlapCount) { if (node == null || start.CompareTo(node.Max) >= 0) { @@ -206,10 +206,10 @@ namespace ARMeilleure.Translation /// This should only be called if the max increases - not for rebalancing or removals. /// /// The node to start propagating from - private void PropagateIncrease(IntervalTreeNode node) + private static void PropagateIncrease(IntervalTreeNode node) { - K max = node.Max; - IntervalTreeNode ptr = node; + TK max = node.Max; + IntervalTreeNode ptr = node; while ((ptr = ptr.Parent) != null) { @@ -229,13 +229,13 @@ namespace ARMeilleure.Translation /// This fully recalculates the max value from all children when there is potential for it to decrease. /// /// The node to start propagating from - private void PropagateFull(IntervalTreeNode node) + private static void PropagateFull(IntervalTreeNode node) { - IntervalTreeNode ptr = node; + IntervalTreeNode ptr = node; do { - K max = ptr.End; + TK max = ptr.End; if (ptr.Left != null && ptr.Left.Max.CompareTo(max) > 0) { @@ -263,10 +263,10 @@ namespace ARMeilleure.Translation /// Optional factory used to create a new value if is already on the tree /// Node that was inserted or modified /// True if was not yet on the tree, false otherwise - private bool BSTInsert(K start, K end, V value, Func updateFactoryCallback, out IntervalTreeNode outNode) + private bool BSTInsert(TK start, TK end, TV value, Func updateFactoryCallback, out IntervalTreeNode outNode) { - IntervalTreeNode parent = null; - IntervalTreeNode node = _root; + IntervalTreeNode parent = null; + IntervalTreeNode node = _root; while (node != null) { @@ -311,7 +311,7 @@ namespace ARMeilleure.Translation return false; } } - IntervalTreeNode newNode = new IntervalTreeNode(start, end, value, parent); + IntervalTreeNode newNode = new(start, end, value, parent); if (newNode.Parent == null) { _root = newNode; @@ -337,16 +337,16 @@ namespace ARMeilleure.Translation /// /// Key to search for /// Number of deleted values - private int Delete(K key) + private int Delete(TK key) { - IntervalTreeNode nodeToDelete = GetNode(key); + IntervalTreeNode nodeToDelete = GetNode(key); if (nodeToDelete == null) { return 0; } - IntervalTreeNode replacementNode; + IntervalTreeNode replacementNode; if (LeftOf(nodeToDelete) == null || RightOf(nodeToDelete) == null) { @@ -357,7 +357,7 @@ namespace ARMeilleure.Translation replacementNode = PredecessorOf(nodeToDelete); } - IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode); + IntervalTreeNode tmp = LeftOf(replacementNode) ?? RightOf(replacementNode); if (tmp != null) { @@ -400,9 +400,9 @@ namespace ARMeilleure.Translation /// /// Root Node /// Node with the maximum key in the tree of - private static IntervalTreeNode Maximum(IntervalTreeNode node) + private static IntervalTreeNode Maximum(IntervalTreeNode node) { - IntervalTreeNode tmp = node; + IntervalTreeNode tmp = node; while (tmp.Right != null) { tmp = tmp.Right; @@ -416,13 +416,13 @@ namespace ARMeilleure.Translation /// /// Node to find the predecessor of /// Predecessor of - private static IntervalTreeNode PredecessorOf(IntervalTreeNode node) + private static IntervalTreeNode PredecessorOf(IntervalTreeNode node) { if (node.Left != null) { return Maximum(node.Left); } - IntervalTreeNode parent = node.Parent; + IntervalTreeNode parent = node.Parent; while (parent != null && node == parent.Left) { node = parent; @@ -435,15 +435,15 @@ namespace ARMeilleure.Translation #region Private Methods (RBL) - private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode) + private void RestoreBalanceAfterRemoval(IntervalTreeNode balanceNode) { - IntervalTreeNode ptr = balanceNode; + IntervalTreeNode ptr = balanceNode; while (ptr != _root && ColorOf(ptr) == Black) { if (ptr == LeftOf(ParentOf(ptr))) { - IntervalTreeNode sibling = RightOf(ParentOf(ptr)); + IntervalTreeNode sibling = RightOf(ParentOf(ptr)); if (ColorOf(sibling) == Red) { @@ -475,7 +475,7 @@ namespace ARMeilleure.Translation } else { - IntervalTreeNode sibling = LeftOf(ParentOf(ptr)); + IntervalTreeNode sibling = LeftOf(ParentOf(ptr)); if (ColorOf(sibling) == Red) { @@ -509,14 +509,14 @@ namespace ARMeilleure.Translation SetColor(ptr, Black); } - private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode) + private void RestoreBalanceAfterInsertion(IntervalTreeNode balanceNode) { SetColor(balanceNode, Red); while (balanceNode != null && balanceNode != _root && ColorOf(ParentOf(balanceNode)) == Red) { if (ParentOf(balanceNode) == LeftOf(ParentOf(ParentOf(balanceNode)))) { - IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode))); + IntervalTreeNode sibling = RightOf(ParentOf(ParentOf(balanceNode))); if (ColorOf(sibling) == Red) { @@ -539,7 +539,7 @@ namespace ARMeilleure.Translation } else { - IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode))); + IntervalTreeNode sibling = LeftOf(ParentOf(ParentOf(balanceNode))); if (ColorOf(sibling) == Red) { @@ -564,17 +564,17 @@ namespace ARMeilleure.Translation SetColor(_root, Black); } - private void RotateLeft(IntervalTreeNode node) + private void RotateLeft(IntervalTreeNode node) { if (node != null) { - IntervalTreeNode right = RightOf(node); + IntervalTreeNode right = RightOf(node); node.Right = LeftOf(right); if (node.Right != null) { node.Right.Parent = node; } - IntervalTreeNode nodeParent = ParentOf(node); + IntervalTreeNode nodeParent = ParentOf(node); right.Parent = nodeParent; if (nodeParent == null) { @@ -595,17 +595,17 @@ namespace ARMeilleure.Translation } } - private void RotateRight(IntervalTreeNode node) + private void RotateRight(IntervalTreeNode node) { if (node != null) { - IntervalTreeNode left = LeftOf(node); + IntervalTreeNode left = LeftOf(node); node.Left = RightOf(left); if (node.Left != null) { node.Left.Parent = node; } - IntervalTreeNode nodeParent = ParentOf(node); + IntervalTreeNode nodeParent = ParentOf(node); left.Parent = nodeParent; if (nodeParent == null) { @@ -637,7 +637,7 @@ namespace ARMeilleure.Translation /// /// Node /// The boolean color of , or black if null - private static bool ColorOf(IntervalTreeNode node) + private static bool ColorOf(IntervalTreeNode node) { return node == null || node.Color; } @@ -649,7 +649,7 @@ namespace ARMeilleure.Translation /// /// Node to set the color of /// Color (Boolean) - private static void SetColor(IntervalTreeNode node, bool color) + private static void SetColor(IntervalTreeNode node, bool color) { if (node != null) { @@ -662,7 +662,7 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the left child from /// Left child of - private static IntervalTreeNode LeftOf(IntervalTreeNode node) + private static IntervalTreeNode LeftOf(IntervalTreeNode node) { return node?.Left; } @@ -672,7 +672,7 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the right child from /// Right child of - private static IntervalTreeNode RightOf(IntervalTreeNode node) + private static IntervalTreeNode RightOf(IntervalTreeNode node) { return node?.Right; } @@ -682,14 +682,14 @@ namespace ARMeilleure.Translation /// /// Node to retrieve the parent from /// Parent of - private static IntervalTreeNode ParentOf(IntervalTreeNode node) + private static IntervalTreeNode ParentOf(IntervalTreeNode node) { return node?.Parent; } #endregion - public bool ContainsKey(K key) + public bool ContainsKey(TK key) { return GetNode(key) != null; } @@ -704,36 +704,36 @@ namespace ARMeilleure.Translation /// /// Represents a node in the IntervalTree which contains start and end keys of type K, and a value of generic type V. /// - /// Key type of the node - /// Value type of the node - class IntervalTreeNode + /// Key type of the node + /// Value type of the node + class IntervalTreeNode { public bool Color = true; - public IntervalTreeNode Left = null; - public IntervalTreeNode Right = null; - public IntervalTreeNode Parent = null; + public IntervalTreeNode Left = null; + public IntervalTreeNode Right = null; + public IntervalTreeNode Parent = null; /// /// The start of the range. /// - public K Start; + public TK Start; /// /// The end of the range. /// - public K End; + public TK End; /// /// The maximum end value of this node and all its children. /// - public K Max; + public TK Max; /// /// Value stored on this node. /// - public V Value; + public TV Value; - public IntervalTreeNode(K start, K end, V value, IntervalTreeNode parent) + public IntervalTreeNode(TK start, TK end, TV value, IntervalTreeNode parent) { Start = start; End = end; diff --git a/src/ARMeilleure/Translation/PTC/EncodingCache.cs b/src/ARMeilleure/Translation/PTC/EncodingCache.cs index 90d40c475..d9b38ace7 100644 --- a/src/ARMeilleure/Translation/PTC/EncodingCache.cs +++ b/src/ARMeilleure/Translation/PTC/EncodingCache.cs @@ -6,4 +6,4 @@ namespace ARMeilleure.Translation.PTC { public static readonly Encoding UTF8NoBOM = new UTF8Encoding(encoderShouldEmitUTF8Identifier: false, throwOnInvalidBytes: true); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs index 1b11ac0b5..efff45a9f 100644 --- a/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs +++ b/src/ARMeilleure/Translation/PTC/IPtcLoadState.cs @@ -7,4 +7,4 @@ namespace ARMeilleure.Translation.PTC event Action PtcStateChanged; void Continue(); } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/Ptc.cs b/src/ARMeilleure/Translation/PTC/Ptc.cs index 3c697bffe..665f568d2 100644 --- a/src/ARMeilleure/Translation/PTC/Ptc.cs +++ b/src/ARMeilleure/Translation/PTC/Ptc.cs @@ -17,13 +17,12 @@ using System.Runtime; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Threading; - using static ARMeilleure.Translation.PTC.PtcFormatter; namespace ARMeilleure.Translation.PTC { - using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities; - using X86HardwareCapabilities = ARMeilleure.CodeGen.X86.HardwareCapabilities; + using Arm64HardwareCapabilities = CodeGen.Arm64.HardwareCapabilities; + using X86HardwareCapabilities = CodeGen.X86.HardwareCapabilities; class Ptc : IPtcLoadState { @@ -187,8 +186,8 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{CachePathActual}.cache"; string fileNameBackup = $"{CachePathBackup}.cache"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); - FileInfo fileInfoBackup = new FileInfo(fileNameBackup); + FileInfo fileInfoActual = new(fileNameActual); + FileInfo fileInfoBackup = new(fileNameBackup); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -275,104 +274,102 @@ namespace ARMeilleure.Translation.PTC { intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize)); - using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite)) + using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite); + try { - try - { - deflateStream.CopyTo(stream); - } - catch - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek(0L, SeekOrigin.Begin); - - InnerHeader innerHeader = DeserializeStructure(stream); - - if (!innerHeader.IsHeaderValid()) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - if (innerHeader.Magic != _innerHeaderMagic) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); - stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); - - Hash128 infosHash = XXHash128.ComputeHash(infosBytes); - - if (innerHeader.InfosHash != infosHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; - stream.Seek(innerHeader.CodesLength, SeekOrigin.Current); - - Hash128 codesHash = XXHash128.ComputeHash(codesBytes); - - if (innerHeader.CodesHash != codesHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); - stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); - - Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes); - - if (innerHeader.RelocsHash != relocsHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); - stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); - - Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); - - if (innerHeader.UnwindInfosHash != unwindInfosHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); - - _infosStream.Write(infosBytes); - stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); - - _codesList.ReadFrom(stream); - - _relocsStream.Write(relocsBytes); - stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); - - _unwindInfosStream.Write(unwindInfosBytes); - stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); - - Debug.Assert(stream.Position == stream.Length); + deflateStream.CopyTo(stream); } + catch + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek(0L, SeekOrigin.Begin); + + InnerHeader innerHeader = DeserializeStructure(stream); + + if (!innerHeader.IsHeaderValid()) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + if (innerHeader.Magic != _innerHeaderMagic) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); + stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); + + Hash128 infosHash = XXHash128.ComputeHash(infosBytes); + + if (innerHeader.InfosHash != infosHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; + stream.Seek(innerHeader.CodesLength, SeekOrigin.Current); + + Hash128 codesHash = XXHash128.ComputeHash(codesBytes); + + if (innerHeader.CodesHash != codesHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); + stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); + + Hash128 relocsHash = XXHash128.ComputeHash(relocsBytes); + + if (innerHeader.RelocsHash != relocsHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); + stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); + + Hash128 unwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); + + if (innerHeader.UnwindInfosHash != unwindInfosHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); + + _infosStream.Write(infosBytes); + stream.Seek(innerHeader.InfosLength, SeekOrigin.Current); + + _codesList.ReadFrom(stream); + + _relocsStream.Write(relocsBytes); + stream.Seek(innerHeader.RelocsLength, SeekOrigin.Current); + + _unwindInfosStream.Write(unwindInfosBytes); + stream.Seek(innerHeader.UnwindInfosLength, SeekOrigin.Current); + + Debug.Assert(stream.Position == stream.Length); } finally { @@ -390,7 +387,7 @@ namespace ARMeilleure.Translation.PTC return true; } - private void InvalidateCompressedStream(FileStream compressedStream) + private static void InvalidateCompressedStream(FileStream compressedStream) { compressedStream.SetLength(0L); } @@ -404,7 +401,7 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{CachePathActual}.cache"; string fileNameBackup = $"{CachePathBackup}.cache"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); + FileInfo fileInfoActual = new(fileNameActual); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -427,32 +424,34 @@ namespace ARMeilleure.Translation.PTC { int translatedFuncsCount; - InnerHeader innerHeader = new InnerHeader(); + InnerHeader innerHeader = new() + { + Magic = _innerHeaderMagic, - innerHeader.Magic = _innerHeaderMagic; + InfosLength = (int)_infosStream.Length, + CodesLength = _codesList.Length(), + RelocsLength = (int)_relocsStream.Length, + UnwindInfosLength = (int)_unwindInfosStream.Length, + }; - innerHeader.InfosLength = (int)_infosStream.Length; - innerHeader.CodesLength = _codesList.Length(); - innerHeader.RelocsLength = (int)_relocsStream.Length; - innerHeader.UnwindInfosLength = (int)_unwindInfosStream.Length; + OuterHeader outerHeader = new() + { + Magic = _outerHeaderMagic, - OuterHeader outerHeader = new OuterHeader(); + CacheFileVersion = InternalVersion, + Endianness = GetEndianness(), + FeatureInfo = GetFeatureInfo(), + MemoryManagerMode = GetMemoryManagerMode(), + OSPlatform = GetOSPlatform(), + Architecture = (uint)RuntimeInformation.ProcessArchitecture, - outerHeader.Magic = _outerHeaderMagic; - - outerHeader.CacheFileVersion = InternalVersion; - outerHeader.Endianness = GetEndianness(); - outerHeader.FeatureInfo = GetFeatureInfo(); - outerHeader.MemoryManagerMode = GetMemoryManagerMode(); - outerHeader.OSPlatform = GetOSPlatform(); - outerHeader.Architecture = (uint)RuntimeInformation.ProcessArchitecture; - - outerHeader.UncompressedStreamSize = + UncompressedStreamSize = (long)Unsafe.SizeOf() + innerHeader.InfosLength + innerHeader.CodesLength + innerHeader.RelocsLength + - innerHeader.UnwindInfosLength; + innerHeader.UnwindInfosLength, + }; outerHeader.SetHeaderHash(); @@ -462,58 +461,54 @@ namespace ARMeilleure.Translation.PTC { intPtr = Marshal.AllocHGlobal(new IntPtr(outerHeader.UncompressedStreamSize)); - using (UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite)) + using UnmanagedMemoryStream stream = new((byte*)intPtr.ToPointer(), outerHeader.UncompressedStreamSize, outerHeader.UncompressedStreamSize, FileAccess.ReadWrite); + stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); + + ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); + _infosStream.WriteTo(stream); + + ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; + _codesList.WriteTo(stream); + + ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); + _relocsStream.WriteTo(stream); + + ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); + _unwindInfosStream.WriteTo(stream); + + Debug.Assert(stream.Position == stream.Length); + + innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes); + innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes); + innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes); + innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); + + innerHeader.SetHeaderHash(); + + stream.Seek(0L, SeekOrigin.Begin); + SerializeStructure(stream, innerHeader); + + translatedFuncsCount = GetEntriesCount(); + + ResetCarriersIfNeeded(); + + using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate); + using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true); + try { - stream.Seek((long)Unsafe.SizeOf(), SeekOrigin.Begin); - - ReadOnlySpan infosBytes = new(stream.PositionPointer, innerHeader.InfosLength); - _infosStream.WriteTo(stream); - - ReadOnlySpan codesBytes = (int)innerHeader.CodesLength > 0 ? new(stream.PositionPointer, (int)innerHeader.CodesLength) : ReadOnlySpan.Empty; - _codesList.WriteTo(stream); - - ReadOnlySpan relocsBytes = new(stream.PositionPointer, innerHeader.RelocsLength); - _relocsStream.WriteTo(stream); - - ReadOnlySpan unwindInfosBytes = new(stream.PositionPointer, innerHeader.UnwindInfosLength); - _unwindInfosStream.WriteTo(stream); - - Debug.Assert(stream.Position == stream.Length); - - innerHeader.InfosHash = XXHash128.ComputeHash(infosBytes); - innerHeader.CodesHash = XXHash128.ComputeHash(codesBytes); - innerHeader.RelocsHash = XXHash128.ComputeHash(relocsBytes); - innerHeader.UnwindInfosHash = XXHash128.ComputeHash(unwindInfosBytes); - - innerHeader.SetHeaderHash(); + SerializeStructure(compressedStream, outerHeader); stream.Seek(0L, SeekOrigin.Begin); - SerializeStructure(stream, innerHeader); + stream.CopyTo(deflateStream); + } + catch + { + compressedStream.Position = 0L; + } - translatedFuncsCount = GetEntriesCount(); - - ResetCarriersIfNeeded(); - - using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate)) - using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true)) - { - try - { - SerializeStructure(compressedStream, outerHeader); - - stream.Seek(0L, SeekOrigin.Begin); - stream.CopyTo(deflateStream); - } - catch - { - compressedStream.Position = 0L; - } - - if (compressedStream.Position < compressedStream.Length) - { - compressedStream.SetLength(compressedStream.Position); - } - } + if (compressedStream.Position < compressedStream.Length) + { + compressedStream.SetLength(compressedStream.Position); } } finally @@ -647,7 +642,7 @@ namespace ARMeilleure.Translation.PTC return _codesList[index]; } - private RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount) + private static RelocEntry[] GetRelocEntries(BinaryReader relocsReader, int relocEntriesCount) { RelocEntry[] relocEntries = new RelocEntry[relocEntriesCount]; @@ -663,7 +658,7 @@ namespace ARMeilleure.Translation.PTC return relocEntries; } - private void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter) + private static void PatchCode(Translator translator, Span code, RelocEntry[] relocEntries, out Counter callCounter) { callCounter = null; @@ -678,7 +673,10 @@ namespace ARMeilleure.Translation.PTC if (translator.FunctionTable.IsValid(guestAddress)) { - unsafe { imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress)); } + unsafe + { + imm = (IntPtr)Unsafe.AsPointer(ref translator.FunctionTable.GetValue(guestAddress)); + } } } else if (symbol.Type == SymbolType.DelegateTable) @@ -696,12 +694,12 @@ namespace ARMeilleure.Translation.PTC } else if (symbol == CountTableSymbol) { - if (callCounter == null) - { - callCounter = new Counter(translator.CountTable); - } + callCounter ??= new Counter(translator.CountTable); - unsafe { imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value); } + unsafe + { + imm = (IntPtr)Unsafe.AsPointer(ref callCounter.Value); + } } else if (symbol == DispatchStubSymbol) { @@ -717,7 +715,7 @@ namespace ARMeilleure.Translation.PTC } } - private UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader) + private static UnwindInfo ReadUnwindInfo(BinaryReader unwindInfosReader) { int pushEntriesLength = unwindInfosReader.ReadInt32(); @@ -738,7 +736,7 @@ namespace ARMeilleure.Translation.PTC return new UnwindInfo(pushEntries, prologueSize); } - private TranslatedFunction FastTranslate( + private static TranslatedFunction FastTranslate( byte[] code, Counter callCounter, ulong guestSize, @@ -809,13 +807,13 @@ namespace ARMeilleure.Translation.PTC PtcStateChanged?.Invoke(PtcLoadingState.Start, _translateCount, _translateTotalCount); - using AutoResetEvent progressReportEvent = new AutoResetEvent(false); + using AutoResetEvent progressReportEvent = new(false); - Thread progressReportThread = new Thread(ReportProgress) + Thread progressReportThread = new(ReportProgress) { Name = "Ptc.ProgressReporter", Priority = ThreadPriority.Lowest, - IsBackground = true + IsBackground = true, }; progressReportThread.Start(progressReportEvent); @@ -845,12 +843,14 @@ namespace ARMeilleure.Translation.PTC } } - List threads = new List(); + List threads = new(); for (int i = 0; i < degreeOfParallelism; i++) { - Thread thread = new Thread(TranslateFuncs); - thread.IsBackground = true; + Thread thread = new(TranslateFuncs) + { + IsBackground = true, + }; threads.Add(thread); } @@ -871,8 +871,10 @@ namespace ARMeilleure.Translation.PTC Logger.Info?.Print(LogClass.Ptc, $"{_translateCount} of {_translateTotalCount} functions translated | Thread count: {degreeOfParallelism} in {sw.Elapsed.TotalSeconds} s"); - Thread preSaveThread = new Thread(PreSave); - preSaveThread.IsBackground = true; + Thread preSaveThread = new(PreSave) + { + IsBackground = true, + }; preSaveThread.Start(); } @@ -910,15 +912,16 @@ namespace ARMeilleure.Translation.PTC RelocInfo relocInfo = compiledFunc.RelocInfo; UnwindInfo unwindInfo = compiledFunc.UnwindInfo; - InfoEntry infoEntry = new InfoEntry(); - - infoEntry.Address = address; - infoEntry.GuestSize = guestSize; - infoEntry.Hash = hash; - infoEntry.HighCq = highCq; - infoEntry.Stubbed = false; - infoEntry.CodeLength = code.Length; - infoEntry.RelocEntriesCount = relocInfo.Entries.Length; + InfoEntry infoEntry = new() + { + Address = address, + GuestSize = guestSize, + Hash = hash, + HighCq = highCq, + Stubbed = false, + CodeLength = code.Length, + RelocEntriesCount = relocInfo.Entries.Length, + }; SerializeStructure(_infosStream, infoEntry); @@ -996,10 +999,12 @@ namespace ARMeilleure.Translation.PTC { uint osPlatform = 0u; +#pragma warning disable IDE0055 // Disable formatting osPlatform |= (OperatingSystem.IsFreeBSD() ? 1u : 0u) << 0; osPlatform |= (OperatingSystem.IsLinux() ? 1u : 0u) << 1; osPlatform |= (OperatingSystem.IsMacOS() ? 1u : 0u) << 2; osPlatform |= (OperatingSystem.IsWindows() ? 1u : 0u) << 3; +#pragma warning restore IDE0055 return osPlatform; } @@ -1025,14 +1030,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } @@ -1060,14 +1065,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } diff --git a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs index 2f7a9c21f..ddac31338 100644 --- a/src/ARMeilleure/Translation/PTC/PtcFormatter.cs +++ b/src/ARMeilleure/Translation/PTC/PtcFormatter.cs @@ -47,7 +47,7 @@ namespace ARMeilleure.Translation.PTC [MethodImpl(MethodImplOptions.AggressiveInlining)] public static T DeserializeStructure(Stream stream) where T : struct { - T structure = default(T); + T structure = default; Span spanT = MemoryMarshal.CreateSpan(ref structure, 1); int bytesCount = stream.Read(MemoryMarshal.AsBytes(spanT)); @@ -176,4 +176,4 @@ namespace ARMeilleure.Translation.PTC } #endregion } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs index 526cf91fb..587be7939 100644 --- a/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs +++ b/src/ARMeilleure/Translation/PTC/PtcLoadingState.cs @@ -4,6 +4,6 @@ namespace ARMeilleure.Translation.PTC { Start, Loading, - Loaded + Loaded, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs index 391e29c76..3a4bfcec6 100644 --- a/src/ARMeilleure/Translation/PTC/PtcProfiler.cs +++ b/src/ARMeilleure/Translation/PTC/PtcProfiler.cs @@ -12,7 +12,6 @@ using System.IO.Compression; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Threading; - using static ARMeilleure.Translation.PTC.PtcFormatter; namespace ARMeilleure.Translation.PTC @@ -46,7 +45,7 @@ namespace ARMeilleure.Translation.PTC public bool Enabled { get; private set; } public ulong StaticCodeStart { get; set; } - public ulong StaticCodeSize { get; set; } + public ulong StaticCodeSize { get; set; } public PtcProfiler(Ptc ptc) { @@ -129,8 +128,8 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{_ptc.CachePathActual}.info"; string fileNameBackup = $"{_ptc.CachePathBackup}.info"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); - FileInfo fileInfoBackup = new FileInfo(fileNameBackup); + FileInfo fileInfoActual = new(fileNameActual); + FileInfo fileInfoBackup = new(fileNameBackup); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -183,42 +182,40 @@ namespace ARMeilleure.Translation.PTC return false; } - using (MemoryStream stream = MemoryStreamManager.Shared.GetStream()) + using MemoryStream stream = MemoryStreamManager.Shared.GetStream(); + Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L); + + try { - Debug.Assert(stream.Seek(0L, SeekOrigin.Begin) == 0L && stream.Length == 0L); - - try - { - deflateStream.CopyTo(stream); - } - catch - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - Debug.Assert(stream.Position == stream.Length); - - stream.Seek(0L, SeekOrigin.Begin); - - Hash128 expectedHash = DeserializeStructure(stream); - - Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream)); - - if (actualHash != expectedHash) - { - InvalidateCompressedStream(compressedStream); - - return false; - } - - ProfiledFuncs = Deserialize(stream); - - Debug.Assert(stream.Position == stream.Length); - - _lastHash = actualHash; + deflateStream.CopyTo(stream); } + catch + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + Debug.Assert(stream.Position == stream.Length); + + stream.Seek(0L, SeekOrigin.Begin); + + Hash128 expectedHash = DeserializeStructure(stream); + + Hash128 actualHash = XXHash128.ComputeHash(GetReadOnlySpan(stream)); + + if (actualHash != expectedHash) + { + InvalidateCompressedStream(compressedStream); + + return false; + } + + ProfiledFuncs = Deserialize(stream); + + Debug.Assert(stream.Position == stream.Length); + + _lastHash = actualHash; } long fileSize = new FileInfo(fileName).Length; @@ -233,12 +230,12 @@ namespace ARMeilleure.Translation.PTC return DeserializeDictionary(stream, (stream) => DeserializeStructure(stream)); } - private ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream) + private static ReadOnlySpan GetReadOnlySpan(MemoryStream memoryStream) { return new(memoryStream.GetBuffer(), (int)memoryStream.Position, (int)memoryStream.Length - (int)memoryStream.Position); } - private void InvalidateCompressedStream(FileStream compressedStream) + private static void InvalidateCompressedStream(FileStream compressedStream) { compressedStream.SetLength(0L); } @@ -250,7 +247,7 @@ namespace ARMeilleure.Translation.PTC string fileNameActual = $"{_ptc.CachePathActual}.info"; string fileNameBackup = $"{_ptc.CachePathBackup}.info"; - FileInfo fileInfoActual = new FileInfo(fileNameActual); + FileInfo fileInfoActual = new(fileNameActual); if (fileInfoActual.Exists && fileInfoActual.Length != 0L) { @@ -266,12 +263,13 @@ namespace ARMeilleure.Translation.PTC { int profiledFuncsCount; - OuterHeader outerHeader = new OuterHeader(); + OuterHeader outerHeader = new() + { + Magic = _outerHeaderMagic, - outerHeader.Magic = _outerHeaderMagic; - - outerHeader.InfoFileVersion = InternalVersion; - outerHeader.Endianness = Ptc.GetEndianness(); + InfoFileVersion = InternalVersion, + Endianness = Ptc.GetEndianness(), + }; outerHeader.SetHeaderHash(); @@ -301,28 +299,26 @@ namespace ARMeilleure.Translation.PTC return; } - using (FileStream compressedStream = new(fileName, FileMode.OpenOrCreate)) - using (DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true)) + using FileStream compressedStream = new(fileName, FileMode.OpenOrCreate); + using DeflateStream deflateStream = new(compressedStream, SaveCompressionLevel, true); + try { - try - { - SerializeStructure(compressedStream, outerHeader); + SerializeStructure(compressedStream, outerHeader); - stream.WriteTo(deflateStream); + stream.WriteTo(deflateStream); - _lastHash = hash; - } - catch - { - compressedStream.Position = 0L; + _lastHash = hash; + } + catch + { + compressedStream.Position = 0L; - _lastHash = default; - } + _lastHash = default; + } - if (compressedStream.Position < compressedStream.Length) - { - compressedStream.SetLength(compressedStream.Position); - } + if (compressedStream.Position < compressedStream.Length) + { + compressedStream.SetLength(compressedStream.Position); } } @@ -334,7 +330,7 @@ namespace ARMeilleure.Translation.PTC } } - private void Serialize(Stream stream, Dictionary profiledFuncs) + private static void Serialize(Stream stream, Dictionary profiledFuncs) { SerializeDictionary(stream, profiledFuncs, (stream, structure) => SerializeStructure(stream, structure)); } @@ -354,14 +350,14 @@ namespace ARMeilleure.Translation.PTC { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())); + HeaderHash = XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]); } public bool IsHeaderValid() { Span spanHeader = MemoryMarshal.CreateSpan(ref this, 1); - return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader).Slice(0, Unsafe.SizeOf() - Unsafe.SizeOf())) == HeaderHash; + return XXHash128.ComputeHash(MemoryMarshal.AsBytes(spanHeader)[..(Unsafe.SizeOf() - Unsafe.SizeOf())]) == HeaderHash; } } @@ -418,4 +414,4 @@ namespace ARMeilleure.Translation.PTC } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/PTC/PtcState.cs b/src/ARMeilleure/Translation/PTC/PtcState.cs index ca4f41080..f6692e870 100644 --- a/src/ARMeilleure/Translation/PTC/PtcState.cs +++ b/src/ARMeilleure/Translation/PTC/PtcState.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Translation.PTC Enabled, Continuing, Closing, - Disabled + Disabled, } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/RegisterToLocal.cs b/src/ARMeilleure/Translation/RegisterToLocal.cs index abb9b373c..91372eb00 100644 --- a/src/ARMeilleure/Translation/RegisterToLocal.cs +++ b/src/ARMeilleure/Translation/RegisterToLocal.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.Translation { public static void Rename(ControlFlowGraph cfg) { - Dictionary registerToLocalMap = new Dictionary(); + Dictionary registerToLocalMap = new(); Operand GetLocal(Operand op) { @@ -49,4 +49,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/RegisterUsage.cs b/src/ARMeilleure/Translation/RegisterUsage.cs index 3ec0a7b4f..c8c250626 100644 --- a/src/ARMeilleure/Translation/RegisterUsage.cs +++ b/src/ARMeilleure/Translation/RegisterUsage.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Translation static class RegisterUsage { private const int RegsCount = 32; - private const int RegsMask = RegsCount - 1; + private const int RegsMask = RegsCount - 1; private readonly struct RegisterMask : IEquatable { @@ -90,7 +90,7 @@ namespace ARMeilleure.Translation public static void RunPass(ControlFlowGraph cfg, ExecutionMode mode) { // Compute local register inputs and outputs used inside blocks. - RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count]; + RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Count]; RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Count]; for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext) @@ -119,7 +119,7 @@ namespace ARMeilleure.Translation // Compute global register inputs and outputs used across blocks. RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Count]; - RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count]; + RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Count]; RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Count]; bool modified; @@ -286,10 +286,12 @@ namespace ARMeilleure.Translation switch (register.Type) { +#pragma warning disable IDE0055 // Disable formatting case RegisterType.Flag: intMask = (1L << RegsCount) << register.Index; break; case RegisterType.Integer: intMask = 1L << register.Index; break; case RegisterType.FpFlag: vecMask = (1L << RegsCount) << register.Index; break; case RegisterType.Vector: vecMask = 1L << register.Index; break; +#pragma warning restore IDE0055 } return new RegisterMask(intMask, vecMask); @@ -373,15 +375,14 @@ namespace ARMeilleure.Translation private static OperandType GetOperandType(RegisterType type, ExecutionMode mode) { - switch (type) + return type switch { - case RegisterType.Flag: return OperandType.I32; - case RegisterType.FpFlag: return OperandType.I32; - case RegisterType.Integer: return (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32; - case RegisterType.Vector: return OperandType.V128; - } - - throw new ArgumentException($"Invalid register type \"{type}\"."); + RegisterType.Flag => OperandType.I32, + RegisterType.FpFlag => OperandType.I32, + RegisterType.Integer => (mode == ExecutionMode.Aarch64) ? OperandType.I64 : OperandType.I32, + RegisterType.Vector => OperandType.V128, + _ => throw new ArgumentException($"Invalid register type \"{type}\"."), + }; } private static bool EndsWithReturn(BasicBlock block) @@ -391,4 +392,4 @@ namespace ARMeilleure.Translation return last != default && last.Instruction == Instruction.Return; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/SsaConstruction.cs b/src/ARMeilleure/Translation/SsaConstruction.cs index 2b6efc113..cddcfcd4f 100644 --- a/src/ARMeilleure/Translation/SsaConstruction.cs +++ b/src/ARMeilleure/Translation/SsaConstruction.cs @@ -180,7 +180,7 @@ namespace ARMeilleure.Translation } previous = current; - current = current.ImmediateDominator; + current = current.ImmediateDominator; } while (previous != current); @@ -286,4 +286,4 @@ namespace ARMeilleure.Translation return key; } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/SsaDeconstruction.cs b/src/ARMeilleure/Translation/SsaDeconstruction.cs index cd6bcca1f..68af54e5d 100644 --- a/src/ARMeilleure/Translation/SsaDeconstruction.cs +++ b/src/ARMeilleure/Translation/SsaDeconstruction.cs @@ -45,4 +45,4 @@ namespace ARMeilleure.Translation } } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/TranslatedFunction.cs b/src/ARMeilleure/Translation/TranslatedFunction.cs index f007883ef..1446c254a 100644 --- a/src/ARMeilleure/Translation/TranslatedFunction.cs +++ b/src/ARMeilleure/Translation/TranslatedFunction.cs @@ -31,4 +31,4 @@ namespace ARMeilleure.Translation return dispatcher(context.NativeContextPtr, (ulong)FuncPointer); } } -} \ No newline at end of file +} diff --git a/src/ARMeilleure/Translation/Translator.cs b/src/ARMeilleure/Translation/Translator.cs index 234be2ac7..dc18038ba 100644 --- a/src/ARMeilleure/Translation/Translator.cs +++ b/src/ARMeilleure/Translation/Translator.cs @@ -22,24 +22,24 @@ namespace ARMeilleure.Translation { public class Translator { - private static readonly AddressTable.Level[] Levels64Bit = + private static readonly AddressTable.Level[] _levels64Bit = new AddressTable.Level[] { new(31, 17), new(23, 8), new(15, 8), new( 7, 8), - new( 2, 5) + new( 2, 5), }; - private static readonly AddressTable.Level[] Levels32Bit = + private static readonly AddressTable.Level[] _levels32Bit = new AddressTable.Level[] { new(31, 17), new(23, 8), new(15, 8), new( 7, 8), - new( 1, 6) + new( 1, 6), }; private readonly IJitMemoryAllocator _allocator; @@ -75,7 +75,7 @@ namespace ARMeilleure.Translation CountTable = new EntryTable(); Functions = new TranslatorCache(); - FunctionTable = new AddressTable(for64Bits ? Levels64Bit : Levels32Bit); + FunctionTable = new AddressTable(for64Bits ? _levels64Bit : _levels32Bit); Stubs = new TranslatorStubs(this); FunctionTable.Fill = (ulong)Stubs.SlowDispatchStub; @@ -126,7 +126,7 @@ namespace ARMeilleure.Translation // TODO: Use physical cores rather than logical. This only really makes sense for processors with // hyperthreading. Requires OS specific code. int unboundedThreadCount = Math.Max(1, (Environment.ProcessorCount - 6) / 3); - int threadCount = Math.Min(4, unboundedThreadCount); + int threadCount = Math.Min(4, unboundedThreadCount); Thread[] backgroundTranslationThreads = new Thread[threadCount]; @@ -134,10 +134,10 @@ namespace ARMeilleure.Translation { bool last = i != 0 && i == unboundedThreadCount - 1; - backgroundTranslationThreads[i] = new Thread(BackgroundTranslate) + backgroundTranslationThreads[i] = new(BackgroundTranslate) { Name = "CPU.BackgroundTranslatorThread." + i, - Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal + Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal, }; backgroundTranslationThreads[i].Start(); diff --git a/src/ARMeilleure/Translation/TranslatorStubs.cs b/src/ARMeilleure/Translation/TranslatorStubs.cs index 69648df44..eceb1b742 100644 --- a/src/ARMeilleure/Translation/TranslatorStubs.cs +++ b/src/ARMeilleure/Translation/TranslatorStubs.cs @@ -224,7 +224,7 @@ namespace ARMeilleure.Translation /// Emitter context for the method /// Pointer to the native context /// True if entering guest code, false otherwise - private void EmitSyncFpContext(EmitterContext context, Operand nativeContext, bool enter) + private static void EmitSyncFpContext(EmitterContext context, Operand nativeContext, bool enter) { if (enter) { diff --git a/src/ARMeilleure/Translation/TranslatorTestMethods.cs b/src/ARMeilleure/Translation/TranslatorTestMethods.cs index ab96019a6..35cd8dc56 100644 --- a/src/ARMeilleure/Translation/TranslatorTestMethods.cs +++ b/src/ARMeilleure/Translation/TranslatorTestMethods.cs @@ -1,7 +1,6 @@ using ARMeilleure.CodeGen.X86; using ARMeilleure.IntermediateRepresentation; using ARMeilleure.State; -using ARMeilleure.Translation; using System; using System.Runtime.InteropServices; using static ARMeilleure.IntermediateRepresentation.Operand.Factory; @@ -62,7 +61,7 @@ namespace ARMeilleure.Translation public static FpFlagsPInvokeTest GenerateFpFlagsPInvokeTest() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand methodAddress = context.Copy(context.LoadArgument(OperandType.I64, 0)); @@ -110,7 +109,7 @@ namespace ARMeilleure.Translation context.MarkLabel(correct2Label); - // Call a managed method. This method should not change Fz state. + // Call a managed method. This method should not change Fz state. context.Call(methodAddress, OperandType.None); From e96299eef5a9e951d9161b5a13bde9feecc2178c Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Mon, 26 Jun 2023 07:35:19 +0200 Subject: [PATCH 09/19] [Ryujinx.Horizon.Generators] Address dotnet-format issues (#5383) * dotnet format style --severity info Some changes were manually reverted. * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * dotnet format whitespace after rebase --- src/Ryujinx.Horizon.Generators/CodeGenerator.cs | 2 +- src/Ryujinx.Horizon.Generators/Hipc/HipcGenerator.cs | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/Ryujinx.Horizon.Generators/CodeGenerator.cs b/src/Ryujinx.Horizon.Generators/CodeGenerator.cs index 29e1c75c8..59052499e 100644 --- a/src/Ryujinx.Horizon.Generators/CodeGenerator.cs +++ b/src/Ryujinx.Horizon.Generators/CodeGenerator.cs @@ -40,7 +40,7 @@ namespace Ryujinx.Horizon.Generators { if (_currentIndentCount - 1 >= 0) { - _currentIndentCount--; + _currentIndentCount--; } } diff --git a/src/Ryujinx.Horizon.Generators/Hipc/HipcGenerator.cs b/src/Ryujinx.Horizon.Generators/Hipc/HipcGenerator.cs index 284df4820..47b3c8cfb 100644 --- a/src/Ryujinx.Horizon.Generators/Hipc/HipcGenerator.cs +++ b/src/Ryujinx.Horizon.Generators/Hipc/HipcGenerator.cs @@ -39,7 +39,7 @@ namespace Ryujinx.Horizon.Generators.Hipc In } - private struct OutParameter + private readonly struct OutParameter { public readonly string Name; public readonly string TypeName; @@ -341,7 +341,7 @@ namespace Ryujinx.Horizon.Generators.Hipc generator.AppendLine($"using var {argName} = {value};"); string spanGenericTypeName = GetCanonicalTypeNameOfGenericArgument(compilation, parameter.Type, 0); - argName = GenerateSpanCast(spanGenericTypeName, $"{argName}.Memory.Span"); ; + argName = GenerateSpanCast(spanGenericTypeName, $"{argName}.Memory.Span"); } else if (isNonSpanBuffer) { @@ -604,7 +604,7 @@ namespace Ryujinx.Horizon.Generators.Hipc return type; } - private static bool IsArgument(Compilation compilation,ParameterSyntax parameter) + private static bool IsArgument(Compilation compilation, ParameterSyntax parameter) { return !IsBuffer(compilation, parameter) && !IsHandle(compilation, parameter) && From 0191e2396a3a6e499f49aa3b7c9937ccd489856c Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Tue, 27 Jun 2023 16:35:48 +0200 Subject: [PATCH 10/19] [Ryujinx.Graphics.Host1x] Address dotnet-format issues (#5368) * dotnet format style --severity info Some changes were manually reverted. * Address most dotnet format whitespace warnings * Add comments to disabled warnings * dotnet format whitespace after rebase --- src/Ryujinx.Graphics.Host1x/Devices.cs | 2 +- src/Ryujinx.Graphics.Host1x/Host1xClassRegisters.cs | 2 +- src/Ryujinx.Graphics.Host1x/Host1xDevice.cs | 2 +- src/Ryujinx.Graphics.Host1x/SyncptIncrManager.cs | 2 +- src/Ryujinx.Graphics.Host1x/ThiRegisters.cs | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/Ryujinx.Graphics.Host1x/Devices.cs b/src/Ryujinx.Graphics.Host1x/Devices.cs index 5b3bed6b0..95c67c9c4 100644 --- a/src/Ryujinx.Graphics.Host1x/Devices.cs +++ b/src/Ryujinx.Graphics.Host1x/Devices.cs @@ -6,7 +6,7 @@ namespace Ryujinx.Graphics.Host1x { class Devices : IDisposable { - private readonly Dictionary _devices = new Dictionary(); + private readonly Dictionary _devices = new(); public void RegisterDevice(ClassId classId, IDeviceState device) { diff --git a/src/Ryujinx.Graphics.Host1x/Host1xClassRegisters.cs b/src/Ryujinx.Graphics.Host1x/Host1xClassRegisters.cs index f9f4889be..9eeb18d10 100644 --- a/src/Ryujinx.Graphics.Host1x/Host1xClassRegisters.cs +++ b/src/Ryujinx.Graphics.Host1x/Host1xClassRegisters.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Host1x { struct Host1xClassRegisters { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public uint IncrSyncpt; public uint IncrSyncptCntrl; public uint IncrSyncptError; diff --git a/src/Ryujinx.Graphics.Host1x/Host1xDevice.cs b/src/Ryujinx.Graphics.Host1x/Host1xDevice.cs index 90dd4fa05..73dabaf42 100644 --- a/src/Ryujinx.Graphics.Host1x/Host1xDevice.cs +++ b/src/Ryujinx.Graphics.Host1x/Host1xDevice.cs @@ -24,7 +24,7 @@ namespace Ryujinx.Graphics.Host1x private readonly SyncptIncrManager _syncptIncrMgr; private readonly AsyncWorkQueue _commandQueue; - private readonly Devices _devices = new Devices(); + private readonly Devices _devices = new(); public Host1xClass Class { get; } diff --git a/src/Ryujinx.Graphics.Host1x/SyncptIncrManager.cs b/src/Ryujinx.Graphics.Host1x/SyncptIncrManager.cs index 62c499175..fe8c87395 100644 --- a/src/Ryujinx.Graphics.Host1x/SyncptIncrManager.cs +++ b/src/Ryujinx.Graphics.Host1x/SyncptIncrManager.cs @@ -23,7 +23,7 @@ namespace Ryujinx.Graphics.Host1x } } - private readonly List _incrs = new List(); + private readonly List _incrs = new(); private uint _currentId; diff --git a/src/Ryujinx.Graphics.Host1x/ThiRegisters.cs b/src/Ryujinx.Graphics.Host1x/ThiRegisters.cs index 71c485110..74e646952 100644 --- a/src/Ryujinx.Graphics.Host1x/ThiRegisters.cs +++ b/src/Ryujinx.Graphics.Host1x/ThiRegisters.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Host1x { struct ThiRegisters { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public uint IncrSyncpt; public uint Reserved4; public uint IncrSyncptErr; From b186ec9fc5684bd8fa831a1777f6e936b897c352 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Tue, 27 Jun 2023 16:45:33 +0200 Subject: [PATCH 11/19] [Ryujinx.Graphics.Video] Address dotnet-format issues (#5377) * Address most dotnet format whitespace warnings * dotnet format whitespace after rebase --- src/Ryujinx.Graphics.Video/FrameField.cs | 2 +- src/Ryujinx.Graphics.Video/Vp8PictureInfo.cs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Ryujinx.Graphics.Video/FrameField.cs b/src/Ryujinx.Graphics.Video/FrameField.cs index 2bff0e75f..eafd74e07 100644 --- a/src/Ryujinx.Graphics.Video/FrameField.cs +++ b/src/Ryujinx.Graphics.Video/FrameField.cs @@ -5,4 +5,4 @@ namespace Ryujinx.Graphics.Video Progressive, Interlaced } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Video/Vp8PictureInfo.cs b/src/Ryujinx.Graphics.Video/Vp8PictureInfo.cs index 878674b8e..df398d843 100644 --- a/src/Ryujinx.Graphics.Video/Vp8PictureInfo.cs +++ b/src/Ryujinx.Graphics.Video/Vp8PictureInfo.cs @@ -8,4 +8,4 @@ public ushort FrameWidth; public ushort FrameHeight; } -} \ No newline at end of file +} From fbaf62c2309f2987fa73a2022167ee3e81e31ea9 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 01:18:19 +0200 Subject: [PATCH 12/19] Apply new naming rule to all projects except Vp9 (#5407) --- src/ARMeilleure/CodeGen/X86/CodeGenerator.cs | 10 +- src/ARMeilleure/Decoders/Decoder.cs | 4 +- .../Decoders/Optimizations/TailCallRemover.cs | 6 +- .../Instructions/InstEmitSimdHelper.cs | 32 ++--- .../Instructions/InstEmitSimdLogical.cs | 52 ++++----- src/ARMeilleure/Instructions/SoftFloat.cs | 66 +++++------ src/ARMeilleure/Signal/NativeSignalHandler.cs | 25 ++-- src/ARMeilleure/Translation/PTC/Ptc.cs | 4 +- .../Dsp/Command/CircularBufferSinkCommand.cs | 8 +- .../Renderer/Dsp/Command/DelayCommand.cs | 18 +-- .../Renderer/Dsp/Command/DeviceSinkCommand.cs | 10 +- .../Renderer/Dsp/Command/Reverb3dCommand.cs | 8 +- .../Renderer/Dsp/DataSourceHelper.cs | 10 +- .../Renderer/Dsp/UpsamplerHelper.cs | 16 +-- .../CommandProcessingTimeEstimatorVersion2.cs | 6 +- .../Renderer/Server/MemoryPool/PoolMapper.cs | 8 +- .../Controls/ApplicationContextMenu.axaml.cs | 2 +- src/Ryujinx.Ava/UI/Models/SaveModel.cs | 8 +- .../UI/ViewModels/MainWindowViewModel.cs | 12 +- .../UI/ViewModels/SettingsViewModel.cs | 4 +- .../SystemInfo/MacOSSystemInfo.cs | 6 +- .../SystemInterop/StdErrAdapter.cs | 4 +- .../Memory/PhysicalMemory.cs | 2 +- src/Ryujinx.Graphics.Vulkan/BufferManager.cs | 2 +- .../FileSystem/VirtualFileSystem.cs | 8 +- src/Ryujinx.HLE/HOS/Horizon.cs | 6 +- src/Ryujinx.HLE/HOS/Services/Hid/Hid.cs | 18 +-- src/Ryujinx.HLE/HOS/Services/Mii/Helper.cs | 4 +- .../HOS/Services/Sdb/Pl/SharedFontManager.cs | 6 +- src/Ryujinx.HLE/HOS/Services/ServerBase.cs | 4 +- .../Settings/ISystemSettingsServer.cs | 36 +++--- .../RootService/IApplicationDisplayService.cs | 10 +- .../HOS/Tamper/InstructionHelper.cs | 10 +- .../MultiRegionTrackingTests.cs | 60 +++++----- src/Ryujinx.Tests.Memory/TrackingTests.cs | 36 +++--- src/Ryujinx.Tests/Cpu/CpuTestMisc.cs | 8 +- src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs | 110 +++++++++--------- src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs | 2 +- src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs | 10 +- src/Ryujinx.Ui.Common/App/ApplicationData.cs | 12 +- .../App/ApplicationLibrary.cs | 2 +- .../Ui/Widgets/GameTableContextMenu.cs | 4 +- 42 files changed, 334 insertions(+), 335 deletions(-) diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs index 3cab0b6ce..9e94a077f 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -1296,11 +1296,11 @@ namespace ARMeilleure.CodeGen.X86 } else { - const byte mask = 0b01_00_11_10; + const byte Mask = 0b01_00_11_10; - context.Assembler.Pshufd(src1, src1, mask); + context.Assembler.Pshufd(src1, src1, Mask); context.Assembler.Movq(dest, src1); - context.Assembler.Pshufd(src1, src1, mask); + context.Assembler.Pshufd(src1, src1, Mask); } } else @@ -1853,9 +1853,9 @@ namespace ARMeilleure.CodeGen.X86 // that the OS will map all pages that we'll use. We do that by // doing a dummy read on those pages, forcing a page fault and // the OS to map them. If they are already mapped, nothing happens. - const int pageMask = PageSize - 1; + const int PageMask = PageSize - 1; - size = (size + pageMask) & ~pageMask; + size = (size + PageMask) & ~PageMask; Operand rsp = Register(X86Register.Rsp); Operand temp = Register(CallingConvention.GetIntReturnRegister()); diff --git a/src/ARMeilleure/Decoders/Decoder.cs b/src/ARMeilleure/Decoders/Decoder.cs index d8abeb9c8..6d07827a2 100644 --- a/src/ARMeilleure/Decoders/Decoder.cs +++ b/src/ARMeilleure/Decoders/Decoder.cs @@ -304,9 +304,9 @@ namespace ARMeilleure.Decoders } else if (opCode is IOpCode32MemMult opMemMult) { - const int pcMask = 1 << RegisterAlias.Aarch32Pc; + const int PCMask = 1 << RegisterAlias.Aarch32Pc; - rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; + rt = (opMemMult.RegisterMask & PCMask) != 0 ? RegisterAlias.Aarch32Pc : 0; rn = opMemMult.Rn; wBack = opMemMult.PostOffset != 0; isLoad = opMemMult.IsLoad; diff --git a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs index ff9a6f271..20759f356 100644 --- a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs +++ b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs @@ -17,7 +17,7 @@ namespace ARMeilleure.Decoders.Optimizations throw new InvalidOperationException("Function entry point is not contained in a block."); } - const ulong allowance = 4; + const ulong Allowance = 4; Block entryBlock = blocks[entryBlockId]; @@ -31,7 +31,7 @@ namespace ARMeilleure.Decoders.Optimizations { Block block = blocks[i]; - if (endBlock.EndAddress < block.Address - allowance) + if (endBlock.EndAddress < block.Address - Allowance) { break; // End of contiguous function. } @@ -44,7 +44,7 @@ namespace ARMeilleure.Decoders.Optimizations { Block block = blocks[i]; - if (startBlock.Address > block.EndAddress + allowance) + if (startBlock.Address > block.EndAddress + Allowance) { break; // End of contiguous function. } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs index 35052ad11..0b5527409 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdHelper.cs @@ -1299,17 +1299,17 @@ namespace ARMeilleure.Instructions Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128); - const int sm0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0; - const int sm1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0; - const int sm2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0; - const int sm3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0; + const int SM0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0; + const int SM1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0; + const int SM2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0; + const int SM3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0; Operand nCopy = context.Copy(GetVec(op.Rn)); - Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm0)); - Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm1)); - Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm2)); - Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm3)); + Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM0)); + Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM1)); + Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM2)); + Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM3)); Operand res = emit(emit(part0, part1), emit(part2, part3)); @@ -1340,13 +1340,13 @@ namespace ARMeilleure.Instructions if ((op.Size & 1) == 0) { - const int sm0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0; - const int sm1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0; + const int SM0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0; + const int SM1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0; Operand zeroN = context.VectorZeroUpper64(n); - op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm0)); - op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm1)); + op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM0)); + op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM1)); } else /* if ((op.Size & 1) == 1) */ { @@ -1412,11 +1412,11 @@ namespace ARMeilleure.Instructions } else /* if (op.RegisterSize == RegisterSize.Simd128) */ { - const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0; - const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0; + const int SM0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0; + const int SM1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0; - Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm0)); - Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm1)); + Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM0)); + Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM1)); context.Copy(GetVec(op.Rd), emit(part0, part1)); } diff --git a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs index 97e3da67e..ace8e4c54 100644 --- a/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs +++ b/src/ARMeilleure/Instructions/InstEmitSimdLogical.cs @@ -408,7 +408,7 @@ namespace ARMeilleure.Instructions if (Optimizations.UseGfni) { - const long bitMatrix = + const long BitMatrix = (0b10000000L << 56) | (0b01000000L << 48) | (0b00100000L << 40) | @@ -418,7 +418,7 @@ namespace ARMeilleure.Instructions (0b00000010L << 8) | (0b00000001L << 0); - Operand vBitMatrix = X86GetAllElements(context, bitMatrix); + Operand vBitMatrix = X86GetAllElements(context, BitMatrix); Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0)); @@ -469,12 +469,12 @@ namespace ARMeilleure.Instructions Operand n = GetVec(op.Rn); - const long maskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0; - const long maskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0; + const long MaskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0; + const long MaskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0; - Operand mask = X86GetScalar(context, maskE0); + Operand mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask); @@ -503,21 +503,21 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { - const long maskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0; - const long maskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0; + const long MaskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0; + const long MaskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0; - mask = X86GetScalar(context, maskE0); + mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); } else /* if (op.Size == 1) */ { - const long maskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0; - const long maskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0; + const long MaskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0; + const long MaskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0; - mask = X86GetScalar(context, maskE0); + mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); } Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask); @@ -547,30 +547,30 @@ namespace ARMeilleure.Instructions if (op.Size == 0) { - const long maskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0; - const long maskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0; + const long MaskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0; + const long MaskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0; - mask = X86GetScalar(context, maskE0); + mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); } else if (op.Size == 1) { - const long maskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0; - const long maskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0; + const long MaskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0; + const long MaskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0; - mask = X86GetScalar(context, maskE0); + mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); } else /* if (op.Size == 2) */ { - const long maskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0; - const long maskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0; + const long MaskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0; + const long MaskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0; - mask = X86GetScalar(context, maskE0); + mask = X86GetScalar(context, MaskE0); - mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3); + mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3); } Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask); diff --git a/src/ARMeilleure/Instructions/SoftFloat.cs b/src/ARMeilleure/Instructions/SoftFloat.cs index e8f44ce30..05975d04f 100644 --- a/src/ARMeilleure/Instructions/SoftFloat.cs +++ b/src/ARMeilleure/Instructions/SoftFloat.cs @@ -175,10 +175,10 @@ namespace ARMeilleure.Instructions public static ushort FPRoundCv(double real, ExecutionContext context) { - const int minimumExp = -14; + const int MinimumExp = -14; - const int e = 5; - const int f = 10; + const int E = 5; + const int F = 10; bool sign; double mantissa; @@ -208,15 +208,15 @@ namespace ARMeilleure.Instructions exponent++; } - uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0); + uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0); if (biasedExp == 0u) { - mantissa /= Math.Pow(2d, minimumExp - exponent); + mantissa /= Math.Pow(2d, MinimumExp - exponent); } - uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f)); - double error = mantissa * Math.Pow(2d, f) - (double)intMant; + uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F)); + double error = mantissa * Math.Pow(2d, F) - (double)intMant; if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0)) { @@ -256,12 +256,12 @@ namespace ARMeilleure.Instructions { intMant++; - if (intMant == 1u << f) + if (intMant == 1u << F) { biasedExp = 1u; } - if (intMant == 1u << (f + 1)) + if (intMant == 1u << (F + 1)) { biasedExp++; intMant >>= 1; @@ -272,7 +272,7 @@ namespace ARMeilleure.Instructions if ((context.Fpcr & FPCR.Ahp) == 0) { - if (biasedExp >= (1u << e) - 1u) + if (biasedExp >= (1u << E) - 1u) { resultBits = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); @@ -287,7 +287,7 @@ namespace ARMeilleure.Instructions } else { - if (biasedExp >= 1u << e) + if (biasedExp >= 1u << E) { resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu); @@ -354,10 +354,10 @@ namespace ARMeilleure.Instructions private static float FPRoundCv(double real, ExecutionContext context) { - const int minimumExp = -126; + const int MinimumExp = -126; - const int e = 8; - const int f = 23; + const int E = 8; + const int F = 23; bool sign; double mantissa; @@ -387,22 +387,22 @@ namespace ARMeilleure.Instructions exponent++; } - if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp) + if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp) { context.Fpsr |= FPSR.Ufc; return SoftFloat32.FPZero(sign); } - uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0); + uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0); if (biasedExp == 0u) { - mantissa /= Math.Pow(2d, minimumExp - exponent); + mantissa /= Math.Pow(2d, MinimumExp - exponent); } - uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f)); - double error = mantissa * Math.Pow(2d, f) - (double)intMant; + uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F)); + double error = mantissa * Math.Pow(2d, F) - (double)intMant; if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0)) { @@ -442,12 +442,12 @@ namespace ARMeilleure.Instructions { intMant++; - if (intMant == 1u << f) + if (intMant == 1u << F) { biasedExp = 1u; } - if (intMant == 1u << (f + 1)) + if (intMant == 1u << (F + 1)) { biasedExp++; intMant >>= 1; @@ -456,7 +456,7 @@ namespace ARMeilleure.Instructions float result; - if (biasedExp >= (1u << e) - 1u) + if (biasedExp >= (1u << E) - 1u) { result = overflowToInf ? SoftFloat32.FPInfinity(sign) : SoftFloat32.FPMaxNormal(sign); @@ -529,10 +529,10 @@ namespace ARMeilleure.Instructions private static double FPRoundCv(double real, ExecutionContext context) { - const int minimumExp = -1022; + const int MinimumExp = -1022; - const int e = 11; - const int f = 52; + const int E = 11; + const int F = 52; bool sign; double mantissa; @@ -562,22 +562,22 @@ namespace ARMeilleure.Instructions exponent++; } - if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp) + if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp) { context.Fpsr |= FPSR.Ufc; return SoftFloat64.FPZero(sign); } - uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0); + uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0); if (biasedExp == 0u) { - mantissa /= Math.Pow(2d, minimumExp - exponent); + mantissa /= Math.Pow(2d, MinimumExp - exponent); } - ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, f)); - double error = mantissa * Math.Pow(2d, f) - (double)intMant; + ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, F)); + double error = mantissa * Math.Pow(2d, F) - (double)intMant; if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0)) { @@ -617,12 +617,12 @@ namespace ARMeilleure.Instructions { intMant++; - if (intMant == 1ul << f) + if (intMant == 1ul << F) { biasedExp = 1u; } - if (intMant == 1ul << (f + 1)) + if (intMant == 1ul << (F + 1)) { biasedExp++; intMant >>= 1; @@ -631,7 +631,7 @@ namespace ARMeilleure.Instructions double result; - if (biasedExp >= (1u << e) - 1u) + if (biasedExp >= (1u << E) - 1u) { result = overflowToInf ? SoftFloat64.FPInfinity(sign) : SoftFloat64.FPMaxNormal(sign); diff --git a/src/ARMeilleure/Signal/NativeSignalHandler.cs b/src/ARMeilleure/Signal/NativeSignalHandler.cs index ed284677d..3f0e9e4bf 100644 --- a/src/ARMeilleure/Signal/NativeSignalHandler.cs +++ b/src/ARMeilleure/Signal/NativeSignalHandler.cs @@ -5,7 +5,6 @@ using ARMeilleure.Translation.Cache; using System; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; - using static ARMeilleure.IntermediateRepresentation.Operand.Factory; namespace ARMeilleure.Signal @@ -261,20 +260,20 @@ namespace ARMeilleure.Signal { if (OperatingSystem.IsMacOS()) { - const ulong mcontextOffset = 48; // uc_mcontext - Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(mcontextOffset))); + const ulong McontextOffset = 48; // uc_mcontext + Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(McontextOffset))); if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64) { - const ulong esrOffset = 8; // __es.__esr - Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(esrOffset))); + const ulong EsrOffset = 8; // __es.__esr + Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(EsrOffset))); return context.BitwiseAnd(esr, Const(0x40ul)); } if (RuntimeInformation.ProcessArchitecture == Architecture.X64) { - const ulong errOffset = 4; // __es.__err - Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(errOffset))); + const ulong ErrOffset = 4; // __es.__err + Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(ErrOffset))); return context.BitwiseAnd(err, Const(2ul)); } } @@ -287,10 +286,10 @@ namespace ARMeilleure.Signal Operand loopLabel = Label(); Operand successLabel = Label(); - const ulong auxOffset = 464; // uc_mcontext.__reserved - const uint esrMagic = 0x45535201; + const ulong AuxOffset = 464; // uc_mcontext.__reserved + const uint EsrMagic = 0x45535201; - context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset))); + context.Copy(auxPtr, context.Add(ucontextPtr, Const(AuxOffset))); context.MarkLabel(loopLabel); @@ -299,7 +298,7 @@ namespace ARMeilleure.Signal // _aarch64_ctx::size Operand size = context.Load(OperandType.I32, context.Add(auxPtr, Const(4ul))); - context.BranchIf(successLabel, magic, Const(esrMagic), Comparison.Equal); + context.BranchIf(successLabel, magic, Const(EsrMagic), Comparison.Equal); context.Copy(auxPtr, context.Add(auxPtr, context.ZeroExtend32(OperandType.I64, size))); @@ -314,8 +313,8 @@ namespace ARMeilleure.Signal if (RuntimeInformation.ProcessArchitecture == Architecture.X64) { - const int errOffset = 192; // uc_mcontext.gregs[REG_ERR] - Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(errOffset))); + const int ErrOffset = 192; // uc_mcontext.gregs[REG_ERR] + Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(ErrOffset))); return context.BitwiseAnd(err, Const(2ul)); } } diff --git a/src/ARMeilleure/Translation/PTC/Ptc.cs b/src/ARMeilleure/Translation/PTC/Ptc.cs index 665f568d2..72b60fab0 100644 --- a/src/ARMeilleure/Translation/PTC/Ptc.cs +++ b/src/ARMeilleure/Translation/PTC/Ptc.cs @@ -880,7 +880,7 @@ namespace ARMeilleure.Translation.PTC private void ReportProgress(object state) { - const int refreshRate = 50; // ms. + const int RefreshRate = 50; // ms. AutoResetEvent endEvent = (AutoResetEvent)state; @@ -896,7 +896,7 @@ namespace ARMeilleure.Translation.PTC count = newCount; } } - while (!endEvent.WaitOne(refreshRate)); + while (!endEvent.WaitOne(RefreshRate)); } public static Hash128 ComputeHash(IMemoryManager memory, ulong address, ulong guestSize) diff --git a/src/Ryujinx.Audio/Renderer/Dsp/Command/CircularBufferSinkCommand.cs b/src/Ryujinx.Audio/Renderer/Dsp/Command/CircularBufferSinkCommand.cs index e50637eb3..59ef70932 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/Command/CircularBufferSinkCommand.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/Command/CircularBufferSinkCommand.cs @@ -43,7 +43,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command public void Process(CommandList context) { - const int targetChannelCount = 2; + const int TargetChannelCount = 2; ulong currentOffset = CurrentOffset; @@ -59,10 +59,10 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command for (int y = 0; y < context.SampleCount; y++) { - context.MemoryManager.Write(targetOffset + (ulong)y * targetChannelCount, PcmHelper.Saturate(inputBuffer[y])); + context.MemoryManager.Write(targetOffset + (ulong)y * TargetChannelCount, PcmHelper.Saturate(inputBuffer[y])); } - currentOffset += context.SampleCount * targetChannelCount; + currentOffset += context.SampleCount * TargetChannelCount; if (currentOffset >= CircularBufferSize) { @@ -73,4 +73,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Dsp/Command/DelayCommand.cs b/src/Ryujinx.Audio/Renderer/Dsp/Command/DelayCommand.cs index 6dc766594..e7e179389 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/Command/DelayCommand.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/Command/DelayCommand.cs @@ -56,7 +56,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command [MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)] private unsafe void ProcessDelayMono(ref DelayState state, float* outputBuffer, float* inputBuffer, uint sampleCount) { - const ushort channelCount = 1; + const ushort ChannelCount = 1; float feedbackGain = FixedPointHelper.ToFloat(Parameter.FeedbackGain, FixedPointPrecision); float inGain = FixedPointHelper.ToFloat(Parameter.InGain, FixedPointPrecision); @@ -70,7 +70,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command float temp = input * inGain + delayLineValue * feedbackGain; - state.UpdateLowPassFilter(ref temp, channelCount); + state.UpdateLowPassFilter(ref temp, ChannelCount); outputBuffer[i] = (input * dryGain + delayLineValue * outGain) / 64; } @@ -79,7 +79,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command [MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)] private unsafe void ProcessDelayStereo(ref DelayState state, Span outputBuffers, ReadOnlySpan inputBuffers, uint sampleCount) { - const ushort channelCount = 2; + const ushort ChannelCount = 2; float delayFeedbackBaseGain = state.DelayFeedbackBaseGain; float delayFeedbackCrossGain = state.DelayFeedbackCrossGain; @@ -106,7 +106,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command Vector2 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain; - state.UpdateLowPassFilter(ref Unsafe.As(ref temp), channelCount); + state.UpdateLowPassFilter(ref Unsafe.As(ref temp), ChannelCount); *((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64; *((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64; @@ -116,7 +116,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command [MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)] private unsafe void ProcessDelayQuadraphonic(ref DelayState state, Span outputBuffers, ReadOnlySpan inputBuffers, uint sampleCount) { - const ushort channelCount = 4; + const ushort ChannelCount = 4; float delayFeedbackBaseGain = state.DelayFeedbackBaseGain; float delayFeedbackCrossGain = state.DelayFeedbackCrossGain; @@ -150,7 +150,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command Vector4 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain; - state.UpdateLowPassFilter(ref Unsafe.As(ref temp), channelCount); + state.UpdateLowPassFilter(ref Unsafe.As(ref temp), ChannelCount); *((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64; *((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64; @@ -162,7 +162,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command [MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)] private unsafe void ProcessDelaySurround(ref DelayState state, Span outputBuffers, ReadOnlySpan inputBuffers, uint sampleCount) { - const ushort channelCount = 6; + const ushort ChannelCount = 6; float feedbackGain = FixedPointHelper.ToFloat(Parameter.FeedbackGain, FixedPointPrecision); float delayFeedbackBaseGain = state.DelayFeedbackBaseGain; @@ -202,7 +202,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command Vector6 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain; - state.UpdateLowPassFilter(ref Unsafe.As(ref temp), channelCount); + state.UpdateLowPassFilter(ref Unsafe.As(ref temp), ChannelCount); *((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64; *((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64; @@ -277,4 +277,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command ProcessDelay(context, ref state); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Dsp/Command/DeviceSinkCommand.cs b/src/Ryujinx.Audio/Renderer/Dsp/Command/DeviceSinkCommand.cs index 27bb34bf3..19afc66f4 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/Command/DeviceSinkCommand.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/Command/DeviceSinkCommand.cs @@ -65,7 +65,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command int channelCount = (int)device.GetChannelCount(); uint bufferCount = Math.Min(device.GetChannelCount(), InputCount); - const int sampleCount = Constants.TargetSampleCount; + const int SampleCount = Constants.TargetSampleCount; uint inputCount; @@ -79,13 +79,13 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command inputCount = bufferCount; } - short[] outputBuffer = new short[inputCount * sampleCount]; + short[] outputBuffer = new short[inputCount * SampleCount]; for (int i = 0; i < bufferCount; i++) { - ReadOnlySpan inputBuffer = GetBuffer(InputBufferIndices[i], sampleCount); + ReadOnlySpan inputBuffer = GetBuffer(InputBufferIndices[i], SampleCount); - for (int j = 0; j < sampleCount; j++) + for (int j = 0; j < SampleCount; j++) { outputBuffer[i + j * channelCount] = PcmHelper.Saturate(inputBuffer[j]); } @@ -100,4 +100,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Dsp/Command/Reverb3dCommand.cs b/src/Ryujinx.Audio/Renderer/Dsp/Command/Reverb3dCommand.cs index 74b53b24b..d1177e60f 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/Command/Reverb3dCommand.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/Command/Reverb3dCommand.cs @@ -96,7 +96,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command private unsafe void ProcessReverb3dGeneric(ref Reverb3dState state, ReadOnlySpan outputBuffers, ReadOnlySpan inputBuffers, uint sampleCount, ReadOnlySpan outputEarlyIndicesTable, ReadOnlySpan targetEarlyDelayLineIndicesTable, ReadOnlySpan targetOutputFeedbackIndicesTable) { - const int delayLineSampleIndexOffset = 1; + const int DelayLineSampleIndexOffset = 1; bool isMono = Parameter.ChannelCount == 1; bool isSurround = Parameter.ChannelCount == 6; @@ -111,14 +111,14 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command { outputValues.Fill(0); - float tapOut = state.PreDelayLine.TapUnsafe(state.ReflectionDelayTime, delayLineSampleIndexOffset); + float tapOut = state.PreDelayLine.TapUnsafe(state.ReflectionDelayTime, DelayLineSampleIndexOffset); for (int i = 0; i < targetEarlyDelayLineIndicesTable.Length; i++) { int earlyDelayIndex = targetEarlyDelayLineIndicesTable[i]; int outputIndex = outputEarlyIndicesTable[earlyDelayIndex]; - float tempTapOut = state.PreDelayLine.TapUnsafe(state.EarlyDelayTime[earlyDelayIndex], delayLineSampleIndexOffset); + float tempTapOut = state.PreDelayLine.TapUnsafe(state.EarlyDelayTime[earlyDelayIndex], DelayLineSampleIndexOffset); outputValues[outputIndex] += tempTapOut * state.EarlyGain[earlyDelayIndex]; } @@ -251,4 +251,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command ProcessReverb3d(context, ref state); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Dsp/DataSourceHelper.cs b/src/Ryujinx.Audio/Renderer/Dsp/DataSourceHelper.cs index 721830c9a..12e0f13ff 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/DataSourceHelper.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/DataSourceHelper.cs @@ -44,9 +44,9 @@ namespace Ryujinx.Audio.Renderer.Dsp public static void ProcessWaveBuffers(IVirtualMemoryManager memoryManager, Span outputBuffer, ref WaveBufferInformation info, Span wavebuffers, ref VoiceUpdateState voiceState, uint targetSampleRate, int sampleCount) { - const int tempBufferSize = 0x3F00; + const int TempBufferSize = 0x3F00; - Span tempBuffer = stackalloc short[tempBufferSize]; + Span tempBuffer = stackalloc short[TempBufferSize]; float sampleRateRatio = (float)info.SourceSampleRate / targetSampleRate * info.Pitch; @@ -60,11 +60,11 @@ namespace Ryujinx.Audio.Renderer.Dsp int totalNeededSize = (int)MathF.Truncate(fraction + sampleRateRatio * sampleCount); - if (totalNeededSize + pitchMaxLength <= tempBufferSize && totalNeededSize >= 0) + if (totalNeededSize + pitchMaxLength <= TempBufferSize && totalNeededSize >= 0) { int sourceSampleCountToProcess = sampleCount; - int maxSampleCountPerIteration = Math.Min((int)MathF.Truncate((tempBufferSize - fraction) / sampleRateRatio), sampleCount); + int maxSampleCountPerIteration = Math.Min((int)MathF.Truncate((TempBufferSize - fraction) / sampleRateRatio), sampleCount); bool isStarving = false; @@ -463,4 +463,4 @@ namespace Ryujinx.Audio.Renderer.Dsp } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Dsp/UpsamplerHelper.cs b/src/Ryujinx.Audio/Renderer/Dsp/UpsamplerHelper.cs index 6cdab5a7b..54a63ace0 100644 --- a/src/Ryujinx.Audio/Renderer/Dsp/UpsamplerHelper.cs +++ b/src/Ryujinx.Audio/Renderer/Dsp/UpsamplerHelper.cs @@ -32,13 +32,13 @@ namespace Ryujinx.Audio.Renderer.Dsp float BlackmanWindow(float x) { - const float a = 0.18f; - const float a0 = 0.5f - 0.5f * a; - const float a1 = -0.5f; - const float a2 = 0.5f * a; - return a0 + a1 * MathF.Cos(2 * MathF.PI * x) + a2 * MathF.Cos(4 * MathF.PI * x); + const float A = 0.18f; + const float A0 = 0.5f - 0.5f * A; + const float A1 = -0.5f; + const float A2 = 0.5f * A; + return A0 + A1 * MathF.Cos(2 * MathF.PI * x) + A2 * MathF.Cos(4 * MathF.PI * x); } - + Array20 result = new Array20(); for (int i = 0; i < FilterBankLength; i++) @@ -112,7 +112,7 @@ namespace Ryujinx.Audio.Renderer.Dsp int inputBufferIndex = 0; switch (state.Scale) - { + { case 6.0f: for (int i = 0; i < outputSampleCount; i++) { @@ -189,4 +189,4 @@ namespace Ryujinx.Audio.Renderer.Dsp } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Server/CommandProcessingTimeEstimatorVersion2.cs b/src/Ryujinx.Audio/Renderer/Server/CommandProcessingTimeEstimatorVersion2.cs index 7ee491cd6..d4f28a07d 100644 --- a/src/Ryujinx.Audio/Renderer/Server/CommandProcessingTimeEstimatorVersion2.cs +++ b/src/Ryujinx.Audio/Renderer/Server/CommandProcessingTimeEstimatorVersion2.cs @@ -60,7 +60,7 @@ namespace Ryujinx.Audio.Renderer.Server public uint Estimate(MixRampGroupedCommand command) { - const float costPerSample = 7.245f; + const float CostPerSample = 7.245f; Debug.Assert(_sampleCount == 160 || _sampleCount == 240); @@ -74,7 +74,7 @@ namespace Ryujinx.Audio.Renderer.Server } } - return (uint)(_sampleCount * costPerSample * volumeCount); + return (uint)(_sampleCount * CostPerSample * volumeCount); } public uint Estimate(MixRampCommand command) @@ -549,4 +549,4 @@ namespace Ryujinx.Audio.Renderer.Server return 0; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Audio/Renderer/Server/MemoryPool/PoolMapper.cs b/src/Ryujinx.Audio/Renderer/Server/MemoryPool/PoolMapper.cs index 6c79da157..4a29ead3e 100644 --- a/src/Ryujinx.Audio/Renderer/Server/MemoryPool/PoolMapper.cs +++ b/src/Ryujinx.Audio/Renderer/Server/MemoryPool/PoolMapper.cs @@ -256,19 +256,19 @@ namespace Ryujinx.Audio.Renderer.Server.MemoryPool MemoryPoolUserState outputState; - const uint pageSize = 0x1000; + const uint PageSize = 0x1000; if (inputState != MemoryPoolUserState.RequestAttach && inputState != MemoryPoolUserState.RequestDetach) { return UpdateResult.Success; } - if (inParameter.CpuAddress == 0 || (inParameter.CpuAddress % pageSize) != 0) + if (inParameter.CpuAddress == 0 || (inParameter.CpuAddress % PageSize) != 0) { return UpdateResult.InvalidParameter; } - if (inParameter.Size == 0 || (inParameter.Size % pageSize) != 0) + if (inParameter.Size == 0 || (inParameter.Size % PageSize) != 0) { return UpdateResult.InvalidParameter; } @@ -363,4 +363,4 @@ namespace Ryujinx.Audio.Renderer.Server.MemoryPool } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Ava/UI/Controls/ApplicationContextMenu.axaml.cs b/src/Ryujinx.Ava/UI/Controls/ApplicationContextMenu.axaml.cs index 73c53e7f6..fba24d68b 100644 --- a/src/Ryujinx.Ava/UI/Controls/ApplicationContextMenu.axaml.cs +++ b/src/Ryujinx.Ava/UI/Controls/ApplicationContextMenu.axaml.cs @@ -10,8 +10,8 @@ using Ryujinx.Ava.UI.Helpers; using Ryujinx.Ava.UI.ViewModels; using Ryujinx.Ava.UI.Windows; using Ryujinx.Common.Configuration; -using Ryujinx.Ui.App.Common; using Ryujinx.HLE.HOS; +using Ryujinx.Ui.App.Common; using Ryujinx.Ui.Common.Helper; using System; using System.Collections.Generic; diff --git a/src/Ryujinx.Ava/UI/Models/SaveModel.cs b/src/Ryujinx.Ava/UI/Models/SaveModel.cs index ab919c88d..e8486459b 100644 --- a/src/Ryujinx.Ava/UI/Models/SaveModel.cs +++ b/src/Ryujinx.Ava/UI/Models/SaveModel.cs @@ -40,9 +40,9 @@ namespace Ryujinx.Ava.UI.Models private string GetSizeString() { - const int scale = 1024; + const int Scale = 1024; string[] orders = { "GiB", "MiB", "KiB" }; - long max = (long)Math.Pow(scale, orders.Length); + long max = (long)Math.Pow(Scale, orders.Length); foreach (string order in orders) { @@ -51,7 +51,7 @@ namespace Ryujinx.Ava.UI.Models return $"{decimal.Divide(Size, max):##.##} {order}"; } - max /= scale; + max /= Scale; } return "0 KiB"; @@ -109,4 +109,4 @@ namespace Ryujinx.Ava.UI.Models } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Ava/UI/ViewModels/MainWindowViewModel.cs b/src/Ryujinx.Ava/UI/ViewModels/MainWindowViewModel.cs index 409ccad3c..0976e2fae 100644 --- a/src/Ryujinx.Ava/UI/ViewModels/MainWindowViewModel.cs +++ b/src/Ryujinx.Ava/UI/ViewModels/MainWindowViewModel.cs @@ -622,7 +622,7 @@ namespace Ryujinx.Ava.UI.ViewModels OnPropertyChanged(); } } - + public double WindowWidth { get => _windowWidth; @@ -1124,13 +1124,13 @@ namespace Ryujinx.Ava.UI.ViewModels var dominantColor = IconColorPicker.GetFilteredColor(gameIconBmp).ToPixel(); - const float colorMultiple = 0.5f; + const float ColorMultiple = 0.5f; Color progressFgColor = Color.FromRgb(dominantColor.R, dominantColor.G, dominantColor.B); Color progressBgColor = Color.FromRgb( - (byte)(dominantColor.R * colorMultiple), - (byte)(dominantColor.G * colorMultiple), - (byte)(dominantColor.B * colorMultiple)); + (byte)(dominantColor.R * ColorMultiple), + (byte)(dominantColor.G * ColorMultiple), + (byte)(dominantColor.B * ColorMultiple)); ProgressBarForegroundColor = new SolidColorBrush(progressFgColor); ProgressBarBackgroundColor = new SolidColorBrush(progressBgColor); @@ -1677,4 +1677,4 @@ namespace Ryujinx.Ava.UI.ViewModels #endregion } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Ava/UI/ViewModels/SettingsViewModel.cs b/src/Ryujinx.Ava/UI/ViewModels/SettingsViewModel.cs index d260b6fc7..0a2ffae3b 100644 --- a/src/Ryujinx.Ava/UI/ViewModels/SettingsViewModel.cs +++ b/src/Ryujinx.Ava/UI/ViewModels/SettingsViewModel.cs @@ -18,14 +18,14 @@ using Ryujinx.HLE.FileSystem; using Ryujinx.HLE.HOS.Services.Time.TimeZone; using Ryujinx.Ui.Common.Configuration; using Ryujinx.Ui.Common.Configuration.System; +using Silk.NET.Vulkan; using System; using System.Collections.Generic; using System.Collections.ObjectModel; using System.Linq; -using System.Runtime.InteropServices; using System.Net.NetworkInformation; +using System.Runtime.InteropServices; using TimeZone = Ryujinx.Ava.UI.Models.TimeZone; -using Silk.NET.Vulkan; namespace Ryujinx.Ava.UI.ViewModels { diff --git a/src/Ryujinx.Common/SystemInfo/MacOSSystemInfo.cs b/src/Ryujinx.Common/SystemInfo/MacOSSystemInfo.cs index 06324a54c..168960f71 100644 --- a/src/Ryujinx.Common/SystemInfo/MacOSSystemInfo.cs +++ b/src/Ryujinx.Common/SystemInfo/MacOSSystemInfo.cs @@ -44,10 +44,10 @@ namespace Ryujinx.Common.SystemInfo return 0; } - const int flavor = 4; // HOST_VM_INFO64 + const int Flavor = 4; // HOST_VM_INFO64 uint count = (uint)(Marshal.SizeOf() / sizeof(int)); // HOST_VM_INFO64_COUNT VMStatistics64 stats = new(); - result = host_statistics64(port, flavor, ref stats, ref count); + result = host_statistics64(port, Flavor, ref stats, ref count); if (result != 0) { @@ -154,4 +154,4 @@ namespace Ryujinx.Common.SystemInfo [LibraryImport(SystemLibraryName, SetLastError = true)] private static partial int host_statistics64(uint host_priv, int host_flavor, ref VMStatistics64 host_info64_out, ref uint host_info64_outCnt); } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Common/SystemInterop/StdErrAdapter.cs b/src/Ryujinx.Common/SystemInterop/StdErrAdapter.cs index b1ed7b689..4802178e2 100644 --- a/src/Ryujinx.Common/SystemInterop/StdErrAdapter.cs +++ b/src/Ryujinx.Common/SystemInterop/StdErrAdapter.cs @@ -29,10 +29,10 @@ namespace Ryujinx.Common.SystemInterop [SupportedOSPlatform("macos")] private void RegisterPosix() { - const int stdErrFileno = 2; + const int StdErrFileno = 2; (int readFd, int writeFd) = MakePipe(); - dup2(writeFd, stdErrFileno); + dup2(writeFd, StdErrFileno); _pipeReader = CreateFileDescriptorStream(readFd); _pipeWriter = CreateFileDescriptorStream(writeFd); diff --git a/src/Ryujinx.Graphics.Gpu/Memory/PhysicalMemory.cs b/src/Ryujinx.Graphics.Gpu/Memory/PhysicalMemory.cs index 364488aae..cb95b04a8 100644 --- a/src/Ryujinx.Graphics.Gpu/Memory/PhysicalMemory.cs +++ b/src/Ryujinx.Graphics.Gpu/Memory/PhysicalMemory.cs @@ -6,8 +6,8 @@ using Ryujinx.Memory.Range; using Ryujinx.Memory.Tracking; using System; using System.Collections.Generic; -using System.Runtime.InteropServices; using System.Linq; +using System.Runtime.InteropServices; using System.Threading; namespace Ryujinx.Graphics.Gpu.Memory diff --git a/src/Ryujinx.Graphics.Vulkan/BufferManager.cs b/src/Ryujinx.Graphics.Vulkan/BufferManager.cs index 521a132a7..1b55909d3 100644 --- a/src/Ryujinx.Graphics.Vulkan/BufferManager.cs +++ b/src/Ryujinx.Graphics.Vulkan/BufferManager.cs @@ -4,8 +4,8 @@ using Silk.NET.Vulkan; using System; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; -using VkFormat = Silk.NET.Vulkan.Format; using VkBuffer = Silk.NET.Vulkan.Buffer; +using VkFormat = Silk.NET.Vulkan.Format; namespace Ryujinx.Graphics.Vulkan { diff --git a/src/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs b/src/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs index 1b3968eab..e21c28145 100644 --- a/src/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs +++ b/src/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs @@ -354,8 +354,8 @@ namespace Ryujinx.HLE.FileSystem if (info.SpaceId != SaveDataSpaceId.User && info.SpaceId != SaveDataSpaceId.System) return Result.Success; - const string mountName = "SaveDir"; - var mountNameU8 = mountName.ToU8Span(); + const string MountName = "SaveDir"; + var mountNameU8 = MountName.ToU8Span(); BisPartitionId partitionId = info.SpaceId switch { @@ -368,7 +368,7 @@ namespace Ryujinx.HLE.FileSystem if (rc.IsFailure()) return rc; try { - var path = $"{mountName}:/save/{info.SaveDataId:x16}".ToU8Span(); + var path = $"{MountName}:/save/{info.SaveDataId:x16}".ToU8Span(); rc = hos.Fs.GetEntryType(out _, path); @@ -612,4 +612,4 @@ namespace Ryujinx.HLE.FileSystem } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.HLE/HOS/Horizon.cs b/src/Ryujinx.HLE/HOS/Horizon.cs index 166761c2c..2f163fa22 100644 --- a/src/Ryujinx.HLE/HOS/Horizon.cs +++ b/src/Ryujinx.HLE/HOS/Horizon.cs @@ -332,13 +332,13 @@ namespace Ryujinx.HLE.HOS foreach (var service in services) { - const ProcessCreationFlags flags = + const ProcessCreationFlags Flags = ProcessCreationFlags.EnableAslr | ProcessCreationFlags.AddressSpace64Bit | ProcessCreationFlags.Is64Bit | ProcessCreationFlags.PoolPartitionSystem; - ProcessCreationInfo creationInfo = new ProcessCreationInfo("Service", 1, 0, 0x8000000, 1, flags, 0, 0); + ProcessCreationInfo creationInfo = new ProcessCreationInfo("Service", 1, 0, 0x8000000, 1, Flags, 0, 0); uint[] defaultCapabilities = new uint[] { @@ -554,4 +554,4 @@ namespace Ryujinx.HLE.HOS IsPaused = pause; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.HLE/HOS/Services/Hid/Hid.cs b/src/Ryujinx.HLE/HOS/Services/Hid/Hid.cs index b1466c787..e4755f787 100644 --- a/src/Ryujinx.HLE/HOS/Services/Hid/Hid.cs +++ b/src/Ryujinx.HLE/HOS/Services/Hid/Hid.cs @@ -83,18 +83,18 @@ namespace Ryujinx.HLE.HOS.Services.Hid public ControllerKeys UpdateStickButtons(JoystickPosition leftStick, JoystickPosition rightStick) { - const int stickButtonThreshold = short.MaxValue / 2; + const int StickButtonThreshold = short.MaxValue / 2; ControllerKeys result = 0; - result |= (leftStick.Dx < -stickButtonThreshold) ? ControllerKeys.LStickLeft : result; - result |= (leftStick.Dx > stickButtonThreshold) ? ControllerKeys.LStickRight : result; - result |= (leftStick.Dy < -stickButtonThreshold) ? ControllerKeys.LStickDown : result; - result |= (leftStick.Dy > stickButtonThreshold) ? ControllerKeys.LStickUp : result; + result |= (leftStick.Dx < -StickButtonThreshold) ? ControllerKeys.LStickLeft : result; + result |= (leftStick.Dx > StickButtonThreshold) ? ControllerKeys.LStickRight : result; + result |= (leftStick.Dy < -StickButtonThreshold) ? ControllerKeys.LStickDown : result; + result |= (leftStick.Dy > StickButtonThreshold) ? ControllerKeys.LStickUp : result; - result |= (rightStick.Dx < -stickButtonThreshold) ? ControllerKeys.RStickLeft : result; - result |= (rightStick.Dx > stickButtonThreshold) ? ControllerKeys.RStickRight : result; - result |= (rightStick.Dy < -stickButtonThreshold) ? ControllerKeys.RStickDown : result; - result |= (rightStick.Dy > stickButtonThreshold) ? ControllerKeys.RStickUp : result; + result |= (rightStick.Dx < -StickButtonThreshold) ? ControllerKeys.RStickLeft : result; + result |= (rightStick.Dx > StickButtonThreshold) ? ControllerKeys.RStickRight : result; + result |= (rightStick.Dy < -StickButtonThreshold) ? ControllerKeys.RStickDown : result; + result |= (rightStick.Dy > StickButtonThreshold) ? ControllerKeys.RStickUp : result; return result; } diff --git a/src/Ryujinx.HLE/HOS/Services/Mii/Helper.cs b/src/Ryujinx.HLE/HOS/Services/Mii/Helper.cs index b02bbfd18..b8dbce155 100644 --- a/src/Ryujinx.HLE/HOS/Services/Mii/Helper.cs +++ b/src/Ryujinx.HLE/HOS/Services/Mii/Helper.cs @@ -8,7 +8,7 @@ namespace Ryujinx.HLE.HOS.Services.Mii { public static ushort CalculateCrc16(ReadOnlySpan data, int crc, bool reverseEndianess) { - const ushort poly = 0x1021; + const ushort Poly = 0x1021; for (int i = 0; i < data.Length; i++) { @@ -20,7 +20,7 @@ namespace Ryujinx.HLE.HOS.Services.Mii if ((crc & 0x10000) != 0) { - crc = (crc ^ poly) & 0xFFFF; + crc = (crc ^ Poly) & 0xFFFF; } } } diff --git a/src/Ryujinx.HLE/HOS/Services/Sdb/Pl/SharedFontManager.cs b/src/Ryujinx.HLE/HOS/Services/Sdb/Pl/SharedFontManager.cs index fef82cbc4..c0556c316 100644 --- a/src/Ryujinx.HLE/HOS/Services/Sdb/Pl/SharedFontManager.cs +++ b/src/Ryujinx.HLE/HOS/Services/Sdb/Pl/SharedFontManager.cs @@ -134,9 +134,9 @@ namespace Ryujinx.HLE.HOS.Services.Sdb.Pl private void WriteMagicAndSize(ulong offset, int size) { - const int key = 0x49621806; + const int Key = 0x49621806; - int encryptedSize = BinaryPrimitives.ReverseEndianness(size ^ key); + int encryptedSize = BinaryPrimitives.ReverseEndianness(size ^ Key); _storage.GetRef(offset + 0) = (int)BFTTFMagic; _storage.GetRef(offset + 4) = encryptedSize; @@ -180,4 +180,4 @@ namespace Ryujinx.HLE.HOS.Services.Sdb.Pl } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.HLE/HOS/Services/ServerBase.cs b/src/Ryujinx.HLE/HOS/Services/ServerBase.cs index ff6df8a38..f8ce465f9 100644 --- a/src/Ryujinx.HLE/HOS/Services/ServerBase.cs +++ b/src/Ryujinx.HLE/HOS/Services/ServerBase.cs @@ -70,13 +70,13 @@ namespace Ryujinx.HLE.HOS.Services Name = name; SmObjectFactory = smObjectFactory; - const ProcessCreationFlags flags = + const ProcessCreationFlags Flags = ProcessCreationFlags.EnableAslr | ProcessCreationFlags.AddressSpace64Bit | ProcessCreationFlags.Is64Bit | ProcessCreationFlags.PoolPartitionSystem; - ProcessCreationInfo creationInfo = new ProcessCreationInfo("Service", 1, 0, 0x8000000, 1, flags, 0, 0); + ProcessCreationInfo creationInfo = new ProcessCreationInfo("Service", 1, 0, 0x8000000, 1, Flags, 0, 0); KernelStatic.StartInitialProcess(context, creationInfo, DefaultCapabilities, 44, Main); } diff --git a/src/Ryujinx.HLE/HOS/Services/Settings/ISystemSettingsServer.cs b/src/Ryujinx.HLE/HOS/Services/Settings/ISystemSettingsServer.cs index ef95fa5cb..07c9f6b3b 100644 --- a/src/Ryujinx.HLE/HOS/Services/Settings/ISystemSettingsServer.cs +++ b/src/Ryujinx.HLE/HOS/Services/Settings/ISystemSettingsServer.cs @@ -43,43 +43,43 @@ namespace Ryujinx.HLE.HOS.Services.Settings return ResultCode.Success; } - const byte majorFwVersion = 0x03; - const byte minorFwVersion = 0x00; - const byte microFwVersion = 0x00; - const byte unknown = 0x00; //Build? + const byte MajorFwVersion = 0x03; + const byte MinorFwVersion = 0x00; + const byte MicroFwVersion = 0x00; + const byte Unknown = 0x00; //Build? - const int revisionNumber = 0x0A; + const int RevisionNumber = 0x0A; - const string platform = "NX"; - const string unknownHex = "7fbde2b0bba4d14107bf836e4643043d9f6c8e47"; - const string version = "3.0.0"; - const string build = "NintendoSDK Firmware for NX 3.0.0-10.0"; + const string Platform = "NX"; + const string UnknownHex = "7fbde2b0bba4d14107bf836e4643043d9f6c8e47"; + const string Version = "3.0.0"; + const string Build = "NintendoSDK Firmware for NX 3.0.0-10.0"; // http://switchbrew.org/index.php?title=System_Version_Title using (MemoryStream ms = new MemoryStream(0x100)) { BinaryWriter writer = new BinaryWriter(ms); - writer.Write(majorFwVersion); - writer.Write(minorFwVersion); - writer.Write(microFwVersion); - writer.Write(unknown); + writer.Write(MajorFwVersion); + writer.Write(MinorFwVersion); + writer.Write(MicroFwVersion); + writer.Write(Unknown); - writer.Write(revisionNumber); + writer.Write(RevisionNumber); - writer.Write(Encoding.ASCII.GetBytes(platform)); + writer.Write(Encoding.ASCII.GetBytes(Platform)); ms.Seek(0x28, SeekOrigin.Begin); - writer.Write(Encoding.ASCII.GetBytes(unknownHex)); + writer.Write(Encoding.ASCII.GetBytes(UnknownHex)); ms.Seek(0x68, SeekOrigin.Begin); - writer.Write(Encoding.ASCII.GetBytes(version)); + writer.Write(Encoding.ASCII.GetBytes(Version)); ms.Seek(0x80, SeekOrigin.Begin); - writer.Write(Encoding.ASCII.GetBytes(build)); + writer.Write(Encoding.ASCII.GetBytes(Build)); context.Memory.Write(replyPos, ms.ToArray()); } diff --git a/src/Ryujinx.HLE/HOS/Services/Vi/RootService/IApplicationDisplayService.cs b/src/Ryujinx.HLE/HOS/Services/Vi/RootService/IApplicationDisplayService.cs index 52ed52220..89eed5b57 100644 --- a/src/Ryujinx.HLE/HOS/Services/Vi/RootService/IApplicationDisplayService.cs +++ b/src/Ryujinx.HLE/HOS/Services/Vi/RootService/IApplicationDisplayService.cs @@ -354,16 +354,16 @@ namespace Ryujinx.HLE.HOS.Services.Vi.RootService private ulong GetA8B8G8R8LayerSize(int width, int height, out int pitch, out int alignment) { - const int defaultAlignment = 0x1000; - const ulong defaultSize = 0x20000; + const int DefaultAlignment = 0x1000; + const ulong DefaultSize = 0x20000; - alignment = defaultAlignment; + alignment = DefaultAlignment; pitch = BitUtils.AlignUp(BitUtils.DivRoundUp(width * 32, 8), 64); int memorySize = pitch * BitUtils.AlignUp(height, 64); ulong requiredMemorySize = (ulong)BitUtils.AlignUp(memorySize, alignment); - return (requiredMemorySize + defaultSize - 1) / defaultSize * defaultSize; + return (requiredMemorySize + DefaultSize - 1) / DefaultSize * DefaultSize; } [CommandCmif(2450)] @@ -484,4 +484,4 @@ namespace Ryujinx.HLE.HOS.Services.Vi.RootService return ResultCode.Success; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.HLE/HOS/Tamper/InstructionHelper.cs b/src/Ryujinx.HLE/HOS/Tamper/InstructionHelper.cs index e85d99c76..a31c055fa 100644 --- a/src/Ryujinx.HLE/HOS/Tamper/InstructionHelper.cs +++ b/src/Ryujinx.HLE/HOS/Tamper/InstructionHelper.cs @@ -96,14 +96,14 @@ namespace Ryujinx.HLE.HOS.Tamper public static byte[] ParseRawInstruction(string rawInstruction) { - const int wordSize = 2 * sizeof(uint); + const int WordSize = 2 * sizeof(uint); // Instructions are multi-word, with 32bit words. Split the raw instruction // and parse each word into individual nybbles of bits. var words = rawInstruction.Split((char[])null, StringSplitOptions.RemoveEmptyEntries); - byte[] instruction = new byte[wordSize * words.Length]; + byte[] instruction = new byte[WordSize * words.Length]; if (words.Length == 0) { @@ -114,14 +114,14 @@ namespace Ryujinx.HLE.HOS.Tamper { string word = words[wordIndex]; - if (word.Length != wordSize) + if (word.Length != WordSize) { throw new TamperCompilationException($"Invalid word length for {word} in Atmosphere cheat"); } - for (int nybbleIndex = 0; nybbleIndex < wordSize; nybbleIndex++) + for (int nybbleIndex = 0; nybbleIndex < WordSize; nybbleIndex++) { - int index = wordIndex * wordSize + nybbleIndex; + int index = wordIndex * WordSize + nybbleIndex; instruction[index] = byte.Parse(word.AsSpan(nybbleIndex, 1), NumberStyles.HexNumber, CultureInfo.InvariantCulture); } diff --git a/src/Ryujinx.Tests.Memory/MultiRegionTrackingTests.cs b/src/Ryujinx.Tests.Memory/MultiRegionTrackingTests.cs index dffbe74d8..a97571293 100644 --- a/src/Ryujinx.Tests.Memory/MultiRegionTrackingTests.cs +++ b/src/Ryujinx.Tests.Memory/MultiRegionTrackingTests.cs @@ -100,14 +100,14 @@ namespace Ryujinx.Tests.Memory [Test] public void DirtyRegionOrdering([Values] bool smart) { - const int pageCount = 32; - IMultiRegionHandle handle = GetGranular(smart, 0, PageSize * pageCount, PageSize); + const int PageCount = 32; + IMultiRegionHandle handle = GetGranular(smart, 0, PageSize * PageCount, PageSize); Random random = new(); - PreparePages(handle, pageCount); + PreparePages(handle, PageCount); - IEnumerable halfRange = Enumerable.Range(0, pageCount / 2); + IEnumerable halfRange = Enumerable.Range(0, PageCount / 2); List odd = halfRange.Select(x => x * 2 + 1).ToList(); List even = halfRange.Select(x => x * 2).ToList(); @@ -117,9 +117,9 @@ namespace Ryujinx.Tests.Memory _tracking.VirtualMemoryEvent((ulong)i * PageSize, PageSize, true); }); - int oddRegionCount = ExpectQueryInOrder(handle, 0, PageSize * pageCount, (address) => (address / PageSize) % 2 == 1); + int oddRegionCount = ExpectQueryInOrder(handle, 0, PageSize * PageCount, (address) => (address / PageSize) % 2 == 1); - Assert.AreEqual(oddRegionCount, pageCount / 2); // Must have written to all odd pages. + Assert.AreEqual(oddRegionCount, PageCount / 2); // Must have written to all odd pages. // Write to all the even pages. RandomOrder(random, even, (i) => @@ -127,9 +127,9 @@ namespace Ryujinx.Tests.Memory _tracking.VirtualMemoryEvent((ulong)i * PageSize, PageSize, true); }); - int evenRegionCount = ExpectQueryInOrder(handle, 0, PageSize * pageCount, (address) => (address / PageSize) % 2 == 0); + int evenRegionCount = ExpectQueryInOrder(handle, 0, PageSize * PageCount, (address) => (address / PageSize) % 2 == 0); - Assert.AreEqual(evenRegionCount, pageCount / 2); + Assert.AreEqual(evenRegionCount, PageCount / 2); } [Test] @@ -142,14 +142,14 @@ namespace Ryujinx.Tests.Memory // This is useful for situations where we know that the data was complete when the sequence number was set. // ...essentially, when that data can only be updated on a future sequence number. - const int pageCount = 32; - IMultiRegionHandle handle = GetGranular(smart, 0, PageSize * pageCount, PageSize); + const int PageCount = 32; + IMultiRegionHandle handle = GetGranular(smart, 0, PageSize * PageCount, PageSize); - PreparePages(handle, pageCount); + PreparePages(handle, PageCount); Random random = new(); - IEnumerable halfRange = Enumerable.Range(0, pageCount / 2); + IEnumerable halfRange = Enumerable.Range(0, PageCount / 2); List odd = halfRange.Select(x => x * 2 + 1).ToList(); List even = halfRange.Select(x => x * 2).ToList(); @@ -172,29 +172,29 @@ namespace Ryujinx.Tests.Memory }, 1); } - Assert.AreEqual(oddRegionCount, pageCount / 2); // Must have written to all odd pages. + Assert.AreEqual(oddRegionCount, PageCount / 2); // Must have written to all odd pages. // Write to all pages. - _tracking.VirtualMemoryEvent(0, PageSize * pageCount, true); + _tracking.VirtualMemoryEvent(0, PageSize * PageCount, true); // Only the even regions should be reported for sequence number 1. - int evenRegionCount = ExpectQueryInOrder(handle, 0, PageSize * pageCount, (address) => (address / PageSize) % 2 == 0, 1); + int evenRegionCount = ExpectQueryInOrder(handle, 0, PageSize * PageCount, (address) => (address / PageSize) % 2 == 0, 1); - Assert.AreEqual(evenRegionCount, pageCount / 2); // Must have written to all even pages. + Assert.AreEqual(evenRegionCount, PageCount / 2); // Must have written to all even pages. oddRegionCount = 0; - handle.QueryModified(0, PageSize * pageCount, (address, range) => { oddRegionCount++; }, 1); + handle.QueryModified(0, PageSize * PageCount, (address, range) => { oddRegionCount++; }, 1); Assert.AreEqual(oddRegionCount, 0); // Sequence number has not changed, so found no dirty subregions. // With sequence number 2, all all pages should be reported as modified. - oddRegionCount = ExpectQueryInOrder(handle, 0, PageSize * pageCount, (address) => (address / PageSize) % 2 == 1, 2); + oddRegionCount = ExpectQueryInOrder(handle, 0, PageSize * PageCount, (address) => (address / PageSize) % 2 == 1, 2); - Assert.AreEqual(oddRegionCount, pageCount / 2); // Must have written to all odd pages. + Assert.AreEqual(oddRegionCount, PageCount / 2); // Must have written to all odd pages. } [Test] @@ -203,8 +203,8 @@ namespace Ryujinx.Tests.Memory // Smart multi region handles dynamically change their tracking granularity based on QueryMemory calls. // This can save on reprotects on larger resources. - const int pageCount = 32; - IMultiRegionHandle handle = GetGranular(true, 0, PageSize * pageCount, PageSize); + const int PageCount = 32; + IMultiRegionHandle handle = GetGranular(true, 0, PageSize * PageCount, PageSize); // Query some large regions to prep the subdivision of the tracking region. @@ -253,27 +253,27 @@ namespace Ryujinx.Tests.Memory public void DisposeMultiHandles([Values] bool smart) { // Create and initialize two overlapping Multi Region Handles, with PageSize granularity. - const int pageCount = 32; - const int overlapStart = 16; + const int PageCount = 32; + const int OverlapStart = 16; Assert.AreEqual(0, _tracking.GetRegionCount()); - IMultiRegionHandle handleLow = GetGranular(smart, 0, PageSize * pageCount, PageSize); - PreparePages(handleLow, pageCount); + IMultiRegionHandle handleLow = GetGranular(smart, 0, PageSize * PageCount, PageSize); + PreparePages(handleLow, PageCount); - Assert.AreEqual(pageCount, _tracking.GetRegionCount()); + Assert.AreEqual(PageCount, _tracking.GetRegionCount()); - IMultiRegionHandle handleHigh = GetGranular(smart, PageSize * overlapStart, PageSize * pageCount, PageSize); - PreparePages(handleHigh, pageCount, PageSize * overlapStart); + IMultiRegionHandle handleHigh = GetGranular(smart, PageSize * OverlapStart, PageSize * PageCount, PageSize); + PreparePages(handleHigh, PageCount, PageSize * OverlapStart); // Combined pages (and assuming overlapStart <= pageCount) should be pageCount after overlapStart. - int totalPages = overlapStart + pageCount; + int totalPages = OverlapStart + PageCount; Assert.AreEqual(totalPages, _tracking.GetRegionCount()); handleLow.Dispose(); // After disposing one, the pages for the other remain. - Assert.AreEqual(pageCount, _tracking.GetRegionCount()); + Assert.AreEqual(PageCount, _tracking.GetRegionCount()); handleHigh.Dispose(); // After disposing the other, there are no pages left. diff --git a/src/Ryujinx.Tests.Memory/TrackingTests.cs b/src/Ryujinx.Tests.Memory/TrackingTests.cs index dce73cf4f..035f0c228 100644 --- a/src/Ryujinx.Tests.Memory/TrackingTests.cs +++ b/src/Ryujinx.Tests.Memory/TrackingTests.cs @@ -201,11 +201,11 @@ namespace Ryujinx.Tests.Memory // This test should not throw or deadlock due to invalid state. - const int threadCount = 1; - const int handlesPerThread = 16; + const int ThreadCount = 1; + const int HandlesPerThread = 16; long finishedTime = 0; - RegionHandle[] handles = new RegionHandle[threadCount * handlesPerThread]; + RegionHandle[] handles = new RegionHandle[ThreadCount * HandlesPerThread]; Random globalRand = new(); for (int i = 0; i < handles.Length; i++) @@ -218,16 +218,16 @@ namespace Ryujinx.Tests.Memory // Dirty flag consumer threads int dirtyFlagReprotects = 0; - for (int i = 0; i < threadCount; i++) + for (int i = 0; i < ThreadCount; i++) { int randSeed = i; testThreads.Add(new Thread(() => { - int handleBase = randSeed * handlesPerThread; + int handleBase = randSeed * HandlesPerThread; while (Stopwatch.GetTimestamp() < finishedTime) { Random random = new(randSeed); - RegionHandle handle = handles[handleBase + random.Next(handlesPerThread)]; + RegionHandle handle = handles[handleBase + random.Next(HandlesPerThread)]; if (handle.Dirty) { @@ -240,16 +240,16 @@ namespace Ryujinx.Tests.Memory // Write trigger threads int writeTriggers = 0; - for (int i = 0; i < threadCount; i++) + for (int i = 0; i < ThreadCount; i++) { int randSeed = i; testThreads.Add(new Thread(() => { Random random = new(randSeed); - ulong handleBase = (ulong)(randSeed * handlesPerThread * PageSize); + ulong handleBase = (ulong)(randSeed * HandlesPerThread * PageSize); while (Stopwatch.GetTimestamp() < finishedTime) { - _tracking.VirtualMemoryEvent(handleBase + (ulong)random.Next(PageSize * handlesPerThread), PageSize / 2, true); + _tracking.VirtualMemoryEvent(handleBase + (ulong)random.Next(PageSize * HandlesPerThread), PageSize / 2, true); Interlocked.Increment(ref writeTriggers); } })); @@ -257,12 +257,12 @@ namespace Ryujinx.Tests.Memory // Handle create/delete threads int handleLifecycles = 0; - for (int i = 0; i < threadCount; i++) + for (int i = 0; i < ThreadCount; i++) { int randSeed = i; testThreads.Add(new Thread(() => { - int maxAddress = threadCount * handlesPerThread * PageSize; + int maxAddress = ThreadCount * HandlesPerThread * PageSize; Random random = new(randSeed + 512); while (Stopwatch.GetTimestamp() < finishedTime) { @@ -315,17 +315,17 @@ namespace Ryujinx.Tests.Memory }); } - const int threadCount = 16; - const int iterationCount = 10000; - Thread[] signalThreads = new Thread[threadCount]; + const int ThreadCount = 16; + const int IterationCount = 10000; + Thread[] signalThreads = new Thread[ThreadCount]; - for (int i = 0; i < threadCount; i++) + for (int i = 0; i < ThreadCount; i++) { int randSeed = i; signalThreads[i] = new Thread(() => { Random random = new(randSeed); - for (int j = 0; j < iterationCount; j++) + for (int j = 0; j < IterationCount; j++) { _tracking.VirtualMemoryEvent((ulong)random.Next(PageSize), 4, false); } @@ -333,14 +333,14 @@ namespace Ryujinx.Tests.Memory }); } - for (int i = 0; i < threadCount; i++) + for (int i = 0; i < ThreadCount; i++) { signalThreads[i].Start(); } while (signalThreadsDone != -1) { - if (signalThreadsDone == threadCount) + if (signalThreadsDone == ThreadCount) { signalThreadsDone = -1; } diff --git a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs index b643a1021..c86d3996e 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestMisc.cs @@ -359,7 +359,7 @@ namespace Ryujinx.Tests.Cpu [Test] public void MiscR() { - const ulong result = 5; + const ulong Result = 5; /* 0x0000000000001000: MOV X0, #2 @@ -374,7 +374,7 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.That(GetContext().GetX(0), Is.EqualTo(result)); + Assert.That(GetContext().GetX(0), Is.EqualTo(Result)); Reset(); @@ -391,7 +391,7 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.That(GetContext().GetX(0), Is.EqualTo(result)); + Assert.That(GetContext().GetX(0), Is.EqualTo(Result)); } [Explicit] @@ -479,4 +479,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs index e1e81a000..d5ac3c27b 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdIns.cs @@ -110,9 +110,9 @@ namespace Ryujinx.Tests.Cpu public void Dup_S_B([ValueSource(nameof(_8B_))] ulong a, [Values(0u, 15u)] uint index) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x5E000420; // RESERVED opcode |= (imm5 << 16); @@ -130,9 +130,9 @@ namespace Ryujinx.Tests.Cpu public void Dup_S_H([ValueSource(nameof(_4H_))] ulong a, [Values(0u, 7u)] uint index) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x5E000420; // RESERVED opcode |= (imm5 << 16); @@ -150,9 +150,9 @@ namespace Ryujinx.Tests.Cpu public void Dup_S_S([ValueSource(nameof(_2S_))] ulong a, [Values(0u, 1u, 2u, 3u)] uint index) { - const int size = 2; + const int TestSize = 2; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x5E000420; // RESERVED opcode |= (imm5 << 16); @@ -170,9 +170,9 @@ namespace Ryujinx.Tests.Cpu public void Dup_S_D([ValueSource(nameof(_1D_))] ulong a, [Values(0u, 1u)] uint index) { - const int size = 3; + const int TestSize = 3; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x5E000420; // RESERVED opcode |= (imm5 << 16); @@ -194,9 +194,9 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 15u)] uint index, [Values(0b0u, 0b1u)] uint q) // <8B, 16B> { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -219,9 +219,9 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 7u)] uint index, [Values(0b0u, 0b1u)] uint q) // <4H, 8H> { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -244,9 +244,9 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 1u, 2u, 3u)] uint index, [Values(0b0u, 0b1u)] uint q) // <2S, 4S> { - const int size = 2; + const int TestSize = 2; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -269,9 +269,9 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 1u)] uint index, [Values(0b1u)] uint q) // <2D> { - const int size = 3; + const int TestSize = 3; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -293,9 +293,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_W_))] uint wn, [Values(0u, 15u)] uint index) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E001C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -316,9 +316,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_W_))] uint wn, [Values(0u, 7u)] uint index) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E001C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -339,9 +339,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_W_))] uint wn, [Values(0u, 1u, 2u, 3u)] uint index) { - const int size = 2; + const int TestSize = 2; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E001C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -362,9 +362,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_X_))] ulong xn, [Values(0u, 1u)] uint index) { - const int size = 3; + const int TestSize = 3; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E001C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -386,10 +386,10 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 15u)] uint dstIndex, [Values(0u, 15u)] uint srcIndex) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu; - uint imm4 = (srcIndex << size) & 0xFu; + uint imm5 = (dstIndex << (TestSize + 1) | 1u << TestSize) & 0x1Fu; + uint imm4 = (srcIndex << TestSize) & 0xFu; uint opcode = 0x6E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -412,10 +412,10 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 7u)] uint dstIndex, [Values(0u, 7u)] uint srcIndex) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu; - uint imm4 = (srcIndex << size) & 0xFu; + uint imm5 = (dstIndex << (TestSize + 1) | 1u << TestSize) & 0x1Fu; + uint imm4 = (srcIndex << TestSize) & 0xFu; uint opcode = 0x6E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -438,10 +438,10 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 1u, 2u, 3u)] uint dstIndex, [Values(0u, 1u, 2u, 3u)] uint srcIndex) { - const int size = 2; + const int TestSize = 2; - uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu; - uint imm4 = (srcIndex << size) & 0xFu; + uint imm5 = (dstIndex << (TestSize + 1) | 1u << TestSize) & 0x1Fu; + uint imm4 = (srcIndex << TestSize) & 0xFu; uint opcode = 0x6E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -464,10 +464,10 @@ namespace Ryujinx.Tests.Cpu [Values(0u, 1u)] uint dstIndex, [Values(0u, 1u)] uint srcIndex) { - const int size = 3; + const int TestSize = 3; - uint imm5 = (dstIndex << (size + 1) | 1u << size) & 0x1Fu; - uint imm4 = (srcIndex << size) & 0xFu; + uint imm5 = (dstIndex << (TestSize + 1) | 1u << TestSize) & 0x1Fu; + uint imm4 = (srcIndex << TestSize) & 0xFu; uint opcode = 0x6E000400; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -488,9 +488,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8B_))] ulong a, [Values(0u, 15u)] uint index) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E002C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -511,9 +511,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_4H_))] ulong a, [Values(0u, 7u)] uint index) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E002C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -534,9 +534,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8B_))] ulong a, [Values(0u, 15u)] uint index) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E002C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -556,9 +556,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_4H_))] ulong a, [Values(0u, 7u)] uint index) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E002C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -578,9 +578,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_2S_))] ulong a, [Values(0u, 1u, 2u, 3u)] uint index) { - const int size = 2; + const int TestSize = 2; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E002C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -600,9 +600,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_8B_))] ulong a, [Values(0u, 15u)] uint index) { - const int size = 0; + const int TestSize = 0; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E003C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -623,9 +623,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_4H_))] ulong a, [Values(0u, 7u)] uint index) { - const int size = 1; + const int TestSize = 1; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E003C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -646,9 +646,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_2S_))] ulong a, [Values(0u, 1u, 2u, 3u)] uint index) { - const int size = 2; + const int TestSize = 2; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x0E003C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -669,9 +669,9 @@ namespace Ryujinx.Tests.Cpu [ValueSource(nameof(_1D_))] ulong a, [Values(0u, 1u)] uint index) { - const int size = 3; + const int TestSize = 3; - uint imm5 = (index << (size + 1) | 1u << size) & 0x1Fu; + uint imm5 = (index << (TestSize + 1) | 1u << TestSize) & 0x1Fu; uint opcode = 0x4E003C00; // RESERVED opcode |= ((rn & 31) << 5) | ((rd & 31) << 0); @@ -686,4 +686,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs index c88c02c1b..50915fd34 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs @@ -1,8 +1,8 @@ #define SimdMemory32 using ARMeilleure.State; -using Ryujinx.Memory; using NUnit.Framework; +using Ryujinx.Memory; using System; namespace Ryujinx.Tests.Cpu diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs index 7bafc195e..830a748ab 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs @@ -14,17 +14,17 @@ namespace Ryujinx.Tests.Cpu #region "Helper methods" private static ulong GenIdxsForTbls(int regs) { - const byte idxInRngMin = 0; + const byte IdxInRngMin = 0; byte idxInRngMax = (byte)((16 * regs) - 1); byte idxOutRngMin = (byte) (16 * regs); - const byte idxOutRngMax = 255; + const byte IdxOutRngMax = 255; ulong idxs = 0ul; for (int cnt = 1; cnt <= 8; cnt++) { - ulong idxInRng = TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax); - ulong idxOutRng = TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax); + ulong idxInRng = TestContext.CurrentContext.Random.NextByte(IdxInRngMin, idxInRngMax); + ulong idxOutRng = TestContext.CurrentContext.Random.NextByte(idxOutRngMin, IdxOutRngMax); ulong idx = TestContext.CurrentContext.Random.NextBool() ? idxInRng : idxOutRng; @@ -314,4 +314,4 @@ namespace Ryujinx.Tests.Cpu } #endif } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Ui.Common/App/ApplicationData.cs b/src/Ryujinx.Ui.Common/App/ApplicationData.cs index f0aa40be2..1081fcf32 100644 --- a/src/Ryujinx.Ui.Common/App/ApplicationData.cs +++ b/src/Ryujinx.Ui.Common/App/ApplicationData.cs @@ -1,9 +1,9 @@ using LibHac.Common; -using LibHac.Ns; using LibHac.Fs; using LibHac.Fs.Fsa; using LibHac.FsSystem; using LibHac.Loader; +using LibHac.Ns; using LibHac.Tools.Fs; using LibHac.Tools.FsSystem; using LibHac.Tools.FsSystem.NcaUtils; @@ -146,9 +146,9 @@ namespace Ryujinx.Ui.App.Common return string.Empty; } - const string mainExeFs = "main"; + const string MainExeFs = "main"; - if (!codeFs.FileExists($"/{mainExeFs}")) + if (!codeFs.FileExists($"/{MainExeFs}")) { Logger.Error?.Print(LogClass.Loader, "No main binary ExeFS found in ExeFS"); @@ -157,12 +157,12 @@ namespace Ryujinx.Ui.App.Common using var nsoFile = new UniqueRef(); - codeFs.OpenFile(ref nsoFile.Ref, $"/{mainExeFs}".ToU8Span(), OpenMode.Read).ThrowIfFailure(); + codeFs.OpenFile(ref nsoFile.Ref, $"/{MainExeFs}".ToU8Span(), OpenMode.Read).ThrowIfFailure(); NsoReader reader = new NsoReader(); reader.Initialize(nsoFile.Release().AsStorage().AsFile(OpenMode.Read)).ThrowIfFailure(); - + return BitConverter.ToString(reader.Header.ModuleId.ItemsRo.ToArray()).Replace("-", "").ToUpper()[..16]; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Ui.Common/App/ApplicationLibrary.cs b/src/Ryujinx.Ui.Common/App/ApplicationLibrary.cs index f52af611e..28280bd9f 100644 --- a/src/Ryujinx.Ui.Common/App/ApplicationLibrary.cs +++ b/src/Ryujinx.Ui.Common/App/ApplicationLibrary.cs @@ -18,9 +18,9 @@ using Ryujinx.Ui.Common.Configuration; using Ryujinx.Ui.Common.Configuration.System; using System; using System.Collections.Generic; -using System.Linq; using System.Globalization; using System.IO; +using System.Linq; using System.Reflection; using System.Text; using System.Text.Json; diff --git a/src/Ryujinx/Ui/Widgets/GameTableContextMenu.cs b/src/Ryujinx/Ui/Widgets/GameTableContextMenu.cs index 74f6043d4..6279891e6 100644 --- a/src/Ryujinx/Ui/Widgets/GameTableContextMenu.cs +++ b/src/Ryujinx/Ui/Widgets/GameTableContextMenu.cs @@ -389,12 +389,12 @@ namespace Ryujinx.Ui.Widgets using (destHandle) { - const int maxBufferSize = 1024 * 1024; + const int MaxBufferSize = 1024 * 1024; rc = fs.GetFileSize(out long fileSize, sourceHandle); if (rc.IsFailure()) return rc; - int bufferSize = (int)Math.Min(maxBufferSize, fileSize); + int bufferSize = (int)Math.Min(MaxBufferSize, fileSize); byte[] buffer = ArrayPool.Shared.Rent(bufferSize); try From e055217292e034e46ebadd2e839b301b996d7064 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 01:27:48 +0200 Subject: [PATCH 13/19] [Ryujinx.Horizon.Kernel.Generators] Address dotnet-format issues (#5376) * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Run dotnet format pass * Remove left-over files and adjust namespaces * Fix alignment --- .../CodeGenerator.cs | 2 +- .../{Kernel => }/SyscallGenerator.cs | 12 ++++++------ .../{Kernel => }/SyscallSyntaxReceiver.cs | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) rename src/Ryujinx.Horizon.Kernel.Generators/{Kernel => }/SyscallGenerator.cs (97%) rename src/Ryujinx.Horizon.Kernel.Generators/{Kernel => }/SyscallSyntaxReceiver.cs (97%) diff --git a/src/Ryujinx.Horizon.Kernel.Generators/CodeGenerator.cs b/src/Ryujinx.Horizon.Kernel.Generators/CodeGenerator.cs index 80a33c66c..121b6dd58 100644 --- a/src/Ryujinx.Horizon.Kernel.Generators/CodeGenerator.cs +++ b/src/Ryujinx.Horizon.Kernel.Generators/CodeGenerator.cs @@ -1,6 +1,6 @@ using System.Text; -namespace Ryujinx.Horizon.Generators +namespace Ryujinx.Horizon.Kernel.Generators { class CodeGenerator { diff --git a/src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallGenerator.cs b/src/Ryujinx.Horizon.Kernel.Generators/SyscallGenerator.cs similarity index 97% rename from src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallGenerator.cs rename to src/Ryujinx.Horizon.Kernel.Generators/SyscallGenerator.cs index 51da21878..75f966f39 100644 --- a/src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallGenerator.cs +++ b/src/Ryujinx.Horizon.Kernel.Generators/SyscallGenerator.cs @@ -6,7 +6,7 @@ using System.Collections.Generic; using System.Diagnostics; using System.Linq; -namespace Ryujinx.Horizon.Generators.Kernel +namespace Ryujinx.Horizon.Kernel.Generators { [Generator] class SyscallGenerator : ISourceGenerator @@ -157,10 +157,10 @@ namespace Ryujinx.Horizon.Generators.Kernel GetCanonicalTypeName(context.Compilation, attribute) == TypeSvcAttribute))) { syscalls.AddRange(from attributeArg in attribute.ArgumentList.Arguments - where attributeArg.Expression.Kind() == SyntaxKind.NumericLiteralExpression - select (LiteralExpressionSyntax)attributeArg.Expression - into numericLiteral - select new SyscallIdAndName((int)numericLiteral.Token.Value, method.Identifier.Text)); + where attributeArg.Expression.Kind() == SyntaxKind.NumericLiteralExpression + select (LiteralExpressionSyntax)attributeArg.Expression + into numericLiteral + select new SyscallIdAndName((int)numericLiteral.Token.Value, method.Identifier.Text)); } } @@ -369,7 +369,7 @@ namespace Ryujinx.Horizon.Generators.Kernel { generator.AppendLine($"context.SetX({returnRegisterIndex++}, (ulong){ResultVariableName});"); } - + result = GetFormattedLogValue(ResultVariableName, canonicalReturnTypeName); } else diff --git a/src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallSyntaxReceiver.cs b/src/Ryujinx.Horizon.Kernel.Generators/SyscallSyntaxReceiver.cs similarity index 97% rename from src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallSyntaxReceiver.cs rename to src/Ryujinx.Horizon.Kernel.Generators/SyscallSyntaxReceiver.cs index e480a8593..f586ee682 100644 --- a/src/Ryujinx.Horizon.Kernel.Generators/Kernel/SyscallSyntaxReceiver.cs +++ b/src/Ryujinx.Horizon.Kernel.Generators/SyscallSyntaxReceiver.cs @@ -3,7 +3,7 @@ using Microsoft.CodeAnalysis.CSharp.Syntax; using System.Collections.Generic; using System.Linq; -namespace Ryujinx.Horizon.Generators.Kernel +namespace Ryujinx.Horizon.Kernel.Generators { class SyscallSyntaxReceiver : ISyntaxReceiver { From 9becbd7d728fc2002c176dfd9d1d1aae86f86b12 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 08:59:13 +0200 Subject: [PATCH 14/19] [Ryujinx.Graphics.Shader] Address dotnet-format issues (#5373) * dotnet format style --severity info Some changes were manually reverted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Silence dotnet format IDE0059 warnings * Address or silence dotnet format CA1069 warnings * Address or silence dotnet format CA2211 warnings * Address review comments * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Run dotnet format whitespace after rebase * Run dotnet format style after rebase * Run dotnet format whitespace after rebase * Run dotnet format style after rebase * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Fix naming rule violation, Convert shader properties to auto-property and convert values to const * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Run dotnet format after rebase * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Run dotnet format after rebase * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Fix naming rule violations * Add trailing commas * Remove unused members and most unnecessary value assignments * Remove more unnecessary assignments * Remove NRE suppressor --- src/Ryujinx.Graphics.Shader/AlphaTestOp.cs | 4 +- src/Ryujinx.Graphics.Shader/AttributeType.cs | 8 +- .../BufferDescriptor.cs | 2 +- .../BufferUsageFlags.cs | 2 +- .../CodeGen/Glsl/CodeGenContext.cs | 2 +- .../CodeGen/Glsl/Declarations.cs | 24 +- .../CodeGen/Glsl/DefaultNames.cs | 4 +- .../CodeGen/Glsl/GlslGenerator.cs | 9 +- .../HelperFunctions/HelperFunctionNames.cs | 10 +- .../CodeGen/Glsl/Instructions/InstGen.cs | 2 +- .../Glsl/Instructions/InstGenBallot.cs | 2 +- .../CodeGen/Glsl/Instructions/InstGenCall.cs | 2 +- .../CodeGen/Glsl/Instructions/InstGenFSI.cs | 2 +- .../Glsl/Instructions/InstGenHelper.cs | 8 +- .../Glsl/Instructions/InstGenMemory.cs | 52 +- .../Glsl/Instructions/InstGenPacking.cs | 2 +- .../Glsl/Instructions/InstGenVector.cs | 2 +- .../CodeGen/Glsl/Instructions/InstInfo.cs | 6 +- .../CodeGen/Glsl/Instructions/InstType.cs | 32 +- .../CodeGen/Glsl/Instructions/IoMap.cs | 6 +- .../CodeGen/Glsl/NumberFormatter.cs | 2 +- .../CodeGen/Glsl/OperandManager.cs | 22 +- .../CodeGen/Glsl/TypeConversion.cs | 28 +- .../CodeGen/Spirv/CodeGenContext.cs | 31 +- .../CodeGen/Spirv/Declarations.cs | 21 +- .../CodeGen/Spirv/EnumConversion.cs | 2 +- .../CodeGen/Spirv/Instructions.cs | 124 +- .../CodeGen/Spirv/IoMap.cs | 12 +- .../CodeGen/Spirv/OperationResult.cs | 2 +- .../CodeGen/Spirv/SpirvGenerator.cs | 38 +- .../CodeGen/Spirv/TextureMeta.cs | 2 +- src/Ryujinx.Graphics.Shader/Constants.cs | 2 +- src/Ryujinx.Graphics.Shader/Decoders/Block.cs | 6 +- .../Decoders/DecodedFunction.cs | 2 +- .../Decoders/DecodedProgram.cs | 2 +- .../Decoders/Decoder.cs | 73 +- .../Decoders/InstDecoders.cs | 1180 +++++++++-------- .../Decoders/InstName.cs | 2 +- .../Decoders/InstOp.cs | 2 +- .../Decoders/InstProps.cs | 4 +- .../Decoders/InstTable.cs | 8 +- .../Decoders/Register.cs | 8 +- .../Decoders/RegisterConsts.cs | 6 +- .../Decoders/RegisterType.cs | 2 +- src/Ryujinx.Graphics.Shader/InputTopology.cs | 8 +- .../Instructions/AttributeMap.cs | 9 +- .../Instructions/InstEmit.cs | 102 +- .../Instructions/InstEmitAluHelper.cs | 17 +- .../Instructions/InstEmitAttribute.cs | 6 +- .../Instructions/InstEmitBarrier.cs | 4 +- .../Instructions/InstEmitBitfield.cs | 2 +- .../Instructions/InstEmitConditionCode.cs | 5 +- .../Instructions/InstEmitConversion.cs | 7 +- .../Instructions/InstEmitFloatArithmetic.cs | 5 +- .../Instructions/InstEmitFloatComparison.cs | 29 +- .../Instructions/InstEmitFloatMinMax.cs | 2 +- .../Instructions/InstEmitFlowControl.cs | 26 +- .../Instructions/InstEmitHelper.cs | 64 +- .../Instructions/InstEmitIntegerArithmetic.cs | 4 +- .../Instructions/InstEmitIntegerComparison.cs | 23 +- .../Instructions/InstEmitIntegerLogical.cs | 11 +- .../Instructions/InstEmitIntegerMinMax.cs | 2 +- .../Instructions/InstEmitMemory.cs | 47 +- .../Instructions/InstEmitMove.cs | 4 +- .../Instructions/InstEmitMultifunction.cs | 2 +- .../Instructions/InstEmitNop.cs | 4 +- .../Instructions/InstEmitPredicate.cs | 2 +- .../Instructions/InstEmitShift.cs | 2 +- .../Instructions/InstEmitSurface.cs | 41 +- .../Instructions/InstEmitTexture.cs | 21 +- .../Instructions/InstEmitVideoArithmetic.cs | 5 +- .../Instructions/InstEmitVideoMinMax.cs | 2 +- .../Instructions/InstEmitWarp.cs | 5 +- .../Instructions/InstEmitter.cs | 2 +- .../Instructions/Lop3Expression.cs | 49 +- .../IntermediateRepresentation/BasicBlock.cs | 6 +- .../IntermediateRepresentation/CommentNode.cs | 2 +- .../IntermediateRepresentation/Function.cs | 2 +- .../IntermediateRepresentation/INode.cs | 2 +- .../IntermediateRepresentation/Instruction.cs | 6 +- .../IntermediateRepresentation/IoVariable.cs | 4 +- .../IntermediateRepresentation/IrConsts.cs | 4 +- .../IntermediateRepresentation/Operand.cs | 10 +- .../OperandHelper.cs | 2 +- .../IntermediateRepresentation/OperandType.cs | 4 +- .../IntermediateRepresentation/Operation.cs | 4 +- .../IntermediateRepresentation/PhiNode.cs | 12 +- .../IntermediateRepresentation/StorageKind.cs | 4 +- .../TextureFlags.cs | 44 +- .../TextureOperation.cs | 2 +- src/Ryujinx.Graphics.Shader/OutputTopology.cs | 21 +- src/Ryujinx.Graphics.Shader/SamplerType.cs | 22 +- .../ShaderIdentification.cs | 4 +- src/Ryujinx.Graphics.Shader/ShaderProgram.cs | 2 +- .../ShaderProgramInfo.cs | 2 +- src/Ryujinx.Graphics.Shader/ShaderStage.cs | 4 +- .../StructuredIr/AstAssignment.cs | 4 +- .../StructuredIr/AstBlock.cs | 6 +- .../StructuredIr/AstBlockType.cs | 4 +- .../StructuredIr/AstBlockVisitor.cs | 2 +- .../StructuredIr/AstComment.cs | 2 +- .../StructuredIr/AstHelper.cs | 9 +- .../StructuredIr/AstNode.cs | 2 +- .../StructuredIr/AstOperand.cs | 6 +- .../StructuredIr/AstOperation.cs | 16 +- .../StructuredIr/AstOptimizer.cs | 8 +- .../StructuredIr/AstTextureOperation.cs | 2 +- .../StructuredIr/BufferDefinition.cs | 2 +- .../StructuredIr/BufferLayout.cs | 4 +- .../StructuredIr/GotoElimination.cs | 39 +- .../StructuredIr/GotoStatement.cs | 8 +- .../StructuredIr/HelperFunctionsMask.cs | 14 +- .../StructuredIr/IAstNode.cs | 2 +- .../StructuredIr/InstructionInfo.cs | 6 +- .../StructuredIr/IoDefinition.cs | 2 +- .../StructuredIr/MemoryDefinition.cs | 2 +- .../StructuredIr/OperandInfo.cs | 4 +- .../StructuredIr/PhiFunctions.cs | 4 +- .../StructuredIr/ShaderProperties.cs | 2 +- .../StructuredIr/StructureType.cs | 2 +- .../StructuredIr/StructuredFunction.cs | 2 +- .../StructuredIr/StructuredProgram.cs | 35 +- .../StructuredIr/StructuredProgramContext.cs | 15 +- .../StructuredIr/StructuredProgramInfo.cs | 2 +- src/Ryujinx.Graphics.Shader/SupportBuffer.cs | 24 +- src/Ryujinx.Graphics.Shader/TessPatchType.cs | 6 +- src/Ryujinx.Graphics.Shader/TessSpacing.cs | 6 +- .../TextureDescriptor.cs | 12 +- src/Ryujinx.Graphics.Shader/TextureFormat.cs | 6 +- src/Ryujinx.Graphics.Shader/TextureHandle.cs | 2 +- .../TextureUsageFlags.cs | 2 +- .../Translation/AggregateType.cs | 6 +- .../Translation/AttributeConsts.cs | 2 +- .../Translation/ControlFlowGraph.cs | 16 +- .../Translation/Dominance.cs | 2 +- .../Translation/EmitterContext.cs | 11 +- .../Translation/EmitterContextInsts.cs | 2 +- .../Translation/FeatureFlags.cs | 4 +- .../Translation/FunctionMatch.cs | 39 +- .../Translation/HelperFunctionManager.cs | 23 +- .../Translation/HelperFunctionName.cs | 4 +- .../Optimizations/BindlessElimination.cs | 8 +- .../Optimizations/BindlessToIndexed.cs | 14 +- .../Optimizations/BranchElimination.cs | 4 +- .../Optimizations/ConstantFolding.cs | 14 +- .../Optimizations/DoubleToFloat.cs | 4 +- .../Optimizations/GlobalToStorage.cs | 63 +- .../Translation/Optimizations/Optimizer.cs | 20 +- .../Optimizations/Simplification.cs | 2 +- .../Translation/Optimizations/Utils.cs | 2 +- .../Translation/RegisterUsage.cs | 38 +- .../Translation/ResourceManager.cs | 34 +- .../Translation/Rewriter.cs | 75 +- .../Translation/ShaderConfig.cs | 66 +- .../Translation/ShaderHeader.cs | 20 +- .../Translation/ShaderIdentifier.cs | 4 +- .../Translation/Ssa.cs | 23 +- .../Translation/TargetApi.cs | 2 +- .../Translation/TargetLanguage.cs | 2 +- .../Translation/TranslationFlags.cs | 8 +- .../Translation/Translator.cs | 14 +- .../Translation/TranslatorContext.cs | 11 +- 162 files changed, 1611 insertions(+), 1627 deletions(-) diff --git a/src/Ryujinx.Graphics.Shader/AlphaTestOp.cs b/src/Ryujinx.Graphics.Shader/AlphaTestOp.cs index 57c0d1314..13958ea48 100644 --- a/src/Ryujinx.Graphics.Shader/AlphaTestOp.cs +++ b/src/Ryujinx.Graphics.Shader/AlphaTestOp.cs @@ -9,6 +9,6 @@ namespace Ryujinx.Graphics.Shader Greater, NotEqual, GreaterOrEqual, - Always + Always, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/AttributeType.cs b/src/Ryujinx.Graphics.Shader/AttributeType.cs index 4e6cad596..50a39945b 100644 --- a/src/Ryujinx.Graphics.Shader/AttributeType.cs +++ b/src/Ryujinx.Graphics.Shader/AttributeType.cs @@ -8,7 +8,7 @@ namespace Ryujinx.Graphics.Shader // Generic types. Float, Sint, - Uint + Uint, } static class AttributeTypeExtensions @@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Shader AttributeType.Float => "vec4", AttributeType.Sint => "ivec4", AttributeType.Uint => "uvec4", - _ => throw new ArgumentException($"Invalid attribute type \"{type}\".") + _ => throw new ArgumentException($"Invalid attribute type \"{type}\"."), }; } @@ -31,8 +31,8 @@ namespace Ryujinx.Graphics.Shader AttributeType.Float => AggregateType.FP32, AttributeType.Sint => AggregateType.S32, AttributeType.Uint => AggregateType.U32, - _ => throw new ArgumentException($"Invalid attribute type \"{type}\".") + _ => throw new ArgumentException($"Invalid attribute type \"{type}\"."), }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/BufferDescriptor.cs b/src/Ryujinx.Graphics.Shader/BufferDescriptor.cs index 410c1991d..d1da95393 100644 --- a/src/Ryujinx.Graphics.Shader/BufferDescriptor.cs +++ b/src/Ryujinx.Graphics.Shader/BufferDescriptor.cs @@ -37,4 +37,4 @@ namespace Ryujinx.Graphics.Shader return this; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/BufferUsageFlags.cs b/src/Ryujinx.Graphics.Shader/BufferUsageFlags.cs index ab81d5756..a69fa46a4 100644 --- a/src/Ryujinx.Graphics.Shader/BufferUsageFlags.cs +++ b/src/Ryujinx.Graphics.Shader/BufferUsageFlags.cs @@ -13,6 +13,6 @@ namespace Ryujinx.Graphics.Shader /// /// Buffer is written to. /// - Write = 1 << 0 + Write = 1 << 0, } } diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/CodeGenContext.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/CodeGenContext.cs index 9eb20f6f8..551e5cefa 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/CodeGenContext.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/CodeGenContext.cs @@ -92,4 +92,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl return indentation; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs index 08e8eb195..94b850e7b 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs @@ -244,16 +244,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl } } - private static string GetTfLayout(TransformFeedbackOutput tfOutput) - { - if (tfOutput.Valid) - { - return $"layout (xfb_buffer = {tfOutput.Buffer}, xfb_offset = {tfOutput.Offset}, xfb_stride = {tfOutput.Stride}) "; - } - - return string.Empty; - } - public static void DeclareLocals(CodeGenContext context, StructuredFunction function) { foreach (AstOperand decl in function.Locals) @@ -294,7 +284,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl AggregateType.Vector4 | AggregateType.FP64 => "dvec4", AggregateType.Vector4 | AggregateType.S32 => "ivec4", AggregateType.Vector4 | AggregateType.U32 => "uvec4", - _ => throw new ArgumentException($"Invalid variable type \"{type}\".") + _ => throw new ArgumentException($"Invalid variable type \"{type}\"."), }; } @@ -315,7 +305,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl string layout = buffer.Layout switch { BufferLayout.Std140 => "std140", - _ => "std430" + _ => "std430", }; string set = string.Empty; @@ -507,7 +497,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { PixelImap.Constant => "flat ", PixelImap.ScreenLinear => "noperspective ", - _ => string.Empty + _ => string.Empty, }; } @@ -524,7 +514,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl 2 => "vec2", 3 => "vec3", 4 => "vec4", - _ => "float" + _ => "float", }; context.AppendLine($"layout (location = {attr}) in {type} {name};"); @@ -611,7 +601,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl 2 => "vec2", 3 => "vec3", 4 => "vec4", - _ => "float" + _ => "float", }; string xfb = string.Empty; @@ -647,7 +637,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { AttributeType.Sint => "ivec4", AttributeType.Uint => "uvec4", - _ => "vec4" + _ => "vec4", }; if (context.Config.GpuAccessor.QueryHostReducedPrecision() && context.Config.Stage == ShaderStage.Vertex && attr == 0) @@ -721,4 +711,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl context.AppendLine(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/DefaultNames.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/DefaultNames.cs index e909dcf04..842228edf 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/DefaultNames.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/DefaultNames.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl public const string LocalNamePrefix = "temp"; public const string SamplerNamePrefix = "tex"; - public const string ImageNamePrefix = "img"; + public const string ImageNamePrefix = "img"; public const string PerPatchAttributePrefix = "patch_attr_"; public const string IAttributePrefix = "in_attr"; @@ -15,4 +15,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl public const string UndefinedName = "undef"; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/GlslGenerator.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/GlslGenerator.cs index fe0d275b6..0140c1b93 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/GlslGenerator.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/GlslGenerator.cs @@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl public static string Generate(StructuredProgramInfo info, ShaderConfig config) { - CodeGenContext context = new CodeGenContext(info, config); + CodeGenContext context = new(info, config); Declarations.Declare(context, info); @@ -74,7 +74,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl private static void PrintBlock(CodeGenContext context, AstBlock block, bool isMainFunction) { - AstBlockVisitor visitor = new AstBlockVisitor(block); + AstBlockVisitor visitor = new(block); visitor.BlockEntered += (sender, e) => { @@ -96,7 +96,8 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl context.AppendLine($"if ({GetCondExpr(context, e.Block.Condition)})"); break; - default: throw new InvalidOperationException($"Found unexpected block type \"{e.Block.Type}\"."); + default: + throw new InvalidOperationException($"Found unexpected block type \"{e.Block.Type}\"."); } context.EnterScope(); @@ -173,4 +174,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl return ReinterpretCast(context, cond, srcType, AggregateType.Bool); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/HelperFunctions/HelperFunctionNames.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/HelperFunctions/HelperFunctionNames.cs index 21c435475..221802727 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/HelperFunctions/HelperFunctionNames.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/HelperFunctions/HelperFunctionNames.cs @@ -5,10 +5,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl public static string MultiplyHighS32 = "Helper_MultiplyHighS32"; public static string MultiplyHighU32 = "Helper_MultiplyHighU32"; - public static string Shuffle = "Helper_Shuffle"; + public static string Shuffle = "Helper_Shuffle"; public static string ShuffleDown = "Helper_ShuffleDown"; - public static string ShuffleUp = "Helper_ShuffleUp"; - public static string ShuffleXor = "Helper_ShuffleXor"; - public static string SwizzleAdd = "Helper_SwizzleAdd"; + public static string ShuffleUp = "Helper_ShuffleUp"; + public static string ShuffleXor = "Helper_ShuffleXor"; + public static string SwizzleAdd = "Helper_SwizzleAdd"; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGen.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGen.cs index b2577a999..9208ceead 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGen.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGen.cs @@ -197,4 +197,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions throw new InvalidOperationException($"Unexpected instruction type \"{info.Type}\"."); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenBallot.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenBallot.cs index 68793c5dd..9a2bfef0c 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenBallot.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenBallot.cs @@ -24,4 +24,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenCall.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenCall.cs index 2df6960d9..0618ba8a3 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenCall.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenCall.cs @@ -26,4 +26,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return $"{function.Name}({string.Join(", ", args)})"; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenFSI.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenFSI.cs index f61a53cbe..a3d68028f 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenFSI.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenFSI.cs @@ -26,4 +26,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return null; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenHelper.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenHelper.cs index 8b0b744ad..c3d52b2c5 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenHelper.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenHelper.cs @@ -14,6 +14,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { _infoTable = new InstInfo[(int)Instruction.Count]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.AtomicAdd, InstType.AtomicBinary, "atomicAdd"); Add(Instruction.AtomicAnd, InstType.AtomicBinary, "atomicAnd"); Add(Instruction.AtomicCompareAndSwap, InstType.AtomicTernary, "atomicCompSwap"); @@ -125,6 +126,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions Add(Instruction.VoteAll, InstType.CallUnary, "allInvocationsARB"); Add(Instruction.VoteAllEqual, InstType.CallUnary, "allInvocationsEqualARB"); Add(Instruction.VoteAny, InstType.CallUnary, "anyInvocationARB"); +#pragma warning restore IDE0055 } private static void Add(Instruction inst, InstType flags, string opName = null, int precedence = 0) @@ -163,7 +165,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { // If the node isn't a operation, then it can only be a operand, // and those never needs to be surrounded in parenthesis. - if (!(node is AstOperation operation)) + if (node is not AstOperation operation) { // This is sort of a special case, if this is a negative constant, // and it is consumed by a unary operation, we need to put on the parenthesis, @@ -208,7 +210,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions private static bool IsNegativeConst(IAstNode node) { - if (!(node is AstOperand operand)) + if (node is not AstOperand operand) { return false; } @@ -216,4 +218,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return operand.Type == OperandType.Constant && operand.Value < 0; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenMemory.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenMemory.cs index 99376ffb2..e0faed298 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenMemory.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenMemory.cs @@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.StructuredIr; using Ryujinx.Graphics.Shader.Translation; using System; using System.Text; - using static Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions.InstGenHelper; using static Ryujinx.Graphics.Shader.StructuredIr.InstructionInfo; @@ -42,14 +41,16 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions } } - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; var texCallBuilder = new StringBuilder(); if (texOp.Inst == Instruction.ImageAtomic) { - texCallBuilder.Append((texOp.Flags & TextureFlags.AtomicMask) switch { + texCallBuilder.Append((texOp.Flags & TextureFlags.AtomicMask) switch + { +#pragma warning disable IDE0055 // Disable formatting TextureFlags.Add => "imageAtomicAdd", TextureFlags.Minimum => "imageAtomicMin", TextureFlags.Maximum => "imageAtomicMax", @@ -61,6 +62,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions TextureFlags.Swap => "imageAtomicExchange", TextureFlags.CAS => "imageAtomicCompSwap", _ => "imageAtomicAdd", +#pragma warning restore IDE0055 }); } else @@ -131,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { AggregateType.S32 => NumberFormatter.FormatInt(0), AggregateType.U32 => NumberFormatter.FormatUint(0), - _ => NumberFormatter.FormatFloat(0) + _ => NumberFormatter.FormatFloat(0), }; } } @@ -140,7 +142,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { AggregateType.S32 => "i", AggregateType.U32 => "u", - _ => string.Empty + _ => string.Empty, }; Append($"{prefix}vec4({string.Join(", ", cElems)})"); @@ -159,7 +161,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { TextureFlags.Increment => NumberFormatter.FormatInt(1, type), // TODO: Clamp value TextureFlags.Decrement => NumberFormatter.FormatInt(-1, type), // TODO: Clamp value - _ => Src(type) + _ => Src(type), }; Append(value); @@ -248,25 +250,25 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { AstTextureOperation texOp = (AstTextureOperation)operation; - bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; + bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; + bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; bool hasDerivatives = (texOp.Flags & TextureFlags.Derivatives) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; - bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; - bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; - bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0; + bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; + bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; + bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; + bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; + bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0; - bool isArray = (texOp.Type & SamplerType.Array) != 0; - bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; bool isMultisample = (texOp.Type & SamplerType.Multisample) != 0; - bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; + bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; bool colorIsVector = isGather || !isShadow; SamplerType type = texOp.Type & SamplerType.Mask; - bool is2D = type == SamplerType.Texture2D; + bool is2D = type == SamplerType.Texture2D; bool isCube = type == SamplerType.TextureCube; // 2D Array and Cube shadow samplers with LOD level or bias requires an extension. @@ -500,14 +502,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions if (hasLodBias) { - Append(Src(AggregateType.FP32)); + Append(Src(AggregateType.FP32)); } // textureGather* optional extra component index, // not needed for shadow samplers. if (isGather && !isShadow) { - Append(Src(AggregateType.S32)); + Append(Src(AggregateType.S32)); } texCall += ")" + (colorIsVector ? GetMaskMultiDest(texOp.Index) : ""); @@ -584,7 +586,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { case StorageKind.ConstantBuffer: case StorageKind.StorageBuffer: - if (!(operation.GetSource(srcIndex++) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -594,7 +596,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions ? context.Config.Properties.ConstantBuffers[binding] : context.Config.Properties.StorageBuffers[binding]; - if (!(operation.GetSource(srcIndex++) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -606,7 +608,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions case StorageKind.LocalMemory: case StorageKind.SharedMemory: - if (!(operation.GetSource(srcIndex++) is AstOperand bindingId) || bindingId.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand { Type: OperandType.Constant } bindingId) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -623,7 +625,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions case StorageKind.InputPerPatch: case StorageKind.Output: case StorageKind.OutputPerPatch: - if (!(operation.GetSource(srcIndex++) is AstOperand varId) || varId.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand varId || varId.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -636,7 +638,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput)) { - if (!(operation.GetSource(srcIndex++) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -733,4 +735,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return swizzle; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenPacking.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenPacking.cs index 5a888e9c5..ad84c4850 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenPacking.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenPacking.cs @@ -53,4 +53,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return $".{"xy".AsSpan(index, 1)}"; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenVector.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenVector.cs index f09ea2e8a..70174a5ba 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenVector.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstGenVector.cs @@ -29,4 +29,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstInfo.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstInfo.cs index 7b2a6b464..a784e2bb3 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstInfo.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstInfo.cs @@ -10,9 +10,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions public InstInfo(InstType type, string opName, int precedence) { - Type = type; - OpName = opName; + Type = type; + OpName = opName; Precedence = precedence; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstType.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstType.cs index 84e36cdd6..56985ae08 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstType.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/InstType.cs @@ -1,33 +1,35 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum InstType { - OpNullary = Op | 0, - OpUnary = Op | 1, - OpBinary = Op | 2, + OpNullary = Op | 0, + OpUnary = Op | 1, + OpBinary = Op | 2, OpBinaryCom = Op | 2 | Commutative, - OpTernary = Op | 3, + OpTernary = Op | 3, - CallNullary = Call | 0, - CallUnary = Call | 1, - CallBinary = Call | 2, - CallTernary = Call | 3, + CallNullary = Call | 0, + CallUnary = Call | 1, + CallBinary = Call | 2, + CallTernary = Call | 3, CallQuaternary = Call | 4, // The atomic instructions have one extra operand, // for the storage slot and offset pair. - AtomicBinary = Call | Atomic | 3, + AtomicBinary = Call | Atomic | 3, AtomicTernary = Call | Atomic | 4, Commutative = 1 << 8, - Op = 1 << 9, - Call = 1 << 10, - Atomic = 1 << 11, - Special = 1 << 12, + Op = 1 << 9, + Call = 1 << 10, + Atomic = 1 << 11, + Special = 1 << 12, - ArityMask = 0xff + ArityMask = 0xff, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/IoMap.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/IoMap.cs index 2a73b8b07..3f88d2b32 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/IoMap.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/Instructions/IoMap.cs @@ -28,7 +28,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions IoVariable.FragmentOutputColor => GetFragmentOutputColorVariableName(config, location), IoVariable.FragmentOutputDepth => ("gl_FragDepth", AggregateType.FP32), IoVariable.FrontColorDiffuse => ("gl_FrontColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated. - IoVariable.FrontColorSpecular => ("gl_FrontSecondaryColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated. + IoVariable.FrontColorSpecular => ("gl_FrontSecondaryColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated. IoVariable.FrontFacing => ("gl_FrontFacing", AggregateType.Bool), IoVariable.InstanceId => ("gl_InstanceID", AggregateType.S32), IoVariable.InstanceIndex => ("gl_InstanceIndex", AggregateType.S32), @@ -56,7 +56,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions IoVariable.VertexIndex => ("gl_VertexIndex", AggregateType.S32), IoVariable.ViewportIndex => ("gl_ViewportIndex", AggregateType.S32), IoVariable.ViewportMask => ("gl_ViewportMask", AggregateType.Array | AggregateType.S32), - _ => (null, AggregateType.Invalid) + _ => (null, AggregateType.Invalid), }; } @@ -139,4 +139,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions return (name, config.GetUserDefinedType(location, isOutput)); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/NumberFormatter.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/NumberFormatter.cs index eb27e9bf1..28e44c900 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/NumberFormatter.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/NumberFormatter.cs @@ -101,4 +101,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl return "0x" + value.ToString("X", CultureInfo.InvariantCulture) + "u"; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/OperandManager.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/OperandManager.cs index 4f6ca642c..0ca3b55fc 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/OperandManager.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/OperandManager.cs @@ -5,7 +5,6 @@ using Ryujinx.Graphics.Shader.Translation; using System; using System.Collections.Generic; using System.Diagnostics; - using static Ryujinx.Graphics.Shader.StructuredIr.InstructionInfo; namespace Ryujinx.Graphics.Shader.CodeGen.Glsl @@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { private static readonly string[] _stagePrefixes = new string[] { "cp", "vp", "tcp", "tep", "gp", "fp" }; - private Dictionary _locals; + private readonly Dictionary _locals; public OperandManager() { @@ -38,7 +37,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl OperandType.Constant => NumberFormatter.FormatInt(operand.Value), OperandType.LocalVariable => _locals[operand], OperandType.Undefined => DefaultNames.UndefinedName, - _ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\".") + _ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\"."), }; } @@ -96,11 +95,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl return _stagePrefixes[index]; } - private static char GetSwizzleMask(int value) - { - return "xyzw"[value]; - } - public static string GetArgumentName(int argIndex) { return $"{DefaultNames.ArgumentNamePrefix}{argIndex}"; @@ -119,12 +113,12 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { case StorageKind.ConstantBuffer: case StorageKind.StorageBuffer: - if (!(operation.GetSource(0) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant) + if (operation.GetSource(0) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand."); } - if (!(operation.GetSource(1) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant) + if (operation.GetSource(1) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand."); } @@ -138,7 +132,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl case StorageKind.LocalMemory: case StorageKind.SharedMemory: - if (!(operation.GetSource(0) is AstOperand bindingId) || bindingId.Type != OperandType.Constant) + if (operation.GetSource(0) is not AstOperand { Type: OperandType.Constant } bindingId) { throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand."); } @@ -153,7 +147,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl case StorageKind.InputPerPatch: case StorageKind.Output: case StorageKind.OutputPerPatch: - if (!(operation.GetSource(0) is AstOperand varId) || varId.Type != OperandType.Constant) + if (operation.GetSource(0) is not AstOperand varId || varId.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand."); } @@ -166,7 +160,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput)) { - if (!(operation.GetSource(1) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant) + if (operation.GetSource(1) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand."); } @@ -232,4 +226,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/TypeConversion.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/TypeConversion.cs index 22c8623ce..3d7d0d0c1 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/TypeConversion.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Glsl/TypeConversion.cs @@ -10,9 +10,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { public static string ReinterpretCast( CodeGenContext context, - IAstNode node, - AggregateType srcType, - AggregateType dstType) + IAstNode node, + AggregateType srcType, + AggregateType dstType) { if (node is AstOperand operand && operand.Type == OperandType.Constant) { @@ -38,18 +38,24 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl { switch (dstType) { - case AggregateType.Bool: return $"(floatBitsToInt({expr}) != 0)"; - case AggregateType.S32: return $"floatBitsToInt({expr})"; - case AggregateType.U32: return $"floatBitsToUint({expr})"; + case AggregateType.Bool: + return $"(floatBitsToInt({expr}) != 0)"; + case AggregateType.S32: + return $"floatBitsToInt({expr})"; + case AggregateType.U32: + return $"floatBitsToUint({expr})"; } } else if (dstType == AggregateType.FP32) { switch (srcType) { - case AggregateType.Bool: return $"intBitsToFloat({ReinterpretBoolToInt(expr, node, AggregateType.S32)})"; - case AggregateType.S32: return $"intBitsToFloat({expr})"; - case AggregateType.U32: return $"uintBitsToFloat({expr})"; + case AggregateType.Bool: + return $"intBitsToFloat({ReinterpretBoolToInt(expr, node, AggregateType.S32)})"; + case AggregateType.S32: + return $"intBitsToFloat({expr})"; + case AggregateType.U32: + return $"uintBitsToFloat({expr})"; } } else if (srcType == AggregateType.Bool) @@ -76,7 +82,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl private static string ReinterpretBoolToInt(string expr, IAstNode node, AggregateType dstType) { - string trueExpr = NumberFormatter.FormatInt(IrConsts.True, dstType); + string trueExpr = NumberFormatter.FormatInt(IrConsts.True, dstType); string falseExpr = NumberFormatter.FormatInt(IrConsts.False, dstType); expr = InstGenHelper.Enclose(expr, node, Instruction.ConditionalSelect, isLhs: false); @@ -84,4 +90,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl return $"({expr} ? {trueExpr} : {falseExpr})"; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/CodeGenContext.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/CodeGenContext.cs index a4daaa67e..9956e90a3 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/CodeGenContext.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/CodeGenContext.cs @@ -1,13 +1,14 @@ -using Ryujinx.Graphics.Shader.StructuredIr; +using Ryujinx.Graphics.Shader.IntermediateRepresentation; +using Ryujinx.Graphics.Shader.StructuredIr; using Ryujinx.Graphics.Shader.Translation; using Spv.Generator; using System; using System.Collections.Generic; using static Spv.Specification; +using Instruction = Spv.Generator.Instruction; namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { - using IrConsts = IntermediateRepresentation.IrConsts; using IrOperandType = IntermediateRepresentation.OperandType; partial class CodeGenContext : Module @@ -36,15 +37,15 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv public Dictionary OutputsPerPatch { get; } = new Dictionary(); public StructuredFunction CurrentFunction { get; set; } - private readonly Dictionary _locals = new Dictionary(); - private readonly Dictionary _localForArgs = new Dictionary(); - private readonly Dictionary _funcArgs = new Dictionary(); - private readonly Dictionary _functions = new Dictionary(); + private readonly Dictionary _locals = new(); + private readonly Dictionary _localForArgs = new(); + private readonly Dictionary _funcArgs = new(); + private readonly Dictionary _functions = new(); private class BlockState { private int _entryCount; - private readonly List _labels = new List(); + private readonly List _labels = new(); public Instruction GetNextLabel(CodeGenContext context) { @@ -67,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv } } - private readonly Dictionary _labels = new Dictionary(); + private readonly Dictionary _labels = new(); public Dictionary LoopTargets { get; set; } @@ -98,7 +99,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv InputTopology.LinesAdjacency => 2, InputTopology.Triangles => 3, InputTopology.TrianglesAdjacency => 3, - _ => throw new InvalidOperationException($"Invalid input topology \"{inPrimitive}\".") + _ => throw new InvalidOperationException($"Invalid input topology \"{inPrimitive}\"."), }; } @@ -222,7 +223,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv IrOperandType.Constant => GetConstant(type, operand), IrOperandType.LocalVariable => GetLocal(type, operand), IrOperandType.Undefined => GetUndefined(type), - _ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\".") + _ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\"."), }; } @@ -259,7 +260,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv AggregateType.Bool => ConstantFalse(TypeBool()), AggregateType.FP32 => Constant(TypeFP32(), 0f), AggregateType.FP64 => Constant(TypeFP64(), 0d), - _ => Constant(GetType(type), 0) + _ => Constant(GetType(type), 0), }; } @@ -272,7 +273,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv AggregateType.FP64 => Constant(TypeFP64(), (double)BitConverter.Int32BitsToSingle(operand.Value)), AggregateType.S32 => Constant(TypeS32(), operand.Value), AggregateType.U32 => Constant(TypeU32(), (uint)operand.Value), - _ => throw new ArgumentException($"Invalid type \"{type}\".") + _ => throw new ArgumentException($"Invalid type \"{type}\"."), }; } @@ -328,7 +329,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv AggregateType.Vector2 => 2, AggregateType.Vector3 => 3, AggregateType.Vector4 => 4, - _ => 1 + _ => 1, }; return TypeVector(GetType(type & ~AggregateType.ElementCountMask), vectorLength); @@ -342,7 +343,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv AggregateType.FP64 => TypeFP64(), AggregateType.S32 => TypeS32(), AggregateType.U32 => TypeU32(), - _ => throw new ArgumentException($"Invalid attribute type \"{type}\".") + _ => throw new ArgumentException($"Invalid attribute type \"{type}\"."), }; } @@ -359,7 +360,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv } else if (srcType == AggregateType.Bool) { - var intTrue = Constant(TypeS32(), IrConsts.True); + var intTrue = Constant(TypeS32(), IrConsts.True); var intFalse = Constant(TypeS32(), IrConsts.False); return BitcastIfNeeded(dstType, AggregateType.S32, Select(TypeS32(), value, intTrue, intFalse)); diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Declarations.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Declarations.cs index 59acea4f6..da1e385a7 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Declarations.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Declarations.cs @@ -1,5 +1,4 @@ -using Ryujinx.Common; -using Ryujinx.Graphics.Shader.IntermediateRepresentation; +using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.StructuredIr; using Ryujinx.Graphics.Shader.Translation; using Spv.Generator; @@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { static class Declarations { - private static readonly string[] StagePrefixes = new string[] { "cp", "vp", "tcp", "tep", "gp", "fp" }; + private static readonly string[] _stagePrefixes = { "cp", "vp", "tcp", "tep", "gp", "fp" }; public static void DeclareParameters(CodeGenContext context, StructuredFunction function) { @@ -107,7 +106,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv private static void DeclareBuffers(CodeGenContext context, IEnumerable buffers, bool isBuffer) { - HashSet decoratedTypes = new HashSet(); + HashSet decoratedTypes = new(); foreach (BufferDefinition buffer in buffers) { @@ -199,7 +198,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv SamplerType.Texture3D => Dim.Dim3D, SamplerType.TextureCube => Dim.Cube, SamplerType.TextureBuffer => Dim.Buffer, - _ => throw new InvalidOperationException($"Invalid sampler type \"{descriptor.Type & SamplerType.Mask}\".") + _ => throw new InvalidOperationException($"Invalid sampler type \"{descriptor.Type & SamplerType.Mask}\"."), }; var imageType = context.TypeImage( @@ -282,7 +281,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv SamplerType.Texture3D => Dim.Dim3D, SamplerType.TextureCube => Dim.Cube, SamplerType.TextureBuffer => Dim.Buffer, - _ => throw new ArgumentException($"Invalid sampler type \"{type & SamplerType.Mask}\".") + _ => throw new ArgumentException($"Invalid sampler type \"{type & SamplerType.Mask}\"."), }; } @@ -330,7 +329,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv TextureFormat.R10G10B10A2Unorm => ImageFormat.Rgb10A2, TextureFormat.R10G10B10A2Uint => ImageFormat.Rgb10a2ui, TextureFormat.R11G11B10Float => ImageFormat.R11fG11fB10f, - _ => throw new ArgumentException($"Invalid texture format \"{format}\".") + _ => throw new ArgumentException($"Invalid texture format \"{format}\"."), }; } @@ -352,7 +351,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv (_, AggregateType varType) = IoMap.GetSpirvBuiltIn(ioVariable); AggregateType elemType = varType & AggregateType.ElementTypeMask; - if (elemType == AggregateType.S32 || elemType == AggregateType.U32) + if (elemType is AggregateType.S32 or AggregateType.U32) { iq = PixelImap.Constant; } @@ -410,7 +409,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv 2 => AggregateType.Vector2, 3 => AggregateType.Vector3, 4 => AggregateType.Vector4, - _ => AggregateType.Invalid + _ => AggregateType.Invalid, }; } @@ -420,7 +419,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv if (!isPerPatch && IoMap.IsPerVertex(ioVariable, context.Config.Stage, isOutput)) { int arraySize = context.Config.Stage == ShaderStage.Geometry ? context.InputVertices : 32; - spvType = context.TypeArray(spvType, context.Constant(context.TypeU32(), (LiteralInteger)arraySize)); + spvType = context.TypeArray(spvType, context.Constant(context.TypeU32(), arraySize)); if (context.Config.GpPassthrough && context.Config.GpuAccessor.QueryHostSupportsGeometryShaderPassthrough()) { @@ -542,7 +541,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv private static string GetStagePrefix(ShaderStage stage) { - return StagePrefixes[(int)stage]; + return _stagePrefixes[(int)stage]; } } } diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/EnumConversion.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/EnumConversion.cs index 72541774d..2bb7e8369 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/EnumConversion.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/EnumConversion.cs @@ -15,7 +15,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv ShaderStage.TessellationEvaluation => ExecutionModel.TessellationEvaluation, ShaderStage.Geometry => ExecutionModel.Geometry, ShaderStage.Fragment => ExecutionModel.Fragment, - _ => throw new ArgumentException($"Invalid shader stage \"{stage}\".") + _ => throw new ArgumentException($"Invalid shader stage \"{stage}\"."), }; } } diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Instructions.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Instructions.cs index b451f7a48..a53b40b24 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Instructions.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/Instructions.cs @@ -14,19 +14,20 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv static class Instructions { - private const MemorySemanticsMask DefaultMemorySemantics = + private const MemorySemanticsMask DefaultMemorySemantics = MemorySemanticsMask.ImageMemory | MemorySemanticsMask.AtomicCounterMemory | MemorySemanticsMask.WorkgroupMemory | MemorySemanticsMask.UniformMemory | MemorySemanticsMask.AcquireRelease; - private static readonly Func[] InstTable; + private static readonly Func[] _instTable; static Instructions() { - InstTable = new Func[(int)Instruction.Count]; + _instTable = new Func[(int)Instruction.Count]; +#pragma warning disable IDE0055 // Disable formatting Add(Instruction.Absolute, GenerateAbsolute); Add(Instruction.Add, GenerateAdd); Add(Instruction.AtomicAdd, GenerateAtomicAdd); @@ -141,16 +142,17 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv Add(Instruction.VoteAll, GenerateVoteAll); Add(Instruction.VoteAllEqual, GenerateVoteAllEqual); Add(Instruction.VoteAny, GenerateVoteAny); +#pragma warning restore IDE0055 } private static void Add(Instruction inst, Func handler) { - InstTable[(int)(inst & Instruction.Mask)] = handler; + _instTable[(int)(inst & Instruction.Mask)] = handler; } public static OperationResult Generate(CodeGenContext context, AstOperation operation) { - var handler = InstTable[(int)(operation.Inst & Instruction.Mask)]; + var handler = _instTable[(int)(operation.Inst & Instruction.Mask)]; if (handler != null) { return handler(context, operation); @@ -305,7 +307,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv Debug.Assert(funcId.Type == OperandType.Constant); - (var function, var spvFunc) = context.GetFunction(funcId.Value); + var (function, spvFunc) = context.GetFunction(funcId.Value); var args = new SpvInstruction[operation.SourcesCount - 1]; var spvLocals = context.GetLocalForArgsPointers(funcId.Value); @@ -615,7 +617,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv }); } - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; int srcIndex = isBindless ? 1 : 0; @@ -625,11 +627,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return context.Get(type, texOp.GetSource(srcIndex++)); } - SpvInstruction index = null; - if (isIndexed) { - index = Src(AggregateType.S32); + Src(AggregateType.S32); } int coordsCount = texOp.Type.GetDimensions(); @@ -657,9 +657,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv SpvInstruction value = Src(componentType); - (var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; + (SpvInstruction imageType, SpvInstruction imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; - var image = context.Load(imageType, imageVariable); + context.Load(imageType, imageVariable); SpvInstruction resultType = context.GetType(componentType); SpvInstruction imagePointerType = context.TypePointer(StorageClass.Image, resultType); @@ -670,21 +670,21 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv var result = (texOp.Flags & TextureFlags.AtomicMask) switch { - TextureFlags.Add => context.AtomicIAdd(resultType, pointer, one, zero, value), - TextureFlags.Minimum => componentType == AggregateType.S32 + TextureFlags.Add => context.AtomicIAdd(resultType, pointer, one, zero, value), + TextureFlags.Minimum => componentType == AggregateType.S32 ? context.AtomicSMin(resultType, pointer, one, zero, value) : context.AtomicUMin(resultType, pointer, one, zero, value), - TextureFlags.Maximum => componentType == AggregateType.S32 + TextureFlags.Maximum => componentType == AggregateType.S32 ? context.AtomicSMax(resultType, pointer, one, zero, value) : context.AtomicUMax(resultType, pointer, one, zero, value), - TextureFlags.Increment => context.AtomicIIncrement(resultType, pointer, one, zero), - TextureFlags.Decrement => context.AtomicIDecrement(resultType, pointer, one, zero), + TextureFlags.Increment => context.AtomicIIncrement(resultType, pointer, one, zero), + TextureFlags.Decrement => context.AtomicIDecrement(resultType, pointer, one, zero), TextureFlags.BitwiseAnd => context.AtomicAnd(resultType, pointer, one, zero, value), - TextureFlags.BitwiseOr => context.AtomicOr(resultType, pointer, one, zero, value), + TextureFlags.BitwiseOr => context.AtomicOr(resultType, pointer, one, zero, value), TextureFlags.BitwiseXor => context.AtomicXor(resultType, pointer, one, zero, value), - TextureFlags.Swap => context.AtomicExchange(resultType, pointer, one, zero, value), - TextureFlags.CAS => context.AtomicCompareExchange(resultType, pointer, one, zero, zero, Src(componentType), value), - _ => context.AtomicIAdd(resultType, pointer, one, zero, value), + TextureFlags.Swap => context.AtomicExchange(resultType, pointer, one, zero, value), + TextureFlags.CAS => context.AtomicCompareExchange(resultType, pointer, one, zero, zero, Src(componentType), value), + _ => context.AtomicIAdd(resultType, pointer, one, zero, value), }; return new OperationResult(componentType, result); @@ -704,7 +704,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return GetZeroOperationResult(context, texOp, componentType, isVector: true); } - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; int srcIndex = isBindless ? 1 : 0; @@ -714,11 +714,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return context.Get(type, texOp.GetSource(srcIndex++)); } - SpvInstruction index = null; - if (isIndexed) { - index = Src(AggregateType.S32); + Src(AggregateType.S32); } int coordsCount = texOp.Type.GetDimensions(); @@ -744,7 +742,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv pCoords = Src(AggregateType.S32); } - (var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; + var (imageType, imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; var image = context.Load(imageType, imageVariable); var imageComponentType = context.GetType(componentType); @@ -768,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return OperationResult.Invalid; } - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; int srcIndex = isBindless ? 1 : 0; @@ -778,11 +776,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return context.Get(type, texOp.GetSource(srcIndex++)); } - SpvInstruction index = null; - if (isIndexed) { - index = Src(AggregateType.S32); + Src(AggregateType.S32); } int coordsCount = texOp.Type.GetDimensions(); @@ -833,7 +829,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv var texel = context.CompositeConstruct(context.TypeVector(context.GetType(componentType), ComponentsCount), cElems); - (var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; + var (imageType, imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)]; var image = context.Load(imageType, imageVariable); @@ -886,11 +882,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return context.Get(type, texOp.GetSource(srcIndex++)); } - SpvInstruction index = null; - if (isIndexed) { - index = Src(AggregateType.S32); + Src(AggregateType.S32); } int pCount = texOp.Type.GetDimensions(); @@ -916,7 +910,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format); - (_, var sampledImageType, var sampledImageVariable) = context.Samplers[meta]; + var (_, sampledImageType, sampledImageVariable) = context.Samplers[meta]; var image = context.Load(sampledImageType, sampledImageVariable); @@ -973,7 +967,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv loopBlock = loopBlock.Parent; } - (var loopTarget, var continueTarget) = context.LoopTargets[loopBlock]; + (_, SpvInstruction continueTarget) = context.LoopTargets[loopBlock]; context.Branch(continueTarget); @@ -1278,19 +1272,19 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { AstTextureOperation texOp = (AstTextureOperation)operation; - bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; + bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; + bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; bool hasDerivatives = (texOp.Flags & TextureFlags.Derivatives) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; - bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; - bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; - bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0; + bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; + bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; + bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; + bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; + bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0; - bool isArray = (texOp.Type & SamplerType.Array) != 0; - bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; bool isMultisample = (texOp.Type & SamplerType.Multisample) != 0; - bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; + bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; bool colorIsVector = isGather || !isShadow; @@ -1307,11 +1301,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return context.Get(type, texOp.GetSource(srcIndex++)); } - SpvInstruction index = null; - if (isIndexed) { - index = Src(AggregateType.S32); + Src(AggregateType.S32); } int coordsCount = texOp.Type.GetDimensions(); @@ -1395,7 +1387,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv derivatives = new[] { AssembleDerivativesVector(coordsCount), // dPdx - AssembleDerivativesVector(coordsCount) // dPdy + AssembleDerivativesVector(coordsCount), // dPdy }; } @@ -1445,7 +1437,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv AssembleOffsetVector(coordsCount), AssembleOffsetVector(coordsCount), AssembleOffsetVector(coordsCount), - AssembleOffsetVector(coordsCount) + AssembleOffsetVector(coordsCount), }; } @@ -1474,7 +1466,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv // not needed for shadow samplers. if (isGather && !isShadow) { - compIdx = Src(AggregateType.S32); + compIdx = Src(AggregateType.S32); } var operandsList = new List(); @@ -1521,7 +1513,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format); - (var imageType, var sampledImageType, var sampledImageVariable) = context.Samplers[meta]; + var (imageType, sampledImageType, sampledImageVariable) = context.Samplers[meta]; var image = context.Load(sampledImageType, sampledImageVariable); @@ -1595,16 +1587,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; - SpvInstruction index = null; - if (isIndexed) { - index = context.GetS32(texOp.GetSource(0)); + context.GetS32(texOp.GetSource(0)); } var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format); - (var imageType, var sampledImageType, var sampledImageVariable) = context.Samplers[meta]; + (SpvInstruction imageType, SpvInstruction sampledImageType, SpvInstruction sampledImageVariable) = context.Samplers[meta]; var image = context.Load(sampledImageType, sampledImageVariable); image = context.Image(imageType, image); @@ -1809,12 +1799,12 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { case StorageKind.ConstantBuffer: case StorageKind.StorageBuffer: - if (!(operation.GetSource(srcIndex++) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } - if (!(operation.GetSource(srcIndex) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -1833,7 +1823,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv case StorageKind.LocalMemory: case StorageKind.SharedMemory: - if (!(operation.GetSource(srcIndex++) is AstOperand bindingId) || bindingId.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand { Type: OperandType.Constant } bindingId) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -1856,7 +1846,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv case StorageKind.InputPerPatch: case StorageKind.Output: case StorageKind.OutputPerPatch: - if (!(operation.GetSource(srcIndex++) is AstOperand varId) || varId.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand varId || varId.Type != OperandType.Constant) { throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -1869,7 +1859,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput)) { - if (!(operation.GetSource(srcIndex++) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant) + if (operation.GetSource(srcIndex++) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant) { throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand."); } @@ -1964,7 +1954,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv private static SpvInstruction GetScalarInput(CodeGenContext context, IoVariable ioVariable) { - (_, var varType) = IoMap.GetSpirvBuiltIn(ioVariable); + var (_, varType) = IoMap.GetSpirvBuiltIn(ioVariable); varType &= AggregateType.ElementTypeMask; var ioDefinition = new IoDefinition(StorageKind.Input, ioVariable); @@ -2061,10 +2051,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv return new OperationResult(AggregateType.Bool, emitB(context.TypeBool(), context.Get(AggregateType.Bool, source))); } - private static OperationResult GenerateUnaryFP32( - CodeGenContext context, - AstOperation operation, - Func emit) + private static OperationResult GenerateUnaryFP32( + CodeGenContext context, + AstOperation operation, + Func emit) { var source = operation.GetSource(0); return new OperationResult(AggregateType.FP32, emit(context.TypeFP32(), context.GetFP32(source))); diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/IoMap.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/IoMap.cs index d2ff0085c..8a6103237 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/IoMap.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/IoMap.cs @@ -45,7 +45,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv IoVariable.VertexIndex => (BuiltIn.VertexIndex, AggregateType.S32), IoVariable.ViewportIndex => (BuiltIn.ViewportIndex, AggregateType.S32), IoVariable.ViewportMask => (BuiltIn.ViewportMaskNV, AggregateType.Array | AggregateType.S32), - _ => (default, AggregateType.Invalid) + _ => (default, AggregateType.Invalid), }; } @@ -58,7 +58,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv IoVariable.TessellationLevelOuter => 4, IoVariable.ViewportMask => 1, IoVariable.UserDefined => MaxAttributes, - _ => 1 + _ => 1, }; } @@ -74,13 +74,11 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv case IoVariable.ClipDistance: case IoVariable.PointCoord: case IoVariable.ViewportMask: - return !isOutput && - (stage == ShaderStage.TessellationControl || - stage == ShaderStage.TessellationEvaluation || - stage == ShaderStage.Geometry); + return !isOutput && + stage is ShaderStage.TessellationControl or ShaderStage.TessellationEvaluation or ShaderStage.Geometry; } return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/OperationResult.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/OperationResult.cs index f80c8110b..a6e8e91f6 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/OperationResult.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/OperationResult.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { readonly struct OperationResult { - public static OperationResult Invalid => new OperationResult(AggregateType.Invalid, null); + public static OperationResult Invalid => new(AggregateType.Invalid, null); public AggregateType Type { get; } public Instruction Value { get; } diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/SpirvGenerator.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/SpirvGenerator.cs index 5c736b605..c8fcd75a1 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/SpirvGenerator.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/SpirvGenerator.cs @@ -17,15 +17,15 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { // Resource pools for Spirv generation. Note: Increase count when more threads are being used. private const int GeneratorPoolCount = 1; - private static ObjectPool InstructionPool; - private static ObjectPool IntegerPool; - private static object PoolLock; + private static readonly ObjectPool _instructionPool; + private static readonly ObjectPool _integerPool; + private static readonly object _poolLock; static SpirvGenerator() { - InstructionPool = new (() => new SpvInstructionPool(), GeneratorPoolCount); - IntegerPool = new (() => new SpvLiteralIntegerPool(), GeneratorPoolCount); - PoolLock = new object(); + _instructionPool = new(() => new SpvInstructionPool(), GeneratorPoolCount); + _integerPool = new(() => new SpvLiteralIntegerPool(), GeneratorPoolCount); + _poolLock = new object(); } private const HelperFunctionsMask NeedsInvocationIdMask = @@ -40,13 +40,13 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv SpvInstructionPool instPool; SpvLiteralIntegerPool integerPool; - lock (PoolLock) + lock (_poolLock) { - instPool = InstructionPool.Allocate(); - integerPool = IntegerPool.Allocate(); + instPool = _instructionPool.Allocate(); + integerPool = _integerPool.Allocate(); } - CodeGenContext context = new CodeGenContext(info, config, instPool, integerPool); + CodeGenContext context = new(info, config, instPool, integerPool); context.AddCapability(Capability.GroupNonUniformBallot); context.AddCapability(Capability.GroupNonUniformShuffle); @@ -133,10 +133,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv byte[] result = context.Generate(); - lock (PoolLock) + lock (_poolLock) { - InstructionPool.Release(instPool); - IntegerPool.Release(integerPool); + _instructionPool.Release(instPool); + _integerPool.Release(integerPool); } return result; @@ -144,7 +144,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv private static void Generate(CodeGenContext context, StructuredProgramInfo info, int funcIndex) { - (var function, var spvFunc) = context.GetFunction(funcIndex); + var (function, spvFunc) = context.GetFunction(funcIndex); context.CurrentFunction = function; context.AddFunction(spvFunc); @@ -160,7 +160,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv Generate(context, function.MainBlock); // Functions must always end with a return. - if (!(function.MainBlock.Last is AstOperation operation) || + if (function.MainBlock.Last is not AstOperation operation || (operation.Inst != Instruction.Return && operation.Inst != Instruction.Discard)) { context.Return(); @@ -232,7 +232,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv InputTopology.LinesAdjacency => ExecutionMode.InputLinesAdjacency, InputTopology.Triangles => ExecutionMode.Triangles, InputTopology.TrianglesAdjacency => ExecutionMode.InputTrianglesAdjacency, - _ => throw new InvalidOperationException($"Invalid input topology \"{inputTopology}\".") + _ => throw new InvalidOperationException($"Invalid input topology \"{inputTopology}\"."), }); context.AddExecutionMode(spvFunc, ExecutionMode.Invocations, (SpvLiteralInteger)context.Config.ThreadsPerInputPrimitive); @@ -242,7 +242,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv OutputTopology.PointList => ExecutionMode.OutputPoints, OutputTopology.LineStrip => ExecutionMode.OutputLineStrip, OutputTopology.TriangleStrip => ExecutionMode.OutputTriangleStrip, - _ => throw new InvalidOperationException($"Invalid output topology \"{context.Config.OutputTopology}\".") + _ => throw new InvalidOperationException($"Invalid output topology \"{context.Config.OutputTopology}\"."), }); int maxOutputVertices = context.Config.GpPassthrough ? context.InputVertices : context.Config.MaxOutputVertices; @@ -294,7 +294,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv private static void Generate(CodeGenContext context, AstBlock block) { - AstBlockVisitor visitor = new AstBlockVisitor(block); + AstBlockVisitor visitor = new(block); var loopTargets = new Dictionary(); @@ -346,7 +346,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv // if the condition is true. AstBlock mergeBlock = e.Block.Parent; - (var loopTarget, var continueTarget) = loopTargets[e.Block]; + var (loopTarget, continueTarget) = loopTargets[e.Block]; context.Branch(continueTarget); context.AddLabel(continueTarget); diff --git a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/TextureMeta.cs b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/TextureMeta.cs index 4de056037..56ea9a2a6 100644 --- a/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/TextureMeta.cs +++ b/src/Ryujinx.Graphics.Shader/CodeGen/Spirv/TextureMeta.cs @@ -1,4 +1,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv { readonly record struct TextureMeta(int CbufSlot, int Handle, TextureFormat Format); -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Constants.cs b/src/Ryujinx.Graphics.Shader/Constants.cs index 39d6b2381..cff2c37a0 100644 --- a/src/Ryujinx.Graphics.Shader/Constants.cs +++ b/src/Ryujinx.Graphics.Shader/Constants.cs @@ -17,4 +17,4 @@ namespace Ryujinx.Graphics.Shader public const int TfeBufferBaseBinding = 1; public const int TfeBuffersCount = 4; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/Block.cs b/src/Ryujinx.Graphics.Shader/Decoders/Block.cs index 7d94e3f9a..1a694898b 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/Block.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/Block.cs @@ -92,7 +92,7 @@ namespace Ryujinx.Graphics.Shader.Decoders pushOpInfo.Consumers.Add(rightBlock, local); } - foreach ((ulong key, SyncTarget value) in SyncTargets) + foreach ((ulong key, SyncTarget value) in SyncTargets) { rightBlock.SyncTargets.Add(key, value); } @@ -148,7 +148,7 @@ namespace Ryujinx.Graphics.Shader.Decoders { if (OpCodes.Count != 0) { - return OpCodes[OpCodes.Count - 1]; + return OpCodes[^1]; } return default; @@ -165,4 +165,4 @@ namespace Ryujinx.Graphics.Shader.Decoders PushOpCodes.Add(new PushOpInfo(op)); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/DecodedFunction.cs b/src/Ryujinx.Graphics.Shader/Decoders/DecodedFunction.cs index 7a172fe6f..49cd3a30a 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/DecodedFunction.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/DecodedFunction.cs @@ -45,4 +45,4 @@ namespace Ryujinx.Graphics.Shader.Decoders } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/DecodedProgram.cs b/src/Ryujinx.Graphics.Shader/Decoders/DecodedProgram.cs index 2dd60155e..7776ccc52 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/DecodedProgram.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/DecodedProgram.cs @@ -54,4 +54,4 @@ namespace Ryujinx.Graphics.Shader.Decoders return GetEnumerator(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/Decoder.cs b/src/Ryujinx.Graphics.Shader/Decoders/Decoder.cs index 4e6c6a5df..ba31c0205 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/Decoder.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/Decoder.cs @@ -3,7 +3,6 @@ using System; using System.Collections.Generic; using System.Linq; using System.Runtime.CompilerServices; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Decoders @@ -12,8 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public static DecodedProgram Decode(ShaderConfig config, ulong startAddress) { - Queue functionsQueue = new Queue(); - Dictionary functionsVisited = new Dictionary(); + Queue functionsQueue = new(); + Dictionary functionsVisited = new(); DecodedFunction EnqueueFunction(ulong address) { @@ -30,9 +29,9 @@ namespace Ryujinx.Graphics.Shader.Decoders while (functionsQueue.TryDequeue(out DecodedFunction currentFunction)) { - List blocks = new List(); - Queue workQueue = new Queue(); - Dictionary visited = new Dictionary(); + List blocks = new(); + Queue workQueue = new(); + Dictionary visited = new(); Block GetBlock(ulong blkAddress) { @@ -168,7 +167,7 @@ namespace Ryujinx.Graphics.Shader.Decoders { index = 0; - int left = 0; + int left = 0; int right = blocks.Count - 1; while (left <= right) @@ -273,12 +272,12 @@ namespace Ryujinx.Graphics.Shader.Decoders int offset; int count = 1; bool isStore = false; - bool indexed = false; + bool indexed; bool perPatch = false; if (name == InstName.Ast) { - InstAst opAst = new InstAst(opCode); + InstAst opAst = new(opCode); count = (int)opAst.AlSize + 1; offset = opAst.Imm11; indexed = opAst.Phys; @@ -287,7 +286,7 @@ namespace Ryujinx.Graphics.Shader.Decoders } else if (name == InstName.Ald) { - InstAld opAld = new InstAld(opCode); + InstAld opAld = new(opCode); count = (int)opAld.AlSize + 1; offset = opAld.Imm11; indexed = opAld.Phys; @@ -296,7 +295,7 @@ namespace Ryujinx.Graphics.Shader.Decoders } else /* if (name == InstName.Ipa) */ { - InstIpa opIpa = new InstIpa(opCode); + InstIpa opIpa = new(opCode); offset = opIpa.Imm10; indexed = opIpa.Idx; } @@ -370,7 +369,7 @@ namespace Ryujinx.Graphics.Shader.Decoders private static bool IsUnconditional(ref InstOp op) { - InstConditional condOp = new InstConditional(op.RawOpCode); + InstConditional condOp = new(op.RawOpCode); if ((op.Name == InstName.Bra || op.Name == InstName.Exit) && condOp.Ccc != Ccc.T) { @@ -391,9 +390,9 @@ namespace Ryujinx.Graphics.Shader.Decoders if (lastOp.Name == InstName.Brx && block.Successors.Count == (hasNext ? 1 : 0)) { - HashSet visited = new HashSet(); + HashSet visited = new(); - InstBrx opBrx = new InstBrx(lastOp.RawOpCode); + InstBrx opBrx = new(lastOp.RawOpCode); ulong baseOffset = lastOp.GetAbsoluteAddress(); // An indirect branch could go anywhere, @@ -437,7 +436,7 @@ namespace Ryujinx.Graphics.Shader.Decoders // On a successful match, "BaseOffset" is the offset in bytes where the jump offsets are // located on the constant buffer, and "UpperBound" is the total number of offsets for the BRX, minus 1. - HashSet visited = new HashSet(); + HashSet visited = new(); var ldcLocation = FindFirstRegWrite(visited, new BlockLocation(block, block.OpCodes.Count - 1), brxReg); if (ldcLocation.Block == null || ldcLocation.Block.OpCodes[ldcLocation.Index].Name != InstName.Ldc) @@ -507,7 +506,7 @@ namespace Ryujinx.Graphics.Shader.Decoders private static BlockLocation FindFirstRegWrite(HashSet visited, BlockLocation location, int regIndex) { - Queue toVisit = new Queue(); + Queue toVisit = new(); toVisit.Enqueue(location); visited.Add(location.Block); @@ -554,10 +553,10 @@ namespace Ryujinx.Graphics.Shader.Decoders { Brk, Cont, - Sync + Sync, } - private struct PathBlockState + private readonly struct PathBlockState { public Block Block { get; } @@ -565,37 +564,37 @@ namespace Ryujinx.Graphics.Shader.Decoders { None, PopPushOp, - PushBranchOp + PushBranchOp, } - private RestoreType _restoreType; + private readonly RestoreType _restoreType; - private ulong _restoreValue; - private MergeType _restoreMergeType; + private readonly ulong _restoreValue; + private readonly MergeType _restoreMergeType; public bool ReturningFromVisit => _restoreType != RestoreType.None; public PathBlockState(Block block) { - Block = block; - _restoreType = RestoreType.None; - _restoreValue = 0; + Block = block; + _restoreType = RestoreType.None; + _restoreValue = 0; _restoreMergeType = default; } public PathBlockState(int oldStackSize) { - Block = null; - _restoreType = RestoreType.PopPushOp; - _restoreValue = (ulong)oldStackSize; + Block = null; + _restoreType = RestoreType.PopPushOp; + _restoreValue = (ulong)oldStackSize; _restoreMergeType = default; } public PathBlockState(ulong syncAddress, MergeType mergeType) { - Block = null; - _restoreType = RestoreType.PushBranchOp; - _restoreValue = syncAddress; + Block = null; + _restoreType = RestoreType.PushBranchOp; + _restoreValue = syncAddress; _restoreMergeType = mergeType; } @@ -622,9 +621,9 @@ namespace Ryujinx.Graphics.Shader.Decoders Block target = blocks[pushOp.GetAbsoluteAddress()]; - Stack workQueue = new Stack(); - HashSet visited = new HashSet(); - Stack<(ulong, MergeType)> branchStack = new Stack<(ulong, MergeType)>(); + Stack workQueue = new(); + HashSet visited = new(); + Stack<(ulong, MergeType)> branchStack = new(); void Push(PathBlockState pbs) { @@ -759,7 +758,7 @@ namespace Ryujinx.Graphics.Shader.Decoders { InstName.Pbk => MergeType.Brk, InstName.Pcnt => MergeType.Cont, - _ => MergeType.Sync + _ => MergeType.Sync, }; } @@ -769,8 +768,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { InstName.Brk => MergeType.Brk, InstName.Cont => MergeType.Cont, - _ => MergeType.Sync + _ => MergeType.Sync, }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/InstDecoders.cs b/src/Ryujinx.Graphics.Shader/Decoders/InstDecoders.cs index c7c506ec4..8bf5671ac 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/InstDecoders.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/InstDecoders.cs @@ -684,7 +684,7 @@ namespace Ryujinx.Graphics.Shader.Decoders Texture2DLodZeroMultisample = 0x6, Texture3DLodZero = 0x7, Texture2DArrayLodZero = 0x8, - Texture2DLodLevelOffset = 0xc + Texture2DLodLevelOffset = 0xc, } enum TexComp @@ -848,18 +848,18 @@ namespace Ryujinx.Graphics.Shader.Decoders S16h0 = 3, } - struct InstConditional + readonly struct InstConditional { - private ulong _opcode; + private readonly ulong _opcode; public InstConditional(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstAl2p + readonly struct InstAl2p { - private ulong _opcode; + private readonly ulong _opcode; public InstAl2p(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -871,9 +871,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 44) & 0x7); } - struct InstAld + readonly struct InstAld { - private ulong _opcode; + private readonly ulong _opcode; public InstAld(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -887,9 +887,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Phys => !P && Imm11 == 0 && SrcA != RegisterConsts.RegisterZeroIndex; } - struct InstAst + readonly struct InstAst { - private ulong _opcode; + private readonly ulong _opcode; public InstAst(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)(_opcode & 0xFF); @@ -902,9 +902,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Phys => !P && Imm11 == 0 && SrcA != RegisterConsts.RegisterZeroIndex; } - struct InstAtom + readonly struct InstAtom { - private ulong _opcode; + private readonly ulong _opcode; public InstAtom(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -917,9 +917,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool E => (_opcode & 0x1000000000000) != 0; } - struct InstAtomCas + readonly struct InstAtomCas { - private ulong _opcode; + private readonly ulong _opcode; public InstAtomCas(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -930,9 +930,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool E => (_opcode & 0x1000000000000) != 0; } - struct InstAtoms + readonly struct InstAtoms { - private ulong _opcode; + private readonly ulong _opcode; public InstAtoms(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -944,9 +944,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public AtomOp AtomOp => (AtomOp)((_opcode >> 52) & 0xF); } - struct InstAtomsCas + readonly struct InstAtomsCas { - private ulong _opcode; + private readonly ulong _opcode; public InstAtomsCas(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -956,9 +956,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int AtomsBcRz => (int)((_opcode >> 28) & 0x3); } - struct InstB2r + readonly struct InstB2r { - private ulong _opcode; + private readonly ulong _opcode; public InstB2r(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int DestPred => (int)((_opcode >> 45) & 0x7); @@ -968,9 +968,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public BarMode Mode => (BarMode)((_opcode >> 32) & 0x3); } - struct InstBar + readonly struct InstBar { - private ulong _opcode; + private readonly ulong _opcode; public InstBar(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Imm12 => (int)((_opcode >> 20) & 0xFFF); @@ -984,9 +984,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BFixBar => (_opcode & 0x80000000000) != 0; } - struct InstBfeR + readonly struct InstBfeR { - private ulong _opcode; + private readonly ulong _opcode; public InstBfeR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -998,9 +998,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Brev => (_opcode & 0x10000000000) != 0; } - struct InstBfeI + readonly struct InstBfeI { - private ulong _opcode; + private readonly ulong _opcode; public InstBfeI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1012,9 +1012,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Brev => (_opcode & 0x10000000000) != 0; } - struct InstBfeC + readonly struct InstBfeC { - private ulong _opcode; + private readonly ulong _opcode; public InstBfeC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1027,9 +1027,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Brev => (_opcode & 0x10000000000) != 0; } - struct InstBfiR + readonly struct InstBfiR { - private ulong _opcode; + private readonly ulong _opcode; public InstBfiR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1040,9 +1040,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x800000000000) != 0; } - struct InstBfiI + readonly struct InstBfiI { - private ulong _opcode; + private readonly ulong _opcode; public InstBfiI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1053,9 +1053,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x800000000000) != 0; } - struct InstBfiC + readonly struct InstBfiC { - private ulong _opcode; + private readonly ulong _opcode; public InstBfiC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1067,9 +1067,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x800000000000) != 0; } - struct InstBfiRc + readonly struct InstBfiRc { - private ulong _opcode; + private readonly ulong _opcode; public InstBfiRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1081,17 +1081,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x800000000000) != 0; } - struct InstBpt + readonly struct InstBpt { - private ulong _opcode; + private readonly ulong _opcode; public InstBpt(ulong opcode) => _opcode = opcode; public int Imm20 => (int)((_opcode >> 20) & 0xFFFFF); public Bpt Bpt => (Bpt)((_opcode >> 6) & 0x7); } - struct InstBra + readonly struct InstBra { - private ulong _opcode; + private readonly ulong _opcode; public InstBra(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -1102,18 +1102,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool U => (_opcode & 0x80) != 0; } - struct InstBrk + readonly struct InstBrk { - private ulong _opcode; + private readonly ulong _opcode; public InstBrk(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstBrx + readonly struct InstBrx { - private ulong _opcode; + private readonly ulong _opcode; public InstBrx(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -1124,18 +1124,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Lmt => (_opcode & 0x40) != 0; } - struct InstCal + readonly struct InstCal { - private ulong _opcode; + private readonly ulong _opcode; public InstCal(ulong opcode) => _opcode = opcode; public bool Ca => (_opcode & 0x20) != 0; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Inc => (_opcode & 0x40) != 0; } - struct InstCctl + readonly struct InstCctl { - private ulong _opcode; + private readonly ulong _opcode; public InstCctl(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -1146,9 +1146,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public CctlOp CctlOp => (CctlOp)(_opcode & 0xF); } - struct InstCctll + readonly struct InstCctll { - private ulong _opcode; + private readonly ulong _opcode; public InstCctll(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -1158,9 +1158,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public CctlOp CctlOp => (CctlOp)(_opcode & 0xF); } - struct InstCctlt + readonly struct InstCctlt { - private ulong _opcode; + private readonly ulong _opcode; public InstCctlt(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -1168,26 +1168,26 @@ namespace Ryujinx.Graphics.Shader.Decoders public CctltOp CctltOp => (CctltOp)(_opcode & 0x3); } - struct InstCctltR + readonly struct InstCctltR { - private ulong _opcode; + private readonly ulong _opcode; public InstCctltR(ulong opcode) => _opcode = opcode; public int SrcC => (int)((_opcode >> 39) & 0xFF); public CctltOp CctltOp => (CctltOp)(_opcode & 0x3); } - struct InstCont + readonly struct InstCont { - private ulong _opcode; + private readonly ulong _opcode; public InstCont(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstCset + readonly struct InstCset { - private ulong _opcode; + private readonly ulong _opcode; public InstCset(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -1200,9 +1200,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public BoolOp Bop => (BoolOp)((_opcode >> 45) & 0x3); } - struct InstCsetp + readonly struct InstCsetp { - private ulong _opcode; + private readonly ulong _opcode; public InstCsetp(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -1215,9 +1215,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public BoolOp Bop => (BoolOp)((_opcode >> 45) & 0x3); } - struct InstCs2r + readonly struct InstCs2r { - private ulong _opcode; + private readonly ulong _opcode; public InstCs2r(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -1225,9 +1225,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SReg SReg => (SReg)((_opcode >> 20) & 0xFF); } - struct InstDaddR + readonly struct InstDaddR { - private ulong _opcode; + private readonly ulong _opcode; public InstDaddR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1242,9 +1242,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstDaddI + readonly struct InstDaddI { - private ulong _opcode; + private readonly ulong _opcode; public InstDaddI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1259,9 +1259,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstDaddC + readonly struct InstDaddC { - private ulong _opcode; + private readonly ulong _opcode; public InstDaddC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1277,9 +1277,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstDepbar + readonly struct InstDepbar { - private ulong _opcode; + private readonly ulong _opcode; public InstDepbar(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -1289,9 +1289,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm6 => (int)(_opcode & 0x3F); } - struct InstDfmaR + readonly struct InstDfmaR { - private ulong _opcode; + private readonly ulong _opcode; public InstDfmaR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1305,9 +1305,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDfmaI + readonly struct InstDfmaI { - private ulong _opcode; + private readonly ulong _opcode; public InstDfmaI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1321,9 +1321,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDfmaC + readonly struct InstDfmaC { - private ulong _opcode; + private readonly ulong _opcode; public InstDfmaC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1338,9 +1338,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDfmaRc + readonly struct InstDfmaRc { - private ulong _opcode; + private readonly ulong _opcode; public InstDfmaRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1355,9 +1355,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDmnmxR + readonly struct InstDmnmxR { - private ulong _opcode; + private readonly ulong _opcode; public InstDmnmxR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1373,9 +1373,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDmnmxI + readonly struct InstDmnmxI { - private ulong _opcode; + private readonly ulong _opcode; public InstDmnmxI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1391,9 +1391,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDmnmxC + readonly struct InstDmnmxC { - private ulong _opcode; + private readonly ulong _opcode; public InstDmnmxC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1410,9 +1410,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDmulR + readonly struct InstDmulR { - private ulong _opcode; + private readonly ulong _opcode; public InstDmulR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1424,9 +1424,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDmulI + readonly struct InstDmulI { - private ulong _opcode; + private readonly ulong _opcode; public InstDmulI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1438,9 +1438,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDmulC + readonly struct InstDmulC { - private ulong _opcode; + private readonly ulong _opcode; public InstDmulC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1453,9 +1453,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegA => (_opcode & 0x1000000000000) != 0; } - struct InstDsetR + readonly struct InstDsetR { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1474,9 +1474,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDsetI + readonly struct InstDsetI { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1495,9 +1495,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDsetC + readonly struct InstDsetC { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1517,9 +1517,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstDsetpR + readonly struct InstDsetpR { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetpR(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -1537,9 +1537,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstDsetpI + readonly struct InstDsetpI { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetpI(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -1557,9 +1557,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstDsetpC + readonly struct InstDsetpC { - private ulong _opcode; + private readonly ulong _opcode; public InstDsetpC(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -1578,9 +1578,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstExit + readonly struct InstExit { - private ulong _opcode; + private readonly ulong _opcode; public InstExit(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -1588,9 +1588,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool KeepRefCnt => (_opcode & 0x20) != 0; } - struct InstF2fR + readonly struct InstF2fR { - private ulong _opcode; + private readonly ulong _opcode; public InstF2fR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -1607,9 +1607,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstF2fI + readonly struct InstF2fI { - private ulong _opcode; + private readonly ulong _opcode; public InstF2fI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -1626,9 +1626,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstF2fC + readonly struct InstF2fC { - private ulong _opcode; + private readonly ulong _opcode; public InstF2fC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -1646,9 +1646,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstF2iR + readonly struct InstF2iR { - private ulong _opcode; + private readonly ulong _opcode; public InstF2iR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -1664,9 +1664,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode2 RoundMode => (RoundMode2)((_opcode >> 39) & 0x3); } - struct InstF2iI + readonly struct InstF2iI { - private ulong _opcode; + private readonly ulong _opcode; public InstF2iI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -1682,9 +1682,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode2 RoundMode => (RoundMode2)((_opcode >> 39) & 0x3); } - struct InstF2iC + readonly struct InstF2iC { - private ulong _opcode; + private readonly ulong _opcode; public InstF2iC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -1701,9 +1701,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode2 RoundMode => (RoundMode2)((_opcode >> 39) & 0x3); } - struct InstFaddR + readonly struct InstFaddR { - private ulong _opcode; + private readonly ulong _opcode; public InstFaddR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1720,9 +1720,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstFaddI + readonly struct InstFaddI { - private ulong _opcode; + private readonly ulong _opcode; public InstFaddI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1739,9 +1739,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstFaddC + readonly struct InstFaddC { - private ulong _opcode; + private readonly ulong _opcode; public InstFaddC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1759,9 +1759,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public RoundMode RoundMode => (RoundMode)((_opcode >> 39) & 0x3); } - struct InstFadd32i + readonly struct InstFadd32i { - private ulong _opcode; + private readonly ulong _opcode; public InstFadd32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1776,9 +1776,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x20000000000000) != 0; } - struct InstFchkR + readonly struct InstFchkR { - private ulong _opcode; + private readonly ulong _opcode; public InstFchkR(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1792,9 +1792,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ChkModeF ChkModeF => (ChkModeF)((_opcode >> 39) & 0x3F); } - struct InstFchkI + readonly struct InstFchkI { - private ulong _opcode; + private readonly ulong _opcode; public InstFchkI(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1808,9 +1808,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ChkModeF ChkModeF => (ChkModeF)((_opcode >> 39) & 0x3F); } - struct InstFchkC + readonly struct InstFchkC { - private ulong _opcode; + private readonly ulong _opcode; public InstFchkC(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1825,9 +1825,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ChkModeF ChkModeF => (ChkModeF)((_opcode >> 39) & 0x3F); } - struct InstFcmpR + readonly struct InstFcmpR { - private ulong _opcode; + private readonly ulong _opcode; public InstFcmpR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1839,9 +1839,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFcmpI + readonly struct InstFcmpI { - private ulong _opcode; + private readonly ulong _opcode; public InstFcmpI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1853,9 +1853,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFcmpC + readonly struct InstFcmpC { - private ulong _opcode; + private readonly ulong _opcode; public InstFcmpC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1868,9 +1868,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFcmpRc + readonly struct InstFcmpRc { - private ulong _opcode; + private readonly ulong _opcode; public InstFcmpRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1883,9 +1883,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFfmaR + readonly struct InstFfmaR { - private ulong _opcode; + private readonly ulong _opcode; public InstFfmaR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1901,9 +1901,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 53) & 0x3); } - struct InstFfmaI + readonly struct InstFfmaI { - private ulong _opcode; + private readonly ulong _opcode; public InstFfmaI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1919,9 +1919,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 53) & 0x3); } - struct InstFfmaC + readonly struct InstFfmaC { - private ulong _opcode; + private readonly ulong _opcode; public InstFfmaC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1938,9 +1938,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 53) & 0x3); } - struct InstFfmaRc + readonly struct InstFfmaRc { - private ulong _opcode; + private readonly ulong _opcode; public InstFfmaRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1957,9 +1957,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 53) & 0x3); } - struct InstFfma32i + readonly struct InstFfma32i { - private ulong _opcode; + private readonly ulong _opcode; public InstFfma32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -1973,9 +1973,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 53) & 0x3); } - struct InstFloR + readonly struct InstFloR { - private ulong _opcode; + private readonly ulong _opcode; public InstFloR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -1987,9 +1987,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstFloI + readonly struct InstFloI { - private ulong _opcode; + private readonly ulong _opcode; public InstFloI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -2001,9 +2001,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstFloC + readonly struct InstFloC { - private ulong _opcode; + private readonly ulong _opcode; public InstFloC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -2016,9 +2016,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstFmnmxR + readonly struct InstFmnmxR { - private ulong _opcode; + private readonly ulong _opcode; public InstFmnmxR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2035,9 +2035,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstFmnmxI + readonly struct InstFmnmxI { - private ulong _opcode; + private readonly ulong _opcode; public InstFmnmxI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2054,9 +2054,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstFmnmxC + readonly struct InstFmnmxC { - private ulong _opcode; + private readonly ulong _opcode; public InstFmnmxC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2074,9 +2074,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstFmulR + readonly struct InstFmulR { - private ulong _opcode; + private readonly ulong _opcode; public InstFmulR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2091,9 +2091,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstFmulI + readonly struct InstFmulI { - private ulong _opcode; + private readonly ulong _opcode; public InstFmulI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2108,9 +2108,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstFmulC + readonly struct InstFmulC { - private ulong _opcode; + private readonly ulong _opcode; public InstFmulC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2126,9 +2126,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstFmul32i + readonly struct InstFmul32i { - private ulong _opcode; + private readonly ulong _opcode; public InstFmul32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2140,9 +2140,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x10000000000000) != 0; } - struct InstFsetR + readonly struct InstFsetR { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2162,9 +2162,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVal => (_opcode & 0x10000000000000) != 0; } - struct InstFsetC + readonly struct InstFsetC { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2185,9 +2185,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVal => (_opcode & 0x10000000000000) != 0; } - struct InstFsetI + readonly struct InstFsetI { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2207,9 +2207,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVal => (_opcode & 0x10000000000000) != 0; } - struct InstFsetpR + readonly struct InstFsetpR { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetpR(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2229,9 +2229,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFsetpI + readonly struct InstFsetpI { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetpI(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2251,9 +2251,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFsetpC + readonly struct InstFsetpC { - private ulong _opcode; + private readonly ulong _opcode; public InstFsetpC(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2274,9 +2274,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x800000000000) != 0; } - struct InstFswzadd + readonly struct InstFswzadd { - private ulong _opcode; + private readonly ulong _opcode; public InstFswzadd(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2290,23 +2290,23 @@ namespace Ryujinx.Graphics.Shader.Decoders public int PnWord => (int)((_opcode >> 28) & 0xFF); } - struct InstGetcrsptr + readonly struct InstGetcrsptr { - private ulong _opcode; + private readonly ulong _opcode; public InstGetcrsptr(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); } - struct InstGetlmembase + readonly struct InstGetlmembase { - private ulong _opcode; + private readonly ulong _opcode; public InstGetlmembase(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); } - struct InstHadd2R + readonly struct InstHadd2R { - private ulong _opcode; + private readonly ulong _opcode; public InstHadd2R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2324,9 +2324,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x8000000000) != 0; } - struct InstHadd2I + readonly struct InstHadd2I { - private ulong _opcode; + private readonly ulong _opcode; public InstHadd2I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2342,9 +2342,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x8000000000) != 0; } - struct InstHadd2C + readonly struct InstHadd2C { - private ulong _opcode; + private readonly ulong _opcode; public InstHadd2C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2362,9 +2362,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x8000000000) != 0; } - struct InstHadd232i + readonly struct InstHadd232i { - private ulong _opcode; + private readonly ulong _opcode; public InstHadd232i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2377,9 +2377,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x80000000000000) != 0; } - struct InstHfma2R + readonly struct InstHfma2R { - private ulong _opcode; + private readonly ulong _opcode; public InstHfma2R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2397,9 +2397,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 37) & 0x3); } - struct InstHfma2I + readonly struct InstHfma2I { - private ulong _opcode; + private readonly ulong _opcode; public InstHfma2I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2416,9 +2416,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 57) & 0x3); } - struct InstHfma2C + readonly struct InstHfma2C { - private ulong _opcode; + private readonly ulong _opcode; public InstHfma2C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2436,9 +2436,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 57) & 0x3); } - struct InstHfma2Rc + readonly struct InstHfma2Rc { - private ulong _opcode; + private readonly ulong _opcode; public InstHfma2Rc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2456,9 +2456,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 57) & 0x3); } - struct InstHfma232i + readonly struct InstHfma232i { - private ulong _opcode; + private readonly ulong _opcode; public InstHfma232i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2470,9 +2470,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 57) & 0x3); } - struct InstHmul2R + readonly struct InstHmul2R { - private ulong _opcode; + private readonly ulong _opcode; public InstHmul2R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2489,9 +2489,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 39) & 0x3); } - struct InstHmul2I + readonly struct InstHmul2I { - private ulong _opcode; + private readonly ulong _opcode; public InstHmul2I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2507,9 +2507,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 39) & 0x3); } - struct InstHmul2C + readonly struct InstHmul2C { - private ulong _opcode; + private readonly ulong _opcode; public InstHmul2C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2526,9 +2526,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 39) & 0x3); } - struct InstHmul232i + readonly struct InstHmul232i { - private ulong _opcode; + private readonly ulong _opcode; public InstHmul232i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2540,9 +2540,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Fmz Fmz => (Fmz)((_opcode >> 55) & 0x3); } - struct InstHset2R + readonly struct InstHset2R { - private ulong _opcode; + private readonly ulong _opcode; public InstHset2R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2563,9 +2563,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x4000000000000) != 0; } - struct InstHset2I + readonly struct InstHset2I { - private ulong _opcode; + private readonly ulong _opcode; public InstHset2I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2584,9 +2584,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x40000000000000) != 0; } - struct InstHset2C + readonly struct InstHset2C { - private ulong _opcode; + private readonly ulong _opcode; public InstHset2C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2606,9 +2606,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ftz => (_opcode & 0x40000000000000) != 0; } - struct InstHsetp2R + readonly struct InstHsetp2R { - private ulong _opcode; + private readonly ulong _opcode; public InstHsetp2R(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2630,9 +2630,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public HalfSwizzle BSwizzle => (HalfSwizzle)((_opcode >> 28) & 0x3); } - struct InstHsetp2I + readonly struct InstHsetp2I { - private ulong _opcode; + private readonly ulong _opcode; public InstHsetp2I(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2652,9 +2652,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public HalfSwizzle ASwizzle => (HalfSwizzle)((_opcode >> 47) & 0x3); } - struct InstHsetp2C + readonly struct InstHsetp2C { - private ulong _opcode; + private readonly ulong _opcode; public InstHsetp2C(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int DestPredInv => (int)(_opcode & 0x7); @@ -2676,9 +2676,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public HalfSwizzle ASwizzle => (HalfSwizzle)((_opcode >> 47) & 0x3); } - struct InstI2fR + readonly struct InstI2fR { - private ulong _opcode; + private readonly ulong _opcode; public InstI2fR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -2693,9 +2693,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public DstFmt DstFmt => (DstFmt)((_opcode >> 8) & 0x3); } - struct InstI2fI + readonly struct InstI2fI { - private ulong _opcode; + private readonly ulong _opcode; public InstI2fI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -2710,9 +2710,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public DstFmt DstFmt => (DstFmt)((_opcode >> 8) & 0x3); } - struct InstI2fC + readonly struct InstI2fC { - private ulong _opcode; + private readonly ulong _opcode; public InstI2fC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -2728,9 +2728,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public DstFmt DstFmt => (DstFmt)((_opcode >> 8) & 0x3); } - struct InstI2iR + readonly struct InstI2iR { - private ulong _opcode; + private readonly ulong _opcode; public InstI2iR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -2745,9 +2745,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ISrcDstFmt ISrcFmt => (ISrcDstFmt)((int)((_opcode >> 11) & 0x4) | (int)((_opcode >> 10) & 0x3)); } - struct InstI2iI + readonly struct InstI2iI { - private ulong _opcode; + private readonly ulong _opcode; public InstI2iI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -2762,9 +2762,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ISrcDstFmt ISrcFmt => (ISrcDstFmt)((int)((_opcode >> 11) & 0x4) | (int)((_opcode >> 10) & 0x3)); } - struct InstI2iC + readonly struct InstI2iC { - private ulong _opcode; + private readonly ulong _opcode; public InstI2iC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -2780,9 +2780,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ISrcDstFmt ISrcFmt => (ISrcDstFmt)((int)((_opcode >> 11) & 0x4) | (int)((_opcode >> 10) & 0x3)); } - struct InstIaddR + readonly struct InstIaddR { - private ulong _opcode; + private readonly ulong _opcode; public InstIaddR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2795,9 +2795,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIaddI + readonly struct InstIaddI { - private ulong _opcode; + private readonly ulong _opcode; public InstIaddI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2810,9 +2810,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIaddC + readonly struct InstIaddC { - private ulong _opcode; + private readonly ulong _opcode; public InstIaddC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2826,9 +2826,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIadd32i + readonly struct InstIadd32i { - private ulong _opcode; + private readonly ulong _opcode; public InstIadd32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2841,9 +2841,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x20000000000000) != 0; } - struct InstIadd3R + readonly struct InstIadd3R { - private ulong _opcode; + private readonly ulong _opcode; public InstIadd3R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2862,9 +2862,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public HalfSelect Cpart => (HalfSelect)((_opcode >> 31) & 0x3); } - struct InstIadd3I + readonly struct InstIadd3I { - private ulong _opcode; + private readonly ulong _opcode; public InstIadd3I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2879,9 +2879,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x1000000000000) != 0; } - struct InstIadd3C + readonly struct InstIadd3C { - private ulong _opcode; + private readonly ulong _opcode; public InstIadd3C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2897,9 +2897,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x1000000000000) != 0; } - struct InstIcmpR + readonly struct InstIcmpR { - private ulong _opcode; + private readonly ulong _opcode; public InstIcmpR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2911,9 +2911,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Signed => (_opcode & 0x1000000000000) != 0; } - struct InstIcmpI + readonly struct InstIcmpI { - private ulong _opcode; + private readonly ulong _opcode; public InstIcmpI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2925,9 +2925,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Signed => (_opcode & 0x1000000000000) != 0; } - struct InstIcmpC + readonly struct InstIcmpC { - private ulong _opcode; + private readonly ulong _opcode; public InstIcmpC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2940,9 +2940,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Signed => (_opcode & 0x1000000000000) != 0; } - struct InstIcmpRc + readonly struct InstIcmpRc { - private ulong _opcode; + private readonly ulong _opcode; public InstIcmpRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2955,17 +2955,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Signed => (_opcode & 0x1000000000000) != 0; } - struct InstIde + readonly struct InstIde { - private ulong _opcode; + private readonly ulong _opcode; public InstIde(ulong opcode) => _opcode = opcode; public int Imm16 => (int)((_opcode >> 20) & 0xFFFF); public bool Di => (_opcode & 0x20) != 0; } - struct InstIdpR + readonly struct InstIdpR { - private ulong _opcode; + private readonly ulong _opcode; public InstIdpR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2979,9 +2979,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcBSign => (_opcode & 0x800000000000) != 0; } - struct InstIdpC + readonly struct InstIdpC { - private ulong _opcode; + private readonly ulong _opcode; public InstIdpC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -2996,9 +2996,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcBSign => (_opcode & 0x800000000000) != 0; } - struct InstImadR + readonly struct InstImadR { - private ulong _opcode; + private readonly ulong _opcode; public InstImadR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3015,9 +3015,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool ASigned => (_opcode & 0x1000000000000) != 0; } - struct InstImadI + readonly struct InstImadI { - private ulong _opcode; + private readonly ulong _opcode; public InstImadI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3034,9 +3034,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool ASigned => (_opcode & 0x1000000000000) != 0; } - struct InstImadC + readonly struct InstImadC { - private ulong _opcode; + private readonly ulong _opcode; public InstImadC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3054,9 +3054,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool ASigned => (_opcode & 0x1000000000000) != 0; } - struct InstImadRc + readonly struct InstImadRc { - private ulong _opcode; + private readonly ulong _opcode; public InstImadRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3074,9 +3074,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool ASigned => (_opcode & 0x1000000000000) != 0; } - struct InstImad32i + readonly struct InstImad32i { - private ulong _opcode; + private readonly ulong _opcode; public InstImad32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3090,9 +3090,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Hilo => (_opcode & 0x20000000000000) != 0; } - struct InstImadspR + readonly struct InstImadspR { - private ulong _opcode; + private readonly ulong _opcode; public InstImadspR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3105,9 +3105,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ImadspASelect CSelect => (ImadspASelect)((int)((_opcode >> 50) & 0x6) | (int)((_opcode >> 48) & 0x1)); } - struct InstImadspI + readonly struct InstImadspI { - private ulong _opcode; + private readonly ulong _opcode; public InstImadspI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3120,9 +3120,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ImadspASelect CSelect => (ImadspASelect)((int)((_opcode >> 50) & 0x6) | (int)((_opcode >> 48) & 0x1)); } - struct InstImadspC + readonly struct InstImadspC { - private ulong _opcode; + private readonly ulong _opcode; public InstImadspC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3136,9 +3136,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ImadspASelect CSelect => (ImadspASelect)((int)((_opcode >> 50) & 0x6) | (int)((_opcode >> 48) & 0x1)); } - struct InstImadspRc + readonly struct InstImadspRc { - private ulong _opcode; + private readonly ulong _opcode; public InstImadspRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3152,9 +3152,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public ImadspASelect CSelect => (ImadspASelect)((int)((_opcode >> 50) & 0x6) | (int)((_opcode >> 48) & 0x1)); } - struct InstImnmxR + readonly struct InstImnmxR { - private ulong _opcode; + private readonly ulong _opcode; public InstImnmxR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3168,9 +3168,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstImnmxI + readonly struct InstImnmxI { - private ulong _opcode; + private readonly ulong _opcode; public InstImnmxI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3184,9 +3184,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstImnmxC + readonly struct InstImnmxC { - private ulong _opcode; + private readonly ulong _opcode; public InstImnmxC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3201,9 +3201,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstImulR + readonly struct InstImulR { - private ulong _opcode; + private readonly ulong _opcode; public InstImulR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3216,9 +3216,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Hilo => (_opcode & 0x8000000000) != 0; } - struct InstImulI + readonly struct InstImulI { - private ulong _opcode; + private readonly ulong _opcode; public InstImulI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3231,9 +3231,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Hilo => (_opcode & 0x8000000000) != 0; } - struct InstImulC + readonly struct InstImulC { - private ulong _opcode; + private readonly ulong _opcode; public InstImulC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3247,9 +3247,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Hilo => (_opcode & 0x8000000000) != 0; } - struct InstImul32i + readonly struct InstImul32i { - private ulong _opcode; + private readonly ulong _opcode; public InstImul32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3262,9 +3262,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool WriteCC => (_opcode & 0x10000000000000) != 0; } - struct InstIpa + readonly struct InstIpa { - private ulong _opcode; + private readonly ulong _opcode; public InstIpa(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3281,9 +3281,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x4000000000000) != 0; } - struct InstIsberd + readonly struct InstIsberd { - private ulong _opcode; + private readonly ulong _opcode; public InstIsberd(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3295,9 +3295,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool P => (_opcode & 0x80000000) != 0; } - struct InstIscaddR + readonly struct InstIscaddR { - private ulong _opcode; + private readonly ulong _opcode; public InstIscaddR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3309,9 +3309,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public AvgMode AvgMode => (AvgMode)((_opcode >> 48) & 0x3); } - struct InstIscaddI + readonly struct InstIscaddI { - private ulong _opcode; + private readonly ulong _opcode; public InstIscaddI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3323,9 +3323,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public AvgMode AvgMode => (AvgMode)((_opcode >> 48) & 0x3); } - struct InstIscaddC + readonly struct InstIscaddC { - private ulong _opcode; + private readonly ulong _opcode; public InstIscaddC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3338,9 +3338,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public AvgMode AvgMode => (AvgMode)((_opcode >> 48) & 0x3); } - struct InstIscadd32i + readonly struct InstIscadd32i { - private ulong _opcode; + private readonly ulong _opcode; public InstIscadd32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3351,9 +3351,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm5 => (int)((_opcode >> 53) & 0x1F); } - struct InstIsetR + readonly struct InstIsetR { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3370,9 +3370,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIsetI + readonly struct InstIsetI { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3389,9 +3389,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIsetC + readonly struct InstIsetC { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3409,9 +3409,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool X => (_opcode & 0x80000000000) != 0; } - struct InstIsetpR + readonly struct InstIsetpR { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetpR(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -3427,9 +3427,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstIsetpI + readonly struct InstIsetpI { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetpI(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -3445,9 +3445,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstIsetpC + readonly struct InstIsetpC { - private ulong _opcode; + private readonly ulong _opcode; public InstIsetpC(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -3464,18 +3464,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPredInv => (int)(_opcode & 0x7); } - struct InstJcal + readonly struct InstJcal { - private ulong _opcode; + private readonly ulong _opcode; public InstJcal(ulong opcode) => _opcode = opcode; public int Imm32 => (int)(_opcode >> 20); public bool Ca => (_opcode & 0x20) != 0; public bool Inc => (_opcode & 0x40) != 0; } - struct InstJmp + readonly struct InstJmp { - private ulong _opcode; + private readonly ulong _opcode; public InstJmp(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -3487,9 +3487,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool U => (_opcode & 0x80) != 0; } - struct InstJmx + readonly struct InstJmx { - private ulong _opcode; + private readonly ulong _opcode; public InstJmx(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -3500,18 +3500,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Lmt => (_opcode & 0x40) != 0; } - struct InstKil + readonly struct InstKil { - private ulong _opcode; + private readonly ulong _opcode; public InstKil(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstLd + readonly struct InstLd { - private ulong _opcode; + private readonly ulong _opcode; public InstLd(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3524,9 +3524,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm32 => (int)(_opcode >> 20); } - struct InstLdc + readonly struct InstLdc { - private ulong _opcode; + private readonly ulong _opcode; public InstLdc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3538,9 +3538,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int CbufOffset => (int)((_opcode >> 20) & 0xFFFF); } - struct InstLdg + readonly struct InstLdg { - private ulong _opcode; + private readonly ulong _opcode; public InstLdg(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3552,9 +3552,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstLdl + readonly struct InstLdl { - private ulong _opcode; + private readonly ulong _opcode; public InstLdl(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3565,9 +3565,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstLds + readonly struct InstLds { - private ulong _opcode; + private readonly ulong _opcode; public InstLds(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3578,9 +3578,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstLeaR + readonly struct InstLeaR { - private ulong _opcode; + private readonly ulong _opcode; public InstLeaR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3594,9 +3594,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstLeaI + readonly struct InstLeaI { - private ulong _opcode; + private readonly ulong _opcode; public InstLeaI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3610,9 +3610,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstLeaC + readonly struct InstLeaC { - private ulong _opcode; + private readonly ulong _opcode; public InstLeaC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3627,9 +3627,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstLeaHiR + readonly struct InstLeaHiR { - private ulong _opcode; + private readonly ulong _opcode; public InstLeaHiR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3644,9 +3644,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstLeaHiC + readonly struct InstLeaHiC { - private ulong _opcode; + private readonly ulong _opcode; public InstLeaHiC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3662,22 +3662,24 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstLepc + readonly struct InstLepc { - private ulong _opcode; +#pragma warning disable IDE0052 // Remove unread private member + private readonly ulong _opcode; +#pragma warning restore IDE0052 public InstLepc(ulong opcode) => _opcode = opcode; } - struct InstLongjmp + readonly struct InstLongjmp { - private ulong _opcode; + private readonly ulong _opcode; public InstLongjmp(ulong opcode) => _opcode = opcode; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstLopR + readonly struct InstLopR { - private ulong _opcode; + private readonly ulong _opcode; public InstLopR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3693,9 +3695,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstLopI + readonly struct InstLopI { - private ulong _opcode; + private readonly ulong _opcode; public InstLopI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3711,9 +3713,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstLopC + readonly struct InstLopC { - private ulong _opcode; + private readonly ulong _opcode; public InstLopC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3730,9 +3732,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstLop3R + readonly struct InstLop3R { - private ulong _opcode; + private readonly ulong _opcode; public InstLop3R(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3747,9 +3749,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm => (int)((_opcode >> 28) & 0xFF); } - struct InstLop3I + readonly struct InstLop3I { - private ulong _opcode; + private readonly ulong _opcode; public InstLop3I(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3762,9 +3764,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm => (int)((_opcode >> 48) & 0xFF); } - struct InstLop3C + readonly struct InstLop3C { - private ulong _opcode; + private readonly ulong _opcode; public InstLop3C(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3778,9 +3780,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm => (int)((_opcode >> 48) & 0xFF); } - struct InstLop32i + readonly struct InstLop32i { - private ulong _opcode; + private readonly ulong _opcode; public InstLop32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3794,9 +3796,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x100000000000000) != 0; } - struct InstMembar + readonly struct InstMembar { - private ulong _opcode; + private readonly ulong _opcode; public InstMembar(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -3804,9 +3806,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Ivall Ivall => (Ivall)(_opcode & 0x3); } - struct InstMovR + readonly struct InstMovR { - private ulong _opcode; + private readonly ulong _opcode; public InstMovR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 20) & 0xFF); @@ -3815,9 +3817,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int QuadMask => (int)((_opcode >> 39) & 0xF); } - struct InstMovI + readonly struct InstMovI { - private ulong _opcode; + private readonly ulong _opcode; public InstMovI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -3826,9 +3828,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int QuadMask => (int)((_opcode >> 39) & 0xF); } - struct InstMovC + readonly struct InstMovC { - private ulong _opcode; + private readonly ulong _opcode; public InstMovC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -3838,9 +3840,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int QuadMask => (int)((_opcode >> 39) & 0xF); } - struct InstMov32i + readonly struct InstMov32i { - private ulong _opcode; + private readonly ulong _opcode; public InstMov32i(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm32 => (int)(_opcode >> 20); @@ -3849,9 +3851,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int QuadMask => (int)((_opcode >> 12) & 0xF); } - struct InstMufu + readonly struct InstMufu { - private ulong _opcode; + private readonly ulong _opcode; public InstMufu(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3863,9 +3865,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Sat => (_opcode & 0x4000000000000) != 0; } - struct InstNop + readonly struct InstNop { - private ulong _opcode; + private readonly ulong _opcode; public InstNop(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -3874,9 +3876,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public Ccc Ccc => (Ccc)((_opcode >> 8) & 0x1F); } - struct InstOutR + readonly struct InstOutR { - private ulong _opcode; + private readonly ulong _opcode; public InstOutR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3886,9 +3888,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public OutType OutType => (OutType)((_opcode >> 39) & 0x3); } - struct InstOutI + readonly struct InstOutI { - private ulong _opcode; + private readonly ulong _opcode; public InstOutI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3898,9 +3900,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public OutType OutType => (OutType)((_opcode >> 39) & 0x3); } - struct InstOutC + readonly struct InstOutC { - private ulong _opcode; + private readonly ulong _opcode; public InstOutC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3911,9 +3913,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public OutType OutType => (OutType)((_opcode >> 39) & 0x3); } - struct InstP2rR + readonly struct InstP2rR { - private ulong _opcode; + private readonly ulong _opcode; public InstP2rR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3924,9 +3926,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstP2rI + readonly struct InstP2rI { - private ulong _opcode; + private readonly ulong _opcode; public InstP2rI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3937,9 +3939,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstP2rC + readonly struct InstP2rC { - private ulong _opcode; + private readonly ulong _opcode; public InstP2rC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3951,32 +3953,32 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstPbk + readonly struct InstPbk { - private ulong _opcode; + private readonly ulong _opcode; public InstPbk(ulong opcode) => _opcode = opcode; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Ca => (_opcode & 0x20) != 0; } - struct InstPcnt + readonly struct InstPcnt { - private ulong _opcode; + private readonly ulong _opcode; public InstPcnt(ulong opcode) => _opcode = opcode; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Ca => (_opcode & 0x20) != 0; } - struct InstPexit + readonly struct InstPexit { - private ulong _opcode; + private readonly ulong _opcode; public InstPexit(ulong opcode) => _opcode = opcode; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstPixld + readonly struct InstPixld { - private ulong _opcode; + private readonly ulong _opcode; public InstPixld(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -3987,17 +3989,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm8 => (int)((_opcode >> 20) & 0xFF); } - struct InstPlongjmp + readonly struct InstPlongjmp { - private ulong _opcode; + private readonly ulong _opcode; public InstPlongjmp(ulong opcode) => _opcode = opcode; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Ca => (_opcode & 0x20) != 0; } - struct InstPopcR + readonly struct InstPopcR { - private ulong _opcode; + private readonly ulong _opcode; public InstPopcR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -4006,9 +4008,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstPopcI + readonly struct InstPopcI { - private ulong _opcode; + private readonly ulong _opcode; public InstPopcI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -4017,9 +4019,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstPopcC + readonly struct InstPopcC { - private ulong _opcode; + private readonly ulong _opcode; public InstPopcC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -4029,18 +4031,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool NegB => (_opcode & 0x10000000000) != 0; } - struct InstPret + readonly struct InstPret { - private ulong _opcode; + private readonly ulong _opcode; public InstPret(ulong opcode) => _opcode = opcode; public bool Ca => (_opcode & 0x20) != 0; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Inc => (_opcode & 0x40) != 0; } - struct InstPrmtR + readonly struct InstPrmtR { - private ulong _opcode; + private readonly ulong _opcode; public InstPrmtR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4051,9 +4053,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public PMode PMode => (PMode)((_opcode >> 48) & 0xF); } - struct InstPrmtI + readonly struct InstPrmtI { - private ulong _opcode; + private readonly ulong _opcode; public InstPrmtI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4064,9 +4066,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public PMode PMode => (PMode)((_opcode >> 48) & 0xF); } - struct InstPrmtC + readonly struct InstPrmtC { - private ulong _opcode; + private readonly ulong _opcode; public InstPrmtC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4078,9 +4080,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public PMode PMode => (PMode)((_opcode >> 48) & 0xF); } - struct InstPrmtRc + readonly struct InstPrmtRc { - private ulong _opcode; + private readonly ulong _opcode; public InstPrmtRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4092,9 +4094,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public PMode PMode => (PMode)((_opcode >> 48) & 0xF); } - struct InstPset + readonly struct InstPset { - private ulong _opcode; + private readonly ulong _opcode; public InstPset(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -4111,9 +4113,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVal => (_opcode & 0x100000000000) != 0; } - struct InstPsetp + readonly struct InstPsetp { - private ulong _opcode; + private readonly ulong _opcode; public InstPsetp(ulong opcode) => _opcode = opcode; public int DestPred => (int)((_opcode >> 3) & 0x7); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -4129,9 +4131,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public BoolOp BoolOpC => (BoolOp)((_opcode >> 45) & 0x3); } - struct InstR2b + readonly struct InstR2b { - private ulong _opcode; + private readonly ulong _opcode; public InstR2b(ulong opcode) => _opcode = opcode; public int SrcB => (int)((_opcode >> 20) & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -4140,9 +4142,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Name => (int)((_opcode >> 28) & 0xF); } - struct InstR2pR + readonly struct InstR2pR { - private ulong _opcode; + private readonly ulong _opcode; public InstR2pR(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -4152,9 +4154,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstR2pI + readonly struct InstR2pI { - private ulong _opcode; + private readonly ulong _opcode; public InstR2pI(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -4164,9 +4166,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstR2pC + readonly struct InstR2pC { - private ulong _opcode; + private readonly ulong _opcode; public InstR2pC(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -4177,15 +4179,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ccpr => (_opcode & 0x10000000000) != 0; } - struct InstRam + readonly struct InstRam { - private ulong _opcode; +#pragma warning disable IDE0052 // Remove unread private member + private readonly ulong _opcode; +#pragma warning restore IDE0052 public InstRam(ulong opcode) => _opcode = opcode; } - struct InstRed + readonly struct InstRed { - private ulong _opcode; + private readonly ulong _opcode; public InstRed(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)(_opcode & 0xFF); @@ -4197,18 +4201,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool E => (_opcode & 0x1000000000000) != 0; } - struct InstRet + readonly struct InstRet { - private ulong _opcode; + private readonly ulong _opcode; public InstRet(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstRroR + readonly struct InstRroR { - private ulong _opcode; + private readonly ulong _opcode; public InstRroR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -4219,9 +4223,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool RroOp => (_opcode & 0x8000000000) != 0; } - struct InstRroI + readonly struct InstRroI { - private ulong _opcode; + private readonly ulong _opcode; public InstRroI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Imm20 => (int)((_opcode >> 37) & 0x80000) | (int)((_opcode >> 20) & 0x7FFFF); @@ -4232,9 +4236,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool RroOp => (_opcode & 0x8000000000) != 0; } - struct InstRroC + readonly struct InstRroC { - private ulong _opcode; + private readonly ulong _opcode; public InstRroC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int CbufSlot => (int)((_opcode >> 34) & 0x1F); @@ -4246,15 +4250,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool RroOp => (_opcode & 0x8000000000) != 0; } - struct InstRtt + readonly struct InstRtt { - private ulong _opcode; +#pragma warning disable IDE0052 // Remove unread private member + private readonly ulong _opcode; +#pragma warning restore IDE0052 public InstRtt(ulong opcode) => _opcode = opcode; } - struct InstS2r + readonly struct InstS2r { - private ulong _opcode; + private readonly ulong _opcode; public InstS2r(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -4262,15 +4268,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public SReg SReg => (SReg)((_opcode >> 20) & 0xFF); } - struct InstSam + readonly struct InstSam { - private ulong _opcode; +#pragma warning disable IDE0052 // Remove unread private member + private readonly ulong _opcode; +#pragma warning restore IDE0052 public InstSam(ulong opcode) => _opcode = opcode; } - struct InstSelR + readonly struct InstSelR { - private ulong _opcode; + private readonly ulong _opcode; public InstSelR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4281,9 +4289,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstSelI + readonly struct InstSelI { - private ulong _opcode; + private readonly ulong _opcode; public InstSelI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4294,9 +4302,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstSelC + readonly struct InstSelC { - private ulong _opcode; + private readonly ulong _opcode; public InstSelC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4308,23 +4316,23 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SrcPredInv => (_opcode & 0x40000000000) != 0; } - struct InstSetcrsptr + readonly struct InstSetcrsptr { - private ulong _opcode; + private readonly ulong _opcode; public InstSetcrsptr(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); } - struct InstSetlmembase + readonly struct InstSetlmembase { - private ulong _opcode; + private readonly ulong _opcode; public InstSetlmembase(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); } - struct InstShfLR + readonly struct InstShfLR { - private ulong _opcode; + private readonly ulong _opcode; public InstShfLR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4338,9 +4346,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public MaxShift MaxShift => (MaxShift)((_opcode >> 37) & 0x3); } - struct InstShfRR + readonly struct InstShfRR { - private ulong _opcode; + private readonly ulong _opcode; public InstShfRR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4354,9 +4362,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public MaxShift MaxShift => (MaxShift)((_opcode >> 37) & 0x3); } - struct InstShfLI + readonly struct InstShfLI { - private ulong _opcode; + private readonly ulong _opcode; public InstShfLI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4370,9 +4378,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm6 => (int)((_opcode >> 20) & 0x3F); } - struct InstShfRI + readonly struct InstShfRI { - private ulong _opcode; + private readonly ulong _opcode; public InstShfRI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4386,9 +4394,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm6 => (int)((_opcode >> 20) & 0x3F); } - struct InstShfl + readonly struct InstShfl { - private ulong _opcode; + private readonly ulong _opcode; public InstShfl(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4404,9 +4412,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int DestPred => (int)((_opcode >> 48) & 0x7); } - struct InstShlR + readonly struct InstShlR { - private ulong _opcode; + private readonly ulong _opcode; public InstShlR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4418,9 +4426,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstShlI + readonly struct InstShlI { - private ulong _opcode; + private readonly ulong _opcode; public InstShlI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4432,9 +4440,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstShlC + readonly struct InstShlC { - private ulong _opcode; + private readonly ulong _opcode; public InstShlC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4447,9 +4455,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstShrR + readonly struct InstShrR { - private ulong _opcode; + private readonly ulong _opcode; public InstShrR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4463,9 +4471,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstShrI + readonly struct InstShrI { - private ulong _opcode; + private readonly ulong _opcode; public InstShrI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4479,9 +4487,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstShrC + readonly struct InstShrC { - private ulong _opcode; + private readonly ulong _opcode; public InstShrC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4496,17 +4504,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool M => (_opcode & 0x8000000000) != 0; } - struct InstSsy + readonly struct InstSsy { - private ulong _opcode; + private readonly ulong _opcode; public InstSsy(ulong opcode) => _opcode = opcode; public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); public bool Ca => (_opcode & 0x20) != 0; } - struct InstSt + readonly struct InstSt { - private ulong _opcode; + private readonly ulong _opcode; public InstSt(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4519,9 +4527,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm32 => (int)(_opcode >> 20); } - struct InstStg + readonly struct InstStg { - private ulong _opcode; + private readonly ulong _opcode; public InstStg(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4533,9 +4541,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstStl + readonly struct InstStl { - private ulong _opcode; + private readonly ulong _opcode; public InstStl(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4546,17 +4554,17 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstStp + readonly struct InstStp { - private ulong _opcode; + private readonly ulong _opcode; public InstStp(ulong opcode) => _opcode = opcode; public bool Wait => (_opcode & 0x80000000) != 0; public int Imm8 => (int)((_opcode >> 20) & 0xFF); } - struct InstSts + readonly struct InstSts { - private ulong _opcode; + private readonly ulong _opcode; public InstSts(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4566,9 +4574,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm24 => (int)((_opcode >> 20) & 0xFFFFFF); } - struct InstSuatomB + readonly struct InstSuatomB { - private ulong _opcode; + private readonly ulong _opcode; public InstSuatomB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4583,9 +4591,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ba => (_opcode & 0x10000000) != 0; } - struct InstSuatom + readonly struct InstSuatom { - private ulong _opcode; + private readonly ulong _opcode; public InstSuatom(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4600,9 +4608,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ba => (_opcode & 0x10000000) != 0; } - struct InstSuatomB2 + readonly struct InstSuatomB2 { - private ulong _opcode; + private readonly ulong _opcode; public InstSuatomB2(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4618,9 +4626,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ba => (_opcode & 0x10000000) != 0; } - struct InstSuatomCasB + readonly struct InstSuatomCasB { - private ulong _opcode; + private readonly ulong _opcode; public InstSuatomCasB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4635,9 +4643,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ba => (_opcode & 0x10000000) != 0; } - struct InstSuatomCas + readonly struct InstSuatomCas { - private ulong _opcode; + private readonly ulong _opcode; public InstSuatomCas(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4652,9 +4660,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Ba => (_opcode & 0x10000000) != 0; } - struct InstSuldDB + readonly struct InstSuldDB { - private ulong _opcode; + private readonly ulong _opcode; public InstSuldDB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4669,9 +4677,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuSize Size => (SuSize)((_opcode >> 20) & 0x7); } - struct InstSuldD + readonly struct InstSuldD { - private ulong _opcode; + private readonly ulong _opcode; public InstSuldD(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4686,9 +4694,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuSize Size => (SuSize)((_opcode >> 20) & 0x7); } - struct InstSuldB + readonly struct InstSuldB { - private ulong _opcode; + private readonly ulong _opcode; public InstSuldB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4702,9 +4710,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuRgba Rgba => (SuRgba)((_opcode >> 20) & 0xF); } - struct InstSuld + readonly struct InstSuld { - private ulong _opcode; + private readonly ulong _opcode; public InstSuld(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4718,9 +4726,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuRgba Rgba => (SuRgba)((_opcode >> 20) & 0xF); } - struct InstSuredB + readonly struct InstSuredB { - private ulong _opcode; + private readonly ulong _opcode; public InstSuredB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4734,9 +4742,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuatomSize Size => (SuatomSize)((_opcode >> 20) & 0x7); } - struct InstSured + readonly struct InstSured { - private ulong _opcode; + private readonly ulong _opcode; public InstSured(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4750,9 +4758,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuatomSize Size => (SuatomSize)((_opcode >> 20) & 0x7); } - struct InstSustDB + readonly struct InstSustDB { - private ulong _opcode; + private readonly ulong _opcode; public InstSustDB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4766,9 +4774,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuSize Size => (SuSize)((_opcode >> 20) & 0x7); } - struct InstSustD + readonly struct InstSustD { - private ulong _opcode; + private readonly ulong _opcode; public InstSustD(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4782,9 +4790,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuSize Size => (SuSize)((_opcode >> 20) & 0x7); } - struct InstSustB + readonly struct InstSustB { - private ulong _opcode; + private readonly ulong _opcode; public InstSustB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4797,9 +4805,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuRgba Rgba => (SuRgba)((_opcode >> 20) & 0xF); } - struct InstSust + readonly struct InstSust { - private ulong _opcode; + private readonly ulong _opcode; public InstSust(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4812,18 +4820,18 @@ namespace Ryujinx.Graphics.Shader.Decoders public SuRgba Rgba => (SuRgba)((_opcode >> 20) & 0xF); } - struct InstSync + readonly struct InstSync { - private ulong _opcode; + private readonly ulong _opcode; public InstSync(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; public Ccc Ccc => (Ccc)(_opcode & 0x1F); } - struct InstTex + readonly struct InstTex { - private ulong _opcode; + private readonly ulong _opcode; public InstTex(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4842,9 +4850,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Nodep => (_opcode & 0x2000000000000) != 0; } - struct InstTexB + readonly struct InstTexB { - private ulong _opcode; + private readonly ulong _opcode; public InstTexB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4862,9 +4870,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Nodep => (_opcode & 0x2000000000000) != 0; } - struct InstTexs + readonly struct InstTexs { - private ulong _opcode; + private readonly ulong _opcode; public InstTexs(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4878,9 +4886,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Dest2 => (int)((_opcode >> 28) & 0xFF); } - struct InstTld + readonly struct InstTld { - private ulong _opcode; + private readonly ulong _opcode; public InstTld(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4898,9 +4906,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTldB + readonly struct InstTldB { - private ulong _opcode; + private readonly ulong _opcode; public InstTldB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4917,9 +4925,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTlds + readonly struct InstTlds { - private ulong _opcode; + private readonly ulong _opcode; public InstTlds(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4933,9 +4941,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Dest2 => (int)((_opcode >> 28) & 0xFF); } - struct InstTld4 + readonly struct InstTld4 { - private ulong _opcode; + private readonly ulong _opcode; public InstTld4(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4954,9 +4962,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Nodep => (_opcode & 0x2000000000000) != 0; } - struct InstTld4B + readonly struct InstTld4B { - private ulong _opcode; + private readonly ulong _opcode; public InstTld4B(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4974,9 +4982,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Nodep => (_opcode & 0x2000000000000) != 0; } - struct InstTld4s + readonly struct InstTld4s { - private ulong _opcode; + private readonly ulong _opcode; public InstTld4s(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -4991,9 +4999,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Dest2 => (int)((_opcode >> 28) & 0xFF); } - struct InstTmml + readonly struct InstTmml { - private ulong _opcode; + private readonly ulong _opcode; public InstTmml(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5007,9 +5015,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTmmlB + readonly struct InstTmmlB { - private ulong _opcode; + private readonly ulong _opcode; public InstTmmlB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5022,9 +5030,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTxa + readonly struct InstTxa { - private ulong _opcode; + private readonly ulong _opcode; public InstTxa(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5036,9 +5044,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int WMask => (int)((_opcode >> 31) & 0xF); } - struct InstTxd + readonly struct InstTxd { - private ulong _opcode; + private readonly ulong _opcode; public InstTxd(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5054,9 +5062,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTxdB + readonly struct InstTxdB { - private ulong _opcode; + private readonly ulong _opcode; public InstTxdB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5071,9 +5079,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexDim Dim => (TexDim)((_opcode >> 28) & 0x7); } - struct InstTxq + readonly struct InstTxq { - private ulong _opcode; + private readonly ulong _opcode; public InstTxq(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5085,9 +5093,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexQuery TexQuery => (TexQuery)((_opcode >> 22) & 0x3F); } - struct InstTxqB + readonly struct InstTxqB { - private ulong _opcode; + private readonly ulong _opcode; public InstTxqB(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5098,9 +5106,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public TexQuery TexQuery => (TexQuery)((_opcode >> 22) & 0x3F); } - struct InstVabsdiff + readonly struct InstVabsdiff { - private ulong _opcode; + private readonly ulong _opcode; public InstVabsdiff(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5117,9 +5125,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVabsdiff4 + readonly struct InstVabsdiff4 { - private ulong _opcode; + private readonly ulong _opcode; public InstVabsdiff4(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5138,9 +5146,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public BSelect4 Bsel4 => (BSelect4)((_opcode >> 28) & 0xF); } - struct InstVadd + readonly struct InstVadd { - private ulong _opcode; + private readonly ulong _opcode; public InstVadd(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5159,9 +5167,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVmad + readonly struct InstVmad { - private ulong _opcode; + private readonly ulong _opcode; public InstVmad(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5179,9 +5187,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVmnmx + readonly struct InstVmnmx { - private ulong _opcode; + private readonly ulong _opcode; public InstVmnmx(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5200,9 +5208,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVote + readonly struct InstVote { - private ulong _opcode; + private readonly ulong _opcode; public InstVote(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int Pred => (int)((_opcode >> 16) & 0x7); @@ -5213,9 +5221,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int VpDest => (int)((_opcode >> 45) & 0x7); } - struct InstVotevtg + readonly struct InstVotevtg { - private ulong _opcode; + private readonly ulong _opcode; public InstVotevtg(ulong opcode) => _opcode = opcode; public int Pred => (int)((_opcode >> 16) & 0x7); public bool PredInv => (_opcode & 0x80000) != 0; @@ -5223,9 +5231,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Imm28 => (int)((_opcode >> 20) & 0xFFFFFFF); } - struct InstVset + readonly struct InstVset { - private ulong _opcode; + private readonly ulong _opcode; public InstVset(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5241,9 +5249,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVsetp + readonly struct InstVsetp { - private ulong _opcode; + private readonly ulong _opcode; public InstVsetp(ulong opcode) => _opcode = opcode; public int SrcA => (int)((_opcode >> 8) & 0xFF); public int SrcB => (int)((_opcode >> 20) & 0xFF); @@ -5261,9 +5269,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVshl + readonly struct InstVshl { - private ulong _opcode; + private readonly ulong _opcode; public InstVshl(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5281,9 +5289,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstVshr + readonly struct InstVshr { - private ulong _opcode; + private readonly ulong _opcode; public InstVshr(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5301,9 +5309,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BVideo => (_opcode & 0x4000000000000) != 0; } - struct InstXmadR + readonly struct InstXmadR { - private ulong _opcode; + private readonly ulong _opcode; public InstXmadR(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5322,9 +5330,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool HiloB => (_opcode & 0x800000000) != 0; } - struct InstXmadI + readonly struct InstXmadI { - private ulong _opcode; + private readonly ulong _opcode; public InstXmadI(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5342,9 +5350,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Psl => (_opcode & 0x1000000000) != 0; } - struct InstXmadC + readonly struct InstXmadC { - private ulong _opcode; + private readonly ulong _opcode; public InstXmadC(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5364,9 +5372,9 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool ASigned => (_opcode & 0x1000000000000) != 0; } - struct InstXmadRc + readonly struct InstXmadRc { - private ulong _opcode; + private readonly ulong _opcode; public InstXmadRc(ulong opcode) => _opcode = opcode; public int Dest => (int)(_opcode & 0xFF); public int SrcA => (int)((_opcode >> 8) & 0xFF); @@ -5383,4 +5391,4 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool BSigned => (_opcode & 0x2000000000000) != 0; public bool ASigned => (_opcode & 0x1000000000000) != 0; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/InstName.cs b/src/Ryujinx.Graphics.Shader/Decoders/InstName.cs index 9c79b7a5c..04ad9391f 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/InstName.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/InstName.cs @@ -185,4 +185,4 @@ namespace Ryujinx.Graphics.Shader.Decoders Vshr, Xmad, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/InstOp.cs b/src/Ryujinx.Graphics.Shader/Decoders/InstOp.cs index 39244e647..045257dc6 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/InstOp.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/InstOp.cs @@ -24,4 +24,4 @@ namespace Ryujinx.Graphics.Shader.Decoders return (ulong)((long)Address + (((int)(RawOpCode >> 20) << 8) >> 8) + 8); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/InstProps.cs b/src/Ryujinx.Graphics.Shader/Decoders/InstProps.cs index 3f39e631d..14cdcd060 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/InstProps.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/InstProps.cs @@ -26,6 +26,6 @@ namespace Ryujinx.Graphics.Shader.Decoders Tex = 1 << 12, TexB = 1 << 13, Bra = 1 << 14, - NoPred = 1 << 15 + NoPred = 1 << 15, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/InstTable.cs b/src/Ryujinx.Graphics.Shader/Decoders/InstTable.cs index eaa77930b..35367b8df 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/InstTable.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/InstTable.cs @@ -24,13 +24,14 @@ namespace Ryujinx.Graphics.Shader.Decoders } } - private static TableEntry[] _opCodes; + private static readonly TableEntry[] _opCodes; static InstTable() { _opCodes = new TableEntry[1 << EncodingBits]; #region Instructions +#pragma warning disable IDE0055 // Disable formatting Add("1110111110100xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Al2p, InstEmit.Al2p, InstProps.Rd | InstProps.Ra); Add("1110111111011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ald, InstEmit.Ald, InstProps.Rd | InstProps.Ra); Add("1110111111110xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ast, InstEmit.Ast, InstProps.Ra | InstProps.Rb2 | InstProps.Rc); @@ -325,6 +326,7 @@ namespace Ryujinx.Graphics.Shader.Decoders Add("0011011x00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadI, InstProps.Rd | InstProps.Ra | InstProps.Ib | InstProps.Rc); Add("0100111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadC, InstProps.Rd | InstProps.Ra | InstProps.Rc); Add("010100010xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadRc, InstProps.Rd | InstProps.Ra | InstProps.Rc); +#pragma warning restore IDE0055 #endregion } @@ -357,7 +359,7 @@ namespace Ryujinx.Graphics.Shader.Decoders xMask = ~xMask; - TableEntry entry = new TableEntry(name, emitter, props, xBits); + TableEntry entry = new(name, emitter, props, xBits); for (int index = 0; index < (1 << xBits); index++) { @@ -387,4 +389,4 @@ namespace Ryujinx.Graphics.Shader.Decoders return new InstOp(address, opCode, InstName.Invalid, null, InstProps.None); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/Register.cs b/src/Ryujinx.Graphics.Shader/Decoders/Register.cs index e375096dd..2e6d61996 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/Register.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/Register.cs @@ -8,13 +8,13 @@ namespace Ryujinx.Graphics.Shader.Decoders public RegisterType Type { get; } - public bool IsRZ => Type == RegisterType.Gpr && Index == RegisterConsts.RegisterZeroIndex; + public bool IsRZ => Type == RegisterType.Gpr && Index == RegisterConsts.RegisterZeroIndex; public bool IsPT => Type == RegisterType.Predicate && Index == RegisterConsts.PredicateTrueIndex; public Register(int index, RegisterType type) { Index = index; - Type = type; + Type = type; } public override int GetHashCode() @@ -30,7 +30,7 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Equals(Register other) { return other.Index == Index && - other.Type == Type; + other.Type == Type; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/RegisterConsts.cs b/src/Ryujinx.Graphics.Shader/Decoders/RegisterConsts.cs index d381f9543..416fba966 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/RegisterConsts.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/RegisterConsts.cs @@ -2,12 +2,12 @@ namespace Ryujinx.Graphics.Shader.Decoders { static class RegisterConsts { - public const int GprsCount = 255; + public const int GprsCount = 255; public const int PredsCount = 7; public const int FlagsCount = 4; public const int TotalCount = GprsCount + PredsCount + FlagsCount; - public const int RegisterZeroIndex = GprsCount; + public const int RegisterZeroIndex = GprsCount; public const int PredicateTrueIndex = PredsCount; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Decoders/RegisterType.cs b/src/Ryujinx.Graphics.Shader/Decoders/RegisterType.cs index 648f816a2..c870464ff 100644 --- a/src/Ryujinx.Graphics.Shader/Decoders/RegisterType.cs +++ b/src/Ryujinx.Graphics.Shader/Decoders/RegisterType.cs @@ -6,4 +6,4 @@ namespace Ryujinx.Graphics.Shader.Decoders Gpr, Predicate, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/InputTopology.cs b/src/Ryujinx.Graphics.Shader/InputTopology.cs index da3329090..ebd2930e4 100644 --- a/src/Ryujinx.Graphics.Shader/InputTopology.cs +++ b/src/Ryujinx.Graphics.Shader/InputTopology.cs @@ -6,7 +6,7 @@ namespace Ryujinx.Graphics.Shader Lines, LinesAdjacency, Triangles, - TrianglesAdjacency + TrianglesAdjacency, } static class InputTopologyExtensions @@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Shader InputTopology.LinesAdjacency => "lines_adjacency", InputTopology.Triangles => "triangles", InputTopology.TrianglesAdjacency => "triangles_adjacency", - _ => "points" + _ => "points", }; } @@ -33,8 +33,8 @@ namespace Ryujinx.Graphics.Shader InputTopology.LinesAdjacency => 2, InputTopology.Triangles or InputTopology.TrianglesAdjacency => 3, - _ => 1 + _ => 1, }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/AttributeMap.cs b/src/Ryujinx.Graphics.Shader/Instructions/AttributeMap.cs index 562fb8d53..5e572f5a7 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/AttributeMap.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/AttributeMap.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System.Collections.Generic; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Instructions @@ -21,10 +20,10 @@ namespace Ryujinx.Graphics.Shader.Instructions Tessellation = TessellationControl | TessellationEvaluation, VertexTessellationGeometry = Vertex | Tessellation | Geometry, TessellationGeometryFragment = Tessellation | Geometry | Fragment, - AllGraphics = Vertex | Tessellation | Geometry | Fragment + AllGraphics = Vertex | Tessellation | Geometry | Fragment, } - private struct AttributeEntry + private readonly struct AttributeEntry { public int BaseOffset { get; } public AggregateType Type { get; } @@ -344,8 +343,8 @@ namespace Ryujinx.Graphics.Shader.Instructions AggregateType.Vector2 => 2, AggregateType.Vector3 => 3, AggregateType.Vector4 => 4, - _ => 1 + _ => 1, }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmit.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmit.cs index 963a5c656..f105505dd 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmit.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmit.cs @@ -7,352 +7,352 @@ namespace Ryujinx.Graphics.Shader.Instructions { public static void AtomCas(EmitterContext context) { - InstAtomCas op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction AtomCas is not implemented."); } public static void AtomsCas(EmitterContext context) { - InstAtomsCas op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction AtomsCas is not implemented."); } public static void B2r(EmitterContext context) { - InstB2r op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction B2r is not implemented."); } public static void Bpt(EmitterContext context) { - InstBpt op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Bpt is not implemented."); } public static void Cctl(EmitterContext context) { - InstCctl op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Cctl is not implemented."); } public static void Cctll(EmitterContext context) { - InstCctll op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Cctll is not implemented."); } public static void Cctlt(EmitterContext context) { - InstCctlt op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Cctlt is not implemented."); } public static void Cs2r(EmitterContext context) { - InstCs2r op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Cs2r is not implemented."); } public static void FchkR(EmitterContext context) { - InstFchkR op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction FchkR is not implemented."); } public static void FchkI(EmitterContext context) { - InstFchkI op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction FchkI is not implemented."); } public static void FchkC(EmitterContext context) { - InstFchkC op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction FchkC is not implemented."); } public static void Getcrsptr(EmitterContext context) { - InstGetcrsptr op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Getcrsptr is not implemented."); } public static void Getlmembase(EmitterContext context) { - InstGetlmembase op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Getlmembase is not implemented."); } public static void Ide(EmitterContext context) { - InstIde op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Ide is not implemented."); } public static void IdpR(EmitterContext context) { - InstIdpR op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction IdpR is not implemented."); } public static void IdpC(EmitterContext context) { - InstIdpC op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction IdpC is not implemented."); } public static void ImadspR(EmitterContext context) { - InstImadspR op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction ImadspR is not implemented."); } public static void ImadspI(EmitterContext context) { - InstImadspI op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction ImadspI is not implemented."); } public static void ImadspC(EmitterContext context) { - InstImadspC op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction ImadspC is not implemented."); } public static void ImadspRc(EmitterContext context) { - InstImadspRc op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction ImadspRc is not implemented."); } public static void Jcal(EmitterContext context) { - InstJcal op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Jcal is not implemented."); } public static void Jmp(EmitterContext context) { - InstJmp op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Jmp is not implemented."); } public static void Jmx(EmitterContext context) { - InstJmx op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Jmx is not implemented."); } public static void Ld(EmitterContext context) { - InstLd op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Ld is not implemented."); } public static void Lepc(EmitterContext context) { - InstLepc op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Lepc is not implemented."); } public static void Longjmp(EmitterContext context) { - InstLongjmp op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Longjmp is not implemented."); } public static void Pexit(EmitterContext context) { - InstPexit op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Pexit is not implemented."); } public static void Pixld(EmitterContext context) { - InstPixld op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Pixld is not implemented."); } public static void Plongjmp(EmitterContext context) { - InstPlongjmp op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Plongjmp is not implemented."); } public static void Pret(EmitterContext context) { - InstPret op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Pret is not implemented."); } public static void PrmtR(EmitterContext context) { - InstPrmtR op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction PrmtR is not implemented."); } public static void PrmtI(EmitterContext context) { - InstPrmtI op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction PrmtI is not implemented."); } public static void PrmtC(EmitterContext context) { - InstPrmtC op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction PrmtC is not implemented."); } public static void PrmtRc(EmitterContext context) { - InstPrmtRc op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction PrmtRc is not implemented."); } public static void R2b(EmitterContext context) { - InstR2b op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction R2b is not implemented."); } public static void Ram(EmitterContext context) { - InstRam op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Ram is not implemented."); } public static void Rtt(EmitterContext context) { - InstRtt op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Rtt is not implemented."); } public static void Sam(EmitterContext context) { - InstSam op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Sam is not implemented."); } public static void Setcrsptr(EmitterContext context) { - InstSetcrsptr op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Setcrsptr is not implemented."); } public static void Setlmembase(EmitterContext context) { - InstSetlmembase op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Setlmembase is not implemented."); } public static void St(EmitterContext context) { - InstSt op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction St is not implemented."); } public static void Stp(EmitterContext context) { - InstStp op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Stp is not implemented."); } public static void Txa(EmitterContext context) { - InstTxa op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Txa is not implemented."); } public static void Vabsdiff(EmitterContext context) { - InstVabsdiff op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vabsdiff is not implemented."); } public static void Vabsdiff4(EmitterContext context) { - InstVabsdiff4 op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vabsdiff4 is not implemented."); } public static void Vadd(EmitterContext context) { - InstVadd op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vadd is not implemented."); } public static void Votevtg(EmitterContext context) { - InstVotevtg op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Votevtg is not implemented."); } public static void Vset(EmitterContext context) { - InstVset op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vset is not implemented."); } public static void Vshl(EmitterContext context) { - InstVshl op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vshl is not implemented."); } public static void Vshr(EmitterContext context) { - InstVshr op = context.GetOp(); + context.GetOp(); context.Config.GpuAccessor.Log("Shader instruction Vshr is not implemented."); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAluHelper.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAluHelper.cs index 879075bae..4370560d7 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAluHelper.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAluHelper.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -18,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.Instructions IDstFmt.S16 => short.MinValue, IDstFmt.U32 => uint.MinValue, IDstFmt.S32 => int.MinValue, - _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.") + _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."), }; } @@ -30,7 +29,7 @@ namespace Ryujinx.Graphics.Shader.Instructions IDstFmt.S16 => short.MaxValue, IDstFmt.U32 => uint.MaxValue, IDstFmt.S32 => int.MaxValue, - _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.") + _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."), }; } @@ -44,7 +43,7 @@ namespace Ryujinx.Graphics.Shader.Instructions ISrcDstFmt.S16 => short.MinValue, ISrcDstFmt.U32 => uint.MinValue, ISrcDstFmt.S32 => int.MinValue, - _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.") + _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."), }; } @@ -58,7 +57,7 @@ namespace Ryujinx.Graphics.Shader.Instructions ISrcDstFmt.S16 => short.MaxValue, ISrcDstFmt.U32 => uint.MaxValue, ISrcDstFmt.S32 => int.MaxValue, - _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.") + _ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."), }; } @@ -69,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.Instructions BoolOp.And => context.BitwiseAnd(input, pred), BoolOp.Or => context.BitwiseOr(input, pred), BoolOp.Xor => context.BitwiseExclusiveOr(input, pred), - _ => input + _ => input, }; } @@ -89,7 +88,7 @@ namespace Ryujinx.Graphics.Shader.Instructions VectorSelect.S8B3 => SignExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8), VectorSelect.S16H0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16), VectorSelect.S16H1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16), - _ => src + _ => src, }; } @@ -134,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.Instructions } context.Copy(GetZF(), context.FPCompareEqual(dest, zero, fpType)); - context.Copy(GetNF(), context.FPCompareLess (dest, zero, fpType)); + context.Copy(GetNF(), context.FPCompareLess(dest, zero, fpType)); } } @@ -157,4 +156,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return result; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAttribute.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAttribute.cs index 76b2e0783..1876847c4 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAttribute.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitAttribute.cs @@ -33,7 +33,7 @@ namespace Ryujinx.Graphics.Shader.Instructions for (int index = 0; index < (int)op.AlSize + 1; index++) { - Register rd = new Register(op.Dest + index, RegisterType.Gpr); + Register rd = new(op.Dest + index, RegisterType.Gpr); if (rd.IsRZ) { @@ -91,7 +91,7 @@ namespace Ryujinx.Graphics.Shader.Instructions break; } - Register rd = new Register(op.SrcB + index, RegisterType.Gpr); + Register rd = new(op.SrcB + index, RegisterType.Gpr); if (op.Phys) { @@ -380,4 +380,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBarrier.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBarrier.cs index f3114c6e4..ae5e078f6 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBarrier.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBarrier.cs @@ -22,7 +22,9 @@ namespace Ryujinx.Graphics.Shader.Instructions public static void Depbar(EmitterContext context) { +#pragma warning disable IDE0059 // Remove unnecessary value assignment InstDepbar op = context.GetOp(); +#pragma warning restore IDE0059 // No operation. } @@ -41,4 +43,4 @@ namespace Ryujinx.Graphics.Shader.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBitfield.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBitfield.cs index 719252696..3a8419698 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBitfield.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitBitfield.cs @@ -191,4 +191,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(GetDest(rd), res); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConditionCode.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConditionCode.cs index 74ac76029..b5580a37a 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConditionCode.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConditionCode.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -80,8 +79,8 @@ namespace Ryujinx.Graphics.Shader.Instructions Ccc.Oft => GetVF(), Ccc.Rle => context.BitwiseOr(GetNF(), GetZF()), Ccc.Rgt => context.BitwiseNot(context.BitwiseOr(GetNF(), GetZF())), - _ => Const(defaultCond) + _ => Const(defaultCond), }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConversion.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConversion.cs index bebd96dd9..8d59023ae 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConversion.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitConversion.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -140,7 +139,7 @@ namespace Ryujinx.Graphics.Shader.Instructions IntegerRound.Floor => context.FPFloor(srcB, srcType.ToInstFPType()), IntegerRound.Ceil => context.FPCeiling(srcB, srcType.ToInstFPType()), IntegerRound.Trunc => context.FPTruncate(srcB, srcType.ToInstFPType()), - _ => srcB + _ => srcB, }; } @@ -191,7 +190,7 @@ namespace Ryujinx.Graphics.Shader.Instructions RoundMode2.Floor => context.FPFloor(srcB, fpType), RoundMode2.Ceil => context.FPCeiling(srcB, fpType), RoundMode2.Trunc => context.FPTruncate(srcB, fpType), - _ => srcB + _ => srcB, }; if (!isSignedInt) @@ -422,4 +421,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return type == DstFmt.F64 ? Instruction.FP64 : Instruction.FP32; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatArithmetic.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatArithmetic.cs index 29803c31e..ab643b5c6 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatArithmetic.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatArithmetic.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -458,7 +457,7 @@ namespace Ryujinx.Graphics.Shader.Instructions MultiplyScale.M2 => ConstF(2f), MultiplyScale.M4 => ConstF(4f), MultiplyScale.M8 => ConstF(8f), - _ => ConstF(1f) // Invalid, behave as if it had no scale. + _ => ConstF(1f), // Invalid, behave as if it had no scale. }; if (scaleConst.AsFloat() == 1f) @@ -529,4 +528,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(GetDest(rd), GetHalfPacked(context, swizzle, res, rd)); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatComparison.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatComparison.cs index 8f99ddb3c..59ad7a5de 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatComparison.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatComparison.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -484,8 +483,8 @@ namespace Ryujinx.Graphics.Shader.Instructions } else { - Operand low = context.BitwiseAnd(res[0], Const(0xffff)); - Operand high = context.ShiftLeft (res[1], Const(16)); + Operand low = context.BitwiseAnd(res[0], Const(0xffff)); + Operand high = context.ShiftLeft(res[1], Const(16)); Operand packed = context.BitwiseOr(low, high); @@ -546,20 +545,16 @@ namespace Ryujinx.Graphics.Shader.Instructions } else { - Instruction inst; - - switch (cond & ~FComp.Nan) + var inst = (cond & ~FComp.Nan) switch { - case FComp.Lt: inst = Instruction.CompareLess; break; - case FComp.Eq: inst = Instruction.CompareEqual; break; - case FComp.Le: inst = Instruction.CompareLessOrEqual; break; - case FComp.Gt: inst = Instruction.CompareGreater; break; - case FComp.Ne: inst = Instruction.CompareNotEqual; break; - case FComp.Ge: inst = Instruction.CompareGreaterOrEqual; break; - - default: throw new ArgumentException($"Unexpected condition \"{cond}\"."); - } - + FComp.Lt => Instruction.CompareLess, + FComp.Eq => Instruction.CompareEqual, + FComp.Le => Instruction.CompareLessOrEqual, + FComp.Gt => Instruction.CompareGreater, + FComp.Ne => Instruction.CompareNotEqual, + FComp.Ge => Instruction.CompareGreaterOrEqual, + _ => throw new ArgumentException($"Unexpected condition \"{cond}\"."), + }; res = context.Add(inst | fpType, Local(), srcA, srcB); if ((cond & FComp.Nan) != 0) @@ -572,4 +567,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return res; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatMinMax.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatMinMax.cs index 412a5305a..5757e4fb0 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatMinMax.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFloatMinMax.cs @@ -103,4 +103,4 @@ namespace Ryujinx.Graphics.Shader.Instructions SetFPZnFlags(context, res, writeCC, fpType); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFlowControl.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFlowControl.cs index 736963552..fc1a696fa 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFlowControl.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitFlowControl.cs @@ -3,8 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System.Collections.Generic; using System.Linq; - -using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Instructions @@ -13,14 +11,14 @@ namespace Ryujinx.Graphics.Shader.Instructions { public static void Bra(EmitterContext context) { - InstBra op = context.GetOp(); + context.GetOp(); EmitBranch(context, context.CurrBlock.Successors[^1].Address); } public static void Brk(EmitterContext context) { - InstBrk op = context.GetOp(); + context.GetOp(); EmitBrkContSync(context); } @@ -123,7 +121,7 @@ namespace Ryujinx.Graphics.Shader.Instructions public static void Cal(EmitterContext context) { - InstCal op = context.GetOp(); + context.GetOp(); DecodedFunction function = context.Program.GetFunctionByAddress(context.CurrOp.GetAbsoluteAddress()); @@ -147,7 +145,7 @@ namespace Ryujinx.Graphics.Shader.Instructions public static void Cont(EmitterContext context) { - InstCont op = context.GetOp(); + context.GetOp(); EmitBrkContSync(context); } @@ -185,28 +183,28 @@ namespace Ryujinx.Graphics.Shader.Instructions public static void Kil(EmitterContext context) { - InstKil op = context.GetOp(); + context.GetOp(); context.Discard(); } public static void Pbk(EmitterContext context) { - InstPbk op = context.GetOp(); + context.GetOp(); EmitPbkPcntSsy(context); } public static void Pcnt(EmitterContext context) { - InstPcnt op = context.GetOp(); + context.GetOp(); EmitPbkPcntSsy(context); } public static void Ret(EmitterContext context) { - InstRet op = context.GetOp(); + context.GetOp(); if (context.IsNonMain) { @@ -220,14 +218,14 @@ namespace Ryujinx.Graphics.Shader.Instructions public static void Ssy(EmitterContext context) { - InstSsy op = context.GetOp(); + context.GetOp(); EmitPbkPcntSsy(context); } public static void Sync(EmitterContext context) { - InstSync op = context.GetOp(); + context.GetOp(); EmitBrkContSync(context); } @@ -275,7 +273,7 @@ namespace Ryujinx.Graphics.Shader.Instructions private static void EmitBranch(EmitterContext context, ulong address) { InstOp op = context.CurrOp; - InstConditional opCond = new InstConditional(op.RawOpCode); + InstConditional opCond = new(op.RawOpCode); // If we're branching to the next instruction, then the branch // is useless and we can ignore it. @@ -321,4 +319,4 @@ namespace Ryujinx.Graphics.Shader.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitHelper.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitHelper.cs index 0ba4667ea..8638fb8f2 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitHelper.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitHelper.cs @@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System; using System.Runtime.CompilerServices; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Instructions @@ -111,7 +110,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return new Operand[] { ConstF((float)Unsafe.As(ref low)), - ConstF((float)Unsafe.As(ref high)) + ConstF((float)Unsafe.As(ref high)), }; } @@ -123,7 +122,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return new Operand[] { ConstF((float)Unsafe.As(ref low)), - ConstF((float)Unsafe.As(ref high)) + ConstF((float)Unsafe.As(ref high)), }; } @@ -139,56 +138,51 @@ namespace Ryujinx.Graphics.Shader.Instructions public static Operand[] GetHalfUnpacked(EmitterContext context, Operand src, HalfSwizzle swizzle) { - switch (swizzle) + return swizzle switch { - case HalfSwizzle.F16: - return new Operand[] - { + HalfSwizzle.F16 => new Operand[] + { context.UnpackHalf2x16Low (src), - context.UnpackHalf2x16High(src) - }; - - case HalfSwizzle.F32: return new Operand[] { src, src }; - - case HalfSwizzle.H0H0: - return new Operand[] + context.UnpackHalf2x16High(src), + }, + HalfSwizzle.F32 => new Operand[] { src, src }, + HalfSwizzle.H0H0 => new Operand[] { context.UnpackHalf2x16Low(src), - context.UnpackHalf2x16Low(src) - }; - - case HalfSwizzle.H1H1: - return new Operand[] + context.UnpackHalf2x16Low(src), + }, + HalfSwizzle.H1H1 => new Operand[] { context.UnpackHalf2x16High(src), - context.UnpackHalf2x16High(src) - }; - } - - throw new ArgumentException($"Invalid swizzle \"{swizzle}\"."); + context.UnpackHalf2x16High(src), + }, + _ => throw new ArgumentException($"Invalid swizzle \"{swizzle}\"."), + }; } public static Operand GetHalfPacked(EmitterContext context, OFmt swizzle, Operand[] results, int rd) { switch (swizzle) { - case OFmt.F16: return context.PackHalf2x16(results[0], results[1]); + case OFmt.F16: + return context.PackHalf2x16(results[0], results[1]); - case OFmt.F32: return results[0]; + case OFmt.F32: + return results[0]; case OFmt.MrgH0: - { - Operand h1 = GetHalfDest(context, rd, isHigh: true); + { + Operand h1 = GetHalfDest(context, rd, isHigh: true); - return context.PackHalf2x16(results[0], h1); - } + return context.PackHalf2x16(results[0], h1); + } case OFmt.MrgH1: - { - Operand h0 = GetHalfDest(context, rd, isHigh: false); + { + Operand h0 = GetHalfDest(context, rd, isHigh: false); - return context.PackHalf2x16(h0, results[1]); - } + return context.PackHalf2x16(h0, results[1]); + } } throw new ArgumentException($"Invalid swizzle \"{swizzle}\"."); @@ -263,4 +257,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return context.BitwiseAnd(src, Const(mask)); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerArithmetic.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerArithmetic.cs index 374e3d614..c06f4671f 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerArithmetic.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerArithmetic.cs @@ -510,7 +510,9 @@ namespace Ryujinx.Graphics.Shader.Instructions aLow = context.BitwiseNot(aLow); aHigh = context.BitwiseNot(aHigh); +#pragma warning disable IDE0059 // Remove unnecessary value assignment aLow = AddWithCarry(context, aLow, Const(1), out Operand aLowCOut); +#pragma warning restore IDE0059 aHigh = context.IAdd(aHigh, aLowCOut); } @@ -696,4 +698,4 @@ namespace Ryujinx.Graphics.Shader.Instructions SetZnFlags(context, res, setCC: true, extended: extended); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerComparison.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerComparison.cs index dcdb189fb..18d4e3d19 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerComparison.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerComparison.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -220,7 +219,9 @@ namespace Ryujinx.Graphics.Shader.Instructions else { res = context.ISubtract(srcA, srcB); +#pragma warning disable IDE0059 // Remove unnecessary value assignment res = context.IAdd(res, context.BitwiseNot(GetCF())); +#pragma warning restore IDE0059 switch (cond) { @@ -287,17 +288,25 @@ namespace Ryujinx.Graphics.Shader.Instructions IComp.Gt => Instruction.CompareGreaterU32, IComp.Ne => Instruction.CompareNotEqual, IComp.Ge => Instruction.CompareGreaterOrEqualU32, - _ => throw new InvalidOperationException($"Unexpected condition \"{cond}\".") + _ => throw new InvalidOperationException($"Unexpected condition \"{cond}\"."), }; if (isSigned) { switch (cond) { - case IComp.Lt: inst = Instruction.CompareLess; break; - case IComp.Le: inst = Instruction.CompareLessOrEqual; break; - case IComp.Gt: inst = Instruction.CompareGreater; break; - case IComp.Ge: inst = Instruction.CompareGreaterOrEqual; break; + case IComp.Lt: + inst = Instruction.CompareLess; + break; + case IComp.Le: + inst = Instruction.CompareLessOrEqual; + break; + case IComp.Gt: + inst = Instruction.CompareGreater; + break; + case IComp.Ge: + inst = Instruction.CompareGreaterOrEqual; + break; } } @@ -307,4 +316,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return res; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs index 1f3f66ae4..5993c93dd 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerLogical.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper; using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -103,10 +102,10 @@ namespace Ryujinx.Graphics.Shader.Instructions Operand res = logicOp switch { - LogicOp.And => res = context.BitwiseAnd(srcA, srcB), - LogicOp.Or => res = context.BitwiseOr(srcA, srcB), - LogicOp.Xor => res = context.BitwiseExclusiveOr(srcA, srcB), - _ => srcB + LogicOp.And => context.BitwiseAnd(srcA, srcB), + LogicOp.Or => context.BitwiseOr(srcA, srcB), + LogicOp.Xor => context.BitwiseExclusiveOr(srcA, srcB), + _ => srcB, }; EmitLopPredWrite(context, res, predOp, destPred); @@ -164,4 +163,4 @@ namespace Ryujinx.Graphics.Shader.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerMinMax.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerMinMax.cs index 73930ed1f..739e94413 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerMinMax.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitIntegerMinMax.cs @@ -68,4 +68,4 @@ namespace Ryujinx.Graphics.Shader.Instructions // TODO: X flags. } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs index 40312f4a4..006c14b54 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMemory.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; using System.Numerics; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -48,7 +47,7 @@ namespace Ryujinx.Graphics.Shader.Instructions AtomsSize.S32 => AtomSize.S32, AtomsSize.U64 => AtomSize.U64, AtomsSize.S64 => AtomSize.S64, - _ => AtomSize.U32 + _ => AtomSize.U32, }; Operand id = Const(context.Config.ResourceManager.SharedMemoryId); @@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Instructions for (int index = 0; index < count; index++) { - Register dest = new Register(op.Dest + index, RegisterType.Gpr); + Register dest = new(op.Dest + index, RegisterType.Gpr); if (dest.IsRZ) { @@ -309,14 +308,14 @@ namespace Ryujinx.Graphics.Shader.Instructions { LsSize2.B64 => 2, LsSize2.B128 => 4, - _ => 1 + _ => 1, }; Operand baseOffset = context.Copy(srcA); for (int index = 0; index < count; index++) { - Register dest = new Register(rd + index, RegisterType.Gpr); + Register dest = new(rd + index, RegisterType.Gpr); if (dest.IsRZ) { @@ -354,7 +353,7 @@ namespace Ryujinx.Graphics.Shader.Instructions for (int index = 0; index < count; index++) { - Register dest = new Register(rd + index, RegisterType.Gpr); + Register dest = new(rd + index, RegisterType.Gpr); if (dest.IsRZ) { @@ -390,7 +389,7 @@ namespace Ryujinx.Graphics.Shader.Instructions { LsSize2.B64 => 2, LsSize2.B128 => 4, - _ => 1 + _ => 1, }; Operand baseOffset = context.Copy(srcA); @@ -476,22 +475,18 @@ namespace Ryujinx.Graphics.Shader.Instructions LsSize.S8 => StorageKind.GlobalMemoryS8, LsSize.U16 => StorageKind.GlobalMemoryU16, LsSize.S16 => StorageKind.GlobalMemoryS16, - _ => StorageKind.GlobalMemory + _ => StorageKind.GlobalMemory, }; } private static int GetVectorCount(LsSize size) { - switch (size) + return size switch { - case LsSize.B64: - return 2; - case LsSize.B128: - case LsSize.UB128: - return 4; - } - - return 1; + LsSize.B64 => 2, + LsSize.B128 or LsSize.UB128 => 4, + _ => 1, + }; } private static (Operand, Operand) Get40BitsAddress( @@ -544,10 +539,18 @@ namespace Ryujinx.Graphics.Shader.Instructions switch (size) { - case LsSize.U8: value = ZeroExtendTo32(context, value, 8); break; - case LsSize.U16: value = ZeroExtendTo32(context, value, 16); break; - case LsSize.S8: value = SignExtendTo32(context, value, 8); break; - case LsSize.S16: value = SignExtendTo32(context, value, 16); break; + case LsSize.U8: + value = ZeroExtendTo32(context, value, 8); + break; + case LsSize.U16: + value = ZeroExtendTo32(context, value, 16); + break; + case LsSize.S8: + value = SignExtendTo32(context, value, 8); + break; + case LsSize.S16: + value = SignExtendTo32(context, value, 16); + break; } return value; @@ -578,4 +581,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return value; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMove.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMove.cs index e12177f7d..f6c3bf6f0 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMove.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMove.cs @@ -212,7 +212,7 @@ namespace Ryujinx.Graphics.Shader.Instructions int count = ccpr ? RegisterConsts.FlagsCount : RegisterConsts.PredsCount; RegisterType type = ccpr ? RegisterType.Flag : RegisterType.Predicate; int shift = (int)byteSel * 8; - + for (int bit = 0; bit < count; bit++) { Operand flag = Register(bit, type); @@ -228,4 +228,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(GetDest(rd), res); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMultifunction.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMultifunction.cs index 1ea7d3214..86f154bdb 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMultifunction.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitMultifunction.cs @@ -94,4 +94,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(GetDest(rd), srcB); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitNop.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitNop.cs index 011440071..28ee927d8 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitNop.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitNop.cs @@ -7,9 +7,9 @@ namespace Ryujinx.Graphics.Shader.Instructions { public static void Nop(EmitterContext context) { - InstNop op = context.GetOp(); + context.GetOp(); // No operation. } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs index 79919624e..630162ade 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs @@ -113,4 +113,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(dest, res); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitShift.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitShift.cs index 2873cad88..ee0dac155 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitShift.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitShift.cs @@ -246,4 +246,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(GetDest(rd), res); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitSurface.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitSurface.cs index 3d94b8938..78fc313d8 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitSurface.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitSurface.cs @@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation; using System; using System.Collections.Generic; using System.Numerics; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -221,7 +220,7 @@ namespace Ryujinx.Graphics.Shader.Instructions Operand destOperand = dest != RegisterConsts.RegisterZeroIndex ? Register(dest, RegisterType.Gpr) : null; - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -325,7 +324,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return context.Copy(Register(srcA++, RegisterType.Gpr)); } - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -445,10 +444,18 @@ namespace Ryujinx.Graphics.Shader.Instructions switch (size) { - case SuSize.U8: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8)); break; - case SuSize.U16: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16)); break; - case SuSize.S8: context.Copy(dests[0], SignExtendTo32(context, dests[0], 8)); break; - case SuSize.S16: context.Copy(dests[0], SignExtendTo32(context, dests[0], 16)); break; + case SuSize.U8: + context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8)); + break; + case SuSize.U16: + context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16)); + break; + case SuSize.S8: + context.Copy(dests[0], SignExtendTo32(context, dests[0], 8)); + break; + case SuSize.S16: + context.Copy(dests[0], SignExtendTo32(context, dests[0], 16)); + break; } } } @@ -493,7 +500,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return context.Copy(Register(srcB++, RegisterType.Gpr)); } - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -600,7 +607,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return context.Copy(Register(srcB++, RegisterType.Gpr)); } - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -699,7 +706,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuatomSize.S64 => 3, SuatomSize.Sd32 => 2, SuatomSize.Sd64 => 3, - _ => 2 + _ => 2, }; } @@ -715,7 +722,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuatomSize.S64 => TextureFormat.R32G32Uint, SuatomSize.Sd32 => TextureFormat.R32Uint, SuatomSize.Sd64 => TextureFormat.R32G32Uint, - _ => TextureFormat.R32Uint + _ => TextureFormat.R32Uint, }; } @@ -732,7 +739,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuatomOp.Or => TextureFlags.BitwiseOr, SuatomOp.Xor => TextureFlags.BitwiseXor, SuatomOp.Exch => TextureFlags.Swap, - _ => TextureFlags.Add + _ => TextureFlags.Add, }; } @@ -743,7 +750,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuSize.B64 => 2, SuSize.B128 => 4, SuSize.UB128 => 4, - _ => 1 + _ => 1, }; } @@ -759,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuSize.B64 => 3, SuSize.B128 => 4, SuSize.UB128 => 4, - _ => 2 + _ => 2, }; } @@ -775,7 +782,7 @@ namespace Ryujinx.Graphics.Shader.Instructions SuSize.B64 => TextureFormat.R32G32Uint, SuSize.B128 => TextureFormat.R32G32B32A32Uint, SuSize.UB128 => TextureFormat.R32G32B32A32Uint, - _ => TextureFormat.R32Uint + _ => TextureFormat.R32Uint, }; } @@ -789,8 +796,8 @@ namespace Ryujinx.Graphics.Shader.Instructions SuDim._2d => SamplerType.Texture2D, SuDim._2dArray => SamplerType.Texture2D | SamplerType.Array, SuDim._3d => SamplerType.Texture3D, - _ => SamplerType.None + _ => SamplerType.None, }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs index caa9a7759..3701325e2 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs @@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation; using System; using System.Collections.Generic; using System.Numerics; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Instructions @@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.Instructions private static readonly int[,] _maskLut = new int[,] { { 0b0001, 0b0010, 0b0100, 0b1000, 0b0011, 0b1001, 0b1010, 0b1100 }, - { 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 } + { 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }, }; public const bool Sample1DAs2D = true; @@ -23,7 +22,7 @@ namespace Ryujinx.Graphics.Shader.Instructions { Texs, Tlds, - Tld4s + Tld4s, } public static void Tex(EmitterContext context) @@ -207,7 +206,7 @@ namespace Ryujinx.Graphics.Shader.Instructions Operand arrayIndex = isArray ? Ra() : null; - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -353,7 +352,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return; } - List sourcesList = new List(); + List sourcesList = new(); Operand Ra() { @@ -722,7 +721,7 @@ namespace Ryujinx.Graphics.Shader.Instructions Operand arrayIndex = isArray ? Ra() : null; - List sourcesList = new List(); + List sourcesList = new(); SamplerType type = ConvertSamplerType(dimensions); TextureFlags flags = TextureFlags.Gather; @@ -864,7 +863,7 @@ namespace Ryujinx.Graphics.Shader.Instructions TextureFlags flags = TextureFlags.None; - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -996,7 +995,7 @@ namespace Ryujinx.Graphics.Shader.Instructions TextureFlags flags = TextureFlags.Derivatives; - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -1126,7 +1125,7 @@ namespace Ryujinx.Graphics.Shader.Instructions return context.Copy(Register(srcA++, RegisterType.Gpr)); } - List sourcesList = new List(); + List sourcesList = new(); if (isBindless) { @@ -1195,7 +1194,7 @@ namespace Ryujinx.Graphics.Shader.Instructions TexDim.Array3d => SamplerType.Texture3D | SamplerType.Array, TexDim.Cube => SamplerType.TextureCube, TexDim.ArrayCube => SamplerType.TextureCube | SamplerType.Array, - _ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\".") + _ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\"."), }; } @@ -1309,4 +1308,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return TextureFlags.None; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoArithmetic.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoArithmetic.cs index 2d84c5bdb..a0e9fb384 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoArithmetic.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoArithmetic.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -77,7 +76,7 @@ namespace Ryujinx.Graphics.Shader.Instructions { VideoScale.Shr7 => 7, VideoScale.Shr15 => 15, - _ => 0 + _ => 0, }; if (shift != 0) @@ -115,4 +114,4 @@ namespace Ryujinx.Graphics.Shader.Instructions // TODO: CC. } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoMinMax.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoMinMax.cs index 67b185ab5..d52c972bc 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoMinMax.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitVideoMinMax.cs @@ -180,4 +180,4 @@ namespace Ryujinx.Graphics.Shader.Instructions context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitWarp.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitWarp.cs index 3c8336139..67dc3398b 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitWarp.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitWarp.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper; using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; @@ -39,7 +38,7 @@ namespace Ryujinx.Graphics.Shader.Instructions ShflMode.Up => context.ShuffleUp(srcA, srcB, srcC), ShflMode.Down => context.ShuffleDown(srcA, srcB, srcC), ShflMode.Bfly => context.ShuffleXor(srcA, srcB, srcC), - _ => (null, null) + _ => (null, null), }; context.Copy(GetDest(op.Dest), res); @@ -81,4 +80,4 @@ namespace Ryujinx.Graphics.Shader.Instructions } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitter.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitter.cs index 91c740b68..e1cef26d8 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitter.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitter.cs @@ -3,4 +3,4 @@ using Ryujinx.Graphics.Shader.Translation; namespace Ryujinx.Graphics.Shader.Instructions { delegate void InstEmitter(EmitterContext context); -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Instructions/Lop3Expression.cs b/src/Ryujinx.Graphics.Shader/Instructions/Lop3Expression.cs index 6217ce530..6846ea8d6 100644 --- a/src/Ryujinx.Graphics.Shader/Instructions/Lop3Expression.cs +++ b/src/Ryujinx.Graphics.Shader/Instructions/Lop3Expression.cs @@ -1,6 +1,5 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using Ryujinx.Graphics.Shader.Translation; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Instructions @@ -9,27 +8,27 @@ namespace Ryujinx.Graphics.Shader.Instructions { private enum TruthTable : byte { - False = 0x00, // false - True = 0xff, // true - In = 0xf0, // a - And2 = 0xc0, // a & b - Or2 = 0xfc, // a | b - Xor2 = 0x3c, // a ^ b - And3 = 0x80, // a & b & c - Or3 = 0xfe, // a | b | c - XorAnd = 0x60, // a & (b ^ c) - XorOr = 0xf6, // a | (b ^ c) - OrAnd = 0xe0, // a & (b | c) - AndOr = 0xf8, // a | (b & c) - Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true. - Majority = 0xe8, // Popcount(a, b, c) >= 2 - Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off + False = 0x00, // false + True = 0xff, // true + In = 0xf0, // a + And2 = 0xc0, // a & b + Or2 = 0xfc, // a | b + Xor2 = 0x3c, // a ^ b + And3 = 0x80, // a & b & c + Or3 = 0xfe, // a | b | c + XorAnd = 0x60, // a & (b ^ c) + XorOr = 0xf6, // a | (b ^ c) + OrAnd = 0xe0, // a & (b | c) + AndOr = 0xf8, // a | (b & c) + Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true. + Majority = 0xe8, // Popcount(a, b, c) >= 2 + Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off InverseGamble = 0x7e, // Inverse of Gamble - Dot = 0x1a, // a ^ (c | (a & b)) - Mux = 0xca, // a ? b : c - AndXor = 0x78, // a ^ (b & c) - OrXor = 0x1e, // a ^ (b | c) - Xor3 = 0x96, // a ^ b ^ c + Dot = 0x1a, // a ^ (c | (a & b)) + Mux = 0xca, // a ? b : c + AndXor = 0x78, // a ^ (b & c) + OrXor = 0x1e, // a ^ (b | c) + Xor3 = 0x96, // a ^ b ^ c } public static Operand GetFromTruthTable(EmitterContext context, Operand srcA, Operand srcB, Operand srcC, int imm) @@ -41,7 +40,7 @@ namespace Ryujinx.Graphics.Shader.Instructions Operand x = srcA; Operand y = srcB; Operand z = srcC; - + if ((i & 0x01) != 0) { (x, y) = (y, x); @@ -98,6 +97,7 @@ namespace Ryujinx.Graphics.Shader.Instructions { return imm switch { +#pragma warning disable IDE0055 // Disable formatting TruthTable.False => Const(0), TruthTable.True => Const(-1), TruthTable.In => x, @@ -118,7 +118,8 @@ namespace Ryujinx.Graphics.Shader.Instructions TruthTable.AndXor => context.BitwiseExclusiveOr(x, context.BitwiseAnd(y, z)), TruthTable.OrXor => context.BitwiseExclusiveOr(x, context.BitwiseOr(y, z)), TruthTable.Xor3 => context.BitwiseExclusiveOr(x, context.BitwiseExclusiveOr(y, z)), - _ => null + _ => null, +#pragma warning restore IDE0055 }; } @@ -138,4 +139,4 @@ namespace Ryujinx.Graphics.Shader.Instructions return (TruthTable)result; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/BasicBlock.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/BasicBlock.cs index 2aca118b7..637e120e1 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/BasicBlock.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/BasicBlock.cs @@ -83,9 +83,9 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation case Instruction.Discard: case Instruction.Return: return true; + default: + return false; } - - return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/CommentNode.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/CommentNode.cs index d4d87b067..1d33a9b02 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/CommentNode.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/CommentNode.cs @@ -9,4 +9,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation Comment = comment; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Function.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Function.cs index e535c3fc2..a5f3e0a8c 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Function.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Function.cs @@ -20,4 +20,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation OutArgumentsCount = outArgumentsCount; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/INode.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/INode.cs index 0f545e56f..d5eae00b7 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/INode.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/INode.cs @@ -12,4 +12,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation void SetSource(int index, Operand operand); } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Instruction.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Instruction.cs index de41a2cf7..808cc7ed6 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Instruction.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Instruction.cs @@ -1,8 +1,10 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace Ryujinx.Graphics.Shader.IntermediateRepresentation { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum Instruction { Absolute = 1, @@ -130,7 +132,7 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation FP32 = 1 << 16, FP64 = 1 << 17, - Mask = 0xffff + Mask = 0xffff, } static class InstructionExtensions @@ -161,4 +163,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation return inst == Instruction.Lod || inst == Instruction.TextureSize; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IoVariable.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IoVariable.cs index fb9b57bdd..fdee83451 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IoVariable.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IoVariable.cs @@ -43,6 +43,6 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation VertexId, VertexIndex, ViewportIndex, - ViewportMask + ViewportMask, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IrConsts.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IrConsts.cs index c264e47d1..cc9d6cc20 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IrConsts.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/IrConsts.cs @@ -3,6 +3,6 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation static class IrConsts { public const int False = 0; - public const int True = -1; + public const int True = -1; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operand.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operand.cs index 1df88a3d9..6648457f0 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operand.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operand.cs @@ -7,7 +7,7 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation class Operand { private const int CbufSlotBits = 5; - private const int CbufSlotLsb = 32 - CbufSlotBits; + private const int CbufSlotLsb = 32 - CbufSlotBits; private const int CbufSlotMask = (1 << CbufSlotBits) - 1; public OperandType Type { get; } @@ -30,19 +30,19 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation public Operand(OperandType type, int value) : this() { - Type = type; + Type = type; Value = value; } public Operand(Register reg) : this() { - Type = OperandType.Register; + Type = OperandType.Register; Value = PackRegInfo(reg.Index, reg.Type); } public Operand(int slot, int offset) : this() { - Type = OperandType.ConstantBuffer; + Type = OperandType.ConstantBuffer; Value = PackCbufInfo(slot, offset); } @@ -76,4 +76,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation return BitConverter.Int32BitsToSingle(Value); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandHelper.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandHelper.cs index 37c349e82..f88313552 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandHelper.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandHelper.cs @@ -59,4 +59,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation return new Operand(OperandType.Undefined); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandType.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandType.cs index 4d2da734e..7dbd9d25d 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandType.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/OperandType.cs @@ -8,6 +8,6 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation Label, LocalVariable, Register, - Undefined + Undefined, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs index 425cfd909..f5396a884 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs @@ -62,7 +62,7 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation public Operation(Instruction inst, int index, Operand[] dests, Operand[] sources) : this(sources) { - Inst = inst; + Inst = inst; Index = index; if (dests != null) @@ -286,4 +286,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/PhiNode.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/PhiNode.cs index 8fa25ae9b..6c95c7bdd 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/PhiNode.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/PhiNode.cs @@ -15,21 +15,21 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation public int DestsCount => _dest != null ? 1 : 0; - private HashSet _blocks; + private readonly HashSet _blocks; private class PhiSource { - public BasicBlock Block { get; } - public Operand Operand { get; set; } + public BasicBlock Block { get; } + public Operand Operand { get; set; } public PhiSource(BasicBlock block, Operand operand) { - Block = block; + Block = block; Operand = operand; } } - private List _sources; + private readonly List _sources; public int SourcesCount => _sources.Count; @@ -104,4 +104,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation _sources[index].Operand = source; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/StorageKind.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/StorageKind.cs index 20576a454..669c12816 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/StorageKind.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/StorageKind.cs @@ -17,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation GlobalMemoryS8, // TODO: Remove this and store type as a field on the Operation class itself. GlobalMemoryS16, // TODO: Remove this and store type as a field on the Operation class itself. GlobalMemoryU8, // TODO: Remove this and store type as a field on the Operation class itself. - GlobalMemoryU16 // TODO: Remove this and store type as a field on the Operation class itself. + GlobalMemoryU16, // TODO: Remove this and store type as a field on the Operation class itself. } static class StorageKindExtensions @@ -42,4 +42,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation storageKind == StorageKind.OutputPerPatch; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureFlags.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureFlags.cs index 6c20e856f..51ff09cf8 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureFlags.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureFlags.cs @@ -1,32 +1,34 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace Ryujinx.Graphics.Shader.IntermediateRepresentation { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum TextureFlags { - None = 0, - Bindless = 1 << 0, - Gather = 1 << 1, + None = 0, + Bindless = 1 << 0, + Gather = 1 << 1, Derivatives = 1 << 2, - IntCoords = 1 << 3, - LodBias = 1 << 4, - LodLevel = 1 << 5, - Offset = 1 << 6, - Offsets = 1 << 7, - Coherent = 1 << 8, + IntCoords = 1 << 3, + LodBias = 1 << 4, + LodLevel = 1 << 5, + Offset = 1 << 6, + Offsets = 1 << 7, + Coherent = 1 << 8, - AtomicMask = 15 << 16, + AtomicMask = 15 << 16, - Add = 0 << 16, - Minimum = 1 << 16, - Maximum = 2 << 16, - Increment = 3 << 16, - Decrement = 4 << 16, - BitwiseAnd = 5 << 16, - BitwiseOr = 6 << 16, - BitwiseXor = 7 << 16, - Swap = 8 << 16, - CAS = 9 << 16 + Add = 0 << 16, + Minimum = 1 << 16, + Maximum = 2 << 16, + Increment = 3 << 16, + Decrement = 4 << 16, + BitwiseAnd = 5 << 16, + BitwiseOr = 6 << 16, + BitwiseXor = 7 << 16, + Swap = 8 << 16, + CAS = 9 << 16, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureOperation.cs b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureOperation.cs index 6ab868cdc..b467fe533 100644 --- a/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureOperation.cs +++ b/src/Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureOperation.cs @@ -66,4 +66,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation Flags |= TextureFlags.LodLevel; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/OutputTopology.cs b/src/Ryujinx.Graphics.Shader/OutputTopology.cs index 6f977becb..dc4b304ad 100644 --- a/src/Ryujinx.Graphics.Shader/OutputTopology.cs +++ b/src/Ryujinx.Graphics.Shader/OutputTopology.cs @@ -2,23 +2,22 @@ namespace Ryujinx.Graphics.Shader { enum OutputTopology { - PointList = 1, - LineStrip = 6, - TriangleStrip = 7 + PointList = 1, + LineStrip = 6, + TriangleStrip = 7, } static class OutputTopologyExtensions { public static string ToGlslString(this OutputTopology topology) { - switch (topology) + return topology switch { - case OutputTopology.LineStrip: return "line_strip"; - case OutputTopology.PointList: return "points"; - case OutputTopology.TriangleStrip: return "triangle_strip"; - } - - return "points"; + OutputTopology.LineStrip => "line_strip", + OutputTopology.PointList => "points", + OutputTopology.TriangleStrip => "triangle_strip", + _ => "points", + }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/SamplerType.cs b/src/Ryujinx.Graphics.Shader/SamplerType.cs index 620f4ccf3..85e97368f 100644 --- a/src/Ryujinx.Graphics.Shader/SamplerType.cs +++ b/src/Ryujinx.Graphics.Shader/SamplerType.cs @@ -15,10 +15,10 @@ namespace Ryujinx.Graphics.Shader Mask = 0xff, - Array = 1 << 8, - Indexed = 1 << 9, + Array = 1 << 8, + Indexed = 1 << 9, Multisample = 1 << 10, - Shadow = 1 << 11 + Shadow = 1 << 11, } static class SamplerTypeExtensions @@ -32,7 +32,7 @@ namespace Ryujinx.Graphics.Shader SamplerType.Texture2D => 2, SamplerType.Texture3D => 3, SamplerType.TextureCube => 3, - _ => throw new ArgumentException($"Invalid sampler type \"{type}\".") + _ => throw new ArgumentException($"Invalid sampler type \"{type}\"."), }; } @@ -45,7 +45,7 @@ namespace Ryujinx.Graphics.Shader SamplerType.Texture2D => "sampler2D", SamplerType.Texture3D => "sampler3D", SamplerType.TextureCube => "samplerCube", - _ => throw new ArgumentException($"Invalid sampler type \"{type}\".") + _ => throw new ArgumentException($"Invalid sampler type \"{type}\"."), }; if ((type & SamplerType.Multisample) != 0) @@ -75,7 +75,7 @@ namespace Ryujinx.Graphics.Shader SamplerType.Texture2D => "image2D", SamplerType.Texture3D => "image3D", SamplerType.TextureCube => "imageCube", - _ => throw new ArgumentException($"Invalid sampler type \"{type}\".") + _ => throw new ArgumentException($"Invalid sampler type \"{type}\"."), }; if ((type & SamplerType.Multisample) != 0) @@ -90,11 +90,15 @@ namespace Ryujinx.Graphics.Shader switch (componentType) { - case AggregateType.U32: typeName = 'u' + typeName; break; - case AggregateType.S32: typeName = 'i' + typeName; break; + case AggregateType.U32: + typeName = 'u' + typeName; + break; + case AggregateType.S32: + typeName = 'i' + typeName; + break; } return typeName; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/ShaderIdentification.cs b/src/Ryujinx.Graphics.Shader/ShaderIdentification.cs index 3f0157626..551e318c0 100644 --- a/src/Ryujinx.Graphics.Shader/ShaderIdentification.cs +++ b/src/Ryujinx.Graphics.Shader/ShaderIdentification.cs @@ -3,6 +3,6 @@ namespace Ryujinx.Graphics.Shader public enum ShaderIdentification { None, - GeometryLayerPassthrough + GeometryLayerPassthrough, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/ShaderProgram.cs b/src/Ryujinx.Graphics.Shader/ShaderProgram.cs index 29fff21e6..9e62491bf 100644 --- a/src/Ryujinx.Graphics.Shader/ShaderProgram.cs +++ b/src/Ryujinx.Graphics.Shader/ShaderProgram.cs @@ -32,4 +32,4 @@ namespace Ryujinx.Graphics.Shader Code = line + Environment.NewLine + Code; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/ShaderProgramInfo.cs b/src/Ryujinx.Graphics.Shader/ShaderProgramInfo.cs index 30f0ffaa2..e87769bb9 100644 --- a/src/Ryujinx.Graphics.Shader/ShaderProgramInfo.cs +++ b/src/Ryujinx.Graphics.Shader/ShaderProgramInfo.cs @@ -48,4 +48,4 @@ namespace Ryujinx.Graphics.Shader FragmentOutputMap = fragmentOutputMap; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/ShaderStage.cs b/src/Ryujinx.Graphics.Shader/ShaderStage.cs index f16fe3281..f6cfe4bb2 100644 --- a/src/Ryujinx.Graphics.Shader/ShaderStage.cs +++ b/src/Ryujinx.Graphics.Shader/ShaderStage.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Graphics.Shader Geometry, Fragment, - Count + Count, } public static class ShaderStageExtensions @@ -24,4 +24,4 @@ namespace Ryujinx.Graphics.Shader return stage == ShaderStage.Vertex || stage == ShaderStage.Fragment || stage == ShaderStage.Compute; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstAssignment.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstAssignment.cs index bb3fe7af4..efda774c6 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstAssignment.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstAssignment.cs @@ -27,9 +27,9 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public AstAssignment(IAstNode destination, IAstNode source) { Destination = destination; - Source = source; + Source = source; AddDef(destination, this); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlock.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlock.cs index 2f34bee83..826dbff88 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlock.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlock.cs @@ -29,7 +29,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } } - private LinkedList _nodes; + private readonly LinkedList _nodes; public IAstNode First => _nodes.First?.Value; public IAstNode Last => _nodes.Last?.Value; @@ -38,7 +38,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public AstBlock(AstBlockType type, IAstNode condition = null) { - Type = type; + Type = type; Condition = condition; _nodes = new LinkedList(); @@ -114,4 +114,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return GetEnumerator(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockType.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockType.cs index c12efda90..a7dcc72a1 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockType.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockType.cs @@ -7,6 +7,6 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Else, ElseIf, Main, - While + While, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockVisitor.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockVisitor.cs index 10d5dce0a..16efeff72 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockVisitor.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstBlockVisitor.cs @@ -65,4 +65,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstComment.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstComment.cs index dabe623fd..1c82e646f 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstComment.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstComment.cs @@ -9,4 +9,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Comment = comment; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstHelper.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstHelper.cs index 7aa0409b6..06d13c90b 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstHelper.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstHelper.cs @@ -49,9 +49,10 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public static AstOperand Local(AggregateType type) { - AstOperand local = new AstOperand(OperandType.LocalVariable); - - local.VarType = type; + AstOperand local = new(OperandType.LocalVariable) + { + VarType = type, + }; return local; } @@ -71,4 +72,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return node.LLNode.Previous?.Value; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstNode.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstNode.cs index c667aac98..0b8246171 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstNode.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstNode.cs @@ -8,4 +8,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public LinkedListNode LLNode { get; set; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperand.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperand.cs index 473aa2e7b..b64b96b8d 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperand.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperand.cs @@ -29,10 +29,10 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Value = operand.Value; } - public AstOperand(OperandType type, int value = 0) : this() + public AstOperand(OperandType type, int value = 0) : this() { - Type = type; + Type = type; Value = value; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperation.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperation.cs index 4cf729d09..46555a85a 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperation.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOperation.cs @@ -14,7 +14,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public int Index { get; } - private IAstNode[] _sources; + private readonly IAstNode[] _sources; public int SourcesCount => _sources.Length; @@ -77,12 +77,18 @@ namespace Ryujinx.Graphics.Shader.StructuredIr switch (componentsCount) { - case 2: type |= AggregateType.Vector2; break; - case 3: type |= AggregateType.Vector3; break; - case 4: type |= AggregateType.Vector4; break; + case 2: + type |= AggregateType.Vector2; + break; + case 3: + type |= AggregateType.Vector3; + break; + case 4: + type |= AggregateType.Vector4; + break; } return type; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOptimizer.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOptimizer.cs index b71ae2c41..4fb5d02b3 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstOptimizer.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstOptimizer.cs @@ -17,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr // (this makes comparison with the disassembly easier). if (!context.Config.Options.Flags.HasFlag(TranslationFlags.DebugMode)) { - AstBlockVisitor visitor = new AstBlockVisitor(mainBlock); + AstBlockVisitor visitor = new(mainBlock); foreach (IAstNode node in visitor.Visit()) { @@ -45,7 +45,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr private static bool IsWorthPropagating(IAstNode source) { - if (!(source is AstOperation srcOp)) + if (source is not AstOperation srcOp) { return false; } @@ -87,7 +87,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr private static void RemoveEmptyBlocks(AstBlock mainBlock) { - Queue pending = new Queue(); + Queue pending = new(); pending.Enqueue(mainBlock); @@ -152,4 +152,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/AstTextureOperation.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/AstTextureOperation.cs index a4e097eb6..4ff2035a8 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/AstTextureOperation.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/AstTextureOperation.cs @@ -28,4 +28,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Handle = handle; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/BufferDefinition.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/BufferDefinition.cs index 5afebc75f..e27594804 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/BufferDefinition.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/BufferDefinition.cs @@ -17,4 +17,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Type = type; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/BufferLayout.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/BufferLayout.cs index 43a866626..1c25ed34d 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/BufferLayout.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/BufferLayout.cs @@ -3,6 +3,6 @@ namespace Ryujinx.Graphics.Shader.StructuredIr enum BufferLayout { Std140, - Std430 + Std430, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/GotoElimination.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/GotoElimination.cs index 8bcf9d9c9..3ca1266f6 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/GotoElimination.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/GotoElimination.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using System; using System.Collections.Generic; - using static Ryujinx.Graphics.Shader.StructuredIr.AstHelper; namespace Ryujinx.Graphics.Shader.StructuredIr @@ -110,16 +109,16 @@ namespace Ryujinx.Graphics.Shader.StructuredIr if (lLevel > rLevel) { - block = lBlock; + block = lBlock; blockLvl = lLevel; - other = rBlock; + other = rBlock; otherLvl = rLevel; } else /* if (rLevel > lLevel) */ { - block = rBlock; + block = rBlock; blockLvl = rLevel; - other = lBlock; + other = lBlock; otherLvl = lLevel; } @@ -144,7 +143,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr AstBlock[] path = BackwardsPath(block, ParentBlock(stmt.Label)); - AstBlock loopFirstStmt = path[path.Length - 1]; + AstBlock loopFirstStmt = path[^1]; if (loopFirstStmt.Type == AstBlockType.Else) { @@ -194,7 +193,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr loopBlock.AddAfter(child, stmt.Goto); - block = loopBlock; + block = loopBlock; gLevel = loopLevel; } } @@ -252,7 +251,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr for (int index = path.Length - 1; index >= 0; index--) { AstBlock child = path[index]; - AstBlock last = child; + AstBlock last = child; if (child.Type == AstBlockType.If) { @@ -265,7 +264,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr else if (child.Type == AstBlockType.Else) { // Modify the matching if condition to force the else to be entered by the goto. - if (!(Previous(child) is AstBlock ifBlock) || ifBlock.Type != AstBlockType.If) + if (Previous(child) is not AstBlock ifBlock || ifBlock.Type != AstBlockType.If) { throw new InvalidOperationException("Found an else without a matching if."); } @@ -332,7 +331,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { AstBlock block = ParentBlock(stmt.Goto); - AstBlock newBlock = new AstBlock(AstBlockType.If, stmt.Condition); + AstBlock newBlock = new(AstBlockType.If, stmt.Condition); block.AddAfter(stmt.Goto, newBlock); @@ -340,11 +339,11 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } private static AstBlock Enclose( - AstBlock block, + AstBlock block, AstBlockType type, - IAstNode cond, - IAstNode first, - IAstNode last = null) + IAstNode cond, + IAstNode first, + IAstNode last = null) { if (first == last) { @@ -367,7 +366,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return first as AstBlock; } - AstBlock newBlock = new AstBlock(type, cond); + AstBlock newBlock = new(type, cond); block.AddBefore(first, newBlock); @@ -387,7 +386,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr private static bool BlockMatches(IAstNode node, AstBlockType type, IAstNode cond) { - if (!(node is AstBlock block)) + if (node is not AstBlock block) { return false; } @@ -399,7 +398,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { if (lCond is AstOperation lCondOp && lCondOp.Inst == Instruction.LogicalNot) { - if (!(rCond is AstOperation rCondOp) || rCondOp.Inst != lCondOp.Inst) + if (rCond is not AstOperation rCondOp || rCondOp.Inst != lCondOp.Inst) { return false; } @@ -418,7 +417,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return block.Parent; } - while (!(node is AstBlock)) + while (node is not AstBlock) { node = node.Parent; } @@ -430,7 +429,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { AstBlock block = bottom; - List path = new List(); + List path = new(); while (block != top) { @@ -456,4 +455,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return level; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/GotoStatement.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/GotoStatement.cs index 25216e55f..4607a16c1 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/GotoStatement.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/GotoStatement.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { class GotoStatement { - public AstOperation Goto { get; } + public AstOperation Goto { get; } public AstAssignment Label { get; } public IAstNode Condition => Label.Destination; @@ -15,9 +15,9 @@ namespace Ryujinx.Graphics.Shader.StructuredIr public GotoStatement(AstOperation branch, AstAssignment label, bool isLoop) { - Goto = branch; - Label = label; + Goto = branch; + Label = label; IsLoop = isLoop; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/HelperFunctionsMask.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/HelperFunctionsMask.cs index ed910f96d..73ce90827 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/HelperFunctionsMask.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/HelperFunctionsMask.cs @@ -7,11 +7,11 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { MultiplyHighS32 = 1 << 2, MultiplyHighU32 = 1 << 3, - Shuffle = 1 << 4, - ShuffleDown = 1 << 5, - ShuffleUp = 1 << 6, - ShuffleXor = 1 << 7, - SwizzleAdd = 1 << 10, - FSI = 1 << 11 + Shuffle = 1 << 4, + ShuffleDown = 1 << 5, + ShuffleUp = 1 << 6, + ShuffleXor = 1 << 7, + SwizzleAdd = 1 << 10, + FSI = 1 << 11, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/IAstNode.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/IAstNode.cs index 5ececbb5e..248d8d69f 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/IAstNode.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/IAstNode.cs @@ -8,4 +8,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr LinkedListNode LLNode { get; set; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/InstructionInfo.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/InstructionInfo.cs index b08478ad3..6cd0fd086 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/InstructionInfo.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/InstructionInfo.cs @@ -19,12 +19,13 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } } - private static InstInfo[] _infoTbl; + private static readonly InstInfo[] _infoTbl; static InstructionInfo() { _infoTbl = new InstInfo[(int)Instruction.Count]; +#pragma warning disable IDE0055 // Disable formatting // Inst Destination type Source 1 type Source 2 type Source 3 type Source 4 type Add(Instruction.AtomicAdd, AggregateType.U32, AggregateType.S32, AggregateType.S32, AggregateType.U32); Add(Instruction.AtomicAnd, AggregateType.U32, AggregateType.S32, AggregateType.S32, AggregateType.U32); @@ -130,6 +131,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Add(Instruction.VoteAll, AggregateType.Bool, AggregateType.Bool); Add(Instruction.VoteAllEqual, AggregateType.Bool, AggregateType.Bool); Add(Instruction.VoteAny, AggregateType.Bool, AggregateType.Bool); +#pragma warning restore IDE0055v } private static void Add(Instruction inst, AggregateType destType, params AggregateType[] srcTypes) @@ -201,4 +203,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return _infoTbl[(int)(inst & Instruction.Mask)].SrcTypes.Length == 1; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/IoDefinition.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/IoDefinition.cs index 21a1b3f08..0a0681fa4 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/IoDefinition.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/IoDefinition.cs @@ -41,4 +41,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return $"{StorageKind}.{IoVariable}.{Location}.{Component}"; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/MemoryDefinition.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/MemoryDefinition.cs index c0bb750e7..3ea69fde1 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/MemoryDefinition.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/MemoryDefinition.cs @@ -15,4 +15,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr ArrayLength = arrayLength; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/OperandInfo.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/OperandInfo.cs index 48060f6b9..638a5298f 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/OperandInfo.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/OperandInfo.cs @@ -25,8 +25,8 @@ namespace Ryujinx.Graphics.Shader.StructuredIr OperandType.Argument => AggregateType.S32, OperandType.Constant => AggregateType.S32, OperandType.Undefined => AggregateType.S32, - _ => throw new ArgumentException($"Invalid operand type \"{type}\".") + _ => throw new ArgumentException($"Invalid operand type \"{type}\"."), }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/PhiFunctions.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/PhiFunctions.cs index 541ca298e..8b1cb9c56 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/PhiFunctions.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/PhiFunctions.cs @@ -30,7 +30,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr BasicBlock srcBlock = phi.GetBlock(index); - Operation copyOp = new Operation(Instruction.Copy, phi.Dest, src); + Operation copyOp = new(Instruction.Copy, phi.Dest, src); srcBlock.Append(copyOp); } @@ -42,4 +42,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/ShaderProperties.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/ShaderProperties.cs index c6132ef8c..1da5cb657 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/ShaderProperties.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/ShaderProperties.cs @@ -48,4 +48,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return id; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/StructureType.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/StructureType.cs index 17f497386..fdf824f57 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/StructureType.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/StructureType.cs @@ -2,7 +2,7 @@ using Ryujinx.Graphics.Shader.Translation; namespace Ryujinx.Graphics.Shader.StructuredIr { - struct StructureField + readonly struct StructureField { public AggregateType Type { get; } public string Name { get; } diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredFunction.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredFunction.cs index 61c4fed73..aa5e13867 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredFunction.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredFunction.cs @@ -39,4 +39,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr : InArguments[index]; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgram.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgram.cs index 9d12a73cd..a4e6444b0 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgram.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgram.cs @@ -10,7 +10,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { public static StructuredProgramInfo MakeStructuredProgram(IReadOnlyList functions, ShaderConfig config) { - StructuredProgramContext context = new StructuredProgramContext(config); + StructuredProgramContext context = new(config); for (int funcIndex = 0; funcIndex < functions.Count; funcIndex++) { @@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr AggregateType returnType = function.ReturnsValue ? AggregateType.S32 : AggregateType.Void; - AggregateType[] inArguments = new AggregateType[function.InArgumentsCount]; + AggregateType[] inArguments = new AggregateType[function.InArgumentsCount]; AggregateType[] outArguments = new AggregateType[function.OutArgumentsCount]; for (int i = 0; i < inArguments.Length; i++) @@ -79,7 +79,6 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { IoVariable ioVariable = (IoVariable)operation.GetSource(0).Value; bool isOutput = storageKind.IsOutput(); - bool perPatch = storageKind.IsPerPatch(); int location = 0; int component = 0; @@ -169,9 +168,15 @@ namespace Ryujinx.Graphics.Shader.StructuredIr switch (componentsCount) { - case 2: destType |= AggregateType.Vector2; break; - case 3: destType |= AggregateType.Vector3; break; - case 4: destType |= AggregateType.Vector4; break; + case 2: + destType |= AggregateType.Vector2; + break; + case 3: + destType |= AggregateType.Vector3; + break; + case 4: + destType |= AggregateType.Vector4; + break; } AstOperand destVec = context.NewTemp(destType); @@ -181,7 +186,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr for (int i = 0; i < operation.DestsCount; i++) { AstOperand dest = context.GetOperand(operation.GetDest(i)); - AstOperand index = new AstOperand(OperandType.Constant, i); + AstOperand index = new(OperandType.Constant, i); dest.VarType = destElemType; @@ -202,7 +207,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr } bool isCondSel = inst == Instruction.ConditionalSelect; - bool isCopy = inst == Instruction.Copy; + bool isCopy = inst == Instruction.Copy; if (isCondSel || isCopy) { @@ -304,9 +309,9 @@ namespace Ryujinx.Graphics.Shader.StructuredIr private static AggregateType GetVarTypeFromUses(Operand dest) { - HashSet visited = new HashSet(); + HashSet visited = new(); - Queue pending = new Queue(); + Queue pending = new(); bool Enqueue(Operand operand) { @@ -385,7 +390,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr { Instruction.ImageLoad or Instruction.TextureSample => true, - _ => false + _ => false, }; } @@ -396,7 +401,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Instruction.Branch or Instruction.BranchIfFalse or Instruction.BranchIfTrue => true, - _ => false + _ => false, }; } @@ -408,7 +413,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Instruction.BitwiseExclusiveOr or Instruction.BitwiseNot or Instruction.BitwiseOr => true, - _ => false + _ => false, }; } @@ -420,8 +425,8 @@ namespace Ryujinx.Graphics.Shader.StructuredIr Instruction.BitwiseExclusiveOr => Instruction.LogicalExclusiveOr, Instruction.BitwiseNot => Instruction.LogicalNot, Instruction.BitwiseOr => Instruction.LogicalOr, - _ => throw new ArgumentException($"Unexpected instruction \"{inst}\".") + _ => throw new ArgumentException($"Unexpected instruction \"{inst}\"."), }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramContext.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramContext.cs index a4d079914..019fc332b 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramContext.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramContext.cs @@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.Translation; using System.Collections.Generic; using System.Linq; using System.Numerics; - using static Ryujinx.Graphics.Shader.StructuredIr.AstHelper; namespace Ryujinx.Graphics.Shader.StructuredIr @@ -165,7 +164,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr // this is not valid as the loop condition would be evaluated, // and it could erroneously jump back to the start of the loop. bool inRange = - block.Branch.Index < _currEndIndex || + block.Branch.Index < _currEndIndex || (block.Branch.Index == _currEndIndex && block.Branch.Index < _loopEndIndex); bool isLoop = block.Branch.Index <= block.Index; @@ -184,11 +183,11 @@ namespace Ryujinx.Graphics.Shader.StructuredIr AddNode(Assign(gotoTempAsg.Destination, cond)); - AstOperation branch = new AstOperation(branchOp.Inst); + AstOperation branch = new(branchOp.Inst); AddNode(branch); - GotoStatement gotoStmt = new GotoStatement(branch, gotoTempAsg, isLoop); + GotoStatement gotoStmt = new(branch, gotoTempAsg, isLoop); _gotos.Add(gotoStmt); } @@ -236,13 +235,13 @@ namespace Ryujinx.Graphics.Shader.StructuredIr private void NewBlock(AstBlockType type, IAstNode cond, int endIndex) { - AstBlock childBlock = new AstBlock(type, cond); + AstBlock childBlock = new(type, cond); AddNode(childBlock); _blockStack.Push((_currBlock, _currEndIndex, _loopEndIndex)); - _currBlock = childBlock; + _currBlock = childBlock; _currEndIndex = endIndex; if (type == AstBlockType.DoWhile) @@ -316,7 +315,7 @@ namespace Ryujinx.Graphics.Shader.StructuredIr new AstOperand(OperandType.Constant, binding), new AstOperand(OperandType.Constant, 0), new AstOperand(OperandType.Constant, vecIndex), - new AstOperand(OperandType.Constant, elemIndex) + new AstOperand(OperandType.Constant, elemIndex), }; return new AstOperation(Instruction.Load, StorageKind.ConstantBuffer, false, sources, sources.Length); @@ -349,4 +348,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr return astOperand; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramInfo.cs b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramInfo.cs index c51041467..4f18c7fd7 100644 --- a/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramInfo.cs +++ b/src/Ryujinx.Graphics.Shader/StructuredIr/StructuredProgramInfo.cs @@ -33,4 +33,4 @@ namespace Ryujinx.Graphics.Shader.StructuredIr IoDefinitions = new HashSet(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/SupportBuffer.cs b/src/Ryujinx.Graphics.Shader/SupportBuffer.cs index 5eb7fe467..24a99345a 100644 --- a/src/Ryujinx.Graphics.Shader/SupportBuffer.cs +++ b/src/Ryujinx.Graphics.Shader/SupportBuffer.cs @@ -20,22 +20,22 @@ namespace Ryujinx.Graphics.Shader FragmentIsBgra, ViewportInverse, FragmentRenderScaleCount, - RenderScale + RenderScale, } public struct SupportBuffer { internal const int Binding = 0; - public static int FieldSize; - public static int RequiredSize; + public static readonly int FieldSize; + public static readonly int RequiredSize; - public static int FragmentAlphaTestOffset; - public static int FragmentIsBgraOffset; - public static int ViewportInverseOffset; - public static int FragmentRenderScaleCountOffset; - public static int GraphicsRenderScaleOffset; - public static int ComputeRenderScaleOffset; + public static readonly int FragmentAlphaTestOffset; + public static readonly int FragmentIsBgraOffset; + public static readonly int ViewportInverseOffset; + public static readonly int FragmentRenderScaleCountOffset; + public static readonly int GraphicsRenderScaleOffset; + public static readonly int ComputeRenderScaleOffset; public const int FragmentIsBgraCount = 8; // One for the render target, 64 for the textures, and 8 for the images. @@ -51,7 +51,7 @@ namespace Ryujinx.Graphics.Shader FieldSize = Unsafe.SizeOf>(); RequiredSize = Unsafe.SizeOf(); - SupportBuffer instance = new SupportBuffer(); + SupportBuffer instance = new(); FragmentAlphaTestOffset = OffsetOf(ref instance, ref instance.FragmentAlphaTest); FragmentIsBgraOffset = OffsetOf(ref instance, ref instance.FragmentIsBgra); @@ -69,7 +69,7 @@ namespace Ryujinx.Graphics.Shader new StructureField(AggregateType.Array | AggregateType.U32, "s_is_bgra", FragmentIsBgraCount), new StructureField(AggregateType.Vector4 | AggregateType.FP32, "s_viewport_inverse"), new StructureField(AggregateType.S32, "s_frag_scale_count"), - new StructureField(AggregateType.Array | AggregateType.FP32, "s_render_scale", RenderScaleMaxCount) + new StructureField(AggregateType.Array | AggregateType.FP32, "s_render_scale", RenderScaleMaxCount), }); } @@ -81,4 +81,4 @@ namespace Ryujinx.Graphics.Shader // Render scale max count: 1 + 64 + 8. First scale is fragment output scale, others are textures/image inputs. public Array73> RenderScale; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/TessPatchType.cs b/src/Ryujinx.Graphics.Shader/TessPatchType.cs index 2361b69f8..76be22fd4 100644 --- a/src/Ryujinx.Graphics.Shader/TessPatchType.cs +++ b/src/Ryujinx.Graphics.Shader/TessPatchType.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Shader { Isolines = 0, Triangles = 1, - Quads = 2 + Quads = 2, } static class TessPatchTypeExtensions @@ -15,8 +15,8 @@ namespace Ryujinx.Graphics.Shader { TessPatchType.Isolines => "isolines", TessPatchType.Quads => "quads", - _ => "triangles" + _ => "triangles", }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/TessSpacing.cs b/src/Ryujinx.Graphics.Shader/TessSpacing.cs index 35c44190c..6035366c1 100644 --- a/src/Ryujinx.Graphics.Shader/TessSpacing.cs +++ b/src/Ryujinx.Graphics.Shader/TessSpacing.cs @@ -4,7 +4,7 @@ namespace Ryujinx.Graphics.Shader { EqualSpacing = 0, FractionalEventSpacing = 1, - FractionalOddSpacing = 2 + FractionalOddSpacing = 2, } static class TessSpacingExtensions @@ -15,8 +15,8 @@ namespace Ryujinx.Graphics.Shader { TessSpacing.FractionalEventSpacing => "fractional_even_spacing", TessSpacing.FractionalOddSpacing => "fractional_odd_spacing", - _ => "equal_spacing" + _ => "equal_spacing", }; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/TextureDescriptor.cs b/src/Ryujinx.Graphics.Shader/TextureDescriptor.cs index 85ea9adbe..626faa695 100644 --- a/src/Ryujinx.Graphics.Shader/TextureDescriptor.cs +++ b/src/Ryujinx.Graphics.Shader/TextureDescriptor.cs @@ -16,12 +16,12 @@ namespace Ryujinx.Graphics.Shader public TextureDescriptor(int binding, SamplerType type, TextureFormat format, int cbufSlot, int handleIndex) { - Binding = binding; - Type = type; - Format = format; - CbufSlot = cbufSlot; + Binding = binding; + Type = type; + Format = format; + CbufSlot = cbufSlot; HandleIndex = handleIndex; - Flags = TextureUsageFlags.None; + Flags = TextureUsageFlags.None; } public TextureDescriptor SetFlag(TextureUsageFlags flag) @@ -31,4 +31,4 @@ namespace Ryujinx.Graphics.Shader return this; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/TextureFormat.cs b/src/Ryujinx.Graphics.Shader/TextureFormat.cs index d4c8b96be..f6e57fe8f 100644 --- a/src/Ryujinx.Graphics.Shader/TextureFormat.cs +++ b/src/Ryujinx.Graphics.Shader/TextureFormat.cs @@ -43,7 +43,7 @@ namespace Ryujinx.Graphics.Shader R32G32B32A32Sint, R10G10B10A2Unorm, R10G10B10A2Uint, - R11G11B10Float + R11G11B10Float, } static class TextureFormatExtensions @@ -52,6 +52,7 @@ namespace Ryujinx.Graphics.Shader { return format switch { +#pragma warning disable IDE0055 // Disable formatting TextureFormat.R8Unorm => "r8", TextureFormat.R8Snorm => "r8_snorm", TextureFormat.R8Uint => "r8ui", @@ -91,7 +92,8 @@ namespace Ryujinx.Graphics.Shader TextureFormat.R10G10B10A2Unorm => "rgb10_a2", TextureFormat.R10G10B10A2Uint => "rgb10_a2ui", TextureFormat.R11G11B10Float => "r11f_g11f_b10f", - _ => string.Empty + _ => string.Empty, +#pragma warning restore IDE0055 }; } diff --git a/src/Ryujinx.Graphics.Shader/TextureHandle.cs b/src/Ryujinx.Graphics.Shader/TextureHandle.cs index a59c8cd4a..fc9ab2d67 100644 --- a/src/Ryujinx.Graphics.Shader/TextureHandle.cs +++ b/src/Ryujinx.Graphics.Shader/TextureHandle.cs @@ -8,7 +8,7 @@ namespace Ryujinx.Graphics.Shader CombinedSampler = 0, // Must be 0. SeparateSamplerHandle = 1, SeparateSamplerId = 2, - SeparateConstantSamplerHandle = 3 + SeparateConstantSamplerHandle = 3, } public static class TextureHandle diff --git a/src/Ryujinx.Graphics.Shader/TextureUsageFlags.cs b/src/Ryujinx.Graphics.Shader/TextureUsageFlags.cs index 2419a1de4..3ad1685b6 100644 --- a/src/Ryujinx.Graphics.Shader/TextureUsageFlags.cs +++ b/src/Ryujinx.Graphics.Shader/TextureUsageFlags.cs @@ -14,6 +14,6 @@ namespace Ryujinx.Graphics.Shader ResScaleUnsupported = 1 << 0, NeedsScaleValue = 1 << 1, ImageStore = 1 << 2, - ImageCoherent = 1 << 3 + ImageCoherent = 1 << 3, } } diff --git a/src/Ryujinx.Graphics.Shader/Translation/AggregateType.cs b/src/Ryujinx.Graphics.Shader/Translation/AggregateType.cs index a54eddc59..def8f1a9d 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/AggregateType.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/AggregateType.cs @@ -1,8 +1,10 @@ using System; +using System.Diagnostics.CodeAnalysis; namespace Ryujinx.Graphics.Shader.Translation { [Flags] + [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")] enum AggregateType { Invalid, @@ -23,7 +25,7 @@ namespace Ryujinx.Graphics.Shader.Translation Vector3 = 2 << ElementCountShift, Vector4 = 3 << ElementCountShift, - Array = 1 << 10 + Array = 1 << 10, } static class AggregateTypeExtensions @@ -37,7 +39,7 @@ namespace Ryujinx.Graphics.Shader.Translation AggregateType.S32 or AggregateType.U32 => 4, AggregateType.FP64 => 8, - _ => 0 + _ => 0, }; switch (type & AggregateType.ElementCountMask) diff --git a/src/Ryujinx.Graphics.Shader/Translation/AttributeConsts.cs b/src/Ryujinx.Graphics.Shader/Translation/AttributeConsts.cs index 683b0d8ac..f749cecb8 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/AttributeConsts.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/AttributeConsts.cs @@ -33,4 +33,4 @@ namespace Ryujinx.Graphics.Shader.Translation public const int UserAttributePerPatchBase = 0x18; public const int UserAttributePerPatchEnd = 0x200; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/ControlFlowGraph.cs b/src/Ryujinx.Graphics.Shader/Translation/ControlFlowGraph.cs index 65328fd7f..9b07c28f1 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/ControlFlowGraph.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/ControlFlowGraph.cs @@ -13,11 +13,11 @@ namespace Ryujinx.Graphics.Shader.Translation { Blocks = blocks; - HashSet visited = new HashSet(); + HashSet visited = new(); - Stack blockStack = new Stack(); + Stack blockStack = new(); - List postOrderBlocks = new List(blocks.Length); + List postOrderBlocks = new(blocks.Length); PostOrderMap = new int[blocks.Length]; @@ -50,9 +50,9 @@ namespace Ryujinx.Graphics.Shader.Translation public static ControlFlowGraph Create(Operation[] operations) { - Dictionary labels = new Dictionary(); + Dictionary labels = new(); - List blocks = new List(); + List blocks = new(); BasicBlock currentBlock = null; @@ -68,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.Translation void NewNextBlock() { - BasicBlock block = new BasicBlock(blocks.Count); + BasicBlock block = new(blocks.Count); blocks.Add(block); @@ -110,7 +110,7 @@ namespace Ryujinx.Graphics.Shader.Translation currentBlock.Operations.AddLast(operation); } - needsNewBlock = operation.Inst == Instruction.Branch || + needsNewBlock = operation.Inst == Instruction.Branch || operation.Inst == Instruction.BranchIfTrue || operation.Inst == Instruction.BranchIfFalse; @@ -173,4 +173,4 @@ namespace Ryujinx.Graphics.Shader.Translation return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Dominance.cs b/src/Ryujinx.Graphics.Shader/Translation/Dominance.cs index 09c2eb0fd..cd651ce08 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Dominance.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Dominance.cs @@ -91,4 +91,4 @@ namespace Ryujinx.Graphics.Shader.Translation } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs b/src/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs index 87e5457f9..9eedc3f91 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/EmitterContext.cs @@ -4,7 +4,6 @@ using System.Collections.Generic; using System.Diagnostics; using System.Numerics; using System.Runtime.CompilerServices; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation @@ -84,7 +83,7 @@ namespace Ryujinx.Graphics.Shader.Translation public Operand Add(Instruction inst, Operand dest = null, params Operand[] sources) { - Operation operation = new Operation(inst, dest, sources); + Operation operation = new(inst, dest, sources); _operations.Add(operation); @@ -93,7 +92,7 @@ namespace Ryujinx.Graphics.Shader.Translation public Operand Add(Instruction inst, StorageKind storageKind, Operand dest = null, params Operand[] sources) { - Operation operation = new Operation(inst, storageKind, dest, sources); + Operation operation = new(inst, storageKind, dest, sources); _operations.Add(operation); @@ -104,7 +103,7 @@ namespace Ryujinx.Graphics.Shader.Translation { Operand[] dests = new[] { dest.Item1, dest.Item2 }; - Operation operation = new Operation(inst, 0, dests, sources); + Operation operation = new(inst, 0, dests, sources); Add(operation); @@ -430,7 +429,7 @@ namespace Ryujinx.Graphics.Shader.Translation AlphaTestOp.Less => Instruction.CompareLess, AlphaTestOp.LessOrEqual => Instruction.CompareLessOrEqual, AlphaTestOp.NotEqual => Instruction.CompareNotEqual, - _ => 0 + _ => 0, }; Debug.Assert(comparator != 0, $"Invalid alpha test operation \"{alphaTestOp}\"."); @@ -532,4 +531,4 @@ namespace Ryujinx.Graphics.Shader.Translation return _operations.ToArray(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/EmitterContextInsts.cs b/src/Ryujinx.Graphics.Shader/Translation/EmitterContextInsts.cs index 0ba26107c..c2f1b790f 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/EmitterContextInsts.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/EmitterContextInsts.cs @@ -850,4 +850,4 @@ namespace Ryujinx.Graphics.Shader.Translation return context.Add(Instruction.VoteAny, Local(), a); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/FeatureFlags.cs b/src/Ryujinx.Graphics.Shader/Translation/FeatureFlags.cs index 59d35d906..9d4d032af 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/FeatureFlags.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/FeatureFlags.cs @@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.Translation // Affected by resolution scaling. IntegerSampling = 1 << 0, - FragCoordXY = 1 << 1, + FragCoordXY = 1 << 1, Bindless = 1 << 2, InstanceId = 1 << 3, @@ -23,6 +23,6 @@ namespace Ryujinx.Graphics.Shader.Translation OaIndexing = 1 << 8, FixedFuncAttr = 1 << 9, LocalMemory = 1 << 10, - SharedMemory = 1 << 11 + SharedMemory = 1 << 11, } } diff --git a/src/Ryujinx.Graphics.Shader/Translation/FunctionMatch.cs b/src/Ryujinx.Graphics.Shader/Translation/FunctionMatch.cs index 073e120a3..714a9d68c 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/FunctionMatch.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/FunctionMatch.cs @@ -7,11 +7,11 @@ namespace Ryujinx.Graphics.Shader.Translation { static class FunctionMatch { - private static IPatternTreeNode[] _fsiGetAddressTree = PatternTrees.GetFsiGetAddress(); - private static IPatternTreeNode[] _fsiGetAddressV2Tree = PatternTrees.GetFsiGetAddressV2(); - private static IPatternTreeNode[] _fsiIsLastWarpThreadPatternTree = PatternTrees.GetFsiIsLastWarpThread(); - private static IPatternTreeNode[] _fsiBeginPatternTree = PatternTrees.GetFsiBeginPattern(); - private static IPatternTreeNode[] _fsiEndPatternTree = PatternTrees.GetFsiEndPattern(); + private static readonly IPatternTreeNode[] _fsiGetAddressTree = PatternTrees.GetFsiGetAddress(); + private static readonly IPatternTreeNode[] _fsiGetAddressV2Tree = PatternTrees.GetFsiGetAddressV2(); + private static readonly IPatternTreeNode[] _fsiIsLastWarpThreadPatternTree = PatternTrees.GetFsiIsLastWarpThread(); + private static readonly IPatternTreeNode[] _fsiBeginPatternTree = PatternTrees.GetFsiBeginPattern(); + private static readonly IPatternTreeNode[] _fsiEndPatternTree = PatternTrees.GetFsiEndPattern(); public static void RunPass(DecodedProgram program) { @@ -113,7 +113,7 @@ namespace Ryujinx.Graphics.Shader.Translation private enum TreeNodeType : byte { Op, - Label + Label, } private class TreeNode @@ -150,9 +150,9 @@ namespace Ryujinx.Graphics.Shader.Translation private static TreeNode[] BuildTree(Block[] blocks) { - List nodes = new List(); + List nodes = new(); - Dictionary labels = new Dictionary(); + Dictionary labels = new(); TreeNodeUse[] predDefs = new TreeNodeUse[RegisterConsts.PredsCount]; TreeNodeUse[] gprDefs = new TreeNodeUse[RegisterConsts.GprsCount]; @@ -223,7 +223,7 @@ namespace Ryujinx.Graphics.Shader.Translation if (block.Predecessors.Count > 1) { - TreeNode label = new TreeNode(order++); + TreeNode label = new(order++); nodes.Add(label); labels.Add(block.Address, label); } @@ -232,7 +232,7 @@ namespace Ryujinx.Graphics.Shader.Translation { InstOp op = block.OpCodes[opIndex]; - TreeNode node = new TreeNode(op, IsOrderDependant(op.Name) ? order : (byte)0); + TreeNode node = new(op, IsOrderDependant(op.Name) ? order : (byte)0); // Add uses. @@ -288,7 +288,7 @@ namespace Ryujinx.Graphics.Shader.Translation InstProps.SPd => 30, InstProps.TPd => 51, InstProps.VPd => 45, - _ => throw new InvalidOperationException($"Table has unknown predicate destination {pdType}.") + _ => throw new InvalidOperationException($"Table has unknown predicate destination {pdType}."), }; byte predIndex = (byte)((op.RawOpCode >> bit) & 7); @@ -350,7 +350,7 @@ namespace Ryujinx.Graphics.Shader.Translation public IPatternTreeNode Node { get; } public int Index { get; } public bool Inverted { get; } - public PatternTreeNodeUse Inv => new PatternTreeNodeUse(Index, !Inverted, Node); + public PatternTreeNodeUse Inv => new(Index, !Inverted, Node); private PatternTreeNodeUse(int index, bool inverted, IPatternTreeNode node) { @@ -373,7 +373,7 @@ namespace Ryujinx.Graphics.Shader.Translation public TreeNodeType Type { get; } public byte Order { get; } public bool IsImm { get; } - public PatternTreeNodeUse Out => new PatternTreeNodeUse(0, this); + public PatternTreeNodeUse Out => new(0, this); public PatternTreeNode(InstName name, Func match, TreeNodeType type = TreeNodeType.Op, byte order = 0, bool isImm = false) { @@ -435,7 +435,7 @@ namespace Ryujinx.Graphics.Shader.Translation } DecodedFunction callTarget = program.GetFunctionByAddress(callOp.GetAbsoluteAddress()); - TreeNode[] callTargetTree = null; + TreeNode[] callTargetTree; if (callTarget == null || !Matches(_fsiIsLastWarpThreadPatternTree, callTargetTree = BuildTree(callTarget.Blocks))) { @@ -548,7 +548,7 @@ namespace Ryujinx.Graphics.Shader.Translation .Use(PT) .Use(orderingTicketValue).Out), Iadd(x: true, 0, 405).Use(PT).Use(RZ), - Ret().Use(PT) + Ret().Use(PT), }; } @@ -576,7 +576,7 @@ namespace Ryujinx.Graphics.Shader.Translation .Use(PT) .Use(orderingTicketValue).Out).Out), Iadd(x: true, 0, 405).Use(PT).Use(RZ), - Ret().Use(PT) + Ret().Use(PT), }; } @@ -603,7 +603,7 @@ namespace Ryujinx.Graphics.Shader.Translation .Use(threadKillValue).OutAt(1)) .Use(RZ).Out).OutAt(1)).Out) .Use(laneIdValue), - Ret().Use(PT) + Ret().Use(PT), }; } @@ -638,7 +638,7 @@ namespace Ryujinx.Graphics.Shader.Translation .Use(PT) .Use(addressLowValue).Out).Inv) .Use(label.Out), - Ret().Use(PT) + Ret().Use(PT), }; } @@ -684,7 +684,7 @@ namespace Ryujinx.Graphics.Shader.Translation .Use(incrementValue) .Use(popcResult) .Use(RZ).Out).Out), - Ret().Use(PT) + Ret().Use(PT), }; } @@ -806,7 +806,6 @@ namespace Ryujinx.Graphics.Shader.Translation private static PatternTreeNodeUse PT => PTOrRZ(); private static PatternTreeNodeUse RZ => PTOrRZ(); - private static PatternTreeNodeUse Undef => new PatternTreeNodeUse(0, null); private static PatternTreeNodeUse CallArg(int index) { diff --git a/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionManager.cs b/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionManager.cs index 51a396821..2addff5c0 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionManager.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionManager.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using System; using System.Collections.Generic; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation @@ -65,13 +64,13 @@ namespace Ryujinx.Graphics.Shader.Translation HelperFunctionName.ConvertFloatToDouble => GenerateConvertFloatToDoubleFunction(), HelperFunctionName.TexelFetchScale => GenerateTexelFetchScaleFunction(), HelperFunctionName.TextureSizeUnscale => GenerateTextureSizeUnscaleFunction(), - _ => throw new ArgumentException($"Invalid function name {functionName}") + _ => throw new ArgumentException($"Invalid function name {functionName}"), }; } - private Function GenerateConvertDoubleToFloatFunction() + private static Function GenerateConvertDoubleToFloatFunction() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand valueLow = Argument(0); Operand valueHigh = Argument(1); @@ -119,9 +118,9 @@ namespace Ryujinx.Graphics.Shader.Translation return new Function(ControlFlowGraph.Create(context.GetOperations()).Blocks, "ConvertDoubleToFloat", true, 2, 0); } - private Function GenerateConvertFloatToDoubleFunction() + private static Function GenerateConvertFloatToDoubleFunction() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand value = Argument(0); @@ -164,13 +163,13 @@ namespace Ryujinx.Graphics.Shader.Translation HelperFunctionName.SharedAtomicMinS32 => GenerateSharedAtomicSigned(id, isMin: true), HelperFunctionName.SharedStore8 => GenerateSharedStore8(id), HelperFunctionName.SharedStore16 => GenerateSharedStore16(id), - _ => throw new ArgumentException($"Invalid function name {functionName}") + _ => throw new ArgumentException($"Invalid function name {functionName}"), }; } private static Function GenerateSharedAtomicSigned(int id, bool isMin) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand wordOffset = Argument(0); Operand value = Argument(1); @@ -199,7 +198,7 @@ namespace Ryujinx.Graphics.Shader.Translation private static Function GenerateSharedStore(int id, int bitSize) { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand offset = Argument(0); Operand value = Argument(1); @@ -219,7 +218,7 @@ namespace Ryujinx.Graphics.Shader.Translation private Function GenerateTexelFetchScaleFunction() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand input = Argument(0); Operand samplerIndex = Argument(1); @@ -270,7 +269,7 @@ namespace Ryujinx.Graphics.Shader.Translation private Function GenerateTextureSizeUnscaleFunction() { - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand input = Argument(0); Operand samplerIndex = Argument(1); @@ -328,4 +327,4 @@ namespace Ryujinx.Graphics.Shader.Translation } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionName.cs b/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionName.cs index 984f2d047..e5af17355 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionName.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/HelperFunctionName.cs @@ -9,6 +9,6 @@ namespace Ryujinx.Graphics.Shader.Translation SharedStore8, SharedStore16, TexelFetchScale, - TextureSizeUnscale + TextureSizeUnscale, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessElimination.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessElimination.cs index 0c196c4d0..bb25c1602 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessElimination.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessElimination.cs @@ -16,7 +16,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // - Both sources of the OR operation comes from a constant buffer. for (LinkedListNode node = block.Operations.First; node != null; node = node.Next) { - if (!(node.Value is TextureOperation texOp)) + if (node.Value is not TextureOperation texOp) { continue; } @@ -47,7 +47,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations continue; } - if (!(bindlessHandle.AsgOp is Operation handleCombineOp)) + if (bindlessHandle.AsgOp is not Operation handleCombineOp) { continue; } @@ -66,9 +66,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // and having a "canonical" representation simplifies some checks below. if (src0.Type == OperandType.Constant && src1.Type != OperandType.Constant) { - Operand temp = src1; - src1 = src0; - src0 = temp; + (src0, src1) = (src1, src0); } TextureHandleType handleType = TextureHandleType.SeparateSamplerHandle; diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessToIndexed.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessToIndexed.cs index 9a3ae1b8f..f966a4fc5 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessToIndexed.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessToIndexed.cs @@ -17,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // The base offset of the array of handles on the constant buffer is the constant offset. for (LinkedListNode node = block.Operations.First; node != null; node = node.Next) { - if (!(node.Value is TextureOperation texOp)) + if (node.Value is not TextureOperation texOp) { continue; } @@ -27,7 +27,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations continue; } - if (!(texOp.GetSource(0).AsgOp is Operation handleAsgOp)) + if (texOp.GetSource(0).AsgOp is not Operation handleAsgOp) { continue; } @@ -64,17 +64,17 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // Plus this whole transform is fundamentally flawed as-is since we have no way to know the array size. // Eventually, this should be entirely removed in favor of a implementation that supports true bindless // texture access. - if (!(ldcSrc2.AsgOp is Operation shrOp) || shrOp.Inst != Instruction.ShiftRightU32) + if (ldcSrc2.AsgOp is not Operation shrOp || shrOp.Inst != Instruction.ShiftRightU32) { continue; } - if (!(shrOp.GetSource(0).AsgOp is Operation shrOp2) || shrOp2.Inst != Instruction.ShiftRightU32) + if (shrOp.GetSource(0).AsgOp is not Operation shrOp2 || shrOp2.Inst != Instruction.ShiftRightU32) { continue; } - if (!(shrOp2.GetSource(0).AsgOp is Operation addOp) || addOp.Inst != Instruction.Add) + if (shrOp2.GetSource(0).AsgOp is not Operation addOp || addOp.Inst != Instruction.Add) { continue; } @@ -92,7 +92,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations Operand source = addOp.GetSource(0); - Operation shrBy3 = new Operation(Instruction.ShiftRightU32, index, source, Const(3)); + Operation shrBy3 = new(Instruction.ShiftRightU32, index, source, Const(3)); block.Operations.AddBefore(node, shrBy3); @@ -106,4 +106,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations config.SetUsedTexture(texOp.Inst, texOp.Type, texOp.Format, texOp.Flags, texOp.CbufSlot, handle); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BranchElimination.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BranchElimination.cs index c87d14748..bd2eceda5 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BranchElimination.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/BranchElimination.cs @@ -31,7 +31,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations return false; } - if (!(nextBlock.Operations.First?.Value is Operation next)) + if (nextBlock.Operations.First?.Value is not Operation next) { return false; } @@ -61,4 +61,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations return block; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/ConstantFolding.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/ConstantFolding.cs index 4caadb737..0cca0ac6c 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/ConstantFolding.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/ConstantFolding.cs @@ -1,7 +1,6 @@ using Ryujinx.Common.Utilities; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using System; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation.Optimizations @@ -262,8 +261,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations private static int GetBitfieldExtractValue(Operation operation) { - int value = operation.GetSource(0).Value; - int lsb = operation.GetSource(1).Value; + int value = operation.GetSource(0).Value; + int lsb = operation.GetSource(1).Value; int length = operation.GetSource(2).Value; return value.Extract(lsb, length); @@ -278,13 +277,6 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations operation.TurnIntoCopy(ConstF((float)BitConverter.UInt16BitsToHalf((ushort)value))); } - private static void FPNegate(Operation operation) - { - float value = operation.GetSource(0).AsFloat(); - - operation.TurnIntoCopy(ConstF(-value)); - } - private static void EvaluateUnary(Operation operation, Func op) { int x = operation.GetSource(0).Value; @@ -356,4 +348,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations operation.TurnIntoCopy(ConstF(op(x, y, z))); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/DoubleToFloat.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/DoubleToFloat.cs index 42bce5cc2..aec95a9cc 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/DoubleToFloat.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/DoubleToFloat.cs @@ -11,7 +11,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations { for (LinkedListNode node = block.Operations.First; node != null; node = node.Next) { - if (node.Value is not Operation operation) + if (node.Value is not Operation) { continue; } @@ -67,4 +67,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/GlobalToStorage.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/GlobalToStorage.cs index 9d260c678..2433aeb20 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/GlobalToStorage.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/GlobalToStorage.cs @@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation; using System; using System.Collections.Generic; using System.Linq; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation.Optimizations @@ -14,12 +13,12 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations enum LsMemoryType { Local, - Shared + Shared, } private class GtsContext { - private struct Entry + private readonly struct Entry { public readonly int FunctionId; public readonly Instruction Inst; @@ -42,7 +41,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations } } - private struct LsKey : IEquatable + private readonly struct LsKey : IEquatable { public readonly Operand BaseOffset; public readonly int ConstOffset; @@ -127,7 +126,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations public void AddMemoryTargetCb(LsMemoryType type, Operand baseOffset, int constOffset, uint targetCb, SearchResult result) { - LsKey key = new LsKey(baseOffset, constOffset, type); + LsKey key = new(baseOffset, constOffset, type); if (!_sharedEntries.TryGetValue(key, out Dictionary targetCbs)) { @@ -162,7 +161,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations public bool TryGetMemoryTargetCb(LsMemoryType type, Operand baseOffset, int constOffset, out SearchResult result) { - LsKey key = new LsKey(baseOffset, constOffset, type); + LsKey key = new(baseOffset, constOffset, type); if (_sharedEntries.TryGetValue(key, out Dictionary targetCbs) && targetCbs.Count == 1) { @@ -182,9 +181,9 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations } } - private struct SearchResult + private readonly struct SearchResult { - public static SearchResult NotFound => new SearchResult(-1, 0); + public static SearchResult NotFound => new(-1, 0); public bool Found => SbCbSlot != -1; public int SbCbSlot { get; } public int SbCbOffset { get; } @@ -208,13 +207,13 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations public static void RunPass(HelperFunctionManager hfm, BasicBlock[] blocks, ShaderConfig config) { - GtsContext gtsContext = new GtsContext(hfm); + GtsContext gtsContext = new(hfm); foreach (BasicBlock block in blocks) { for (LinkedListNode node = block.Operations.First; node != null; node = node.Next) { - if (!(node.Value is Operation operation)) + if (node.Value is not Operation operation) { continue; } @@ -315,8 +314,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations int alignment = config.GpuAccessor.QueryHostStorageBufferOffsetAlignment(); - Operation maskOp = new Operation(Instruction.BitwiseAnd, baseAddressMasked, new[] { baseAddress, Const(-alignment) }); - Operation subOp = new Operation(Instruction.Subtract, hostOffset, new[] { globalAddress, baseAddressMasked }); + Operation maskOp = new(Instruction.BitwiseAnd, baseAddressMasked, baseAddress, Const(-alignment)); + Operation subOp = new(Instruction.Subtract, hostOffset, globalAddress, baseAddressMasked); node.List.AddBefore(node, maskOp); node.List.AddBefore(node, subOp); @@ -327,7 +326,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations { Operand newOffset = Local(); - Operation addOp = new Operation(Instruction.Add, newOffset, new[] { offset, Const(result.ConstOffset) }); + Operation addOp = new(Instruction.Add, newOffset, offset, Const(result.ConstOffset)); node.List.AddBefore(node, addOp); @@ -394,26 +393,26 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations if (operation.Inst == Instruction.AtomicCompareAndSwap) { - sources = new Operand[] + sources = new[] { Const(binding), Const(0), wordOffset, operation.GetSource(operation.SourcesCount - 2), - operation.GetSource(operation.SourcesCount - 1) + operation.GetSource(operation.SourcesCount - 1), }; } else if (isStore) { - sources = new Operand[] { Const(binding), Const(0), wordOffset, operation.GetSource(operation.SourcesCount - 1) }; + sources = new[] { Const(binding), Const(0), wordOffset, operation.GetSource(operation.SourcesCount - 1) }; } else { - sources = new Operand[] { Const(binding), Const(0), wordOffset }; + sources = new[] { Const(binding), Const(0), wordOffset }; } - Operation shiftOp = new Operation(Instruction.ShiftRightU32, wordOffset, new[] { offset, Const(2) }); - Operation storageOp = new Operation(operation.Inst, StorageKind.StorageBuffer, operation.Dest, sources); + Operation shiftOp = new(Instruction.ShiftRightU32, wordOffset, offset, Const(2)); + Operation storageOp = new(operation.Inst, StorageKind.StorageBuffer, operation.Dest, sources); node.List.AddBefore(node, shiftOp); LinkedListNode newNode = node.List.AddBefore(node, storageOp); @@ -455,7 +454,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations bool returnsValue = operation.Dest != null; Operand returnValue = returnsValue ? Local() : null; - Operation callOp = new Operation(Instruction.Call, returnValue, sources); + Operation callOp = new(Instruction.Call, returnValue, sources); LinkedListNode newNode = node.List.AddBefore(node, callOp); @@ -480,7 +479,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations SearchResult result, out int functionId) { - List targetCbs = new List() { PackCbSlotAndOffset(result.SbCbSlot, result.SbCbOffset) }; + List targetCbs = new() { PackCbSlotAndOffset(result.SbCbSlot, result.SbCbOffset) }; if (gtsContext.TryGetFunctionId(operation, isMultiTarget: false, targetCbs, out functionId)) { @@ -498,7 +497,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations inArgumentsCount = 2; } - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand offset = Argument(0); Operand compare = null; @@ -542,7 +541,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations string functionName = GetFunctionName(operation, isMultiTarget: false, targetCbs); - Function function = new Function( + Function function = new( ControlFlowGraph.Create(context.GetOperations()).Blocks, functionName, returnsValue, @@ -561,9 +560,9 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations Operation operation, out int functionId) { - Queue phis = new Queue(); - HashSet visited = new HashSet(); - List targetCbs = new List(); + Queue phis = new(); + HashSet visited = new(); + List targetCbs = new(); Operand globalAddress = operation.GetSource(0); @@ -644,7 +643,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations inArgumentsCount = 3; } - EmitterContext context = new EmitterContext(); + EmitterContext context = new(); Operand globalAddressLow = Argument(0); Operand globalAddressHigh = Argument(1); @@ -684,7 +683,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations value = Argument(2); } - SearchResult result = new SearchResult(sbCbSlot, sbCbOffset); + SearchResult result = new(sbCbSlot, sbCbOffset); int alignment = config.GpuAccessor.QueryHostStorageBufferOffsetAlignment(); @@ -731,7 +730,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations string functionName = GetFunctionName(operation, isMultiTarget: true, targetCbs); - Function function = new Function( + Function function = new( ControlFlowGraph.Create(context.GetOperations()).Blocks, functionName, returnsValue, @@ -763,7 +762,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations StorageKind.GlobalMemoryS16 => "S16", StorageKind.GlobalMemoryU8 => "U8", StorageKind.GlobalMemoryU16 => "U16", - _ => string.Empty + _ => string.Empty, }; if (isMultiTarget) @@ -871,7 +870,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations StorageKind.GlobalMemoryU8 => 8, StorageKind.GlobalMemoryS16 or StorageKind.GlobalMemoryU16 => 16, - _ => 32 + _ => 32, }; if (bitSize < 32) @@ -1137,4 +1136,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Optimizer.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Optimizer.cs index 8d2669c0d..e7805027f 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Optimizer.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Optimizer.cs @@ -60,7 +60,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations bool isUnused = IsUnused(node.Value); - if (!(node.Value is Operation operation) || isUnused) + if (node.Value is not Operation operation || isUnused) { if (node.Value is PhiNode phi && !isUnused) { @@ -93,7 +93,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations modified = true; } else if ((operation.Inst == Instruction.PackHalf2x16 && PropagatePack(operation)) || - (operation.Inst == Instruction.ShuffleXor && MatchDdxOrDdy(operation))) + (operation.Inst == Instruction.ShuffleXor && MatchDdxOrDdy(operation))) { if (DestHasNoUses(operation)) { @@ -124,7 +124,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // the destination operand. Operand dest = copyOp.Dest; - Operand src = copyOp.GetSource(0); + Operand src = copyOp.GetSource(0); INode[] uses = dest.UseOps.ToArray(); @@ -199,7 +199,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations foreach (INode useNode in uses) { - if (!(useNode is Operation operation) || operation.Inst != Instruction.UnpackHalf2x16) + if (useNode is not Operation operation || operation.Inst != Instruction.UnpackHalf2x16) { continue; } @@ -248,12 +248,12 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations foreach (INode use in uses) { - if (!(use is Operation test)) + if (use is not Operation test) { continue; } - if (!(use is Operation useOp) || useOp.Inst != Instruction.SwizzleAdd) + if (use is not Operation useOp || useOp.Inst != Instruction.SwizzleAdd) { continue; } @@ -323,7 +323,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations Operand rhs = operation.GetSource(1); // Check LHS of the the main multiplication operation. We expect an input being multiplied by gl_FragCoord.w. - if (!(lhs.AsgOp is Operation attrMulOp) || attrMulOp.Inst != (Instruction.FP32 | Instruction.Multiply)) + if (lhs.AsgOp is not Operation attrMulOp || attrMulOp.Inst != (Instruction.FP32 | Instruction.Multiply)) { return; } @@ -338,7 +338,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations } // RHS of the main multiplication should be a reciprocal operation (1.0 / x). - if (!(rhs.AsgOp is Operation reciprocalOp) || reciprocalOp.Inst != (Instruction.FP32 | Instruction.Divide)) + if (rhs.AsgOp is not Operation reciprocalOp || reciprocalOp.Inst != (Instruction.FP32 | Instruction.Divide)) { return; } @@ -368,7 +368,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations // from all the use lists on the operands that this node uses. block.Operations.Remove(llNode); - Queue nodes = new Queue(); + Queue nodes = new(); nodes.Enqueue(llNode.Value); @@ -457,4 +457,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations return true; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Simplification.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Simplification.cs index 9b78c8aaa..a509fcb42 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Simplification.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Simplification.cs @@ -202,4 +202,4 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations return operand.Value == comparand; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Utils.cs b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Utils.cs index ffbd16f85..baf8e66e7 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Utils.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Optimizations/Utils.cs @@ -14,7 +14,7 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations public static bool IsInputLoad(INode node, IoVariable ioVariable, int elemIndex) { - if (!(node is Operation operation) || + if (node is not Operation operation || operation.Inst != Instruction.Load || operation.StorageKind != StorageKind.Input || operation.SourcesCount != 2) diff --git a/src/Ryujinx.Graphics.Shader/Translation/RegisterUsage.cs b/src/Ryujinx.Graphics.Shader/Translation/RegisterUsage.cs index 9e31831de..e27e47070 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/RegisterUsage.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/RegisterUsage.cs @@ -10,7 +10,7 @@ namespace Ryujinx.Graphics.Shader.Translation static class RegisterUsage { private const int RegsCount = 256; - private const int RegsMask = RegsCount - 1; + private const int RegsMask = RegsCount - 1; private const int GprMasks = 4; private const int PredMasks = 1; @@ -36,7 +36,7 @@ namespace Ryujinx.Graphics.Shader.Translation FlagMask = flagMask; } - public long GetMask(int index) + public readonly long GetMask(int index) { return index switch { @@ -46,7 +46,7 @@ namespace Ryujinx.Graphics.Shader.Translation 3 => GprMask3, 4 => PredMask, 5 => FlagMask, - _ => throw new ArgumentOutOfRangeException(nameof(index)) + _ => throw new ArgumentOutOfRangeException(nameof(index)), }; } @@ -93,12 +93,12 @@ namespace Ryujinx.Graphics.Shader.Translation return !x.Equals(y); } - public override bool Equals(object obj) + public readonly override bool Equals(object obj) { return obj is RegisterMask regMask && Equals(regMask); } - public bool Equals(RegisterMask other) + public readonly bool Equals(RegisterMask other) { return GprMask0 == other.GprMask0 && GprMask1 == other.GprMask1 && @@ -108,7 +108,7 @@ namespace Ryujinx.Graphics.Shader.Translation FlagMask == other.FlagMask; } - public override int GetHashCode() + public readonly override int GetHashCode() { return HashCode.Combine(GprMask0, GprMask1, GprMask2, GprMask3, PredMask, FlagMask); } @@ -121,18 +121,18 @@ namespace Ryujinx.Graphics.Shader.Translation public FunctionRegisterUsage(Register[] inArguments, Register[] outArguments) { - InArguments = inArguments; + InArguments = inArguments; OutArguments = outArguments; } } public static FunctionRegisterUsage RunPass(ControlFlowGraph cfg) { - List inArguments = new List(); - List outArguments = new List(); + List inArguments = new(); + List outArguments = new(); // Compute local register inputs and outputs used inside blocks. - RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Length]; + RegisterMask[] localInputs = new RegisterMask[cfg.Blocks.Length]; RegisterMask[] localOutputs = new RegisterMask[cfg.Blocks.Length]; foreach (BasicBlock block in cfg.Blocks) @@ -165,11 +165,11 @@ namespace Ryujinx.Graphics.Shader.Translation // Compute global register inputs and outputs used across blocks. RegisterMask[] globalCmnOutputs = new RegisterMask[cfg.Blocks.Length]; - RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Length]; + RegisterMask[] globalInputs = new RegisterMask[cfg.Blocks.Length]; RegisterMask[] globalOutputs = new RegisterMask[cfg.Blocks.Length]; - RegisterMask allOutputs = new RegisterMask(); - RegisterMask allCmnOutputs = new RegisterMask(-1L, -1L, -1L, -1L, -1L, -1L); + RegisterMask allOutputs = new(); + RegisterMask allCmnOutputs = new(-1L, -1L, -1L, -1L, -1L, -1L); bool modified; @@ -389,14 +389,14 @@ namespace Ryujinx.Graphics.Shader.Translation mask &= ~(1L << bit); - Register register = new Register(baseRegIndex + bit, regType); + Register register = new(baseRegIndex + bit, regType); if (fillArgsList) { inArguments.Add(register); } - Operation copyOp = new Operation(Instruction.Copy, OperandHelper.Register(register), OperandHelper.Argument(argIndex++)); + Operation copyOp = new(Instruction.Copy, OperandHelper.Register(register), OperandHelper.Argument(argIndex++)); if (node == null) { @@ -429,14 +429,14 @@ namespace Ryujinx.Graphics.Shader.Translation mask &= ~(1L << bit); - Register register = new Register(baseRegIndex + bit, regType); + Register register = new(baseRegIndex + bit, regType); if (fillArgsList) { outArguments.Add(register); } - Operation copyOp = new Operation(Instruction.Copy, OperandHelper.Argument(argIndex++), OperandHelper.Register(register)); + Operation copyOp = new(Instruction.Copy, OperandHelper.Argument(argIndex++), OperandHelper.Register(register)); if (node == null) { @@ -475,7 +475,7 @@ namespace Ryujinx.Graphics.Shader.Translation private static bool EndsWithReturn(BasicBlock block) { - if (!(block.GetLastOp() is Operation operation)) + if (block.GetLastOp() is not Operation operation) { return false; } @@ -483,4 +483,4 @@ namespace Ryujinx.Graphics.Shader.Translation return operation.Inst == Instruction.Return; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/ResourceManager.cs b/src/Ryujinx.Graphics.Shader/Translation/ResourceManager.cs index 3a46f6e4e..f3a5ba6c4 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/ResourceManager.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/ResourceManager.cs @@ -13,10 +13,9 @@ namespace Ryujinx.Graphics.Shader.Translation private const int DefaultLocalMemorySize = 128; private const int DefaultSharedMemorySize = 4096; - private static readonly string[] _stagePrefixes = new string[] { "cp", "vp", "tcp", "tep", "gp", "fp" }; + private static readonly string[] _stagePrefixes = { "cp", "vp", "tcp", "tep", "gp", "fp" }; private readonly IGpuAccessor _gpuAccessor; - private readonly ShaderProperties _properties; private readonly string _stagePrefix; private readonly int[] _cbSlotToBindingMap; @@ -31,12 +30,12 @@ namespace Ryujinx.Graphics.Shader.Translation public int LocalMemoryId { get; private set; } public int SharedMemoryId { get; private set; } - public ShaderProperties Properties => _properties; + public ShaderProperties Properties { get; } public ResourceManager(ShaderStage stage, IGpuAccessor gpuAccessor, ShaderProperties properties) { _gpuAccessor = gpuAccessor; - _properties = properties; + Properties = properties; _stagePrefix = GetShaderStagePrefix(stage); _cbSlotToBindingMap = new int[18]; @@ -83,7 +82,7 @@ namespace Ryujinx.Graphics.Shader.Translation size = DefaultSharedMemorySize; } - var smem = new MemoryDefinition("shared_memory", AggregateType.Array | AggregateType.U32, BitUtils.DivRoundUp(size, sizeof(uint))); + var smem = new MemoryDefinition("shared_memory", AggregateType.Array | AggregateType.U32, BitUtils.DivRoundUp(size, sizeof(uint))); SharedMemoryId = Properties.AddSharedMemory(smem); } @@ -211,7 +210,7 @@ namespace Ryujinx.Graphics.Shader.Translation (int sbCbSlot, int sbCbOffset) = UnpackSbCbInfo(key); descriptors[descriptorIndex++] = new BufferDescriptor(binding, slot, sbCbSlot, sbCbOffset) { - Flags = (_sbSlotWritten & (1u << slot)) != 0 ? BufferUsageFlags.Write : BufferUsageFlags.None + Flags = (_sbSlotWritten & (1u << slot)) != 0 ? BufferUsageFlags.Write : BufferUsageFlags.None, }; } } @@ -226,39 +225,34 @@ namespace Ryujinx.Graphics.Shader.Translation private void AddNewConstantBuffer(int binding, string name) { - StructureType type = new StructureType(new[] + StructureType type = new(new[] { - new StructureField(AggregateType.Array | AggregateType.Vector4 | AggregateType.FP32, "data", Constants.ConstantBufferSize / 16) + new StructureField(AggregateType.Array | AggregateType.Vector4 | AggregateType.FP32, "data", Constants.ConstantBufferSize / 16), }); - _properties.AddConstantBuffer(binding, new BufferDefinition(BufferLayout.Std140, 0, binding, name, type)); + Properties.AddConstantBuffer(binding, new BufferDefinition(BufferLayout.Std140, 0, binding, name, type)); } private void AddNewStorageBuffer(int binding, string name) { - StructureType type = new StructureType(new[] + StructureType type = new(new[] { - new StructureField(AggregateType.Array | AggregateType.U32, "data", 0) + new StructureField(AggregateType.Array | AggregateType.U32, "data", 0), }); - _properties.AddStorageBuffer(binding, new BufferDefinition(BufferLayout.Std430, 1, binding, name, type)); + Properties.AddStorageBuffer(binding, new BufferDefinition(BufferLayout.Std430, 1, binding, name, type)); } public static string GetShaderStagePrefix(ShaderStage stage) { uint index = (uint)stage; - if (index >= _stagePrefixes.Length) - { - return "invalid"; - } - - return _stagePrefixes[index]; + return index >= _stagePrefixes.Length ? "invalid" : _stagePrefixes[index]; } private static int PackSbCbInfo(int sbCbSlot, int sbCbOffset) { - return sbCbOffset | ((int)sbCbSlot << 16); + return sbCbOffset | (sbCbSlot << 16); } private static (int, int) UnpackSbCbInfo(int key) @@ -266,4 +260,4 @@ namespace Ryujinx.Graphics.Shader.Translation return ((byte)(key >> 16), (ushort)key); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Rewriter.cs b/src/Ryujinx.Graphics.Shader/Translation/Rewriter.cs index f5a524a0f..42e3ecee3 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Rewriter.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Rewriter.cs @@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation.Optimizations; using System.Collections.Generic; using System.Diagnostics; using System.Linq; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation @@ -134,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.Translation AggregateType.Vector2 => 2, AggregateType.Vector3 => 3, AggregateType.Vector4 => 4, - _ => 1 + _ => 1, }; if (elemCount == 1) @@ -154,9 +153,9 @@ namespace Ryujinx.Graphics.Shader.Translation inputs[srcIndex] = operation.GetSource(srcIndex); } - inputs[inputs.Length - 1] = Const(i); + inputs[^1] = Const(i); - Operation loadOp = new Operation(Instruction.Load, StorageKind.ConstantBuffer, value, inputs); + Operation loadOp = new(Instruction.Load, StorageKind.ConstantBuffer, value, inputs); node.List.AddBefore(node, loadOp); @@ -169,8 +168,8 @@ namespace Ryujinx.Graphics.Shader.Translation Operand isCurrentIndex = Local(); Operand selection = Local(); - Operation compareOp = new Operation(Instruction.CompareEqual, isCurrentIndex, new Operand[] { elemIndex, Const(i) }); - Operation selectOp = new Operation(Instruction.ConditionalSelect, selection, new Operand[] { isCurrentIndex, value, result }); + Operation compareOp = new(Instruction.CompareEqual, isCurrentIndex, new Operand[] { elemIndex, Const(i) }); + Operation selectOp = new(Instruction.ConditionalSelect, selection, new Operand[] { isCurrentIndex, value, result }); node.List.AddBefore(node, compareOp); node.List.AddBefore(node, selectOp); @@ -267,10 +266,8 @@ namespace Ryujinx.Graphics.Shader.Translation { TextureOperation texOp = (TextureOperation)node.Value; - bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; + bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; int coordsCount = texOp.Type.GetDimensions(); @@ -318,10 +315,7 @@ namespace Ryujinx.Graphics.Shader.Translation { TextureOperation texOp = (TextureOperation)node.Value; - bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; if (texOp.Inst == Instruction.TextureSize && @@ -383,8 +377,8 @@ namespace Ryujinx.Graphics.Shader.Translation TextureOperation texOp = (TextureOperation)node.Value; - bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; + bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; + bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; bool isCoordNormalized = isBindless || config.GpuAccessor.QueryTextureCoordNormalized(texOp.Handle, texOp.CbufSlot); @@ -393,7 +387,6 @@ namespace Ryujinx.Graphics.Shader.Translation return node; } - bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; int coordsCount = texOp.Type.GetDimensions(); @@ -453,7 +446,7 @@ namespace Ryujinx.Graphics.Shader.Translation TextureOperation texOp = (TextureOperation)node.Value; bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0; - bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; + bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; int gatherBiasPrecision = config.GpuAccessor.QueryHostGatherBiasPrecision(); @@ -462,10 +455,12 @@ namespace Ryujinx.Graphics.Shader.Translation return node; } +#pragma warning disable IDE0059 // Remove unnecessary value assignment bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; +#pragma warning restore IDE0059 int coordsCount = texOp.Type.GetDimensions(); int coordsIndex = isBindless || isIndexed ? 1 : 0; @@ -536,7 +531,7 @@ namespace Ryujinx.Graphics.Shader.Translation TextureOperation texOp = (TextureOperation)node.Value; - bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; + bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0; bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0; bool hasInvalidOffset = (hasOffset || hasOffsets) && !config.GpuAccessor.QueryHostSupportsNonConstantTextureOffset(); @@ -548,16 +543,16 @@ namespace Ryujinx.Graphics.Shader.Translation return node; } - bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; + bool isGather = (texOp.Flags & TextureFlags.Gather) != 0; bool hasDerivatives = (texOp.Flags & TextureFlags.Derivatives) != 0; - bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; - bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; - bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; + bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0; + bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0; + bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0; - bool isArray = (texOp.Type & SamplerType.Array) != 0; - bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; + bool isArray = (texOp.Type & SamplerType.Array) != 0; + bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0; bool isMultisample = (texOp.Type & SamplerType.Multisample) != 0; - bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; + bool isShadow = (texOp.Type & SamplerType.Shadow) != 0; int coordsCount = texOp.Type.GetDimensions(); @@ -647,12 +642,12 @@ namespace Ryujinx.Graphics.Shader.Translation if (hasLodBias) { - sources[dstIndex++] = texOp.GetSource(srcIndex++); + sources[dstIndex++] = texOp.GetSource(srcIndex++); } if (isGather && !isShadow) { - sources[dstIndex++] = texOp.GetSource(srcIndex++); + sources[dstIndex++] = texOp.GetSource(srcIndex++); } int coordsIndex = isBindless || isIndexed ? 1 : 0; @@ -712,7 +707,7 @@ namespace Ryujinx.Graphics.Shader.Translation newSources[coordsIndex + index] = coordPlusOffset; } - TextureOperation newTexOp = new TextureOperation( + TextureOperation newTexOp = new( Instruction.TextureSample, texOp.Type, texOp.Format, @@ -771,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.Translation } } - TextureOperation newTexOp = new TextureOperation( + TextureOperation newTexOp = new( Instruction.TextureSample, texOp.Type, texOp.Format, @@ -862,13 +857,13 @@ namespace Ryujinx.Graphics.Shader.Translation int maxPositive = format switch { - TextureFormat.R8Snorm => sbyte.MaxValue, - TextureFormat.R8G8Snorm => sbyte.MaxValue, - TextureFormat.R8G8B8A8Snorm => sbyte.MaxValue, - TextureFormat.R16Snorm => short.MaxValue, - TextureFormat.R16G16Snorm => short.MaxValue, + TextureFormat.R8Snorm => sbyte.MaxValue, + TextureFormat.R8G8Snorm => sbyte.MaxValue, + TextureFormat.R8G8B8A8Snorm => sbyte.MaxValue, + TextureFormat.R16Snorm => short.MaxValue, + TextureFormat.R16G16Snorm => short.MaxValue, TextureFormat.R16G16B16A16Snorm => short.MaxValue, - _ => 0 + _ => 0, }; // The value being 0 means that the format is not a SNORM format, @@ -886,8 +881,8 @@ namespace Ryujinx.Graphics.Shader.Translation INode[] uses = dest.UseOps.ToArray(); - Operation convOp = new Operation(Instruction.ConvertS32ToFP32, Local(), dest); - Operation normOp = new Operation(Instruction.FP32 | Instruction.Multiply, Local(), convOp.Dest, ConstF(1f / maxPositive)); + Operation convOp = new(Instruction.ConvertS32ToFP32, Local(), dest); + Operation normOp = new(Instruction.FP32 | Instruction.Multiply, Local(), convOp.Dest, ConstF(1f / maxPositive)); node = node.List.AddAfter(node, convOp); node = node.List.AddAfter(node, normOp); @@ -990,4 +985,4 @@ namespace Ryujinx.Graphics.Shader.Translation return false; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/ShaderConfig.cs b/src/Ryujinx.Graphics.Shader/Translation/ShaderConfig.cs index e50c9a845..e93a709c2 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/ShaderConfig.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/ShaderConfig.cs @@ -126,9 +126,9 @@ namespace Ryujinx.Graphics.Shader.Translation public ShaderConfig(ShaderStage stage, IGpuAccessor gpuAccessor, TranslationOptions options, int localMemorySize) { - Stage = stage; - GpuAccessor = gpuAccessor; - Options = options; + Stage = stage; + GpuAccessor = gpuAccessor; + Options = options; LocalMemorySize = localMemorySize; _transformFeedbackDefinitions = new Dictionary(); @@ -138,35 +138,35 @@ namespace Ryujinx.Graphics.Shader.Translation gpuAccessor.QueryTransformFeedbackEnabled() && gpuAccessor.QueryHostSupportsTransformFeedback(); - UsedInputAttributesPerPatch = new HashSet(); + UsedInputAttributesPerPatch = new HashSet(); UsedOutputAttributesPerPatch = new HashSet(); _usedTextures = new Dictionary(); - _usedImages = new Dictionary(); + _usedImages = new Dictionary(); ResourceManager = new ResourceManager(stage, gpuAccessor, new ShaderProperties()); if (!gpuAccessor.QueryHostSupportsTransformFeedback() && gpuAccessor.QueryTransformFeedbackEnabled()) { - StructureType tfeInfoStruct = new StructureType(new StructureField[] + StructureType tfeInfoStruct = new(new StructureField[] { - new StructureField(AggregateType.Array | AggregateType.U32, "base_offset", 4), - new StructureField(AggregateType.U32, "vertex_count") + new(AggregateType.Array | AggregateType.U32, "base_offset", 4), + new(AggregateType.U32, "vertex_count"), }); - BufferDefinition tfeInfoBuffer = new BufferDefinition(BufferLayout.Std430, 1, Constants.TfeInfoBinding, "tfe_info", tfeInfoStruct); + BufferDefinition tfeInfoBuffer = new(BufferLayout.Std430, 1, Constants.TfeInfoBinding, "tfe_info", tfeInfoStruct); Properties.AddStorageBuffer(Constants.TfeInfoBinding, tfeInfoBuffer); - StructureType tfeDataStruct = new StructureType(new StructureField[] + StructureType tfeDataStruct = new(new StructureField[] { - new StructureField(AggregateType.Array | AggregateType.U32, "data", 0) + new(AggregateType.Array | AggregateType.U32, "data", 0), }); for (int i = 0; i < Constants.TfeBuffersCount; i++) { int binding = Constants.TfeBufferBaseBinding + i; - BufferDefinition tfeDataBuffer = new BufferDefinition(BufferLayout.Std430, 1, binding, $"tfe_data{i}", tfeDataStruct); + BufferDefinition tfeDataBuffer = new(BufferLayout.Std430, 1, binding, $"tfe_data{i}", tfeDataStruct); Properties.AddStorageBuffer(binding, tfeDataBuffer); } } @@ -180,8 +180,8 @@ namespace Ryujinx.Graphics.Shader.Translation TranslationOptions options) : this(stage, gpuAccessor, options, 0) { ThreadsPerInputPrimitive = 1; - OutputTopology = outputTopology; - MaxOutputVertices = maxOutputVertices; + OutputTopology = outputTopology; + MaxOutputVertices = maxOutputVertices; } public ShaderConfig( @@ -189,15 +189,15 @@ namespace Ryujinx.Graphics.Shader.Translation IGpuAccessor gpuAccessor, TranslationOptions options) : this(header.Stage, gpuAccessor, options, GetLocalMemorySize(header)) { - GpPassthrough = header.Stage == ShaderStage.Geometry && header.GpPassthrough; + GpPassthrough = header.Stage == ShaderStage.Geometry && header.GpPassthrough; ThreadsPerInputPrimitive = header.ThreadsPerInputPrimitive; - OutputTopology = header.OutputTopology; - MaxOutputVertices = header.MaxOutputVertexCount; - ImapTypes = header.ImapTypes; - OmapTargets = header.OmapTargets; - OmapSampleMask = header.OmapSampleMask; - OmapDepth = header.OmapDepth; - LastInVertexPipeline = header.Stage < ShaderStage.Fragment; + OutputTopology = header.OutputTopology; + MaxOutputVertices = header.MaxOutputVertexCount; + ImapTypes = header.ImapTypes; + OmapTargets = header.OmapTargets; + OmapSampleMask = header.OmapSampleMask; + OmapDepth = header.OmapDepth; + LastInVertexPipeline = header.Stage < ShaderStage.Fragment; } private static int GetLocalMemorySize(ShaderHeader header) @@ -524,7 +524,7 @@ namespace Ryujinx.Graphics.Shader.Translation // Regular and per-patch input/output locations can't overlap, // so we must assign on our location using unused regular input/output locations. - Dictionary locationsMap = new Dictionary(); + Dictionary locationsMap = new(); int freeMask = ~UsedOutputAttributes; @@ -718,7 +718,7 @@ namespace Ryujinx.Graphics.Shader.Translation { AccurateType = accurateType, Type = type, - UsageFlags = usageFlags + UsageFlags = usageFlags, }; if (dict.TryGetValue(info, out var existingMeta)) @@ -797,24 +797,6 @@ namespace Ryujinx.Graphics.Shader.Translation return default; } - private static int FindDescriptorIndex(TextureDescriptor[] array, AstTextureOperation texOp) - { - for (int i = 0; i < array.Length; i++) - { - var descriptor = array[i]; - - if (descriptor.Type == texOp.Type && - descriptor.CbufSlot == texOp.CbufSlot && - descriptor.HandleIndex == texOp.Handle && - descriptor.Format == texOp.Format) - { - return i; - } - } - - return -1; - } - private static int FindDescriptorIndex(TextureDescriptor[] array, TextureOperation texOp, bool ignoreType = false) { for (int i = 0; i < array.Length; i++) diff --git a/src/Ryujinx.Graphics.Shader/Translation/ShaderHeader.cs b/src/Ryujinx.Graphics.Shader/Translation/ShaderHeader.cs index 01f7f08ad..39f01b1ce 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/ShaderHeader.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/ShaderHeader.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Graphics.Shader.Translation Unused = 0, Constant = 1, Perspective = 2, - ScreenLinear = 3 + ScreenLinear = 3, } readonly struct ImapPixelType @@ -29,9 +29,19 @@ namespace Ryujinx.Graphics.Shader.Translation public PixelImap GetFirstUsedType() { - if (X != PixelImap.Unused) return X; - if (Y != PixelImap.Unused) return Y; - if (Z != PixelImap.Unused) return Z; + if (X != PixelImap.Unused) + { + return X; + } + if (Y != PixelImap.Unused) + { + return Y; + } + if (Z != PixelImap.Unused) + { + return Z; + } + return W; } } @@ -155,4 +165,4 @@ namespace Ryujinx.Graphics.Shader.Translation OmapDepth = type2Omap.Extract(1); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/ShaderIdentifier.cs b/src/Ryujinx.Graphics.Shader/Translation/ShaderIdentifier.cs index 684004379..e9c259942 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/ShaderIdentifier.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/ShaderIdentifier.cs @@ -43,7 +43,7 @@ namespace Ryujinx.Graphics.Shader.Translation foreach (INode node in block.Operations) { - if (!(node is Operation operation)) + if (node is not Operation operation) { continue; } @@ -84,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Translation } writesLayer = true; - layerInputAttr = srcAttributeAsgOp.GetSource(1).Value * 4 + srcAttributeAsgOp.GetSource(3).Value;; + layerInputAttr = srcAttributeAsgOp.GetSource(1).Value * 4 + srcAttributeAsgOp.GetSource(3).Value; } else { diff --git a/src/Ryujinx.Graphics.Shader/Translation/Ssa.cs b/src/Ryujinx.Graphics.Shader/Translation/Ssa.cs index 16b8b9240..89aaa3b44 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Ssa.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Ssa.cs @@ -1,7 +1,6 @@ using Ryujinx.Graphics.Shader.Decoders; using Ryujinx.Graphics.Shader.IntermediateRepresentation; using System.Collections.Generic; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; namespace Ryujinx.Graphics.Shader.Translation @@ -12,9 +11,9 @@ namespace Ryujinx.Graphics.Shader.Translation private class DefMap { - private Dictionary _map; + private readonly Dictionary _map; - private long[] _phiMasks; + private readonly long[] _phiMasks; public DefMap() { @@ -38,7 +37,7 @@ namespace Ryujinx.Graphics.Shader.Translation int key = GetKeyFromRegister(reg); int index = key / 64; - int bit = key & 63; + int bit = key & 63; long mask = 1L << bit; @@ -57,7 +56,7 @@ namespace Ryujinx.Graphics.Shader.Translation int key = GetKeyFromRegister(reg); int index = key / 64; - int bit = key & 63; + int bit = key & 63; return (_phiMasks[index] & (1L << bit)) != 0; } @@ -65,8 +64,8 @@ namespace Ryujinx.Graphics.Shader.Translation private class LocalDefMap { - private Operand[] _map; - private int[] _uses; + private readonly Operand[] _map; + private readonly int[] _uses; public int UseCount { get; private set; } public LocalDefMap() @@ -111,7 +110,7 @@ namespace Ryujinx.Graphics.Shader.Translation private readonly struct Definition { public BasicBlock Block { get; } - public Operand Local { get; } + public Operand Local { get; } public Definition(BasicBlock block, Operand local) { @@ -123,14 +122,14 @@ namespace Ryujinx.Graphics.Shader.Translation public static void Rename(BasicBlock[] blocks) { DefMap[] globalDefs = new DefMap[blocks.Length]; - LocalDefMap localDefs = new LocalDefMap(); + LocalDefMap localDefs = new(); for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++) { globalDefs[blkIndex] = new DefMap(); } - Queue dfPhiBlocks = new Queue(); + Queue dfPhiBlocks = new(); // First pass, get all defs and locals uses. for (int blkIndex = 0; blkIndex < blocks.Length; blkIndex++) @@ -303,7 +302,7 @@ namespace Ryujinx.Graphics.Shader.Translation // then use the definition from that Phi. Operand local = Local(); - PhiNode phi = new PhiNode(local); + PhiNode phi = new(local); AddPhi(block, phi); @@ -373,4 +372,4 @@ namespace Ryujinx.Graphics.Shader.Translation } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/TargetApi.cs b/src/Ryujinx.Graphics.Shader/Translation/TargetApi.cs index 6ac235a40..519600937 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/TargetApi.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/TargetApi.cs @@ -3,6 +3,6 @@ namespace Ryujinx.Graphics.Shader.Translation public enum TargetApi { OpenGL, - Vulkan + Vulkan, } } diff --git a/src/Ryujinx.Graphics.Shader/Translation/TargetLanguage.cs b/src/Ryujinx.Graphics.Shader/Translation/TargetLanguage.cs index 8314b223c..863c7447b 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/TargetLanguage.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/TargetLanguage.cs @@ -4,6 +4,6 @@ namespace Ryujinx.Graphics.Shader.Translation { Glsl, Spirv, - Arb + Arb, } } diff --git a/src/Ryujinx.Graphics.Shader/Translation/TranslationFlags.cs b/src/Ryujinx.Graphics.Shader/Translation/TranslationFlags.cs index 1874dec3b..df1e76a1f 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/TranslationFlags.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/TranslationFlags.cs @@ -7,8 +7,8 @@ namespace Ryujinx.Graphics.Shader.Translation { None = 0, - VertexA = 1 << 0, - Compute = 1 << 1, - DebugMode = 1 << 2 + VertexA = 1 << 0, + Compute = 1 << 1, + DebugMode = 1 << 2, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/Translator.cs b/src/Ryujinx.Graphics.Shader/Translation/Translator.cs index 255030a4b..010c80db1 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/Translator.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/Translator.cs @@ -45,14 +45,14 @@ namespace Ryujinx.Graphics.Shader.Translation } } - List funcs = new List(functions.Length); + List funcs = new(functions.Length); for (int i = 0; i < functions.Length; i++) { funcs.Add(null); } - HelperFunctionManager hfm = new HelperFunctionManager(funcs, config.Stage); + HelperFunctionManager hfm = new(funcs, config.Stage); for (int i = 0; i < functions.Length; i++) { @@ -65,7 +65,7 @@ namespace Ryujinx.Graphics.Shader.Translation { var fru = frus[i]; - inArgumentsCount = fru.InArguments.Length; + inArgumentsCount = fru.InArguments.Length; outArgumentsCount = fru.OutArguments.Length; } @@ -95,7 +95,7 @@ namespace Ryujinx.Graphics.Shader.Translation { TargetLanguage.Glsl => new ShaderProgram(info, TargetLanguage.Glsl, GlslGenerator.Generate(sInfo, config)), TargetLanguage.Spirv => new ShaderProgram(info, TargetLanguage.Spirv, SpirvGenerator.Generate(sInfo, config)), - _ => throw new NotImplementedException(config.Options.TargetLanguage.ToString()) + _ => throw new NotImplementedException(config.Options.TargetLanguage.ToString()), }; } @@ -149,7 +149,7 @@ namespace Ryujinx.Graphics.Shader.Translation for (int index = 0; index < functions.Length; index++) { - EmitterContext context = new EmitterContext(program, config, index != 0); + EmitterContext context = new(program, config, index != 0); if (initializeOutputs && index == 0) { @@ -306,7 +306,7 @@ namespace Ryujinx.Graphics.Shader.Translation context.Add(new CommentNode(dbgComment)); } - InstConditional opConditional = new InstConditional(op.RawOpCode); + InstConditional opConditional = new(op.RawOpCode); bool noPred = op.Props.HasFlag(InstProps.NoPred); if (!noPred && opConditional.Pred == RegisterConsts.PredicateTrueIndex && opConditional.PredInv) @@ -367,4 +367,4 @@ namespace Ryujinx.Graphics.Shader.Translation } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Shader/Translation/TranslatorContext.cs b/src/Ryujinx.Graphics.Shader/Translation/TranslatorContext.cs index 13c5e0e40..40a79c544 100644 --- a/src/Ryujinx.Graphics.Shader/Translation/TranslatorContext.cs +++ b/src/Ryujinx.Graphics.Shader/Translation/TranslatorContext.cs @@ -7,7 +7,6 @@ using System; using System.Collections.Generic; using System.Linq; using System.Numerics; - using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper; using static Ryujinx.Graphics.Shader.Translation.Translator; @@ -16,7 +15,7 @@ namespace Ryujinx.Graphics.Shader.Translation public class TranslatorContext { private readonly DecodedProgram _program; - private ShaderConfig _config; + private readonly ShaderConfig _config; public ulong Address { get; } @@ -59,7 +58,7 @@ namespace Ryujinx.Graphics.Shader.Translation // temporary variable, as long that attribute is written by shader A. FunctionCode[] output = new FunctionCode[a.Length + b.Length - 1]; - List ops = new List(a.Length + b.Length); + List ops = new(a.Length + b.Length); Operand[] temps = new Operand[AttributeConsts.UserAttributesCount * 4]; @@ -205,9 +204,9 @@ namespace Ryujinx.Graphics.Shader.Translation break; } - ShaderConfig config = new ShaderConfig(ShaderStage.Geometry, outputTopology, maxOutputVertices, GpuAccessor, _config.Options); + ShaderConfig config = new(ShaderStage.Geometry, outputTopology, maxOutputVertices, GpuAccessor, _config.Options); - EmitterContext context = new EmitterContext(default, config, false); + EmitterContext context = new(default, config, false); for (int v = 0; v < maxOutputVertices; v++) { @@ -263,7 +262,7 @@ namespace Ryujinx.Graphics.Shader.Translation { TargetLanguage.Glsl => new ShaderProgram(info, TargetLanguage.Glsl, GlslGenerator.Generate(sInfo, config)), TargetLanguage.Spirv => new ShaderProgram(info, TargetLanguage.Spirv, SpirvGenerator.Generate(sInfo, config)), - _ => throw new NotImplementedException(config.Options.TargetLanguage.ToString()) + _ => throw new NotImplementedException(config.Options.TargetLanguage.ToString()), }; } } From 6aa8d71588af4615019cd91b8a31f69dbfaa815d Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 09:26:39 +0200 Subject: [PATCH 15/19] [Ryujinx.Graphics.Nvdec.Vp9] Address dotnet-format issues (#5371) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Address or silence dotnet format IDE1006 warnings * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Fix empty lines before return Co-authored-by: Ac_K * Add trailing commas, remove redundant code and remove static modifier from Surface.HighBd * Fix naming rule violations * Fix naming rule violations * Fix empty line before return * Fix comment style Co-authored-by: Ac_K * Remove comment alignment * Address review feedback * Separate comments by 2 spaces and fix other formatting issues * Make HighBd an auto-property * Replace if-chain with if-else-chain * Fix new naming rule violations --------- Co-authored-by: Ac_K --- src/Ryujinx.Graphics.Nvdec.Vp9/CodecErr.cs | 2 +- .../Common/BitUtils.cs | 3 +- .../Common/MemoryAllocator.cs | 4 +- src/Ryujinx.Graphics.Nvdec.Vp9/Constants.cs | 14 +- src/Ryujinx.Graphics.Nvdec.Vp9/DecodeFrame.cs | 100 ++- src/Ryujinx.Graphics.Nvdec.Vp9/DecodeMv.cs | 138 ++-- src/Ryujinx.Graphics.Nvdec.Vp9/Decoder.cs | 34 +- src/Ryujinx.Graphics.Nvdec.Vp9/Detokenize.cs | 20 +- .../Dsp/Convolve.cs | 6 +- .../Dsp/IntraPred.cs | 16 +- src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/InvTxfm.cs | 186 +++-- src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Prob.cs | 10 +- src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Reader.cs | 27 +- src/Ryujinx.Graphics.Nvdec.Vp9/Idct.cs | 112 ++- src/Ryujinx.Graphics.Nvdec.Vp9/LoopFilter.cs | 272 +++---- src/Ryujinx.Graphics.Nvdec.Vp9/Luts.cs | 759 +++++++++--------- src/Ryujinx.Graphics.Nvdec.Vp9/PredCommon.cs | 62 +- src/Ryujinx.Graphics.Nvdec.Vp9/QuantCommon.cs | 45 +- src/Ryujinx.Graphics.Nvdec.Vp9/ReconInter.cs | 37 +- src/Ryujinx.Graphics.Nvdec.Vp9/ReconIntra.cs | 136 ++-- .../Types/BModeInfo.cs | 2 +- .../Types/BlockSize.cs | 2 +- .../Types/FrameType.cs | 2 +- .../Types/LoopFilterThresh.cs | 2 +- .../Types/MacroBlockD.cs | 19 +- .../Types/ModeInfo.cs | 12 +- .../Types/MotionVectorContext.cs | 2 +- src/Ryujinx.Graphics.Nvdec.Vp9/Types/Mv.cs | 22 +- .../Types/PartitionType.cs | 2 +- .../Types/PlaneType.cs | 2 +- .../Types/PredictionMode.cs | 22 +- .../Types/ReferenceMode.cs | 2 +- .../Types/ScaleFactors.cs | 246 +++--- .../Types/SegLvlFeatures.cs | 10 +- .../Types/Segmentation.cs | 18 +- .../Types/Surface.cs | 48 +- .../Types/TileInfo.cs | 3 +- .../Types/TxMode.cs | 10 +- .../Types/TxSize.cs | 6 +- .../Types/TxType.cs | 8 +- .../Types/Vp9Common.cs | 24 +- 41 files changed, 1240 insertions(+), 1207 deletions(-) diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/CodecErr.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/CodecErr.cs index b695fed5b..39a26f66f 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/CodecErr.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/CodecErr.cs @@ -51,6 +51,6 @@ /*!\brief An iterator reached the end of list. * */ - CodecListEnd + CodecListEnd, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Common/BitUtils.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Common/BitUtils.cs index 641188f8a..86981930e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Common/BitUtils.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Common/BitUtils.cs @@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Common { 10 => (ushort)Math.Clamp(val, 0, 1023), 12 => (ushort)Math.Clamp(val, 0, 4095), - _ => (ushort)Math.Clamp(val, 0, 255) + _ => (ushort)Math.Clamp(val, 0, 255), }; } @@ -46,6 +46,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Common private static int GetMsb(uint n) { Debug.Assert(n != 0); + return 31 ^ BitOperations.LeadingZeroCount(n); } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Common/MemoryAllocator.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Common/MemoryAllocator.cs index 473dd904a..c75cfeb0f 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Common/MemoryAllocator.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Common/MemoryAllocator.cs @@ -16,7 +16,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Common public bool InUse; } - private PoolItem[] _pool = new PoolItem[PoolEntries]; + private readonly PoolItem[] _pool = new PoolItem[PoolEntries]; public ArrayPtr Allocate(int length) where T : unmanaged { @@ -91,4 +91,4 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Common } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Constants.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Constants.cs index aaf1d7b98..0ce44b294 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Constants.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Constants.cs @@ -14,13 +14,13 @@ public const int MaxRefFrames = 4; public const int MiSizeLog2 = 3; - public const int MiBlockSizeLog2 = 6 - MiSizeLog2; // 64 = 2^6 + public const int MiBlockSizeLog2 = 6 - MiSizeLog2; // 64 = 2^6 - public const int MiSize = 1 << MiSizeLog2; // pixels per mi-unit - public const int MiBlockSize = 1 << MiBlockSizeLog2; // mi-units per max block + public const int MiSize = 1 << MiSizeLog2; // pixels per mi-unit + public const int MiBlockSize = 1 << MiBlockSizeLog2; // mi-units per max block public const int MiMask = MiBlockSize - 1; - public const int PartitionPloffset = 4; // number of probability models per block size + public const int PartitionPloffset = 4; // number of probability models per block size /* Segment Feature Masks */ public const int MaxMvRefCandidates = 2; @@ -48,9 +48,9 @@ public const int MvLow = -(1 << MvInUseBits); // Coefficient token alphabet - public const int ZeroToken = 0; // 0 Extra Bits 0+0 - public const int OneToken = 1; // 1 Extra Bits 0+1 - public const int TwoToken = 2; // 2 Extra Bits 0+1 + public const int ZeroToken = 0; // 0 Extra Bits 0+0 + public const int OneToken = 1; // 1 Extra Bits 0+1 + public const int TwoToken = 2; // 2 Extra Bits 0+1 public const int PivotNode = 2; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeFrame.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeFrame.cs index cdd645a38..6940d187f 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeFrame.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeFrame.cs @@ -9,7 +9,6 @@ using System.Diagnostics; using System.Runtime.CompilerServices; using System.Runtime.InteropServices; using System.Threading.Tasks; -using Mv = Ryujinx.Graphics.Nvdec.Vp9.Types.Mv; namespace Ryujinx.Graphics.Nvdec.Vp9 { @@ -48,7 +47,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 case TxSize.Tx32x32: Idct.HighbdIdct32x32Add(dqcoeff.AsSpan(), dst16, stride, eob, xd.Bd); break; - default: Debug.Assert(false, "Invalid transform size"); break; + default: + Debug.Assert(false, "Invalid transform size"); + break; } } } @@ -62,11 +63,21 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (txSize) { - case TxSize.Tx4x4: Idct.Idct4x4Add(dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx8x8: Idct.Idct8x8Add(dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx16x16: Idct.Idct16x16Add(dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx32x32: Idct.Idct32x32Add(dqcoeff.AsSpan(), dst, stride, eob); break; - default: Debug.Assert(false, "Invalid transform size"); return; + case TxSize.Tx4x4: + Idct.Idct4x4Add(dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx8x8: + Idct.Idct8x8Add(dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx16x16: + Idct.Idct16x16Add(dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx32x32: + Idct.Idct32x32Add(dqcoeff.AsSpan(), dst, stride, eob); + break; + default: + Debug.Assert(false, "Invalid transform size"); + return; } } } @@ -79,15 +90,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { if (txSize <= TxSize.Tx16x16 && eob <= 10) { - dqcoeff.AsSpan().Slice(0, 4 * (4 << (int)txSize)).Fill(0); + dqcoeff.AsSpan()[..(4 * (4 << (int)txSize))].Clear(); } else if (txSize == TxSize.Tx32x32 && eob <= 34) { - dqcoeff.AsSpan().Slice(0, 256).Fill(0); + dqcoeff.AsSpan()[..256].Clear(); } else { - dqcoeff.AsSpan().Slice(0, 16 << ((int)txSize << 1)).Fill(0); + dqcoeff.AsSpan()[..(16 << ((int)txSize << 1))].Clear(); } } } @@ -127,7 +138,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 case TxSize.Tx32x32: Idct.HighbdIdct32x32Add(dqcoeff.AsSpan(), dst16, stride, eob, xd.Bd); break; - default: Debug.Assert(false, "Invalid transform size"); break; + default: + Debug.Assert(false, "Invalid transform size"); + break; } } } @@ -141,11 +154,21 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (txSize) { - case TxSize.Tx4x4: Idct.Iht4x4Add(txType, dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx8x8: Idct.Iht8x8Add(txType, dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx16x16: Idct.Iht16x16Add(txType, dqcoeff.AsSpan(), dst, stride, eob); break; - case TxSize.Tx32x32: Idct.Idct32x32Add(dqcoeff.AsSpan(), dst, stride, eob); break; - default: Debug.Assert(false, "Invalid transform size"); return; + case TxSize.Tx4x4: + Idct.Iht4x4Add(txType, dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx8x8: + Idct.Iht8x8Add(txType, dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx16x16: + Idct.Iht16x16Add(txType, dqcoeff.AsSpan(), dst, stride, eob); + break; + case TxSize.Tx32x32: + Idct.Idct32x32Add(dqcoeff.AsSpan(), dst, stride, eob); + break; + default: + Debug.Assert(false, "Invalid transform size"); + return; } } } @@ -158,15 +181,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { if (txType == TxType.DctDct && txSize <= TxSize.Tx16x16 && eob <= 10) { - dqcoeff.AsSpan().Slice(0, 4 * (4 << (int)txSize)).Fill(0); + dqcoeff.AsSpan()[..(4 * (4 << (int)txSize))].Clear(); } else if (txSize == TxSize.Tx32x32 && eob <= 34) { - dqcoeff.AsSpan().Slice(0, 256).Fill(0); + dqcoeff.AsSpan()[..256].Clear(); } else { - dqcoeff.AsSpan().Slice(0, 16 << ((int)txSize << 1)).Fill(0); + dqcoeff.AsSpan()[..(16 << ((int)txSize << 1))].Clear(); } } } @@ -184,7 +207,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 PredictionMode mode = (plane == 0) ? mi.Mode : mi.UvMode; int dstOffset = 4 * row * pd.Dst.Stride + 4 * col; byte* dst = &pd.Dst.Buf.ToPointer()[dstOffset]; - Span dstSpan = pd.Dst.Buf.AsSpan().Slice(dstOffset); + Span dstSpan = pd.Dst.Buf.AsSpan()[dstOffset..]; if (mi.SbType < BlockSize.Block8x8) { @@ -223,7 +246,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 ref MacroBlockDPlane pd = ref xd.Plane[plane]; var sc = Luts.Vp9DefaultScanOrders[(int)txSize]; int eob = Detokenize.DecodeBlockTokens(ref twd, plane, sc, col, row, txSize, mi.SegmentId); - Span dst = pd.Dst.Buf.AsSpan().Slice(4 * row * pd.Dst.Stride + 4 * col); + Span dst = pd.Dst.Buf.AsSpan()[(4 * row * pd.Dst.Stride + 4 * col)..]; if (eob > 0) { @@ -589,9 +612,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 refr, xs, ys); + return; } } + if (xd.CurBuf.HighBd) { ReconInter.HighbdInterPredictor( @@ -793,6 +818,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 xd.SetMiRowCol(ref tile, miRow, bh, miCol, bw, cm.MiRows, cm.MiCols); ReconInter.SetupDstPlanes(ref xd.Plane, ref xd.CurBuf, miRow, miCol); + return ref xd.Mi[0].Value; } @@ -893,7 +919,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 if (!less8x8 && eobtotal == 0) { - mi.Skip = 1; // Skip loopfilter + mi.Skip = 1; // Skip loopfilter } } } @@ -928,8 +954,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Update the partition context at the end notes. Set partition bits // of block sizes larger than the current one to be one, and partition // bits of smaller block sizes to be zero. - aboveCtx.Slice(0, bw).Fill(Luts.PartitionContextLookup[(int)subsize].Above); - leftCtx.Slice(0, bw).Fill(Luts.PartitionContextLookup[(int)subsize].Left); + aboveCtx[..bw].Fill(Luts.PartitionContextLookup[(int)subsize].Above); + leftCtx[..bw].Fill(Luts.PartitionContextLookup[(int)subsize].Left); } private static PartitionType ReadPartition( @@ -1030,7 +1056,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 DecodePartition(ref twd, ref cm, miRow + hbs, miCol, subsize, n8x8L2); DecodePartition(ref twd, ref cm, miRow + hbs, miCol + hbs, subsize, n8x8L2); break; - default: Debug.Assert(false, "Invalid partition type"); break; + default: + Debug.Assert(false, "Invalid partition type"); + break; } } @@ -1134,7 +1162,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int alignedCols = TileInfo.MiColsAlignedToSb(cm.MiCols); int tileCols = 1 << cm.Log2TileCols; int tileRows = 1 << cm.Log2TileRows; - Array4> tileBuffers = new Array4>(); + Array4> tileBuffers = new(); int tileRow, tileCol; int miRow, miCol; @@ -1168,7 +1196,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 for (tileRow = 0; tileRow < tileRows; ++tileRow) { - TileInfo tile = new TileInfo(); + TileInfo tile = new(); tile.SetRow(ref cm, tileRow); for (miRow = tile.MiRowStart; miRow < tile.MiRowEnd; miRow += Constants.MiBlockSize) { @@ -1234,10 +1262,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } while (!tileData.Xd.Corrupted && ++n <= tileData.BufEnd); tileData.DataEnd = bitReaderEnd; + return !tileData.Xd.Corrupted; } - public static unsafe ArrayPtr DecodeTilesMt(ref Vp9Common cm, ArrayPtr data, int maxThreads) + public static ArrayPtr DecodeTilesMt(ref Vp9Common cm, ArrayPtr data, int maxThreads) { ArrayPtr bitReaderEnd = ArrayPtr.Null; @@ -1250,8 +1279,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Debug.Assert(tileCols <= (1 << 6)); Debug.Assert(tileRows == 1); - cm.AboveContext.AsSpan().Fill(0); - cm.AboveSegContext.AsSpan().Fill(0); + cm.AboveContext.AsSpan().Clear(); + cm.AboveSegContext.AsSpan().Clear(); for (n = 0; n < numWorkers; ++n) { @@ -1262,17 +1291,17 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 tileData.Counts = new Vp9BackwardUpdates(); } - Array64 tileBuffers = new Array64(); + Array64 tileBuffers = new(); GetTileBuffers(ref cm, data, tileCols, ref tileBuffers); - tileBuffers.AsSpan().Slice(0, tileCols).Sort(CompareTileBuffers); + tileBuffers.AsSpan()[..tileCols].Sort(CompareTileBuffers); if (numWorkers == tileCols) { TileBuffer largest = tileBuffers[0]; Span buffers = tileBuffers.AsSpan(); - buffers.Slice(1).CopyTo(buffers.Slice(0, tileBuffers.Length - 1)); + buffers[1..].CopyTo(buffers[..(tileBuffers.Length - 1)]); tileBuffers[tileCols - 1] = largest; } else @@ -1307,9 +1336,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 bufStart += count; } - Ptr cmPtr = new Ptr(ref cm); + Ptr cmPtr = new(ref cm); - Parallel.For(0, numWorkers, (n) => + Parallel.For(0, numWorkers, n => { ref TileWorkerData tileData = ref cmPtr.Value.TileWorkerData[n + totalTiles]; @@ -1335,6 +1364,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } Debug.Assert(!bitReaderEnd.IsNull || cm.Mb.Corrupted); + return bitReaderEnd; } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeMv.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeMv.cs index 3281905c1..8c25c700b 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeMv.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/DecodeMv.cs @@ -5,8 +5,6 @@ using Ryujinx.Graphics.Video; using System; using System.Diagnostics; using System.Runtime.CompilerServices; -using Mv = Ryujinx.Graphics.Nvdec.Vp9.Types.Mv; -using MvRef = Ryujinx.Graphics.Nvdec.Vp9.Types.MvRef; namespace Ryujinx.Graphics.Nvdec.Vp9 { @@ -61,10 +59,16 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (maxTxSize) { - case TxSize.Tx8x8: return fc.Tx8x8Prob[ctx].AsSpan(); - case TxSize.Tx16x16: return fc.Tx16x16Prob[ctx].AsSpan(); - case TxSize.Tx32x32: return fc.Tx32x32Prob[ctx].AsSpan(); - default: Debug.Assert(false, "Invalid maxTxSize."); return ReadOnlySpan.Empty; + case TxSize.Tx8x8: + return fc.Tx8x8Prob[ctx].AsSpan(); + case TxSize.Tx16x16: + return fc.Tx16x16Prob[ctx].AsSpan(); + case TxSize.Tx32x32: + return fc.Tx32x32Prob[ctx].AsSpan(); + default: + Debug.Assert(false, "Invalid maxTxSize."); + + return ReadOnlySpan.Empty; } } @@ -72,10 +76,16 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (maxTxSize) { - case TxSize.Tx8x8: return counts.Tx8x8[ctx].AsSpan(); - case TxSize.Tx16x16: return counts.Tx16x16[ctx].AsSpan(); - case TxSize.Tx32x32: return counts.Tx32x32[ctx].AsSpan(); - default: Debug.Assert(false, "Invalid maxTxSize."); return Span.Empty; + case TxSize.Tx8x8: + return counts.Tx8x8[ctx].AsSpan(); + case TxSize.Tx16x16: + return counts.Tx16x16[ctx].AsSpan(); + case TxSize.Tx32x32: + return counts.Tx32x32[ctx].AsSpan(); + default: + Debug.Assert(false, "Invalid maxTxSize."); + + return Span.Empty; } } @@ -110,10 +120,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { return ReadSelectedTxSize(ref cm, ref xd, maxTxSize, ref r); } - else - { - return (TxSize)Math.Min((int)maxTxSize, (int)Luts.TxModeToBiggestTxSize[(int)txMode]); - } + + return (TxSize)Math.Min((int)maxTxSize, (int)Luts.TxModeToBiggestTxSize[(int)txMode]); } private static int DecGetSegmentId(ref Vp9Common cm, ArrayPtr segmentIds, int miOffset, int xMis, int yMis) @@ -129,6 +137,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } Debug.Assert(segmentId >= 0 && segmentId < Constants.MaxSegments); + return segmentId; } @@ -173,17 +182,19 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 if (!seg.Enabled) { - return 0; // Default for disabled segmentation + return 0; // Default for disabled segmentation } if (!seg.UpdateMap) { CopySegmentId(ref cm, cm.LastFrameSegMap, cm.CurrentFrameSegMap, miOffset, xMis, yMis); + return 0; } segmentId = ReadSegmentId(ref r, ref cm.Fc.Value.SegTreeProb); SetSegmentId(ref cm, miOffset, xMis, yMis, segmentId); + return segmentId; } @@ -203,7 +214,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 if (!seg.Enabled) { - return 0; // Default for disabled segmentation + return 0; // Default for disabled segmentation } predictedSegmentId = !cm.LastFrameSegMap.IsNull @@ -213,6 +224,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 if (!seg.UpdateMap) { CopySegmentId(ref cm, cm.LastFrameSegMap, cm.CurrentFrameSegMap, miOffset, xMis, yMis); + return predictedSegmentId; } @@ -227,6 +239,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 segmentId = ReadSegmentId(ref r, ref cm.Fc.Value.SegTreeProb); } SetSegmentId(ref cm, miOffset, xMis, yMis, segmentId); + return segmentId; } @@ -236,17 +249,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { return 1; } - else - { - int ctx = xd.GetSkipContext(); - int skip = r.Read(cm.Fc.Value.SkipProb[ctx]); - if (!xd.Counts.IsNull) - { - ++xd.Counts.Value.Skip[ctx][skip]; - } - return skip; + int ctx = xd.GetSkipContext(); + int skip = r.Read(cm.Fc.Value.SkipProb[ctx]); + if (!xd.Counts.IsNull) + { + ++xd.Counts.Value.Skip[ctx][skip]; } + + return skip; } private static int ReadMvComponent(ref Reader r, ref Vp9EntropyProbs fc, int mvcomp, bool usehp) @@ -265,7 +276,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 else { int i; - int n = (int)mvClass + Constants.Class0Bits - 1; // Number of bits + int n = (int)mvClass + Constants.Class0Bits - 1; // Number of bits d = 0; for (i = 0; i < n; ++i) @@ -284,6 +295,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Result mag += ((d << 3) | (fr << 1) | hp) + 1; + return sign ? -mag : mag; } @@ -297,7 +309,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { MvJointType jointType = (MvJointType)r.ReadTree(Luts.Vp9MvJointTree, fc.Joints.AsSpan()); bool useHP = allowHP && refr.UseMvHp(); - Mv diff = new Mv(); + Mv diff = new(); if (Mv.MvJointVertical(jointType)) { @@ -326,12 +338,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 ++xd.Counts.Value.CompInter[ctx][(int)mode]; } - return mode; // SingleReference or CompoundReference - } - else - { - return cm.ReferenceMode; + return mode; // SingleReference or CompoundReference } + + return cm.ReferenceMode; } // Read the referncence frame @@ -434,7 +444,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 mi.Bmi[0].Mode = mi.Bmi[1].Mode = ReadIntraModeY(ref cm, ref xd, ref r, 0); mi.Bmi[2].Mode = mi.Bmi[3].Mode = mi.Mode = ReadIntraModeY(ref cm, ref xd, ref r, 0); break; - default: mi.Mode = ReadIntraModeY(ref cm, ref xd, ref r, Luts.SizeGroupLookup[(int)bsize]); break; + default: + mi.Mode = ReadIntraModeY(ref cm, ref xd, ref r, Luts.SizeGroupLookup[(int)bsize]); + break; } mi.UvMode = ReadIntraModeUv(ref cm, ref xd, ref r, (byte)mi.Mode); @@ -503,7 +515,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 ZeroMvPair(ref mv); break; } - default: return false; + default: + return false; } return ret; } @@ -514,17 +527,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { return cm.Seg.GetSegData(segmentId, SegLvlFeatures.SegLvlRefFrame) != Constants.IntraFrame; } - else - { - int ctx = xd.GetIntraInterContext(); - bool isInter = r.Read(cm.Fc.Value.IntraInterProb[ctx]) != 0; - if (!xd.Counts.IsNull) - { - ++xd.Counts.Value.IntraInter[ctx][isInter ? 1 : 0]; - } - return isInter; + int ctx = xd.GetIntraInterContext(); + bool isInter = r.Read(cm.Fc.Value.IntraInterProb[ctx]) != 0; + if (!xd.Counts.IsNull) + { + ++xd.Counts.Value.IntraInter[ctx][isInter ? 1 : 0]; } + + return isInter; } private static void DecFindBestRefMvs(bool allowHP, Span mvlist, ref Mv bestMv, int refmvCount) @@ -547,6 +558,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { mvRefList[refMvCount] = mv; refMvCount++; + return true; } } @@ -605,7 +617,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // This function searches the neighborhood of a given MB/SB // to try and find candidate reference vectors. - private static unsafe int DecFindMvRefs( + private static int DecFindMvRefs( ref Vp9Common cm, ref MacroBlockD xd, PredictionMode mode, @@ -627,7 +639,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 bool earlyBreak = mode != PredictionMode.NearMv; // Blank the reference vector list - mvRefList.Slice(0, Constants.MaxMvRefCandidates).Fill(new Mv()); + mvRefList[..Constants.MaxMvRefCandidates].Clear(); i = 0; if (isSub8X8 != 0) @@ -805,7 +817,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 switch (block) { - case 0: bestSub8x8 = mvList[refmvCount - 1]; break; + case 0: + bestSub8x8 = mvList[refmvCount - 1]; + break; case 1: case 2: if (bMode == PredictionMode.NearestMv) @@ -848,7 +862,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } break; - default: Debug.Assert(false, "Invalid block index."); break; + default: + Debug.Assert(false, "Invalid block index."); + break; } } @@ -883,7 +899,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { BlockSize bsize = mi.SbType; bool allowHP = cm.AllowHighPrecisionMv; - Array2 bestRefMvs = new Array2(); + Array2 bestRefMvs = new(); int refr, isCompound; byte interModeCtx; Span mvRefSearch = Luts.MvRefBlocks[(int)bsize]; @@ -898,6 +914,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 if (bsize < BlockSize.Block8x8) { xd.ErrorInfo.Value.InternalError(CodecErr.CodecUnsupBitstream, "Invalid usage of segement feature on small blocks"); + return; } } @@ -940,11 +957,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int num4X4H = 1 << xd.BmodeBlocksHl; int idx, idy; PredictionMode bMode = 0; - Array2 bestSub8x8 = new Array2(); - const uint invalidMv = 0x80008000; + Array2 bestSub8x8 = new(); + const uint InvalidMv = 0x80008000; // Initialize the 2nd element as even though it won't be used meaningfully // if isCompound is false. - Unsafe.As(ref bestSub8x8[1]) = invalidMv; + Unsafe.As(ref bestSub8x8[1]) = InvalidMv; for (idy = 0; idy < 2; idy += num4X4H) { for (idx = 0; idx < 2; idx += num4X4W) @@ -1026,11 +1043,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 return leftMi.Value.GetYMode(b + 1); } - else - { - Debug.Assert(b == 1 || b == 3); - return curMi.Value.Bmi[b - 1].Mode; - } + + Debug.Assert(b == 1 || b == 3); + + return curMi.Value.Bmi[b - 1].Mode; } private static PredictionMode AboveBlockMode(Ptr curMi, Ptr aboveMi, int b) @@ -1044,11 +1060,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 return aboveMi.Value.GetYMode(b + 2); } - else - { - Debug.Assert(b == 2 || b == 3); - return curMi.Value.Bmi[b - 2].Mode; - } + + Debug.Assert(b == 2 || b == 3); + + return curMi.Value.Bmi[b - 2].Mode; } private static ReadOnlySpan GetYModeProbs( @@ -1060,6 +1075,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { PredictionMode above = AboveBlockMode(mi, aboveMi, block); PredictionMode left = LeftBlockMode(mi, leftMi, block); + return fc.KfYModeProb[(int)above][(int)left].AsSpan(); } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Decoder.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Decoder.cs index acebd8ab9..fea184f15 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Decoder.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Decoder.cs @@ -3,7 +3,6 @@ using Ryujinx.Graphics.Nvdec.Vp9.Common; using Ryujinx.Graphics.Nvdec.Vp9.Types; using Ryujinx.Graphics.Video; using System; -using Vp9MvRef = Ryujinx.Graphics.Video.Vp9MvRef; namespace Ryujinx.Graphics.Nvdec.Vp9 { @@ -11,7 +10,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { public bool IsHardwareAccelerated => false; - private readonly MemoryAllocator _allocator = new MemoryAllocator(); + private readonly MemoryAllocator _allocator = new(); public ISurface CreateSurface(int width, int height) => new Surface(width, height); @@ -20,7 +19,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Constants.EightTapSmooth, Constants.EightTap, Constants.EightTapSharp, - Constants.Bilinear + Constants.Bilinear, }; public unsafe bool Decode( @@ -30,24 +29,25 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 ReadOnlySpan mvsIn, Span mvsOut) { - Vp9Common cm = new Vp9Common(); + Vp9Common cm = new() + { + FrameType = pictureInfo.IsKeyFrame ? FrameType.KeyFrame : FrameType.InterFrame, + IntraOnly = pictureInfo.IntraOnly, - cm.FrameType = pictureInfo.IsKeyFrame ? FrameType.KeyFrame : FrameType.InterFrame; - cm.IntraOnly = pictureInfo.IntraOnly; + Width = output.Width, + Height = output.Height, + SubsamplingX = 1, + SubsamplingY = 1, - cm.Width = output.Width; - cm.Height = output.Height; - cm.SubsamplingX = 1; - cm.SubsamplingY = 1; + UsePrevFrameMvs = pictureInfo.UsePrevInFindMvRefs, - cm.UsePrevFrameMvs = pictureInfo.UsePrevInFindMvRefs; + RefFrameSignBias = pictureInfo.RefFrameSignBias, - cm.RefFrameSignBias = pictureInfo.RefFrameSignBias; - - cm.BaseQindex = pictureInfo.BaseQIndex; - cm.YDcDeltaQ = pictureInfo.YDcDeltaQ; - cm.UvAcDeltaQ = pictureInfo.UvAcDeltaQ; - cm.UvDcDeltaQ = pictureInfo.UvDcDeltaQ; + BaseQindex = pictureInfo.BaseQIndex, + YDcDeltaQ = pictureInfo.YDcDeltaQ, + UvAcDeltaQ = pictureInfo.UvAcDeltaQ, + UvDcDeltaQ = pictureInfo.UvDcDeltaQ, + }; cm.Mb.Lossless = pictureInfo.Lossless; cm.Mb.Bd = 8; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Detokenize.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Detokenize.cs index 52b1b3dc4..8e5f124b6 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Detokenize.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Detokenize.cs @@ -17,9 +17,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private static int GetCoefContext(ReadOnlySpan neighbors, ReadOnlySpan tokenCache, int c) { - const int maxNeighbors = 2; + const int MaxNeighbors = 2; - return (1 + tokenCache[neighbors[maxNeighbors * c + 0]] + tokenCache[neighbors[maxNeighbors * c + 1]]) >> 1; + return (1 + tokenCache[neighbors[MaxNeighbors * c + 0]] + tokenCache[neighbors[MaxNeighbors * c + 1]]) >> 1; } private static int ReadCoeff( @@ -57,13 +57,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int band, c = 0; ref Array6>> coefProbs = ref fc.CoefProbs[(int)txSize][(int)type][refr]; Span tokenCache = stackalloc byte[32 * 32]; - ReadOnlySpan bandTranslate = Luts.get_band_translate(txSize); + ReadOnlySpan bandTranslate = Luts.GetBandTranslate(txSize); int dqShift = (txSize == TxSize.Tx32x32) ? 1 : 0; int v; short dqv = dq[0]; ReadOnlySpan cat6Prob = (xd.Bd == 12) ? Luts.Vp9Cat6ProbHigh12 - : (xd.Bd == 10) ? Luts.Vp9Cat6ProbHigh12.Slice(2) : Luts.Vp9Cat6Prob; + : (xd.Bd == 10) ? Luts.Vp9Cat6ProbHigh12[2..] : Luts.Vp9Cat6Prob; int cat6Bits = (xd.Bd == 12) ? 18 : (xd.Bd == 10) ? 16 : 14; // Keep value, range, and count as locals. The compiler produces better // results with the locals than using r directly. @@ -75,7 +75,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { int val = -1; band = bandTranslate[0]; - bandTranslate = bandTranslate.Slice(1); + bandTranslate = bandTranslate[1..]; ref Array3 prob = ref coefProbs[band][ctx]; if (!xd.Counts.IsNull) { @@ -107,11 +107,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 r.Value = value; r.Range = range; r.Count = count; - return c; // Zero tokens at the end (no eob token) + + return c; // Zero tokens at the end (no eob token) } ctx = GetCoefContext(nb, tokenCache, c); band = bandTranslate[0]; - bandTranslate = bandTranslate.Slice(1); + bandTranslate = bandTranslate[1..]; prob = ref coefProbs[band][ctx]; } @@ -196,6 +197,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 r.Value = value; r.Range = range; r.Count = count; + return c; } @@ -236,8 +238,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 ref MacroBlockDPlane pd = ref xd.Plane[plane]; ref Array2 dequant = ref pd.SegDequant[segId]; int eob; - Span a = pd.AboveContext.AsSpan().Slice(x); - Span l = pd.LeftContext.AsSpan().Slice(y); + Span a = pd.AboveContext.AsSpan()[x..]; + Span l = pd.LeftContext.AsSpan()[y..]; int ctx; int ctxShiftA = 0; int ctxShiftL = 0; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Convolve.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Convolve.cs index d49a6bf63..5d4c4b840 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Convolve.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Convolve.cs @@ -117,6 +117,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (Sse41.IsSupported && UseIntrinsics && xStepQ4 == 1 << SubpelBits) { ConvolveHorizSse41(src, srcStride, dst, dstStride, xFilters, x0Q4, w, h); + return; } @@ -261,6 +262,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (Avx2.IsSupported && UseIntrinsics && yStepQ4 == 1 << SubpelBits) { ConvolveVertAvx2(src, srcStride, dst, dstStride, yFilters, y0Q4, w, h); + return; } @@ -776,7 +778,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Debug.Assert(yStepQ4 <= 32); Debug.Assert(xStepQ4 <= 32); - HighbdConvolveHoriz(src - srcStride * (SubpelTaps / 2 - 1), srcStride, temp, 64, filter, x0Q4, xStepQ4, w, intermediateHeight, bd); + HighbdConvolveHoriz(src - srcStride * (SubpelTaps / 2 - 1), srcStride, temp, 64, filter, x0Q4, xStepQ4, w, intermediateHeight, bd); HighbdConvolveVert(temp + 64 * (SubpelTaps / 2 - 1), 64, dst, dstStride, filter, y0Q4, yStepQ4, w, h, bd); } @@ -811,7 +813,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp int h, int bd) { - HighbdConvolveAvgHoriz(src, srcStride, dst, dstStride, filter, x0Q4, xStepQ4, w, h, bd); + HighbdConvolveAvgHoriz(src, srcStride, dst, dstStride, filter, x0Q4, xStepQ4, w, h, bd); } public static unsafe void HighbdConvolve8Vert( diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/IntraPred.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/IntraPred.cs index 62b3a9b14..8db78ab03 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/IntraPred.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/IntraPred.cs @@ -227,7 +227,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp private static unsafe void D135Predictor(byte* dst, int stride, int bs, byte* above, byte* left) { int i; - byte* border = stackalloc byte[32 + 32 - 1]; // outer border from bottom-left to top-right + byte* border = stackalloc byte[32 + 32 - 1]; // outer border from bottom-left to top-right // Dst(dst, stride, bs, bs - 2)[0], i.e., border starting at bottom-left for (i = 0; i < bs - 2; ++i) @@ -607,13 +607,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Dst(dst, stride, 1, 0) = Dst(dst, stride, 0, 2) = Avg2(b, c); Dst(dst, stride, 2, 0) = Dst(dst, stride, 1, 2) = Avg2(c, d); Dst(dst, stride, 3, 0) = Dst(dst, stride, 2, 2) = Avg2(d, e); - Dst(dst, stride, 3, 2) = Avg2(e, f); // Differs from vp8 + Dst(dst, stride, 3, 2) = Avg2(e, f); // Differs from vp8 Dst(dst, stride, 0, 1) = Avg3(a, b, c); Dst(dst, stride, 1, 1) = Dst(dst, stride, 0, 3) = Avg3(b, c, d); Dst(dst, stride, 2, 1) = Dst(dst, stride, 1, 3) = Avg3(c, d, e); Dst(dst, stride, 3, 1) = Dst(dst, stride, 2, 3) = Avg3(d, e, f); - Dst(dst, stride, 3, 3) = Avg3(e, f, g); // Differs from vp8 + Dst(dst, stride, 3, 3) = Avg3(e, f, g); // Differs from vp8 } public static unsafe void D63ePredictor4x4(byte* dst, int stride, byte* above, byte* left) @@ -655,7 +655,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Dst(dst, stride, 3, 0) = Dst(dst, stride, 2, 1) = Dst(dst, stride, 1, 2) = Dst(dst, stride, 0, 3) = Avg3(d, e, f); Dst(dst, stride, 3, 1) = Dst(dst, stride, 2, 2) = Dst(dst, stride, 1, 3) = Avg3(e, f, g); Dst(dst, stride, 3, 2) = Dst(dst, stride, 2, 3) = Avg3(f, g, h); - Dst(dst, stride, 3, 3) = h; // differs from vp8 + Dst(dst, stride, 3, 3) = h; // differs from vp8 } public static unsafe void D45ePredictor4x4(byte* dst, int stride, byte* above, byte* left) @@ -935,7 +935,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp private static unsafe void HighbdD135Predictor(ushort* dst, int stride, int bs, ushort* above, ushort* left, int bd) { int i; - ushort* border = stackalloc ushort[32 + 32 - 1]; // Outer border from bottom-left to top-right + ushort* border = stackalloc ushort[32 + 32 - 1]; // Outer border from bottom-left to top-right // Dst(dst, stride, bs, bs - 2)[0], i.e., border starting at bottom-left for (i = 0; i < bs - 2; ++i) @@ -1281,13 +1281,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Dst(dst, stride, 1, 0) = Dst(dst, stride, 0, 2) = Avg2(b, c); Dst(dst, stride, 2, 0) = Dst(dst, stride, 1, 2) = Avg2(c, d); Dst(dst, stride, 3, 0) = Dst(dst, stride, 2, 2) = Avg2(d, e); - Dst(dst, stride, 3, 2) = Avg2(e, f); // Differs from vp8 + Dst(dst, stride, 3, 2) = Avg2(e, f); // Differs from vp8 Dst(dst, stride, 0, 1) = Avg3(a, b, c); Dst(dst, stride, 1, 1) = Dst(dst, stride, 0, 3) = Avg3(b, c, d); Dst(dst, stride, 2, 1) = Dst(dst, stride, 1, 3) = Avg3(c, d, e); Dst(dst, stride, 3, 1) = Dst(dst, stride, 2, 3) = Avg3(d, e, f); - Dst(dst, stride, 3, 3) = Avg3(e, f, g); // Differs from vp8 + Dst(dst, stride, 3, 3) = Avg3(e, f, g); // Differs from vp8 } public static unsafe void HighbdD45Predictor4x4(ushort* dst, int stride, ushort* above, ushort* left, int bd) @@ -1306,7 +1306,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Dst(dst, stride, 3, 0) = Dst(dst, stride, 2, 1) = Dst(dst, stride, 1, 2) = Dst(dst, stride, 0, 3) = Avg3(d, e, f); Dst(dst, stride, 3, 1) = Dst(dst, stride, 2, 2) = Dst(dst, stride, 1, 3) = Avg3(e, f, g); Dst(dst, stride, 3, 2) = Dst(dst, stride, 2, 3) = Avg3(f, g, h); - Dst(dst, stride, 3, 3) = h; // Differs from vp8 + Dst(dst, stride, 3, 3) = h; // Differs from vp8 } public static unsafe void HighbdD117Predictor4x4(ushort* dst, int stride, ushort* above, ushort* left, int bd) diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/InvTxfm.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/InvTxfm.cs index 3fc3c72a7..68da7c496 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/InvTxfm.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/InvTxfm.cs @@ -35,6 +35,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp // of this range for invalid/corrupt VP9 streams. Debug.Assert(short.MinValue <= input); Debug.Assert(input <= short.MaxValue); + return input; } @@ -70,6 +71,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp public static byte ClipPixelAdd(byte dest, long trans) { trans = WrapLow(trans); + return BitUtils.ClipPixel(dest + (int)trans); } @@ -77,6 +79,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp public static ushort HighbdClipPixelAdd(ushort dest, long trans, int bd) { trans = HighbdWrapLow(trans, bd); + return BitUtils.ClipPixelHighbd(dest + (int)trans, bd); } @@ -84,6 +87,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp private static long DctConstRoundShift(long input) { long rv = BitUtils.RoundPowerOfTwo(input, DctConstBits); + return rv; } @@ -115,8 +119,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp op[1] = WrapLow(b1); op[2] = WrapLow(c1); op[3] = WrapLow(d1); - ip = ip.Slice(4); - op = op.Slice(4); + ip = ip[4..]; + op = op[4..]; } Span ip2 = output; @@ -138,8 +142,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[stride * 2] = ClipPixelAdd(dest[stride * 2], WrapLow(c1)); dest[stride * 3] = ClipPixelAdd(dest[stride * 3], WrapLow(d1)); - ip2 = ip2.Slice(1); - dest = dest.Slice(1); + ip2 = ip2[1..]; + dest = dest[1..]; } } @@ -167,8 +171,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[stride * 1] = ClipPixelAdd(dest[stride * 1], e1); dest[stride * 2] = ClipPixelAdd(dest[stride * 2], e1); dest[stride * 3] = ClipPixelAdd(dest[stride * 3], e1); - ip2 = ip2.Slice(1); - dest = dest.Slice(1); + ip2 = ip2[1..]; + dest = dest[1..]; } } @@ -182,7 +186,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if ((x0 | x1 | x2 | x3) == 0) { - output.Slice(0, 4).Fill(0); + output[..4].Clear(); + return; } @@ -247,8 +252,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 4; ++i) { Idct4(input, outptr); - input = input.Slice(4); - outptr = outptr.Slice(4); + input = input[4..]; + outptr = outptr[4..]; } // Columns @@ -282,7 +287,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[1] = ClipPixelAdd(dest[1], a1); dest[2] = ClipPixelAdd(dest[2], a1); dest[3] = ClipPixelAdd(dest[3], a1); - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -300,7 +305,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if ((x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7) == 0) { - output.Slice(0, 8).Fill(0); + output[..8].Clear(); + return; } @@ -434,8 +440,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 8; ++i) { Idct8(input, outptr); - input = input.Slice(8); - outptr = outptr.Slice(8); + input = input[8..]; + outptr = outptr[8..]; } // Then transform columns @@ -464,15 +470,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[8]; Span tempOut = stackalloc int[8]; - output.Fill(0); + output.Clear(); // First transform rows // Only first 4 row has non-zero coefs for (i = 0; i < 4; ++i) { Idct8(input, outptr); - input = input.Slice(8); - outptr = outptr.Slice(8); + input = input[8..]; + outptr = outptr[8..]; } // Then transform columns @@ -506,7 +512,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = ClipPixelAdd(dest[i], a1); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -533,7 +539,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if ((x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | x10 | x11 | x12 | x13 | x14 | x15) == 0) { - output.Slice(0, 16).Fill(0); + output[..16].Clear(); + return; } @@ -860,8 +867,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 16; ++i) { Idct16(input, outptr); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -889,15 +896,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - output.Fill(0); + output.Clear(); // First transform rows. Since all non-zero dct coefficients are in // upper-left 8x8 area, we only need to calculate first 8 rows here. for (i = 0; i < 8; ++i) { Idct16(input, outptr); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -925,15 +932,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - output.Fill(0); + output.Clear(); // First transform rows. Since all non-zero dct coefficients are in // upper-left 4x4 area, we only need to calculate first 4 rows here. for (i = 0; i < 4; ++i) { Idct16(input, outptr); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -967,7 +974,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = ClipPixelAdd(dest[i], a1); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -1365,11 +1372,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } else { - outptr.Slice(0, 32).Fill(0); + outptr[..32].Clear(); } - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -1397,15 +1404,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[32]; Span tempOut = stackalloc int[32]; - output.Fill(0); + output.Clear(); // Rows // Only upper-left 16x16 has non-zero coeff for (i = 0; i < 16; ++i) { Idct32(input, outptr); - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -1433,15 +1440,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[32]; Span tempOut = stackalloc int[32]; - output.Fill(0); + output.Clear(); // Rows // Only upper-left 8x8 has non-zero coeff for (i = 0; i < 8; ++i) { Idct32(input, outptr); - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -1476,7 +1483,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = ClipPixelAdd(dest[i], a1); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -1508,8 +1515,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp op[1] = HighbdWrapLow(b1, bd); op[2] = HighbdWrapLow(c1, bd); op[3] = HighbdWrapLow(d1, bd); - ip = ip.Slice(4); - op = op.Slice(4); + ip = ip[4..]; + op = op[4..]; } ReadOnlySpan ip2 = output; @@ -1531,8 +1538,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[stride * 2] = HighbdClipPixelAdd(dest[stride * 2], HighbdWrapLow(c1, bd), bd); dest[stride * 3] = HighbdClipPixelAdd(dest[stride * 3], HighbdWrapLow(d1, bd), bd); - ip2 = ip2.Slice(1); - dest = dest.Slice(1); + ip2 = ip2[1..]; + dest = dest[1..]; } } @@ -1560,8 +1567,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[stride * 1] = HighbdClipPixelAdd(dest[stride * 1], e1, bd); dest[stride * 2] = HighbdClipPixelAdd(dest[stride * 2], e1, bd); dest[stride * 3] = HighbdClipPixelAdd(dest[stride * 3], e1, bd); - ip2 = ip2.Slice(1); - dest = dest.Slice(1); + ip2 = ip2[1..]; + dest = dest[1..]; } } @@ -1576,13 +1583,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 4) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 4).Fill(0); + output[..4].Clear(); + return; } if ((x0 | x1 | x2 | x3) == 0) { - output.Slice(0, 4).Fill(0); + output[..4].Clear(); + return; } @@ -1619,7 +1628,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 4) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 4).Fill(0); + output[..4].Clear(); + return; } @@ -1653,8 +1663,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 4; ++i) { HighbdIdct4(input, outptr, bd); - input = input.Slice(4); - outptr = outptr.Slice(4); + input = input[4..]; + outptr = outptr[4..]; } // Columns @@ -1688,7 +1698,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[1] = HighbdClipPixelAdd(dest[1], a1, bd); dest[2] = HighbdClipPixelAdd(dest[2], a1, bd); dest[3] = HighbdClipPixelAdd(dest[3], a1, bd); - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -1707,13 +1717,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 8) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 8).Fill(0); + output[..8].Clear(); + return; } if ((x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7) == 0) { - output.Slice(0, 8).Fill(0); + output[..8].Clear(); + return; } @@ -1786,7 +1798,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 8) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 8).Fill(0); + output[..8].Clear(); + return; } @@ -1845,8 +1858,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 8; ++i) { HighbdIdct8(input, outptr, bd); - input = input.Slice(8); - outptr = outptr.Slice(8); + input = input[8..]; + outptr = outptr[8..]; } // Then transform columns @@ -1874,15 +1887,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[8]; Span tempOut = stackalloc int[8]; - output.Fill(0); + output.Clear(); // First transform rows // Only first 4 row has non-zero coefs for (i = 0; i < 4; ++i) { HighbdIdct8(input, outptr, bd); - input = input.Slice(8); - outptr = outptr.Slice(8); + input = input[8..]; + outptr = outptr[8..]; } // Then transform columns @@ -1901,7 +1914,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } } - public static void vpx_Highbdidct8x8_1_add_c(ReadOnlySpan input, Span dest, int stride, int bd) + public static void Vpx_Highbdidct8x8_1_add_c(ReadOnlySpan input, Span dest, int stride, int bd) { int i, j; long a1; @@ -1916,7 +1929,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = HighbdClipPixelAdd(dest[i], a1, bd); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -1940,16 +1953,19 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp int x13 = input[12]; int x14 = input[1]; int x15 = input[14]; + if (DetectInvalidHighbdInput(input, 16) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 16).Fill(0); + output[..16].Clear(); + return; } if ((x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | x10 | x11 | x12 | x13 | x14 | x15) == 0) { - output.Slice(0, 16).Fill(0); + output[..16].Clear(); + return; } @@ -2105,7 +2121,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 16) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 16).Fill(0); + output[..16].Clear(); + return; } @@ -2283,8 +2300,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (i = 0; i < 16; ++i) { HighbdIdct16(input, outptr, bd); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -2312,15 +2329,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - output.Fill(0); + output.Clear(); // First transform rows. Since all non-zero dct coefficients are in // upper-left 8x8 area, we only need to calculate first 8 rows here. for (i = 0; i < 8; ++i) { HighbdIdct16(input, outptr, bd); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -2336,7 +2353,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (j = 0; j < 16; ++j) { destT[i] = HighbdClipPixelAdd(destT[i], BitUtils.RoundPowerOfTwo(tempOut[j], 6), bd); - destT = destT.Slice(stride); + destT = destT[stride..]; } } } @@ -2350,15 +2367,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - output.Fill(0); + output.Clear(); // First transform rows. Since all non-zero dct coefficients are in // upper-left 4x4 area, we only need to calculate first 4 rows here. for (i = 0; i < 4; ++i) { HighbdIdct16(input, outptr, bd); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Then transform columns @@ -2392,7 +2409,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = HighbdClipPixelAdd(dest[i], a1, bd); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } @@ -2406,7 +2423,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (DetectInvalidHighbdInput(input, 32) != 0) { Debug.Assert(false, "invalid highbd txfm input"); - output.Slice(0, 32).Fill(0); + output[..32].Clear(); + return; } @@ -2797,11 +2815,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } else { - outptr.Slice(0, 32).Fill(0); + outptr[..32].Clear(); } - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -2829,15 +2847,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[32]; Span tempOut = stackalloc int[32]; - output.Fill(0); + output.Clear(); // Rows // Only upper-left 16x16 has non-zero coeff for (i = 0; i < 16; ++i) { HighbdIdct32(input, outptr, bd); - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -2853,7 +2871,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp for (j = 0; j < 32; ++j) { destT[i] = HighbdClipPixelAdd(destT[i], BitUtils.RoundPowerOfTwo(tempOut[j], 6), bd); - destT = destT.Slice(stride); + destT = destT[stride..]; } } } @@ -2867,15 +2885,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Span tempIn = stackalloc int[32]; Span tempOut = stackalloc int[32]; - output.Fill(0); + output.Clear(); // Rows // Only upper-left 8x8 has non-zero coeff for (i = 0; i < 8; ++i) { HighbdIdct32(input, outptr, bd); - input = input.Slice(32); - outptr = outptr.Slice(32); + input = input[32..]; + outptr = outptr[32..]; } // Columns @@ -2910,7 +2928,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp dest[i] = HighbdClipPixelAdd(dest[i], a1, bd); } - dest = dest.Slice(stride); + dest = dest[stride..]; } } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Prob.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Prob.cs index 0d5e8b6e3..83b427907 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Prob.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Prob.cs @@ -15,6 +15,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp int p = (int)(((ulong)num * 256 + (den >> 1)) / den); // (p > 255) ? 255 : (p < 1) ? 1 : p; int clippedProb = p | ((255 - p) >> 23) | (p == 0 ? 1 : 0); + return (byte)clippedProb; } } @@ -26,10 +27,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } // MODE_MV_MAX_UPDATE_FACTOR (128) * count / MODE_MV_COUNT_SAT; - private static readonly uint[] CountToUpdateFactor = new uint[] - { + private static readonly uint[] _countToUpdateFactor = { 0, 6, 12, 19, 25, 32, 38, 44, 51, 57, 64, - 70, 76, 83, 89, 96, 102, 108, 115, 121, 128 + 70, 76, 83, 89, 96, 102, 108, 115, 121, 128, }; private const int ModeMvCountSat = 20; @@ -44,8 +44,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp else { uint count = Math.Min(den, ModeMvCountSat); - uint factor = CountToUpdateFactor[(int)count]; + uint factor = _countToUpdateFactor[(int)count]; byte prob = GetProb(ct0, den); + return WeightedProb(preProb, prob, (int)factor); } } @@ -62,6 +63,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp int r = tree[i + 1]; uint rightCount = (r <= 0) ? counts[-r] : TreeMergeProbsImpl((uint)r, tree, preProbs, counts, probs); probs[(int)(i >> 1)] = ModeMvMergeProbs(preProbs[(int)(i >> 1)], leftCount, rightCount); + return leftCount + rightCount; } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Reader.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Reader.cs index 050951216..090426e7c 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Reader.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Dsp/Reader.cs @@ -6,8 +6,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp { internal struct Reader { - private static readonly byte[] Norm = new byte[] - { + private static readonly byte[] _norm = { 0, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -17,7 +16,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; private const int BdValueSize = sizeof(ulong) * 8; @@ -44,7 +43,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Count = -8; Range = 255; Fill(); - return ReadBit() != 0; // Marker bit + + return ReadBit() != 0; // Marker bit } } @@ -65,7 +65,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp ulong bigEndianValues = BinaryPrimitives.ReadUInt64BigEndian(buffer); nv = bigEndianValues >> (BdValueSize - bits); count += bits; - buffer = buffer.Slice(bits >> 3); + buffer = buffer[(bits >> 3)..]; value = Value | (nv << (shift & 0x7)); } else @@ -84,7 +84,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp { count += 8; value |= (ulong)buffer[0] << shift; - buffer = buffer.Slice(1); + buffer = buffer[1..]; shift -= 8; } } @@ -98,7 +98,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp Count = count; } - public bool HasError() + public readonly bool HasError() { // Check if we have reached the end of the buffer. // @@ -146,7 +146,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } { - int shift = Norm[range]; + int shift = _norm[range]; range <<= shift; value <<= shift; count -= shift; @@ -160,7 +160,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp public int ReadBit() { - return Read(128); // vpx_prob_half + return Read(128); // vpx_prob_half } public int ReadLiteral(int bits) @@ -181,7 +181,6 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp while ((i = tree[i + Read(probs[i >> 1])]) > 0) { - continue; } return -i; @@ -203,10 +202,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp if (value >= bigsplit) { - range = range - split; - value = value - bigsplit; + range -= split; + value -= bigsplit; { - int shift = Norm[range]; + int shift = _norm[range]; range <<= shift; value <<= shift; count -= shift; @@ -215,7 +214,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Dsp } range = split; { - int shift = Norm[range]; + int shift = _norm[range]; range <<= shift; value <<= shift; count -= shift; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Idct.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Idct.cs index 9fa5842a6..1ee7f68bc 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Idct.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Idct.cs @@ -12,7 +12,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private struct Transform2D { - public Transform1D Cols, Rows; // Vertical and horizontal + public Transform1D Cols, Rows; // Vertical and horizontal public Transform2D(Transform1D cols, Transform1D rows) { @@ -23,7 +23,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private struct HighbdTransform2D { - public HighbdTransform1D Cols, Rows; // Vertical and horizontal + public HighbdTransform1D Cols, Rows; // Vertical and horizontal public HighbdTransform2D(HighbdTransform1D cols, HighbdTransform1D rows) { @@ -32,12 +32,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly Transform2D[] Iht4 = new Transform2D[] - { - new Transform2D(Idct4, Idct4), // DCT_DCT = 0 - new Transform2D(Iadst4, Idct4), // ADST_DCT = 1 - new Transform2D(Idct4, Iadst4), // DCT_ADST = 2 - new Transform2D(Iadst4, Iadst4) // ADST_ADST = 3 + private static readonly Transform2D[] _iht4 = { + new(Idct4, Idct4), // DCT_DCT = 0 + new(Iadst4, Idct4), // ADST_DCT = 1 + new(Idct4, Iadst4), // DCT_ADST = 2 + new(Iadst4, Iadst4), // ADST_ADST = 3 }; public static void Iht4x416Add(ReadOnlySpan input, Span dest, int stride, int txType) @@ -51,9 +50,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Inverse transform row vectors for (i = 0; i < 4; ++i) { - Iht4[txType].Rows(input, outptr); - input = input.Slice(4); - outptr = outptr.Slice(4); + _iht4[txType].Rows(input, outptr); + input = input[4..]; + outptr = outptr[4..]; } // Inverse transform column vectors @@ -64,7 +63,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 tempIn[j] = output[j * 4 + i]; } - Iht4[txType].Cols(tempIn, tempOut); + _iht4[txType].Cols(tempIn, tempOut); for (j = 0; j < 4; ++j) { dest[j * stride + i] = ClipPixelAdd(dest[j * stride + i], BitUtils.RoundPowerOfTwo(tempOut[j], 4)); @@ -72,12 +71,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly Transform2D[] Iht8 = new Transform2D[] - { - new Transform2D(Idct8, Idct8), // DCT_DCT = 0 - new Transform2D(Iadst8, Idct8), // ADST_DCT = 1 - new Transform2D(Idct8, Iadst8), // DCT_ADST = 2 - new Transform2D(Iadst8, Iadst8) // ADST_ADST = 3 + private static readonly Transform2D[] _iht8 = { + new(Idct8, Idct8), // DCT_DCT = 0 + new(Iadst8, Idct8), // ADST_DCT = 1 + new(Idct8, Iadst8), // DCT_ADST = 2 + new(Iadst8, Iadst8), // ADST_ADST = 3 }; public static void Iht8x864Add(ReadOnlySpan input, Span dest, int stride, int txType) @@ -87,14 +85,14 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Span outptr = output; Span tempIn = stackalloc int[8]; Span tempOut = stackalloc int[8]; - Transform2D ht = Iht8[txType]; + Transform2D ht = _iht8[txType]; // Inverse transform row vectors for (i = 0; i < 8; ++i) { ht.Rows(input, outptr); - input = input.Slice(8); - outptr = outptr.Slice(8); + input = input[8..]; + outptr = outptr[8..]; } // Inverse transform column vectors @@ -113,12 +111,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly Transform2D[] Iht16 = new Transform2D[] - { - new Transform2D(Idct16, Idct16), // DCT_DCT = 0 - new Transform2D(Iadst16, Idct16), // ADST_DCT = 1 - new Transform2D(Idct16, Iadst16), // DCT_ADST = 2 - new Transform2D(Iadst16, Iadst16) // ADST_ADST = 3 + private static readonly Transform2D[] _iht16 = { + new(Idct16, Idct16), // DCT_DCT = 0 + new(Iadst16, Idct16), // ADST_DCT = 1 + new(Idct16, Iadst16), // DCT_ADST = 2 + new(Iadst16, Iadst16), // ADST_ADST = 3 }; public static void Iht16x16256Add(ReadOnlySpan input, Span dest, int stride, int txType) @@ -128,14 +125,14 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Span outptr = output; Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - Transform2D ht = Iht16[txType]; + Transform2D ht = _iht16[txType]; // Rows for (i = 0; i < 16; ++i) { ht.Rows(input, outptr); - input = input.Slice(16); - outptr = outptr.Slice(16); + input = input[16..]; + outptr = outptr[16..]; } // Columns @@ -283,12 +280,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly HighbdTransform2D[] HighbdIht4 = new HighbdTransform2D[] - { - new HighbdTransform2D(HighbdIdct4, HighbdIdct4), // DCT_DCT = 0 - new HighbdTransform2D(HighbdIadst4, HighbdIdct4), // ADST_DCT = 1 - new HighbdTransform2D(HighbdIdct4, HighbdIadst4), // DCT_ADST = 2 - new HighbdTransform2D(HighbdIadst4, HighbdIadst4) // ADST_ADST = 3 + private static readonly HighbdTransform2D[] _highbdIht4 = { + new(HighbdIdct4, HighbdIdct4), // DCT_DCT = 0 + new(HighbdIadst4, HighbdIdct4), // ADST_DCT = 1 + new(HighbdIdct4, HighbdIadst4), // DCT_ADST = 2 + new(HighbdIadst4, HighbdIadst4), // ADST_ADST = 3 }; public static void HighbdIht4x416Add(ReadOnlySpan input, Span dest, int stride, int txType, int bd) @@ -302,9 +298,9 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Inverse transform row vectors. for (i = 0; i < 4; ++i) { - HighbdIht4[txType].Rows(input, outptr, bd); - input = input.Slice(4); - outptr = outptr.Slice(4); + _highbdIht4[txType].Rows(input, outptr, bd); + input = input[4..]; + outptr = outptr[4..]; } // Inverse transform column vectors. @@ -315,7 +311,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 tempIn[j] = output[j * 4 + i]; } - HighbdIht4[txType].Cols(tempIn, tempOut, bd); + _highbdIht4[txType].Cols(tempIn, tempOut, bd); for (j = 0; j < 4; ++j) { dest[j * stride + i] = HighbdClipPixelAdd(dest[j * stride + i], BitUtils.RoundPowerOfTwo(tempOut[j], 4), bd); @@ -323,12 +319,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly HighbdTransform2D[] HighIht8 = new HighbdTransform2D[] - { - new HighbdTransform2D(HighbdIdct8, HighbdIdct8), // DCT_DCT = 0 - new HighbdTransform2D(HighbdIadst8, HighbdIdct8), // ADST_DCT = 1 - new HighbdTransform2D(HighbdIdct8, HighbdIadst8), // DCT_ADST = 2 - new HighbdTransform2D(HighbdIadst8, HighbdIadst8) // ADST_ADST = 3 + private static readonly HighbdTransform2D[] _highIht8 = { + new(HighbdIdct8, HighbdIdct8), // DCT_DCT = 0 + new(HighbdIadst8, HighbdIdct8), // ADST_DCT = 1 + new(HighbdIdct8, HighbdIadst8), // DCT_ADST = 2 + new(HighbdIadst8, HighbdIadst8), // ADST_ADST = 3 }; public static void HighbdIht8x864Add(ReadOnlySpan input, Span dest, int stride, int txType, int bd) @@ -338,14 +333,14 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Span outptr = output; Span tempIn = stackalloc int[8]; Span tempOut = stackalloc int[8]; - HighbdTransform2D ht = HighIht8[txType]; + HighbdTransform2D ht = _highIht8[txType]; // Inverse transform row vectors. for (i = 0; i < 8; ++i) { ht.Rows(input, outptr, bd); - input = input.Slice(8); - outptr = output.Slice(8); + input = input[8..]; + outptr = output[8..]; } // Inverse transform column vectors. @@ -364,12 +359,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - private static readonly HighbdTransform2D[] HighIht16 = new HighbdTransform2D[] - { - new HighbdTransform2D(HighbdIdct16, HighbdIdct16), // DCT_DCT = 0 - new HighbdTransform2D(HighbdIadst16, HighbdIdct16), // ADST_DCT = 1 - new HighbdTransform2D(HighbdIdct16, HighbdIadst16), // DCT_ADST = 2 - new HighbdTransform2D(HighbdIadst16, HighbdIadst16) // ADST_ADST = 3 + private static readonly HighbdTransform2D[] _highIht16 = { + new(HighbdIdct16, HighbdIdct16), // DCT_DCT = 0 + new(HighbdIadst16, HighbdIdct16), // ADST_DCT = 1 + new(HighbdIdct16, HighbdIadst16), // DCT_ADST = 2 + new(HighbdIadst16, HighbdIadst16), // ADST_ADST = 3 }; public static void HighbdIht16x16256Add(ReadOnlySpan input, Span dest, int stride, int txType, int bd) @@ -379,14 +373,14 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 Span outptr = output; Span tempIn = stackalloc int[16]; Span tempOut = stackalloc int[16]; - HighbdTransform2D ht = HighIht16[txType]; + HighbdTransform2D ht = _highIht16[txType]; // Rows for (i = 0; i < 16; ++i) { ht.Rows(input, outptr, bd); - input = input.Slice(16); - outptr = output.Slice(16); + input = input[16..]; + outptr = output[16..]; } // Columns @@ -440,7 +434,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // DC only DCT coefficient if (eob == 1) { - vpx_Highbdidct8x8_1_add_c(input, dest, stride, bd); + Vpx_Highbdidct8x8_1_add_c(input, dest, stride, bd); } else if (eob <= 12) { diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/LoopFilter.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/LoopFilter.cs index 9ecccc64e..1c9f83b49 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/LoopFilter.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/LoopFilter.cs @@ -30,12 +30,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // 10101010 // // A loopfilter should be applied to every other 8x8 horizontally. - private static readonly ulong[] Left64X64TxformMask = new ulong[] - { - 0xffffffffffffffffUL, // TX_4X4 - 0xffffffffffffffffUL, // TX_8x8 - 0x5555555555555555UL, // TX_16x16 - 0x1111111111111111UL, // TX_32x32 + private static readonly ulong[] _left64X64TxformMask = { + 0xffffffffffffffffUL, // TX_4X4 + 0xffffffffffffffffUL, // TX_8x8 + 0x5555555555555555UL, // TX_16x16 + 0x1111111111111111UL, // TX_32x32 }; // 64 bit masks for above transform size. Each 1 represents a position where @@ -55,12 +54,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // 00000000 // // A loopfilter should be applied to every other 4 the row vertically. - private static readonly ulong[] Above64X64TxformMask = new ulong[] - { - 0xffffffffffffffffUL, // TX_4X4 - 0xffffffffffffffffUL, // TX_8x8 - 0x00ff00ff00ff00ffUL, // TX_16x16 - 0x000000ff000000ffUL, // TX_32x32 + private static readonly ulong[] _above64X64TxformMask = { + 0xffffffffffffffffUL, // TX_4X4 + 0xffffffffffffffffUL, // TX_8x8 + 0x00ff00ff00ff00ffUL, // TX_16x16 + 0x000000ff000000ffUL, // TX_32x32 }; // 64 bit masks for prediction sizes (left). Each 1 represents a position @@ -78,148 +76,143 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // 00000000 // 00000000 // 00000000 - private static readonly ulong[] LeftPredictionMask = new ulong[] - { - 0x0000000000000001UL, // BLOCK_4X4, - 0x0000000000000001UL, // BLOCK_4X8, - 0x0000000000000001UL, // BLOCK_8X4, - 0x0000000000000001UL, // BLOCK_8X8, - 0x0000000000000101UL, // BLOCK_8X16, - 0x0000000000000001UL, // BLOCK_16X8, - 0x0000000000000101UL, // BLOCK_16X16, - 0x0000000001010101UL, // BLOCK_16X32, - 0x0000000000000101UL, // BLOCK_32X16, - 0x0000000001010101UL, // BLOCK_32X32, - 0x0101010101010101UL, // BLOCK_32X64, - 0x0000000001010101UL, // BLOCK_64X32, - 0x0101010101010101UL, // BLOCK_64X64 + private static readonly ulong[] _leftPredictionMask = { + 0x0000000000000001UL, // BLOCK_4X4, + 0x0000000000000001UL, // BLOCK_4X8, + 0x0000000000000001UL, // BLOCK_8X4, + 0x0000000000000001UL, // BLOCK_8X8, + 0x0000000000000101UL, // BLOCK_8X16, + 0x0000000000000001UL, // BLOCK_16X8, + 0x0000000000000101UL, // BLOCK_16X16, + 0x0000000001010101UL, // BLOCK_16X32, + 0x0000000000000101UL, // BLOCK_32X16, + 0x0000000001010101UL, // BLOCK_32X32, + 0x0101010101010101UL, // BLOCK_32X64, + 0x0000000001010101UL, // BLOCK_64X32, + 0x0101010101010101UL, // BLOCK_64X64 }; // 64 bit mask to shift and set for each prediction size. - private static readonly ulong[] AbovePredictionMask = new ulong[] - { - 0x0000000000000001UL, // BLOCK_4X4 - 0x0000000000000001UL, // BLOCK_4X8 - 0x0000000000000001UL, // BLOCK_8X4 - 0x0000000000000001UL, // BLOCK_8X8 - 0x0000000000000001UL, // BLOCK_8X16, - 0x0000000000000003UL, // BLOCK_16X8 - 0x0000000000000003UL, // BLOCK_16X16 - 0x0000000000000003UL, // BLOCK_16X32, - 0x000000000000000fUL, // BLOCK_32X16, - 0x000000000000000fUL, // BLOCK_32X32, - 0x000000000000000fUL, // BLOCK_32X64, - 0x00000000000000ffUL, // BLOCK_64X32, - 0x00000000000000ffUL, // BLOCK_64X64 + private static readonly ulong[] _abovePredictionMask = { + 0x0000000000000001UL, // BLOCK_4X4 + 0x0000000000000001UL, // BLOCK_4X8 + 0x0000000000000001UL, // BLOCK_8X4 + 0x0000000000000001UL, // BLOCK_8X8 + 0x0000000000000001UL, // BLOCK_8X16, + 0x0000000000000003UL, // BLOCK_16X8 + 0x0000000000000003UL, // BLOCK_16X16 + 0x0000000000000003UL, // BLOCK_16X32, + 0x000000000000000fUL, // BLOCK_32X16, + 0x000000000000000fUL, // BLOCK_32X32, + 0x000000000000000fUL, // BLOCK_32X64, + 0x00000000000000ffUL, // BLOCK_64X32, + 0x00000000000000ffUL, // BLOCK_64X64 }; // 64 bit mask to shift and set for each prediction size. A bit is set for // each 8x8 block that would be in the left most block of the given block // size in the 64x64 block. - private static readonly ulong[] SizeMask = new ulong[] - { - 0x0000000000000001UL, // BLOCK_4X4 - 0x0000000000000001UL, // BLOCK_4X8 - 0x0000000000000001UL, // BLOCK_8X4 - 0x0000000000000001UL, // BLOCK_8X8 - 0x0000000000000101UL, // BLOCK_8X16, - 0x0000000000000003UL, // BLOCK_16X8 - 0x0000000000000303UL, // BLOCK_16X16 - 0x0000000003030303UL, // BLOCK_16X32, - 0x0000000000000f0fUL, // BLOCK_32X16, - 0x000000000f0f0f0fUL, // BLOCK_32X32, - 0x0f0f0f0f0f0f0f0fUL, // BLOCK_32X64, - 0x00000000ffffffffUL, // BLOCK_64X32, - 0xffffffffffffffffUL, // BLOCK_64X64 + private static readonly ulong[] _sizeMask = { + 0x0000000000000001UL, // BLOCK_4X4 + 0x0000000000000001UL, // BLOCK_4X8 + 0x0000000000000001UL, // BLOCK_8X4 + 0x0000000000000001UL, // BLOCK_8X8 + 0x0000000000000101UL, // BLOCK_8X16, + 0x0000000000000003UL, // BLOCK_16X8 + 0x0000000000000303UL, // BLOCK_16X16 + 0x0000000003030303UL, // BLOCK_16X32, + 0x0000000000000f0fUL, // BLOCK_32X16, + 0x000000000f0f0f0fUL, // BLOCK_32X32, + 0x0f0f0f0f0f0f0f0fUL, // BLOCK_32X64, + 0x00000000ffffffffUL, // BLOCK_64X32, + 0xffffffffffffffffUL, // BLOCK_64X64 }; // These are used for masking the left and above borders. +#pragma warning disable IDE0051 // Remove unused private member private const ulong LeftBorder = 0x1111111111111111UL; private const ulong AboveBorder = 0x000000ff000000ffUL; +#pragma warning restore IDE0051 // 16 bit masks for uv transform sizes. - private static readonly ushort[] Left64X64TxformMaskUv = new ushort[] - { - 0xffff, // TX_4X4 - 0xffff, // TX_8x8 - 0x5555, // TX_16x16 - 0x1111, // TX_32x32 + private static readonly ushort[] _left64X64TxformMaskUv = { + 0xffff, // TX_4X4 + 0xffff, // TX_8x8 + 0x5555, // TX_16x16 + 0x1111, // TX_32x32 }; - private static readonly ushort[] Above64X64TxformMaskUv = new ushort[] - { - 0xffff, // TX_4X4 - 0xffff, // TX_8x8 - 0x0f0f, // TX_16x16 - 0x000f, // TX_32x32 + private static readonly ushort[] _above64X64TxformMaskUv = { + 0xffff, // TX_4X4 + 0xffff, // TX_8x8 + 0x0f0f, // TX_16x16 + 0x000f, // TX_32x32 }; // 16 bit left mask to shift and set for each uv prediction size. - private static readonly ushort[] LeftPredictionMaskUv = new ushort[] - { - 0x0001, // BLOCK_4X4, - 0x0001, // BLOCK_4X8, - 0x0001, // BLOCK_8X4, - 0x0001, // BLOCK_8X8, - 0x0001, // BLOCK_8X16, - 0x0001, // BLOCK_16X8, - 0x0001, // BLOCK_16X16, - 0x0011, // BLOCK_16X32, - 0x0001, // BLOCK_32X16, - 0x0011, // BLOCK_32X32, - 0x1111, // BLOCK_32X64 - 0x0011, // BLOCK_64X32, - 0x1111, // BLOCK_64X64 + private static readonly ushort[] _leftPredictionMaskUv = { + 0x0001, // BLOCK_4X4, + 0x0001, // BLOCK_4X8, + 0x0001, // BLOCK_8X4, + 0x0001, // BLOCK_8X8, + 0x0001, // BLOCK_8X16, + 0x0001, // BLOCK_16X8, + 0x0001, // BLOCK_16X16, + 0x0011, // BLOCK_16X32, + 0x0001, // BLOCK_32X16, + 0x0011, // BLOCK_32X32, + 0x1111, // BLOCK_32X64 + 0x0011, // BLOCK_64X32, + 0x1111, // BLOCK_64X64 }; // 16 bit above mask to shift and set for uv each prediction size. - private static readonly ushort[] AbovePredictionMaskUv = new ushort[] - { - 0x0001, // BLOCK_4X4 - 0x0001, // BLOCK_4X8 - 0x0001, // BLOCK_8X4 - 0x0001, // BLOCK_8X8 - 0x0001, // BLOCK_8X16, - 0x0001, // BLOCK_16X8 - 0x0001, // BLOCK_16X16 - 0x0001, // BLOCK_16X32, - 0x0003, // BLOCK_32X16, - 0x0003, // BLOCK_32X32, - 0x0003, // BLOCK_32X64, - 0x000f, // BLOCK_64X32, - 0x000f, // BLOCK_64X64 + private static readonly ushort[] _abovePredictionMaskUv = { + 0x0001, // BLOCK_4X4 + 0x0001, // BLOCK_4X8 + 0x0001, // BLOCK_8X4 + 0x0001, // BLOCK_8X8 + 0x0001, // BLOCK_8X16, + 0x0001, // BLOCK_16X8 + 0x0001, // BLOCK_16X16 + 0x0001, // BLOCK_16X32, + 0x0003, // BLOCK_32X16, + 0x0003, // BLOCK_32X32, + 0x0003, // BLOCK_32X64, + 0x000f, // BLOCK_64X32, + 0x000f, // BLOCK_64X64 }; // 64 bit mask to shift and set for each uv prediction size - private static readonly ushort[] SizeMaskUv = new ushort[] - { - 0x0001, // BLOCK_4X4 - 0x0001, // BLOCK_4X8 - 0x0001, // BLOCK_8X4 - 0x0001, // BLOCK_8X8 - 0x0001, // BLOCK_8X16, - 0x0001, // BLOCK_16X8 - 0x0001, // BLOCK_16X16 - 0x0011, // BLOCK_16X32, - 0x0003, // BLOCK_32X16, - 0x0033, // BLOCK_32X32, - 0x3333, // BLOCK_32X64, - 0x00ff, // BLOCK_64X32, - 0xffff, // BLOCK_64X64 + private static readonly ushort[] _sizeMaskUv = { + 0x0001, // BLOCK_4X4 + 0x0001, // BLOCK_4X8 + 0x0001, // BLOCK_8X4 + 0x0001, // BLOCK_8X8 + 0x0001, // BLOCK_8X16, + 0x0001, // BLOCK_16X8 + 0x0001, // BLOCK_16X16 + 0x0011, // BLOCK_16X32, + 0x0003, // BLOCK_32X16, + 0x0033, // BLOCK_32X32, + 0x3333, // BLOCK_32X64, + 0x00ff, // BLOCK_64X32, + 0xffff, // BLOCK_64X64 }; +#pragma warning disable IDE0051 // Remove unused private member private const ushort LeftBorderUv = 0x1111; private const ushort AboveBorderUv = 0x000f; +#pragma warning restore IDE0051 - private static readonly int[] ModeLfLut = new int[] - { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // INTRA_MODES - 1, 1, 0, 1 // INTER_MODES (ZEROMV == 0) + private static readonly int[] _modeLfLut = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // INTRA_MODES + 1, 1, 0, 1, // INTER_MODES (ZEROMV == 0) }; private static byte GetFilterLevel(ref LoopFilterInfoN lfiN, ref ModeInfo mi) { - return lfiN.Lvl[mi.SegmentId][mi.RefFrame[0]][ModeLfLut[(int)mi.Mode]]; + return lfiN.Lvl[mi.SegmentId][mi.RefFrame[0]][_modeLfLut[(int)mi.Mode]]; } private static ref LoopFilterMask GetLfm(ref Types.LoopFilter lf, int miRow, int miCol) @@ -229,12 +222,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // 8x8 blocks in a superblock. A "1" represents the first block in a 16x16 // or greater area. - private static readonly byte[][] FirstBlockIn16x16 = new byte[][] - { + private static readonly byte[][] _firstBlockIn16X16 = { + new byte[] { 1, 0, 1, 0, 1, 0, 1, 0 }, new byte[] { 0, 0, 0, 0, 0, 0, 0, 0 }, new byte[] { 1, 0, 1, 0, 1, 0, 1, 0 }, new byte[] { 0, 0, 0, 0, 0, 0, 0, 0 }, new byte[] { 1, 0, 1, 0, 1, 0, 1, 0 }, new byte[] { 0, 0, 0, 0, 0, 0, 0, 0 }, new byte[] { 1, 0, 1, 0, 1, 0, 1, 0 }, new byte[] { 0, 0, 0, 0, 0, 0, 0, 0 }, - new byte[] { 1, 0, 1, 0, 1, 0, 1, 0 }, new byte[] { 0, 0, 0, 0, 0, 0, 0, 0 } }; // This function sets up the bit masks for a block represented @@ -257,21 +249,19 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int colInSb = (miCol & 7); int shiftY = colInSb + (rowInSb << 3); int shiftUv = (colInSb >> 1) + ((rowInSb >> 1) << 2); - int buildUv = FirstBlockIn16x16[rowInSb][colInSb]; + int buildUv = _firstBlockIn16X16[rowInSb][colInSb]; if (filterLevel == 0) { return; } - else + + int index = shiftY; + int i; + for (i = 0; i < bh; i++) { - int index = shiftY; - int i; - for (i = 0; i < bh; i++) - { - MemoryMarshal.CreateSpan(ref lfm.LflY[index], 64 - index).Slice(0, bw).Fill((byte)filterLevel); - index += 8; - } + MemoryMarshal.CreateSpan(ref lfm.LflY[index], 64 - index)[..bw].Fill((byte)filterLevel); + index += 8; } // These set 1 in the current block size for the block size edges. @@ -286,13 +276,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // // U and V set things on a 16 bit scale. // - aboveY |= AbovePredictionMask[(int)blockSize] << shiftY; - leftY |= LeftPredictionMask[(int)blockSize] << shiftY; + aboveY |= _abovePredictionMask[(int)blockSize] << shiftY; + leftY |= _leftPredictionMask[(int)blockSize] << shiftY; if (buildUv != 0) { - aboveUv |= (ushort)(AbovePredictionMaskUv[(int)blockSize] << shiftUv); - leftUv |= (ushort)(LeftPredictionMaskUv[(int)blockSize] << shiftUv); + aboveUv |= (ushort)(_abovePredictionMaskUv[(int)blockSize] << shiftUv); + leftUv |= (ushort)(_leftPredictionMaskUv[(int)blockSize] << shiftUv); } // If the block has no coefficients and is not intra we skip applying @@ -305,13 +295,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Add a mask for the transform size. The transform size mask is set to // be correct for a 64x64 prediction block size. Mask to match the size of // the block we are working on and then shift it into place. - aboveY |= (SizeMask[(int)blockSize] & Above64X64TxformMask[(int)txSizeY]) << shiftY; - leftY |= (SizeMask[(int)blockSize] & Left64X64TxformMask[(int)txSizeY]) << shiftY; + aboveY |= (_sizeMask[(int)blockSize] & _above64X64TxformMask[(int)txSizeY]) << shiftY; + leftY |= (_sizeMask[(int)blockSize] & _left64X64TxformMask[(int)txSizeY]) << shiftY; if (buildUv != 0) { - aboveUv |= (ushort)((SizeMaskUv[(int)blockSize] & Above64X64TxformMaskUv[(int)txSizeUv]) << shiftUv); - leftUv |= (ushort)((SizeMaskUv[(int)blockSize] & Left64X64TxformMaskUv[(int)txSizeUv]) << shiftUv); + aboveUv |= (ushort)((_sizeMaskUv[(int)blockSize] & _above64X64TxformMaskUv[(int)txSizeUv]) << shiftUv); + leftUv |= (ushort)((_sizeMaskUv[(int)blockSize] & _left64X64TxformMaskUv[(int)txSizeUv]) << shiftUv); } // Try to determine what to do with the internal 4x4 block boundaries. These @@ -319,12 +309,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // internal ones can be skipped and don't depend on the prediction block size. if (txSizeY == TxSize.Tx4x4) { - int4X4Y |= SizeMask[(int)blockSize] << shiftY; + int4X4Y |= _sizeMask[(int)blockSize] << shiftY; } if (buildUv != 0 && txSizeUv == TxSize.Tx4x4) { - int4X4Uv |= (ushort)((SizeMaskUv[(int)blockSize] & 0xffff) << shiftUv); + int4X4Uv |= (ushort)((_sizeMaskUv[(int)blockSize] & 0xffff) << shiftUv); } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Luts.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Luts.cs index 140181ef8..7320c0943 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Luts.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Luts.cs @@ -8,175 +8,170 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { public static ReadOnlySpan SizeGroupLookup => new byte[] { 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3 }; - public static readonly BlockSize[][] SubsizeLookup = new BlockSize[][] - { - new BlockSize[] + public static readonly BlockSize[][] SubsizeLookup = { + new[] { // PARTITION_NONE BlockSize.Block4x4, BlockSize.Block4x8, BlockSize.Block8x4, BlockSize.Block8x8, BlockSize.Block8x16, BlockSize.Block16x8, BlockSize.Block16x16, BlockSize.Block16x32, BlockSize.Block32x16, BlockSize.Block32x32, BlockSize.Block32x64, - BlockSize.Block64x32, BlockSize.Block64x64 + BlockSize.Block64x32, BlockSize.Block64x64, }, - new BlockSize[] + new[] { // PARTITION_HORZ BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block8x4, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block16x8, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block32x16, - BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block64x32 + BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block64x32, }, - new BlockSize[] + new[] { // PARTITION_VERT BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block4x8, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block8x16, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block16x32, - BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block32x64 + BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block32x64, }, - new BlockSize[] + new[] { // PARTITION_SPLIT BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block4x4, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block8x8, BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block16x16, - BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block32x32 - } + BlockSize.BlockInvalid, BlockSize.BlockInvalid, BlockSize.Block32x32, + }, }; - public static readonly TxSize[] MaxTxSizeLookup = new TxSize[] - { + public static readonly TxSize[] MaxTxSizeLookup = { TxSize.Tx4x4, TxSize.Tx4x4, TxSize.Tx4x4, TxSize.Tx8x8, TxSize.Tx8x8, TxSize.Tx8x8, TxSize.Tx16x16, - TxSize.Tx16x16, TxSize.Tx16x16, TxSize.Tx32x32, TxSize.Tx32x32, TxSize.Tx32x32, TxSize.Tx32x32 + TxSize.Tx16x16, TxSize.Tx16x16, TxSize.Tx32x32, TxSize.Tx32x32, TxSize.Tx32x32, TxSize.Tx32x32, }; - public static readonly TxSize[] TxModeToBiggestTxSize = new TxSize[] - { - TxSize.Tx4x4, // ONLY_4X4 - TxSize.Tx8x8, // ALLOW_8X8 - TxSize.Tx16x16, // ALLOW_16X16 - TxSize.Tx32x32, // ALLOW_32X32 - TxSize.Tx32x32, // TX_MODE_SELECT + public static readonly TxSize[] TxModeToBiggestTxSize = { + TxSize.Tx4x4, // ONLY_4X4 + TxSize.Tx8x8, // ALLOW_8X8 + TxSize.Tx16x16, // ALLOW_16X16 + TxSize.Tx32x32, // ALLOW_32X32 + TxSize.Tx32x32, // TX_MODE_SELECT }; - public static readonly BlockSize[][][] SsSizeLookup = new BlockSize[][][] - { + public static readonly BlockSize[][][] SsSizeLookup = { // ss_x == 0 ss_x == 0 ss_x == 1 ss_x == 1 // ss_y == 0 ss_y == 1 ss_y == 0 ss_y == 1 - new BlockSize[][] { new BlockSize[] { BlockSize.Block4x4, BlockSize.BlockInvalid }, new BlockSize[] { BlockSize.BlockInvalid, BlockSize.BlockInvalid } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block4x8, BlockSize.Block4x4 }, new BlockSize[] { BlockSize.BlockInvalid, BlockSize.BlockInvalid } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block8x4, BlockSize.BlockInvalid }, new BlockSize[] { BlockSize.Block4x4, BlockSize.BlockInvalid } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block8x8, BlockSize.Block8x4 }, new BlockSize[] { BlockSize.Block4x8, BlockSize.Block4x4 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block8x16, BlockSize.Block8x8 }, new BlockSize[] { BlockSize.BlockInvalid, BlockSize.Block4x8 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block16x8, BlockSize.BlockInvalid }, new BlockSize[] { BlockSize.Block8x8, BlockSize.Block8x4 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block16x16, BlockSize.Block16x8 }, new BlockSize[] { BlockSize.Block8x16, BlockSize.Block8x8 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block16x32, BlockSize.Block16x16 }, new BlockSize[] { BlockSize.BlockInvalid, BlockSize.Block8x16 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block32x16, BlockSize.BlockInvalid }, new BlockSize[] { BlockSize.Block16x16, BlockSize.Block16x8 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block32x32, BlockSize.Block32x16 }, new BlockSize[] { BlockSize.Block16x32, BlockSize.Block16x16 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block32x64, BlockSize.Block32x32 }, new BlockSize[] { BlockSize.BlockInvalid, BlockSize.Block16x32 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block64x32, BlockSize.BlockInvalid }, new BlockSize[] { BlockSize.Block32x32, BlockSize.Block32x16 } }, - new BlockSize[][] { new BlockSize[] { BlockSize.Block64x64, BlockSize.Block64x32 }, new BlockSize[] { BlockSize.Block32x64, BlockSize.Block32x32 } }, + new[] { new[] { BlockSize.Block4x4, BlockSize.BlockInvalid }, new[] { BlockSize.BlockInvalid, BlockSize.BlockInvalid } }, + new[] { new[] { BlockSize.Block4x8, BlockSize.Block4x4 }, new[] { BlockSize.BlockInvalid, BlockSize.BlockInvalid } }, + new[] { new[] { BlockSize.Block8x4, BlockSize.BlockInvalid }, new[] { BlockSize.Block4x4, BlockSize.BlockInvalid } }, + new[] { new[] { BlockSize.Block8x8, BlockSize.Block8x4 }, new[] { BlockSize.Block4x8, BlockSize.Block4x4 } }, + new[] { new[] { BlockSize.Block8x16, BlockSize.Block8x8 }, new[] { BlockSize.BlockInvalid, BlockSize.Block4x8 } }, + new[] { new[] { BlockSize.Block16x8, BlockSize.BlockInvalid }, new[] { BlockSize.Block8x8, BlockSize.Block8x4 } }, + new[] { new[] { BlockSize.Block16x16, BlockSize.Block16x8 }, new[] { BlockSize.Block8x16, BlockSize.Block8x8 } }, + new[] { new[] { BlockSize.Block16x32, BlockSize.Block16x16 }, new[] { BlockSize.BlockInvalid, BlockSize.Block8x16 } }, + new[] { new[] { BlockSize.Block32x16, BlockSize.BlockInvalid }, new[] { BlockSize.Block16x16, BlockSize.Block16x8 } }, + new[] { new[] { BlockSize.Block32x32, BlockSize.Block32x16 }, new[] { BlockSize.Block16x32, BlockSize.Block16x16 } }, + new[] { new[] { BlockSize.Block32x64, BlockSize.Block32x32 }, new[] { BlockSize.BlockInvalid, BlockSize.Block16x32 } }, + new[] { new[] { BlockSize.Block64x32, BlockSize.BlockInvalid }, new[] { BlockSize.Block32x32, BlockSize.Block32x16 } }, + new[] { new[] { BlockSize.Block64x64, BlockSize.Block64x32 }, new[] { BlockSize.Block32x64, BlockSize.Block32x32 } }, }; - public static readonly TxSize[][][][] UvTxsizeLookup = new TxSize[][][][] - { + public static readonly TxSize[][][][] UvTxsizeLookup = { // ss_x == 0 ss_x == 0 ss_x == 1 ss_x == 1 // ss_y == 0 ss_y == 1 ss_y == 0 ss_y == 1 - new TxSize[][][] + new[] { // BLOCK_4X4 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, }, - new TxSize[][][] + new[] { // BLOCK_4X8 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, }, - new TxSize[][][] + new[] { // BLOCK_8X4 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, }, - new TxSize[][][] + new[] { // BLOCK_8X8 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, }, - new TxSize[][][] + new[] { // BLOCK_8X16 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, }, - new TxSize[][][] + new[] { // BLOCK_16X8 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx8x8, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx4x4 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, }, - new TxSize[][][] + new[] { // BLOCK_16X16 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, }, - new TxSize[][][] + new[] { // BLOCK_16X32 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, }, - new TxSize[][][] + new[] { // BLOCK_32X16 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new[] { TxSize.Tx16x16, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx8x8 }, new[] { TxSize.Tx16x16, TxSize.Tx8x8 } }, }, - new TxSize[][][] + new[] { // BLOCK_32X32 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx32x32, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx32x32, TxSize.Tx16x16 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, }, - new TxSize[][][] + new[] { // BLOCK_32X64 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx32x32, TxSize.Tx32x32 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx32x32, TxSize.Tx32x32 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, }, - new TxSize[][][] + new[] { // BLOCK_64X32 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx32x32, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx32x32, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx32x32, TxSize.Tx16x16 }, new[] { TxSize.Tx32x32, TxSize.Tx16x16 } }, }, - new TxSize[][][] + new[] { // BLOCK_64X64 - new TxSize[][] { new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new TxSize[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new TxSize[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new TxSize[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, - new TxSize[][] { new TxSize[] { TxSize.Tx32x32, TxSize.Tx32x32 }, new TxSize[] { TxSize.Tx32x32, TxSize.Tx32x32 } }, + new[] { new[] { TxSize.Tx4x4, TxSize.Tx4x4 }, new[] { TxSize.Tx4x4, TxSize.Tx4x4 } }, + new[] { new[] { TxSize.Tx8x8, TxSize.Tx8x8 }, new[] { TxSize.Tx8x8, TxSize.Tx8x8 } }, + new[] { new[] { TxSize.Tx16x16, TxSize.Tx16x16 }, new[] { TxSize.Tx16x16, TxSize.Tx16x16 } }, + new[] { new[] { TxSize.Tx32x32, TxSize.Tx32x32 }, new[] { TxSize.Tx32x32, TxSize.Tx32x32 } }, }, }; @@ -195,27 +190,25 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Generates 4 bit field in which each bit set to 1 represents // a blocksize partition 1111 means we split 64x64, 32x32, 16x16 // and 8x8. 1000 means we just split the 64x64 to 32x32 - public static readonly PartitionContextPair[] PartitionContextLookup = new PartitionContextPair[] - { - new PartitionContextPair(15, 15), // 4X4 - {0b1111, 0b1111} - new PartitionContextPair(15, 14), // 4X8 - {0b1111, 0b1110} - new PartitionContextPair(14, 15), // 8X4 - {0b1110, 0b1111} - new PartitionContextPair(14, 14), // 8X8 - {0b1110, 0b1110} - new PartitionContextPair(14, 12), // 8X16 - {0b1110, 0b1100} - new PartitionContextPair(12, 14), // 16X8 - {0b1100, 0b1110} - new PartitionContextPair(12, 12), // 16X16 - {0b1100, 0b1100} - new PartitionContextPair(12, 8), // 16X32 - {0b1100, 0b1000} - new PartitionContextPair(8, 12), // 32X16 - {0b1000, 0b1100} - new PartitionContextPair(8, 8), // 32X32 - {0b1000, 0b1000} - new PartitionContextPair(8, 0), // 32X64 - {0b1000, 0b0000} - new PartitionContextPair(0, 8), // 64X32 - {0b0000, 0b1000} - new PartitionContextPair(0, 0), // 64X64 - {0b0000, 0b0000} + public static readonly PartitionContextPair[] PartitionContextLookup = { + new(15, 15), // 4X4 - {0b1111, 0b1111} + new(15, 14), // 4X8 - {0b1111, 0b1110} + new(14, 15), // 8X4 - {0b1110, 0b1111} + new(14, 14), // 8X8 - {0b1110, 0b1110} + new(14, 12), // 8X16 - {0b1110, 0b1100} + new(12, 14), // 16X8 - {0b1100, 0b1110} + new(12, 12), // 16X16 - {0b1100, 0b1100} + new(12, 8), // 16X32 - {0b1100, 0b1000} + new(8, 12), // 32X16 - {0b1000, 0b1100} + new(8, 8), // 32X32 - {0b1000, 0b1000} + new(8, 0), // 32X64 - {0b1000, 0b0000} + new(0, 8), // 64X32 - {0b0000, 0b1000} + new(0, 0), // 64X64 - {0b0000, 0b0000} }; // Filter - private static readonly Array8[] BilinearFilters = new Array8[] - { + private static readonly Array8[] _bilinearFilters = { NewArray8Short(0, 0, 0, 128, 0, 0, 0, 0), NewArray8Short(0, 0, 0, 120, 8, 0, 0, 0), NewArray8Short(0, 0, 0, 112, 16, 0, 0, 0), NewArray8Short(0, 0, 0, 104, 24, 0, 0, 0), NewArray8Short(0, 0, 0, 96, 32, 0, 0, 0), NewArray8Short(0, 0, 0, 88, 40, 0, 0, 0), @@ -223,12 +216,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 NewArray8Short(0, 0, 0, 64, 64, 0, 0, 0), NewArray8Short(0, 0, 0, 56, 72, 0, 0, 0), NewArray8Short(0, 0, 0, 48, 80, 0, 0, 0), NewArray8Short(0, 0, 0, 40, 88, 0, 0, 0), NewArray8Short(0, 0, 0, 32, 96, 0, 0, 0), NewArray8Short(0, 0, 0, 24, 104, 0, 0, 0), - NewArray8Short(0, 0, 0, 16, 112, 0, 0, 0), NewArray8Short(0, 0, 0, 8, 120, 0, 0, 0) + NewArray8Short(0, 0, 0, 16, 112, 0, 0, 0), NewArray8Short(0, 0, 0, 8, 120, 0, 0, 0), }; // Lagrangian interpolation filter - private static readonly Array8[] SubPelFilters8 = new Array8[] - { + private static readonly Array8[] _subPelFilters8 = { NewArray8Short(0, 0, 0, 128, 0, 0, 0, 0), NewArray8Short(0, 1, -5, 126, 8, -3, 1, 0), NewArray8Short(-1, 3, -10, 122, 18, -6, 2, 0), NewArray8Short(-1, 4, -13, 118, 27, -9, 3, -1), NewArray8Short(-1, 4, -16, 112, 37, -11, 4, -1), NewArray8Short(-1, 5, -18, 105, 48, -14, 4, -1), @@ -236,12 +228,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 NewArray8Short(-1, 6, -19, 78, 78, -19, 6, -1), NewArray8Short(-1, 5, -18, 68, 88, -19, 6, -1), NewArray8Short(-1, 5, -16, 58, 97, -19, 5, -1), NewArray8Short(-1, 4, -14, 48, 105, -18, 5, -1), NewArray8Short(-1, 4, -11, 37, 112, -16, 4, -1), NewArray8Short(-1, 3, -9, 27, 118, -13, 4, -1), - NewArray8Short(0, 2, -6, 18, 122, -10, 3, -1), NewArray8Short(0, 1, -3, 8, 126, -5, 1, 0) + NewArray8Short(0, 2, -6, 18, 122, -10, 3, -1), NewArray8Short(0, 1, -3, 8, 126, -5, 1, 0), }; // DCT based filter - private static readonly Array8[] SubPelFilters8S = new Array8[] - { + private static readonly Array8[] _subPelFilters8S = { NewArray8Short(0, 0, 0, 128, 0, 0, 0, 0), NewArray8Short(-1, 3, -7, 127, 8, -3, 1, 0), NewArray8Short(-2, 5, -13, 125, 17, -6, 3, -1), NewArray8Short(-3, 7, -17, 121, 27, -10, 5, -2), NewArray8Short(-4, 9, -20, 115, 37, -13, 6, -2), NewArray8Short(-4, 10, -23, 108, 48, -16, 8, -3), @@ -249,12 +240,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 NewArray8Short(-4, 11, -23, 80, 80, -23, 11, -4), NewArray8Short(-4, 10, -21, 70, 90, -24, 11, -4), NewArray8Short(-3, 9, -19, 59, 100, -24, 10, -4), NewArray8Short(-3, 8, -16, 48, 108, -23, 10, -4), NewArray8Short(-2, 6, -13, 37, 115, -20, 9, -4), NewArray8Short(-2, 5, -10, 27, 121, -17, 7, -3), - NewArray8Short(-1, 3, -6, 17, 125, -13, 5, -2), NewArray8Short(0, 1, -3, 8, 127, -7, 3, -1) + NewArray8Short(-1, 3, -6, 17, 125, -13, 5, -2), NewArray8Short(0, 1, -3, 8, 127, -7, 3, -1), }; // freqmultiplier = 0.5 - private static readonly Array8[] SubPelFilters8Lp = new Array8[] - { + private static readonly Array8[] _subPelFilters8Lp = { NewArray8Short(0, 0, 0, 128, 0, 0, 0, 0), NewArray8Short(-3, -1, 32, 64, 38, 1, -3, 0), NewArray8Short(-2, -2, 29, 63, 41, 2, -3, 0), NewArray8Short(-2, -2, 26, 63, 43, 4, -4, 0), NewArray8Short(-2, -3, 24, 62, 46, 5, -4, 0), NewArray8Short(-2, -3, 21, 60, 49, 7, -4, 0), @@ -262,12 +252,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 NewArray8Short(-1, -4, 14, 55, 55, 14, -4, -1), NewArray8Short(-1, -4, 12, 53, 57, 16, -4, -1), NewArray8Short(0, -4, 9, 51, 59, 18, -4, -1), NewArray8Short(0, -4, 7, 49, 60, 21, -3, -2), NewArray8Short(0, -4, 5, 46, 62, 24, -3, -2), NewArray8Short(0, -4, 4, 43, 63, 26, -2, -2), - NewArray8Short(0, -3, 2, 41, 63, 29, -2, -2), NewArray8Short(0, -3, 1, 38, 64, 32, -1, -3) + NewArray8Short(0, -3, 2, 41, 63, 29, -2, -2), NewArray8Short(0, -3, 1, 38, 64, 32, -1, -3), }; private static Array8 NewArray8Short(short e0, short e1, short e2, short e3, short e4, short e5, short e6, short e7) { - Array8 output = new Array8(); + Array8 output = new(); output[0] = e0; output[1] = e1; @@ -281,54 +271,46 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 return output; } - public static readonly Array8[][] Vp9FilterKernels = new Array8[][] - { - SubPelFilters8, SubPelFilters8Lp, SubPelFilters8S, BilinearFilters + public static readonly Array8[][] Vp9FilterKernels = { + _subPelFilters8, _subPelFilters8Lp, _subPelFilters8S, _bilinearFilters, }; // Scan - private static readonly short[] DefaultScan4X4 = new short[] - { + private static readonly short[] _defaultScan4X4 = { 0, 4, 1, 5, 8, 2, 12, 9, 3, 6, 13, 10, 7, 14, 11, 15, }; - private static readonly short[] ColScan4X4 = new short[] - { + private static readonly short[] _colScan4X4 = { 0, 4, 8, 1, 12, 5, 9, 2, 13, 6, 10, 3, 7, 14, 11, 15, }; - private static readonly short[] RowScan4X4 = new short[] - { + private static readonly short[] _rowScan4X4 = { 0, 1, 4, 2, 5, 3, 6, 8, 9, 7, 12, 10, 13, 11, 14, 15, }; - private static readonly short[] DefaultScan8X8 = new short[] - { + private static readonly short[] _defaultScan8X8 = { 0, 8, 1, 16, 9, 2, 17, 24, 10, 3, 18, 25, 32, 11, 4, 26, 33, 19, 40, 12, 34, 27, 5, 41, 20, 48, 13, 35, 42, 28, 21, 6, 49, 56, 36, 43, 29, 7, 14, 50, 57, 44, 22, 37, 15, 51, 58, 30, 45, 23, 52, 59, 38, 31, 60, 53, 46, 39, 61, 54, 47, 62, 55, 63, }; - private static readonly short[] ColScan8X8 = new short[] - { + private static readonly short[] _colScan8X8 = { 0, 8, 16, 1, 24, 9, 32, 17, 2, 40, 25, 10, 33, 18, 48, 3, 26, 41, 11, 56, 19, 34, 4, 49, 27, 42, 12, 35, 20, 57, 50, 28, 5, 43, 13, 36, 58, 51, 21, 44, 6, 29, 59, 37, 14, 52, 22, 7, 45, 60, 30, 15, 38, 53, 23, 46, 31, 61, 39, 54, 47, 62, 55, 63, }; - private static readonly short[] RowScan8X8 = new short[] - { + private static readonly short[] _rowScan8X8 = { 0, 1, 2, 8, 9, 3, 16, 10, 4, 17, 11, 24, 5, 18, 25, 12, 19, 26, 32, 6, 13, 20, 33, 27, 7, 34, 40, 21, 28, 41, 14, 35, 48, 42, 29, 36, 49, 22, 43, 15, 56, 37, 50, 44, 30, 57, 23, 51, 58, 45, 38, 52, 31, 59, 53, 46, 60, 39, 61, 47, 54, 55, 62, 63, }; - private static readonly short[] DefaultScan16X16 = new short[] - { + private static readonly short[] _defaultScan16X16 = { 0, 16, 1, 32, 17, 2, 48, 33, 18, 3, 64, 34, 49, 19, 65, 80, 50, 4, 35, 66, 20, 81, 96, 51, 5, 36, 82, 97, 67, 112, 21, 52, 98, 37, 83, 113, 6, 68, 128, 53, 22, 99, 114, 84, 7, @@ -349,8 +331,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 255, }; - private static readonly short[] ColScan16X16 = new short[] - { + private static readonly short[] _colScan16X16 = { 0, 16, 32, 48, 1, 64, 17, 80, 33, 96, 49, 2, 65, 112, 18, 81, 34, 128, 50, 97, 3, 66, 144, 19, 113, 35, 82, 160, 98, 51, 129, 4, 67, 176, 20, 114, 145, 83, 36, 99, 130, 52, 192, 5, 161, @@ -371,8 +352,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 255, }; - private static readonly short[] RowScan16X16 = new short[] - { + private static readonly short[] _rowScan16X16 = { 0, 1, 2, 16, 3, 17, 4, 18, 32, 5, 33, 19, 6, 34, 48, 20, 49, 7, 35, 21, 50, 64, 8, 36, 65, 22, 51, 37, 80, 9, 66, 52, 23, 38, 81, 67, 10, 53, 24, 82, 68, 96, 39, 11, 54, @@ -393,8 +373,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 255, }; - private static readonly short[] DefaultScan32X32 = new short[] - { + private static readonly short[] _defaultScan32X32 = { 0, 32, 1, 64, 33, 2, 96, 65, 34, 128, 3, 97, 66, 160, 129, 35, 98, 4, 67, 130, 161, 192, 36, 99, 224, 5, 162, 193, 68, 131, 37, 100, 225, 194, 256, 163, 69, 132, 6, @@ -478,26 +457,22 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // Neighborhood 2-tuples for various scans and blocksizes, // in {top, left} order for each position in corresponding scan order. - private static readonly short[] DefaultScan4X4Neighbors = new short[] - { + private static readonly short[] _defaultScan4X4Neighbors = { 0, 0, 0, 0, 0, 0, 1, 4, 4, 4, 1, 1, 8, 8, 5, 8, 2, 2, 2, 5, 9, 12, 6, 9, 3, 6, 10, 13, 7, 10, 11, 14, 0, 0, }; - private static readonly short[] ColScan4X4Neighbors = new short[] - { + private static readonly short[] _colScan4X4Neighbors = { 0, 0, 0, 0, 4, 4, 0, 0, 8, 8, 1, 1, 5, 5, 1, 1, 9, 9, 2, 2, 6, 6, 2, 2, 3, 3, 10, 10, 7, 7, 11, 11, 0, 0, }; - private static readonly short[] RowScan4X4Neighbors = new short[] - { + private static readonly short[] _rowScan4X4Neighbors = { 0, 0, 0, 0, 0, 0, 1, 1, 4, 4, 2, 2, 5, 5, 4, 4, 8, 8, 6, 6, 8, 8, 9, 9, 12, 12, 10, 10, 13, 13, 14, 14, 0, 0, }; - private static readonly short[] ColScan8X8Neighbors = new short[] - { + private static readonly short[] _colScan8X8Neighbors = { 0, 0, 0, 0, 8, 8, 0, 0, 16, 16, 1, 1, 24, 24, 9, 9, 1, 1, 32, 32, 17, 17, 2, 2, 25, 25, 10, 10, 40, 40, 2, 2, 18, 18, 33, 33, 3, 3, 48, 48, 11, 11, 26, 26, 3, 3, 41, 41, 19, 19, 34, 34, 4, 4, 27, 27, 12, @@ -507,8 +482,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 53, 53, 31, 31, 46, 46, 39, 39, 54, 54, 47, 47, 55, 55, 0, 0, }; - private static readonly short[] RowScan8X8Neighbors = new short[] - { + private static readonly short[] _rowScan8X8Neighbors = { 0, 0, 0, 0, 1, 1, 0, 0, 8, 8, 2, 2, 8, 8, 9, 9, 3, 3, 16, 16, 10, 10, 16, 16, 4, 4, 17, 17, 24, 24, 11, 11, 18, 18, 25, 25, 24, 24, 5, 5, 12, 12, 19, 19, 32, 32, 26, 26, 6, 6, 33, 33, 32, 32, 20, 20, 27, @@ -518,8 +492,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 38, 38, 60, 60, 46, 46, 53, 53, 54, 54, 61, 61, 62, 62, 0, 0, }; - private static readonly short[] DefaultScan8X8Neighbors = new short[] - { + private static readonly short[] _defaultScan8X8Neighbors = { 0, 0, 0, 0, 0, 0, 8, 8, 1, 8, 1, 1, 9, 16, 16, 16, 2, 9, 2, 2, 10, 17, 17, 24, 24, 24, 3, 10, 3, 3, 18, 25, 25, 32, 11, 18, 32, 32, 4, 11, 26, 33, 19, 26, 4, 4, 33, 40, 12, 19, 40, 40, 5, 12, 27, 34, 34, @@ -529,8 +502,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 31, 38, 53, 60, 46, 53, 39, 46, 54, 61, 47, 54, 55, 62, 0, 0, }; - private static readonly short[] ColScan16X16Neighbors = new short[] - { + private static readonly short[] _colScan16X16Neighbors = { 0, 0, 0, 0, 16, 16, 32, 32, 0, 0, 48, 48, 1, 1, 64, 64, 17, 17, 80, 80, 33, 33, 1, 1, 49, 49, 96, 96, 2, 2, 65, 65, 18, 18, 112, 112, 34, 34, 81, 81, 2, 2, 50, 50, 128, @@ -568,8 +540,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 239, 239, 0, 0, }; - private static readonly short[] RowScan16X16Neighbors = new short[] - { + private static readonly short[] _rowScan16X16Neighbors = { 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 16, 16, 3, 3, 17, 17, 16, 16, 4, 4, 32, 32, 18, 18, 5, 5, 33, 33, 32, 32, 19, 19, 48, 48, 6, 6, 34, 34, 20, 20, 49, 49, 48, 48, 7, @@ -607,8 +578,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 254, 254, 0, 0, }; - private static readonly short[] DefaultScan16X16Neighbors = new short[] - { + private static readonly short[] _defaultScan16X16Neighbors = { 0, 0, 0, 0, 0, 0, 16, 16, 1, 16, 1, 1, 32, 32, 17, 32, 2, 17, 2, 2, 48, 48, 18, 33, 33, 48, 3, 18, 49, 64, 64, 64, 34, 49, 3, 3, 19, 34, 50, 65, 4, 19, 65, 80, 80, @@ -646,8 +616,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 239, 254, 0, 0, }; - private static readonly short[] DefaultScan32X32Neighbors = new short[] - { + private static readonly short[] _defaultScan32X32Neighbors = { 0, 0, 0, 0, 0, 0, 32, 32, 1, 32, 1, 1, 64, 64, 33, 64, 2, 33, 96, 96, 2, 2, 65, 96, 34, 65, 128, 128, 97, 128, 3, 34, 66, 97, 3, 3, 35, 66, 98, 129, 129, 160, @@ -797,47 +766,40 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 959, 990, 991, 1022, 0, 0, }; - private static readonly short[] Vp9DefaultIscan4X4 = new short[] - { + private static readonly short[] _vp9DefaultIscan4X4 = { 0, 2, 5, 8, 1, 3, 9, 12, 4, 7, 11, 14, 6, 10, 13, 15, }; - private static readonly short[] Vp9ColIscan4X4 = new short[] - { + private static readonly short[] _vp9ColIscan4X4 = { 0, 3, 7, 11, 1, 5, 9, 12, 2, 6, 10, 14, 4, 8, 13, 15, }; - private static readonly short[] Vp9RowIscan4X4 = new short[] - { + private static readonly short[] _vp9RowIscan4X4 = { 0, 1, 3, 5, 2, 4, 6, 9, 7, 8, 11, 13, 10, 12, 14, 15, }; - private static readonly short[] Vp9ColIscan8X8 = new short[] - { + private static readonly short[] _vp9ColIscan8X8 = { 0, 3, 8, 15, 22, 32, 40, 47, 1, 5, 11, 18, 26, 34, 44, 51, 2, 7, 13, 20, 28, 38, 46, 54, 4, 10, 16, 24, 31, 41, 50, 56, 6, 12, 21, 27, 35, 43, 52, 58, 9, 17, 25, 33, 39, 48, 55, 60, 14, 23, 30, 37, 45, 53, 59, 62, 19, 29, 36, 42, 49, 57, 61, 63, }; - private static readonly short[] Vp9RowIscan8X8 = new short[] - { + private static readonly short[] _vp9RowIscan8X8 = { 0, 1, 2, 5, 8, 12, 19, 24, 3, 4, 7, 10, 15, 20, 30, 39, 6, 9, 13, 16, 21, 27, 37, 46, 11, 14, 17, 23, 28, 34, 44, 52, 18, 22, 25, 31, 35, 41, 50, 57, 26, 29, 33, 38, 43, 49, 55, 59, 32, 36, 42, 47, 51, 54, 60, 61, 40, 45, 48, 53, 56, 58, 62, 63, }; - private static readonly short[] Vp9DefaultIscan8X8 = new short[] - { + private static readonly short[] _vp9DefaultIscan8X8 = { 0, 2, 5, 9, 14, 22, 31, 37, 1, 4, 8, 13, 19, 26, 38, 44, 3, 6, 10, 17, 24, 30, 42, 49, 7, 11, 15, 21, 29, 36, 47, 53, 12, 16, 20, 27, 34, 43, 52, 57, 18, 23, 28, 35, 41, 48, 56, 60, 25, 32, 39, 45, 50, 55, 59, 62, 33, 40, 46, 51, 54, 58, 61, 63, }; - private static readonly short[] Vp9ColIscan16X16 = new short[] - { + private static readonly short[] _vp9ColIscan16X16 = { 0, 4, 11, 20, 31, 43, 59, 75, 85, 109, 130, 150, 165, 181, 195, 198, 1, 6, 14, 23, 34, 47, 64, 81, 95, 114, 135, 153, 171, 188, 201, 212, 2, 8, 16, 25, 38, 52, 67, 83, 101, 116, 136, 157, 172, 190, 205, 216, @@ -856,8 +818,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 65, 88, 107, 124, 139, 152, 163, 177, 185, 199, 221, 234, 243, 248, 252, 255, }; - private static readonly short[] Vp9RowIscan16X16 = new short[] - { + private static readonly short[] _vp9RowIscan16X16 = { 0, 1, 2, 4, 6, 9, 12, 17, 22, 29, 36, 43, 54, 64, 76, 86, 3, 5, 7, 11, 15, 19, 25, 32, 38, 48, 59, 68, 84, 99, 115, 130, 8, 10, 13, 18, 23, 27, 33, 42, 51, 60, 72, 88, 103, @@ -878,8 +839,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 255, }; - private static readonly short[] Vp9DefaultIscan16X16 = new short[] - { + private static readonly short[] _vp9DefaultIscan16X16 = { 0, 2, 5, 9, 17, 24, 36, 44, 55, 72, 88, 104, 128, 143, 166, 179, 1, 4, 8, 13, 20, 30, 40, 54, 66, 79, 96, 113, 141, 154, 178, 196, 3, 7, 11, 18, 25, 33, 46, 57, 71, 86, 101, 119, 148, @@ -900,8 +860,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 255, }; - private static readonly short[] Vp9DefaultIscan32X32 = new short[] - { + private static readonly short[] _vp9DefaultIscan32X32 = { 0, 2, 5, 10, 17, 25, 38, 47, 62, 83, 101, 121, 145, 170, 193, 204, 210, 219, 229, 233, 245, 257, 275, 299, 342, 356, 377, 405, 455, 471, 495, 527, 1, 4, 8, 15, 22, 30, 45, @@ -997,55 +956,51 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } - public static readonly ScanOrder[] Vp9DefaultScanOrders = new ScanOrder[] - { - new ScanOrder(DefaultScan4X4, Vp9DefaultIscan4X4, DefaultScan4X4Neighbors), - new ScanOrder(DefaultScan8X8, Vp9DefaultIscan8X8, DefaultScan8X8Neighbors), - new ScanOrder(DefaultScan16X16, Vp9DefaultIscan16X16, DefaultScan16X16Neighbors), - new ScanOrder(DefaultScan32X32, Vp9DefaultIscan32X32, DefaultScan32X32Neighbors) + public static readonly ScanOrder[] Vp9DefaultScanOrders = { + new(_defaultScan4X4, _vp9DefaultIscan4X4, _defaultScan4X4Neighbors), + new(_defaultScan8X8, _vp9DefaultIscan8X8, _defaultScan8X8Neighbors), + new(_defaultScan16X16, _vp9DefaultIscan16X16, _defaultScan16X16Neighbors), + new(_defaultScan32X32, _vp9DefaultIscan32X32, _defaultScan32X32Neighbors), }; - public static readonly ScanOrder[][] Vp9ScanOrders = new ScanOrder[][] - { + public static readonly ScanOrder[][] Vp9ScanOrders = { new ScanOrder[] { // TX_4X4 - new ScanOrder(DefaultScan4X4, Vp9DefaultIscan4X4, DefaultScan4X4Neighbors), - new ScanOrder(RowScan4X4, Vp9RowIscan4X4, RowScan4X4Neighbors), - new ScanOrder(ColScan4X4, Vp9ColIscan4X4, ColScan4X4Neighbors), - new ScanOrder(DefaultScan4X4, Vp9DefaultIscan4X4, DefaultScan4X4Neighbors) + new(_defaultScan4X4, _vp9DefaultIscan4X4, _defaultScan4X4Neighbors), + new(_rowScan4X4, _vp9RowIscan4X4, _rowScan4X4Neighbors), + new(_colScan4X4, _vp9ColIscan4X4, _colScan4X4Neighbors), + new(_defaultScan4X4, _vp9DefaultIscan4X4, _defaultScan4X4Neighbors), }, new ScanOrder[] { // TX_8X8 - new ScanOrder(DefaultScan8X8, Vp9DefaultIscan8X8, DefaultScan8X8Neighbors), - new ScanOrder(RowScan8X8, Vp9RowIscan8X8, RowScan8X8Neighbors), - new ScanOrder(ColScan8X8, Vp9ColIscan8X8, ColScan8X8Neighbors), - new ScanOrder(DefaultScan8X8, Vp9DefaultIscan8X8, DefaultScan8X8Neighbors) + new(_defaultScan8X8, _vp9DefaultIscan8X8, _defaultScan8X8Neighbors), + new(_rowScan8X8, _vp9RowIscan8X8, _rowScan8X8Neighbors), + new(_colScan8X8, _vp9ColIscan8X8, _colScan8X8Neighbors), + new(_defaultScan8X8, _vp9DefaultIscan8X8, _defaultScan8X8Neighbors), }, new ScanOrder[] { // TX_16X16 - new ScanOrder(DefaultScan16X16, Vp9DefaultIscan16X16, DefaultScan16X16Neighbors), - new ScanOrder(RowScan16X16, Vp9RowIscan16X16, RowScan16X16Neighbors), - new ScanOrder(ColScan16X16, Vp9ColIscan16X16, ColScan16X16Neighbors), - new ScanOrder(DefaultScan16X16, Vp9DefaultIscan16X16, DefaultScan16X16Neighbors) + new(_defaultScan16X16, _vp9DefaultIscan16X16, _defaultScan16X16Neighbors), + new(_rowScan16X16, _vp9RowIscan16X16, _rowScan16X16Neighbors), + new(_colScan16X16, _vp9ColIscan16X16, _colScan16X16Neighbors), + new(_defaultScan16X16, _vp9DefaultIscan16X16, _defaultScan16X16Neighbors), }, new ScanOrder[] { // TX_32X32 - new ScanOrder(DefaultScan32X32, Vp9DefaultIscan32X32, DefaultScan32X32Neighbors), - new ScanOrder(DefaultScan32X32, Vp9DefaultIscan32X32, DefaultScan32X32Neighbors), - new ScanOrder(DefaultScan32X32, Vp9DefaultIscan32X32, DefaultScan32X32Neighbors), - new ScanOrder(DefaultScan32X32, Vp9DefaultIscan32X32, DefaultScan32X32Neighbors) - } + new(_defaultScan32X32, _vp9DefaultIscan32X32, _defaultScan32X32Neighbors), + new(_defaultScan32X32, _vp9DefaultIscan32X32, _defaultScan32X32Neighbors), + new(_defaultScan32X32, _vp9DefaultIscan32X32, _defaultScan32X32Neighbors), + new(_defaultScan32X32, _vp9DefaultIscan32X32, _defaultScan32X32Neighbors), + }, }; // Entropy MV - public static readonly sbyte[] Vp9MvJointTree = new sbyte[] - { - -(sbyte)MvJointType.MvJointZero, 2, -(sbyte)MvJointType.MvJointHnzvz, 4, -(sbyte)MvJointType.MvJointHzvnz, -(sbyte)MvJointType.MvJointHnzvnz + public static readonly sbyte[] Vp9MvJointTree = { + -(sbyte)MvJointType.MvJointZero, 2, -(sbyte)MvJointType.MvJointHnzvz, 4, -(sbyte)MvJointType.MvJointHzvnz, -(sbyte)MvJointType.MvJointHnzvnz, }; - public static readonly sbyte[] Vp9MvClassTree = new sbyte[] - { + public static readonly sbyte[] Vp9MvClassTree = { -(sbyte)MvClassType.MvClass0, 2, -(sbyte)MvClassType.MvClass1, @@ -1081,11 +1036,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 public static ReadOnlySpan Vp9Cat6ProbHigh12 => new byte[] { - 255, 255, 255, 255, 254, 254, 54, 252, 249, 243, 230, 196, 177, 153, 140, 133, 130, 129 + 255, 255, 255, 255, 254, 254, 54, 252, 249, 243, 230, 196, 177, 153, 140, 133, 130, 129, }; - private static readonly byte[] Vp9CoefbandTrans8X8Plus = new byte[] - { + private static readonly byte[] _vp9CoefbandTrans8X8Plus = { 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 5, // Beyond MAXBAND_INDEX+1 all values are filled as 5 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, @@ -1134,13 +1088,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, }; - public static ReadOnlySpan get_band_translate(TxSize txSize) + public static ReadOnlySpan GetBandTranslate(TxSize txSize) { - return txSize == TxSize.Tx4x4 ? Vp9CoefbandTrans4X4 : Vp9CoefbandTrans8X8Plus; + return txSize == TxSize.Tx4x4 ? Vp9CoefbandTrans4X4 : _vp9CoefbandTrans8X8Plus; } - public static readonly byte[][] Vp9Pareto8Full = new byte[][] - { + public static readonly byte[][] Vp9Pareto8Full = { new byte[] { 3, 86, 128, 6, 86, 23, 88, 29 }, new byte[] { 6, 86, 128, 11, 87, 42, 91, 52 }, new byte[] { 9, 86, 129, 17, 88, 61, 94, 76 }, @@ -1398,41 +1351,36 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 new byte[] { 255, 246, 247, 255, 239, 255, 253, 255 }, }; - /* Array indices are identical to previously-existing INTRAMODECONTEXTNODES. */ - public static readonly sbyte[] Vp9IntraModeTree = new sbyte[] - { - -(sbyte)PredictionMode.DcPred, 2, /* 0 = DC_NODE */ - -(sbyte)PredictionMode.TmPred, 4, /* 1 = TM_NODE */ - -(sbyte)PredictionMode.VPred, 6, /* 2 = V_NODE */ - 8, 12, /* 3 = COM_NODE */ - -(sbyte)PredictionMode.HPred, 10, /* 4 = H_NODE */ - -(sbyte)PredictionMode.D135Pred, -(sbyte)PredictionMode.D117Pred, /* 5 = D135_NODE */ - -(sbyte)PredictionMode.D45Pred, 14, /* 6 = D45_NODE */ - -(sbyte)PredictionMode.D63Pred, 16, /* 7 = D63_NODE */ - -(sbyte)PredictionMode.D153Pred, -(sbyte)PredictionMode.D207Pred /* 8 = D153_NODE */ + // Array indices are identical to previously-existing INTRAMODECONTEXTNODES. + public static readonly sbyte[] Vp9IntraModeTree = { + -(sbyte)PredictionMode.DcPred, 2, // 0 = DC_NODE + -(sbyte)PredictionMode.TmPred, 4, // 1 = TM_NODE + -(sbyte)PredictionMode.VPred, 6, // 2 = V_NODE + 8, 12, // 3 = COM_NODE + -(sbyte)PredictionMode.HPred, 10, // 4 = H_NODE + -(sbyte)PredictionMode.D135Pred, -(sbyte)PredictionMode.D117Pred, // 5 = D135_NODE + -(sbyte)PredictionMode.D45Pred, 14, // 6 = D45_NODE + -(sbyte)PredictionMode.D63Pred, 16, // 7 = D63_NODE + -(sbyte)PredictionMode.D153Pred, -(sbyte)PredictionMode.D207Pred, // 8 = D153_NODE }; - public static readonly sbyte[] Vp9InterModeTree = new sbyte[] - { + public static readonly sbyte[] Vp9InterModeTree = { -((sbyte)PredictionMode.ZeroMv - (sbyte)PredictionMode. NearestMv), 2, -((sbyte)PredictionMode.NearestMv - (sbyte)PredictionMode.NearestMv), 4, -((sbyte)PredictionMode.NearMv - (sbyte)PredictionMode.NearestMv), - -((sbyte)PredictionMode.NewMv - (sbyte)PredictionMode.NearestMv) + -((sbyte)PredictionMode.NewMv - (sbyte)PredictionMode.NearestMv), }; - public static readonly sbyte[] Vp9PartitionTree = new sbyte[] - { - -(sbyte)PartitionType.PartitionNone, 2, -(sbyte)PartitionType.PartitionHorz, 4, -(sbyte)PartitionType.PartitionVert, -(sbyte)PartitionType.PartitionSplit + public static readonly sbyte[] Vp9PartitionTree = { + -(sbyte)PartitionType.PartitionNone, 2, -(sbyte)PartitionType.PartitionHorz, 4, -(sbyte)PartitionType.PartitionVert, -(sbyte)PartitionType.PartitionSplit, }; - public static readonly sbyte[] Vp9SwitchableInterpTree = new sbyte[] - { - -Constants.EightTap, 2, -Constants.EightTapSmooth, -Constants.EightTapSharp + public static readonly sbyte[] Vp9SwitchableInterpTree = { + -Constants.EightTap, 2, -Constants.EightTapSmooth, -Constants.EightTapSharp, }; - public static readonly sbyte[] Vp9SegmentTree = new sbyte[] - { - 2, 4, 6, 8, 10, 12, 0, -1, -2, -3, -4, -5, -6, -7 + public static readonly sbyte[] Vp9SegmentTree = { + 2, 4, 6, 8, 10, 12, 0, -1, -2, -3, -4, -5, -6, -7, }; // MV Ref @@ -1442,169 +1390,192 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // adding 9 for each intra block, 3 for each zero mv and 1 for each new // motion vector. This single number is then converted into a context // with a single lookup ( CounterToContext ). - public static readonly int[] Mode2Counter = new int[] - { - 9, // DC_PRED - 9, // V_PRED - 9, // H_PRED - 9, // D45_PRED - 9, // D135_PRED - 9, // D117_PRED - 9, // D153_PRED - 9, // D207_PRED - 9, // D63_PRED - 9, // TM_PRED - 0, // NEARESTMV - 0, // NEARMV - 3, // ZEROMV - 1, // NEWMV + public static readonly int[] Mode2Counter = { + 9, // DC_PRED + 9, // V_PRED + 9, // H_PRED + 9, // D45_PRED + 9, // D135_PRED + 9, // D117_PRED + 9, // D153_PRED + 9, // D207_PRED + 9, // D63_PRED + 9, // TM_PRED + 0, // NEARESTMV + 0, // NEARMV + 3, // ZEROMV + 1, // NEWMV }; // There are 3^3 different combinations of 3 counts that can be either 0,1 or // 2. However the actual count can never be greater than 2 so the highest // counter we need is 18. 9 is an invalid counter that's never used. - public static readonly MotionVectorContext[] CounterToContext = new MotionVectorContext[] - { - MotionVectorContext.BothPredicted, // 0 - MotionVectorContext.NewPlusNonIntra, // 1 - MotionVectorContext.BothNew, // 2 + public static readonly MotionVectorContext[] CounterToContext = { + MotionVectorContext.BothPredicted, // 0 + MotionVectorContext.NewPlusNonIntra, // 1 + MotionVectorContext.BothNew, // 2 MotionVectorContext.ZeroPlusPredicted, // 3 - MotionVectorContext.NewPlusNonIntra, // 4 - MotionVectorContext.InvalidCase, // 5 - MotionVectorContext.BothZero, // 6 - MotionVectorContext.InvalidCase, // 7 - MotionVectorContext.InvalidCase, // 8 + MotionVectorContext.NewPlusNonIntra, // 4 + MotionVectorContext.InvalidCase, // 5 + MotionVectorContext.BothZero, // 6 + MotionVectorContext.InvalidCase, // 7 + MotionVectorContext.InvalidCase, // 8 MotionVectorContext.IntraPlusNonIntra, // 9 MotionVectorContext.IntraPlusNonIntra, // 10 - MotionVectorContext.InvalidCase, // 11 + MotionVectorContext.InvalidCase, // 11 MotionVectorContext.IntraPlusNonIntra, // 12 - MotionVectorContext.InvalidCase, // 13 - MotionVectorContext.InvalidCase, // 14 - MotionVectorContext.InvalidCase, // 15 - MotionVectorContext.InvalidCase, // 16 - MotionVectorContext.InvalidCase, // 17 - MotionVectorContext.BothIntra // 18 + MotionVectorContext.InvalidCase, // 13 + MotionVectorContext.InvalidCase, // 14 + MotionVectorContext.InvalidCase, // 15 + MotionVectorContext.InvalidCase, // 16 + MotionVectorContext.InvalidCase, // 17 + MotionVectorContext.BothIntra, // 18 }; - public static readonly Position[][] MvRefBlocks = new Position[][] - { + public static readonly Position[][] MvRefBlocks = { // 4X4 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, -1 ), - new Position( -2, 0 ), - new Position( 0, -2 ), - new Position( -2, -1 ), - new Position( -1, -2 ), - new Position( -2, -2 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, -1), + new(-2, 0), + new(0, -2), + new(-2, -1), + new(-1, -2), + new(-2, -2), + }, // 4X8 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, -1 ), - new Position( -2, 0 ), - new Position( 0, -2 ), - new Position( -2, -1 ), - new Position( -1, -2 ), - new Position( -2, -2 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, -1), + new(-2, 0), + new(0, -2), + new(-2, -1), + new(-1, -2), + new(-2, -2), + }, // 8X4 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, -1 ), - new Position( -2, 0 ), - new Position( 0, -2 ), - new Position( -2, -1 ), - new Position( -1, -2 ), - new Position( -2, -2 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, -1), + new(-2, 0), + new(0, -2), + new(-2, -1), + new(-1, -2), + new(-2, -2), + }, // 8X8 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, -1 ), - new Position( -2, 0 ), - new Position( 0, -2 ), - new Position( -2, -1 ), - new Position( -1, -2 ), - new Position( -2, -2 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, -1), + new(-2, 0), + new(0, -2), + new(-2, -1), + new(-1, -2), + new(-2, -2), + }, // 8X16 - new Position[] { new Position( 0, -1 ), - new Position( -1, 0 ), - new Position( 1, -1 ), - new Position( -1, -1 ), - new Position( 0, -2 ), - new Position( -2, 0 ), - new Position( -2, -1 ), - new Position( -1, -2 ) }, + new Position[] { + new(0, -1), + new(-1, 0), + new(1, -1), + new(-1, -1), + new(0, -2), + new(-2, 0), + new(-2, -1), + new(-1, -2), + }, // 16X8 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, 1 ), - new Position( -1, -1 ), - new Position( -2, 0 ), - new Position( 0, -2 ), - new Position( -1, -2 ), - new Position( -2, -1 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, 1), + new(-1, -1), + new(-2, 0), + new(0, -2), + new(-1, -2), + new(-2, -1), + }, // 16X16 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, 1 ), - new Position( 1, -1 ), - new Position( -1, -1 ), - new Position( -3, 0 ), - new Position( 0, -3 ), - new Position( -3, -3 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, 1), + new(1, -1), + new(-1, -1), + new(-3, 0), + new(0, -3), + new(-3, -3), + }, // 16X32 - new Position[] { new Position( 0, -1 ), - new Position( -1, 0 ), - new Position( 2, -1 ), - new Position( -1, -1 ), - new Position( -1, 1 ), - new Position( 0, -3 ), - new Position( -3, 0 ), - new Position( -3, -3 ) }, + new Position[] { + new(0, -1), + new(-1, 0), + new(2, -1), + new(-1, -1), + new(-1, 1), + new(0, -3), + new(-3, 0), + new(-3, -3), + }, // 32X16 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, 2 ), - new Position( -1, -1 ), - new Position( 1, -1 ), - new Position( -3, 0 ), - new Position( 0, -3 ), - new Position( -3, -3 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, 2), + new(-1, -1), + new(1, -1), + new(-3, 0), + new(0, -3), + new(-3, -3), + }, // 32X32 - new Position[] { new Position( -1, 1 ), - new Position( 1, -1 ), - new Position( -1, 2 ), - new Position( 2, -1 ), - new Position( -1, -1 ), - new Position( -3, 0 ), - new Position( 0, -3 ), - new Position( -3, -3 ) }, + new Position[] { + new(-1, 1), + new(1, -1), + new(-1, 2), + new(2, -1), + new(-1, -1), + new(-3, 0), + new(0, -3), + new(-3, -3), + }, // 32X64 - new Position[] { new Position( 0, -1 ), - new Position( -1, 0 ), - new Position( 4, -1 ), - new Position( -1, 2 ), - new Position( -1, -1 ), - new Position( 0, -3 ), - new Position( -3, 0 ), - new Position( 2, -1 ) }, + new Position[] { + new(0, -1), + new(-1, 0), + new(4, -1), + new(-1, 2), + new(-1, -1), + new(0, -3), + new(-3, 0), + new(2, -1), + }, // 64X32 - new Position[] { new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, 4 ), - new Position( 2, -1 ), - new Position( -1, -1 ), - new Position( -3, 0 ), - new Position( 0, -3 ), - new Position( -1, 2 ) }, + new Position[] { + new(-1, 0), + new(0, -1), + new(-1, 4), + new(2, -1), + new(-1, -1), + new(-3, 0), + new(0, -3), + new(-1, 2), + }, // 64X64 - new Position[] { new Position( -1, 3 ), - new Position( 3, -1 ), - new Position( -1, 4 ), - new Position( 4, -1 ), - new Position( -1, -1 ), - new Position( -1, 0 ), - new Position( 0, -1 ), - new Position( -1, 6 ) } + new Position[] { + new(-1, 3), + new(3, -1), + new(-1, 4), + new(4, -1), + new(-1, -1), + new(-1, 0), + new(0, -1), + new(-1, 6), + }, }; } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/PredCommon.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/PredCommon.cs index a9da10425..9b0c44b76 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/PredCommon.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/PredCommon.cs @@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // left of the entries corresponding to real macroblocks. // The prediction flags in these dummy entries are initialized to 0. if (!xd.AboveMi.IsNull && !xd.LeftMi.IsNull) - { // both edges available + { // both edges available if (!xd.AboveMi.Value.HasSecondRef() && !xd.LeftMi.Value.HasSecondRef()) { // Neither edge uses comp pred (0/1) @@ -30,13 +30,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // One of two edges uses comp pred (2/3) ctx = 2 + (xd.LeftMi.Value.RefFrame[0] == cm.CompFixedRef || !xd.LeftMi.Value.IsInterBlock() ? 1 : 0); } - else // Both edges use comp pred (4) + else // Both edges use comp pred (4) { ctx = 4; } } else if (!xd.AboveMi.IsNull || !xd.LeftMi.IsNull) - { // One edge available + { // One edge available ref ModeInfo edgeMi = ref !xd.AboveMi.IsNull ? ref xd.AboveMi.Value : ref xd.LeftMi.Value; if (!edgeMi.HasSecondRef()) @@ -51,10 +51,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // No edges available (1) + { // No edges available (1) ctx = 1; } Debug.Assert(ctx >= 0 && ctx < Constants.CompInterContexts); + return ctx; } @@ -70,29 +71,29 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int varRefIdx = fixRefIdx == 0 ? 1 : 0; if (!xd.AboveMi.IsNull && !xd.LeftMi.IsNull) - { // Both edges available + { // Both edges available bool aboveIntra = !xd.AboveMi.Value.IsInterBlock(); bool leftIntra = !xd.LeftMi.Value.IsInterBlock(); if (aboveIntra && leftIntra) - { // Intra/Intra (2) + { // Intra/Intra (2) predContext = 2; } else if (aboveIntra || leftIntra) - { // Intra/Inter + { // Intra/Inter ref ModeInfo edgeMi = ref aboveIntra ? ref xd.LeftMi.Value : ref xd.AboveMi.Value; - if (!edgeMi.HasSecondRef()) // single pred (1/3) + if (!edgeMi.HasSecondRef()) // single pred (1/3) { predContext = 1 + 2 * (edgeMi.RefFrame[0] != cm.CompVarRef[1] ? 1 : 0); } - else // Comp pred (1/3) + else // Comp pred (1/3) { predContext = 1 + 2 * (edgeMi.RefFrame[varRefIdx] != cm.CompVarRef[1] ? 1 : 0); } } else - { // Inter/Inter + { // Inter/Inter bool lSg = !xd.LeftMi.Value.HasSecondRef(); bool aSg = !xd.AboveMi.Value.HasSecondRef(); sbyte vrfa = aSg ? xd.AboveMi.Value.RefFrame[0] : xd.AboveMi.Value.RefFrame[varRefIdx]; @@ -103,7 +104,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 predContext = 0; } else if (lSg && aSg) - { // Single/Single + { // Single/Single if ((vrfa == cm.CompFixedRef && vrfl == cm.CompVarRef[0]) || (vrfl == cm.CompFixedRef && vrfa == cm.CompVarRef[0])) { @@ -119,7 +120,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else if (lSg || aSg) - { // Single/Comp + { // Single/Comp sbyte vrfc = lSg ? vrfa : vrfl; sbyte rfs = aSg ? vrfa : vrfl; if (vrfc == cm.CompVarRef[1] && rfs != cm.CompVarRef[1]) @@ -136,7 +137,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else if (vrfa == vrfl) - { // Comp/Comp + { // Comp/Comp predContext = 4; } else @@ -146,7 +147,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else if (!xd.AboveMi.IsNull || !xd.LeftMi.IsNull) - { // One edge available + { // One edge available ref ModeInfo edgeMi = ref !xd.AboveMi.IsNull ? ref xd.AboveMi.Value : ref xd.LeftMi.Value; if (!edgeMi.IsInterBlock()) @@ -166,10 +167,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // No edges available (2) + { // No edges available (2) predContext = 2; } Debug.Assert(predContext >= 0 && predContext < Constants.RefContexts); + return predContext; } @@ -181,16 +183,16 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // left of the entries corresponding to real macroblocks. // The prediction flags in these dummy entries are initialized to 0. if (!xd.AboveMi.IsNull && !xd.LeftMi.IsNull) - { // Both edges available + { // Both edges available bool aboveIntra = !xd.AboveMi.Value.IsInterBlock(); bool leftIntra = !xd.LeftMi.Value.IsInterBlock(); if (aboveIntra && leftIntra) - { // Intra/Intra + { // Intra/Intra predContext = 2; } else if (aboveIntra || leftIntra) - { // Intra/Inter or Inter/Intra + { // Intra/Inter or Inter/Intra ref ModeInfo edgeMi = ref aboveIntra ? ref xd.LeftMi.Value : ref xd.AboveMi.Value; if (!edgeMi.HasSecondRef()) { @@ -203,7 +205,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // Inter/Inter + { // Inter/Inter bool aboveHasSecond = xd.AboveMi.Value.HasSecondRef(); bool leftHasSecond = xd.LeftMi.Value.HasSecondRef(); sbyte above0 = xd.AboveMi.Value.RefFrame[0]; @@ -238,14 +240,14 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else if (!xd.AboveMi.IsNull || !xd.LeftMi.IsNull) - { // One edge available + { // One edge available ref ModeInfo edgeMi = ref !xd.AboveMi.IsNull ? ref xd.AboveMi.Value : ref xd.LeftMi.Value; if (!edgeMi.IsInterBlock()) - { // Intra + { // Intra predContext = 2; } else - { // Inter + { // Inter if (!edgeMi.HasSecondRef()) { predContext = 4 * (edgeMi.RefFrame[0] == Constants.LastFrame ? 1 : 0); @@ -258,10 +260,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // No edges available + { // No edges available predContext = 2; } Debug.Assert(predContext >= 0 && predContext < Constants.RefContexts); + return predContext; } @@ -274,16 +277,16 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 // left of the entries corresponding to real macroblocks. // The prediction flags in these dummy entries are initialized to 0. if (!xd.AboveMi.IsNull && !xd.LeftMi.IsNull) - { // Both edges available + { // Both edges available bool aboveIntra = !xd.AboveMi.Value.IsInterBlock(); bool leftIntra = !xd.LeftMi.Value.IsInterBlock(); if (aboveIntra && leftIntra) - { // Intra/Intra + { // Intra/Intra predContext = 2; } else if (aboveIntra || leftIntra) - { // Intra/Inter or Inter/Intra + { // Intra/Inter or Inter/Intra ref ModeInfo edgeMi = ref aboveIntra ? ref xd.LeftMi.Value : ref xd.AboveMi.Value; if (!edgeMi.HasSecondRef()) { @@ -303,7 +306,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // Inter/Inter + { // Inter/Inter bool aboveHasSecond = xd.AboveMi.Value.HasSecondRef(); bool leftHasSecond = xd.LeftMi.Value.HasSecondRef(); sbyte above0 = xd.AboveMi.Value.RefFrame[0]; @@ -361,7 +364,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else if (!xd.AboveMi.IsNull || !xd.LeftMi.IsNull) - { // One edge available + { // One edge available ref ModeInfo edgeMi = ref !xd.AboveMi.IsNull ? ref xd.AboveMi.Value : ref xd.LeftMi.Value; if (!edgeMi.IsInterBlock() || (edgeMi.RefFrame[0] == Constants.LastFrame && !edgeMi.HasSecondRef())) @@ -379,10 +382,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 } } else - { // No edges available (2) + { // No edges available (2) predContext = 2; } Debug.Assert(predContext >= 0 && predContext < Constants.RefContexts); + return predContext; } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/QuantCommon.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/QuantCommon.cs index 5c52c32f5..ea858222e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/QuantCommon.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/QuantCommon.cs @@ -9,8 +9,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 public const int MinQ = 0; public const int MaxQ = 255; - private static readonly short[] DcQlookup = new short[] - { + private static readonly short[] _dcQlookup = { 4, 8, 8, 9, 10, 11, 12, 12, 13, 14, 15, 16, 17, 18, 19, 19, 20, 21, 22, 23, 24, 25, 26, 26, 27, 28, 29, 30, 31, 32, 32, 33, 34, 35, 36, 37, 38, 38, 39, 40, 41, 42, @@ -32,8 +31,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 1184, 1232, 1282, 1336, }; - private static readonly short[] DcQlookup10 = new short[] - { + private static readonly short[] _dcQlookup10 = { 4, 9, 10, 13, 15, 17, 20, 22, 25, 28, 31, 34, 37, 40, 43, 47, 50, 53, 57, 60, 64, 68, 71, 75, 78, 82, 86, 90, 93, 97, 101, 105, 109, 113, 116, 120, 124, 128, 132, @@ -56,8 +54,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 3953, 4089, 4236, 4394, 4559, 4737, 4929, 5130, 5347, }; - private static readonly short[] DcQlookup12 = new short[] - { + private static readonly short[] _dcQlookup12 = { 4, 12, 18, 25, 33, 41, 50, 60, 70, 80, 91, 103, 115, 127, 140, 153, 166, 180, 194, 208, 222, 237, 251, 266, 281, 296, 312, 327, 343, 358, 374, 390, 405, @@ -84,8 +81,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 19718, 20521, 21387, }; - private static readonly short[] AcQlookup = new short[] - { + private static readonly short[] _acQlookup = { 4, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, @@ -108,8 +104,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 1567, 1597, 1628, 1660, 1692, 1725, 1759, 1793, 1828, }; - private static readonly short[] AcQlookup10 = new short[] - { + private static readonly short[] _acQlookup10 = { 4, 9, 11, 13, 16, 18, 21, 24, 27, 30, 33, 37, 40, 44, 48, 51, 55, 59, 63, 67, 71, 75, 79, 83, 88, 92, 96, 100, 105, 109, 114, 118, 122, 127, 131, 136, 140, 145, 149, @@ -132,8 +127,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 6268, 6388, 6512, 6640, 6768, 6900, 7036, 7172, 7312, }; - private static readonly short[] AcQlookup12 = new short[] - { + private static readonly short[] _acQlookup12 = { 4, 13, 19, 27, 35, 44, 54, 64, 75, 87, 99, 112, 126, 139, 154, 168, 183, 199, 214, 230, 247, 263, 280, 297, 314, 331, 349, 366, 384, 402, 420, 438, 456, @@ -164,11 +158,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (bitDepth) { - case BitDepth.Bits8: return DcQlookup[Math.Clamp(qindex + delta, 0, MaxQ)]; - case BitDepth.Bits10: return DcQlookup10[Math.Clamp(qindex + delta, 0, MaxQ)]; - case BitDepth.Bits12: return DcQlookup12[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits8: + return _dcQlookup[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits10: + return _dcQlookup10[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits12: + return _dcQlookup12[Math.Clamp(qindex + delta, 0, MaxQ)]; default: Debug.Assert(false, "bit_depth should be VPX_BITS_8, VPX_BITS_10 or VPX_BITS_12"); + return -1; } } @@ -177,11 +175,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { switch (bitDepth) { - case BitDepth.Bits8: return AcQlookup[Math.Clamp(qindex + delta, 0, MaxQ)]; - case BitDepth.Bits10: return AcQlookup10[Math.Clamp(qindex + delta, 0, MaxQ)]; - case BitDepth.Bits12: return AcQlookup12[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits8: + return _acQlookup[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits10: + return _acQlookup10[Math.Clamp(qindex + delta, 0, MaxQ)]; + case BitDepth.Bits12: + return _acQlookup12[Math.Clamp(qindex + delta, 0, MaxQ)]; default: Debug.Assert(false, "bit_depth should be VPX_BITS_8, VPX_BITS_10 or VPX_BITS_12"); + return -1; } } @@ -192,12 +194,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { int data = seg.GetSegData(segmentId, SegLvlFeatures.SegLvlAltQ); int segQIndex = seg.AbsDelta == Constants.SegmentAbsData ? data : baseQIndex + data; + return Math.Clamp(segQIndex, 0, MaxQ); } - else - { - return baseQIndex; - } + + return baseQIndex; } } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/ReconInter.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/ReconInter.cs index a4c295e5f..a357cd15b 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/ReconInter.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/ReconInter.cs @@ -84,16 +84,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private static Mv MiMvPredQ4(ref ModeInfo mi, int idx) { - Mv res = new Mv() + return new Mv { Row = (short)RoundMvCompQ4( mi.Bmi[0].Mv[idx].Row + mi.Bmi[1].Mv[idx].Row + mi.Bmi[2].Mv[idx].Row + mi.Bmi[3].Mv[idx].Row), Col = (short)RoundMvCompQ4( mi.Bmi[0].Mv[idx].Col + mi.Bmi[1].Mv[idx].Col + - mi.Bmi[2].Mv[idx].Col + mi.Bmi[3].Mv[idx].Col) + mi.Bmi[2].Mv[idx].Col + mi.Bmi[3].Mv[idx].Col), }; - return res; } private static int RoundMvCompQ2(int value) @@ -103,16 +102,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private static Mv MiMvPredQ2(ref ModeInfo mi, int idx, int block0, int block1) { - Mv res = new Mv() + return new Mv { Row = (short)RoundMvCompQ2( mi.Bmi[block0].Mv[idx].Row + mi.Bmi[block1].Mv[idx].Row), Col = (short)RoundMvCompQ2( mi.Bmi[block0].Mv[idx].Col + - mi.Bmi[block1].Mv[idx].Col) + mi.Bmi[block1].Mv[idx].Col), }; - return res; } public static Mv ClampMvToUmvBorderSb(ref MacroBlockD xd, ref Mv srcMv, int bw, int bh, int ssX, int ssY) @@ -124,10 +122,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 int spelRight = spelLeft - SubpelShifts; int spelTop = (Constants.Vp9InterpExtend + bh) << SubpelBits; int spelBottom = spelTop - SubpelShifts; - Mv clampedMv = new Mv() + Mv clampedMv = new() { Row = (short)(srcMv.Row * (1 << (1 - ssY))), - Col = (short)(srcMv.Col * (1 << (1 - ssX))) + Col = (short)(srcMv.Col * (1 << (1 - ssX))), }; Debug.Assert(ssX <= 1); @@ -145,14 +143,24 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 public static Mv AverageSplitMvs(ref MacroBlockDPlane pd, ref ModeInfo mi, int refr, int block) { int ssIdx = ((pd.SubsamplingX > 0 ? 1 : 0) << 1) | (pd.SubsamplingY > 0 ? 1 : 0); - Mv res = new Mv(); + Mv res = new(); switch (ssIdx) { - case 0: res = mi.Bmi[block].Mv[refr]; break; - case 1: res = MiMvPredQ2(ref mi, refr, block, block + 2); break; - case 2: res = MiMvPredQ2(ref mi, refr, block, block + 1); break; - case 3: res = MiMvPredQ4(ref mi, refr); break; - default: Debug.Assert(ssIdx <= 3 && ssIdx >= 0); break; + case 0: + res = mi.Bmi[block].Mv[refr]; + break; + case 1: + res = MiMvPredQ2(ref mi, refr, block, block + 2); + break; + case 2: + res = MiMvPredQ2(ref mi, refr, block, block + 1); + break; + case 3: + res = MiMvPredQ4(ref mi, refr); + break; + default: + Debug.Assert(ssIdx <= 3 && ssIdx >= 0); + break; } return res; } @@ -161,6 +169,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { int x = !sf.IsNull ? sf.Value.ScaleValueX(xOffset) : xOffset; int y = !sf.IsNull ? sf.Value.ScaleValueY(yOffset) : yOffset; + return y * stride + x; } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/ReconIntra.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/ReconIntra.cs index e346c01d1..270ff8b7e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/ReconIntra.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/ReconIntra.cs @@ -7,18 +7,17 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 { internal static class ReconIntra { - public static readonly TxType[] IntraModeToTxTypeLookup = new TxType[] - { - TxType.DctDct, // DC - TxType.AdstDct, // V - TxType.DctAdst, // H - TxType.DctDct, // D45 - TxType.AdstAdst, // D135 - TxType.AdstDct, // D117 - TxType.DctAdst, // D153 - TxType.DctAdst, // D207 - TxType.AdstDct, // D63 - TxType.AdstAdst // TM + public static readonly TxType[] IntraModeToTxTypeLookup = { + TxType.DctDct, // DC + TxType.AdstDct, // V + TxType.DctAdst, // H + TxType.DctDct, // D45 + TxType.AdstAdst, // D135 + TxType.AdstDct, // D117 + TxType.DctAdst, // D153 + TxType.DctAdst, // D207 + TxType.AdstDct, // D63 + TxType.AdstAdst, // TM }; private const int NeedLeft = 1 << 1; @@ -27,244 +26,240 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 private static ReadOnlySpan ExtendModes => new byte[] { - NeedAbove | NeedLeft, // DC - NeedAbove, // V - NeedLeft, // H - NeedAboveRight, // D45 - NeedLeft | NeedAbove, // D135 - NeedLeft | NeedAbove, // D117 - NeedLeft | NeedAbove, // D153 - NeedLeft, // D207 - NeedAboveRight, // D63 - NeedLeft | NeedAbove, // TM + NeedAbove | NeedLeft, // DC + NeedAbove, // V + NeedLeft, // H + NeedAboveRight, // D45 + NeedLeft | NeedAbove, // D135 + NeedLeft | NeedAbove, // D117 + NeedLeft | NeedAbove, // D153 + NeedLeft, // D207 + NeedAboveRight, // D63 + NeedLeft | NeedAbove, // TM }; private unsafe delegate void IntraPredFn(byte* dst, int stride, byte* above, byte* left); - private static unsafe IntraPredFn[][] _pred = new IntraPredFn[][] - { + private static readonly unsafe IntraPredFn[][] _pred = { new IntraPredFn[] { null, null, null, - null + null, }, new IntraPredFn[] { VPredictor4x4, VPredictor8x8, VPredictor16x16, - VPredictor32x32 + VPredictor32x32, }, new IntraPredFn[] { HPredictor4x4, HPredictor8x8, HPredictor16x16, - HPredictor32x32 + HPredictor32x32, }, new IntraPredFn[] { D45Predictor4x4, D45Predictor8x8, D45Predictor16x16, - D45Predictor32x32 + D45Predictor32x32, }, new IntraPredFn[] { D135Predictor4x4, D135Predictor8x8, D135Predictor16x16, - D135Predictor32x32 + D135Predictor32x32, }, new IntraPredFn[] { D117Predictor4x4, D117Predictor8x8, D117Predictor16x16, - D117Predictor32x32 + D117Predictor32x32, }, new IntraPredFn[] { D153Predictor4x4, D153Predictor8x8, D153Predictor16x16, - D153Predictor32x32 + D153Predictor32x32, }, new IntraPredFn[] { D207Predictor4x4, D207Predictor8x8, D207Predictor16x16, - D207Predictor32x32 + D207Predictor32x32, }, new IntraPredFn[] { D63Predictor4x4, D63Predictor8x8, D63Predictor16x16, - D63Predictor32x32 + D63Predictor32x32, }, new IntraPredFn[] { TMPredictor4x4, TMPredictor8x8, TMPredictor16x16, - TMPredictor32x32 - } + TMPredictor32x32, + }, }; - private static unsafe IntraPredFn[][][] _dcPred = new IntraPredFn[][][] - { - new IntraPredFn[][] + private static readonly unsafe IntraPredFn[][][] _dcPred = { + new[] { new IntraPredFn[] { Dc128Predictor4x4, Dc128Predictor8x8, Dc128Predictor16x16, - Dc128Predictor32x32 + Dc128Predictor32x32, }, new IntraPredFn[] { DcTopPredictor4x4, DcTopPredictor8x8, DcTopPredictor16x16, - DcTopPredictor32x32 - } + DcTopPredictor32x32, + }, }, - new IntraPredFn[][] + new[] { new IntraPredFn[] { DcLeftPredictor4x4, DcLeftPredictor8x8, DcLeftPredictor16x16, - DcLeftPredictor32x32 + DcLeftPredictor32x32, }, new IntraPredFn[] { DcPredictor4x4, DcPredictor8x8, DcPredictor16x16, - DcPredictor32x32 - } - } + DcPredictor32x32, + }, + }, }; private unsafe delegate void IntraHighPredFn(ushort* dst, int stride, ushort* above, ushort* left, int bd); - private static unsafe IntraHighPredFn[][] _predHigh = new IntraHighPredFn[][] - { + private static readonly unsafe IntraHighPredFn[][] _predHigh = { new IntraHighPredFn[] { null, null, null, - null + null, }, new IntraHighPredFn[] { HighbdVPredictor4x4, HighbdVPredictor8x8, HighbdVPredictor16x16, - HighbdVPredictor32x32 + HighbdVPredictor32x32, }, new IntraHighPredFn[] { HighbdHPredictor4x4, HighbdHPredictor8x8, HighbdHPredictor16x16, - HighbdHPredictor32x32 + HighbdHPredictor32x32, }, new IntraHighPredFn[] { HighbdD45Predictor4x4, HighbdD45Predictor8x8, HighbdD45Predictor16x16, - HighbdD45Predictor32x32 + HighbdD45Predictor32x32, }, new IntraHighPredFn[] { HighbdD135Predictor4x4, HighbdD135Predictor8x8, HighbdD135Predictor16x16, - HighbdD135Predictor32x32 + HighbdD135Predictor32x32, }, new IntraHighPredFn[] { HighbdD117Predictor4x4, HighbdD117Predictor8x8, HighbdD117Predictor16x16, - HighbdD117Predictor32x32 + HighbdD117Predictor32x32, }, new IntraHighPredFn[] { HighbdD153Predictor4x4, HighbdD153Predictor8x8, HighbdD153Predictor16x16, - HighbdD153Predictor32x32 + HighbdD153Predictor32x32, }, new IntraHighPredFn[] { HighbdD207Predictor4x4, HighbdD207Predictor8x8, HighbdD207Predictor16x16, - HighbdD207Predictor32x32 + HighbdD207Predictor32x32, }, new IntraHighPredFn[] { HighbdD63Predictor4x4, HighbdD63Predictor8x8, HighbdD63Predictor16x16, - HighbdD63Predictor32x32 + HighbdD63Predictor32x32, }, new IntraHighPredFn[] { HighbdTMPredictor4x4, HighbdTMPredictor8x8, HighbdTMPredictor16x16, - HighbdTMPredictor32x32 - } + HighbdTMPredictor32x32, + }, }; - private static unsafe IntraHighPredFn[][][] _dcPredHigh = new IntraHighPredFn[][][] - { - new IntraHighPredFn[][] + private static readonly unsafe IntraHighPredFn[][][] _dcPredHigh = { + new[] { new IntraHighPredFn[] { HighbdDc128Predictor4x4, HighbdDc128Predictor8x8, HighbdDc128Predictor16x16, - HighbdDc128Predictor32x32 + HighbdDc128Predictor32x32, }, new IntraHighPredFn[] { HighbdDcTopPredictor4x4, HighbdDcTopPredictor8x8, HighbdDcTopPredictor16x16, - HighbdDcTopPredictor32x32 - } + HighbdDcTopPredictor32x32, + }, }, - new IntraHighPredFn[][] + new[] { new IntraHighPredFn[] { HighbdDcLeftPredictor4x4, HighbdDcLeftPredictor8x8, HighbdDcLeftPredictor16x16, - HighbdDcLeftPredictor32x32 + HighbdDcLeftPredictor32x32, }, new IntraHighPredFn[] { HighbdDcPredictor4x4, HighbdDcPredictor8x8, HighbdDcPredictor16x16, - HighbdDcPredictor32x32 - } - } + HighbdDcPredictor32x32, + }, + }, }; private static unsafe void BuildIntraPredictorsHigh( @@ -741,6 +736,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9 x, y, plane); + return; } BuildIntraPredictors( diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BModeInfo.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BModeInfo.cs index 9e1cd8b41..4c8e33c30 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BModeInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BModeInfo.cs @@ -5,6 +5,6 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types internal struct BModeInfo { public PredictionMode Mode; - public Array2 Mv; // First, second inter predictor motion vectors + public Array2 Mv; // First, second inter predictor motion vectors } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BlockSize.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BlockSize.cs index 22a48e207..34fa9487e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BlockSize.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/BlockSize.cs @@ -16,6 +16,6 @@ Block64x32 = 11, Block64x64 = 12, BlockSizes = 13, - BlockInvalid = BlockSizes + BlockInvalid = BlockSizes, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/FrameType.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/FrameType.cs index a783999ef..3d2093030 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/FrameType.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/FrameType.cs @@ -3,6 +3,6 @@ internal enum FrameType { KeyFrame = 0, - InterFrame = 1 + InterFrame = 1, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/LoopFilterThresh.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/LoopFilterThresh.cs index edd79af4a..c0af5495e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/LoopFilterThresh.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/LoopFilterThresh.cs @@ -6,7 +6,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types // passed it can be loaded into vector registers. internal struct LoopFilterThresh { -#pragma warning disable CS0649 +#pragma warning disable CS0649 // Field is never assigned to public Array16 Mblim; public Array16 Lim; public Array16 HevThr; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MacroBlockD.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MacroBlockD.cs index f1111528e..5cdc0d2df 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MacroBlockD.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MacroBlockD.cs @@ -54,7 +54,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public Ptr ErrorInfo; - public int GetPredContextSegId() + public readonly int GetPredContextSegId() { sbyte aboveSip = !AboveMi.IsNull ? AboveMi.Value.SegIdPredicted : (sbyte)0; sbyte leftSip = !LeftMi.IsNull ? LeftMi.Value.SegIdPredicted : (sbyte)0; @@ -62,14 +62,15 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types return aboveSip + leftSip; } - public int GetSkipContext() + public readonly int GetSkipContext() { int aboveSkip = !AboveMi.IsNull ? AboveMi.Value.Skip : 0; int leftSkip = !LeftMi.IsNull ? LeftMi.Value.Skip : 0; + return aboveSkip + leftSkip; } - public int GetPredContextSwitchableInterp() + public readonly int GetPredContextSwitchableInterp() { // Note: // The mode info data structure has a one element border above and to the @@ -103,16 +104,18 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types // 1 - intra/inter, inter/intra // 2 - intra/--, --/intra // 3 - intra/intra - public int GetIntraInterContext() + public readonly int GetIntraInterContext() { if (!AboveMi.IsNull && !LeftMi.IsNull) - { // Both edges available + { // Both edges available bool aboveIntra = !AboveMi.Value.IsInterBlock(); bool leftIntra = !LeftMi.Value.IsInterBlock(); + return leftIntra && aboveIntra ? 3 : (leftIntra || aboveIntra ? 1 : 0); } - else if (!AboveMi.IsNull || !LeftMi.IsNull) - { // One edge available + + if (!AboveMi.IsNull || !LeftMi.IsNull) + { // One edge available return 2 * (!(!AboveMi.IsNull ? AboveMi.Value : LeftMi.Value).IsInterBlock() ? 1 : 0); } return 0; @@ -122,7 +125,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types // The mode info data structure has a one element border above and to the // left of the entries corresponding to real blocks. // The prediction flags in these dummy entries are initialized to 0. - public int GetTxSizeContext() + public readonly int GetTxSizeContext() { int maxTxSize = (int)Luts.MaxTxSizeLookup[(int)Mi[0].Value.SbType]; int aboveCtx = (!AboveMi.IsNull && AboveMi.Value.Skip == 0) ? (int)AboveMi.Value.TxSize : maxTxSize; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ModeInfo.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ModeInfo.cs index 8ef281d83..8af7b6f90 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ModeInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ModeInfo.cs @@ -11,7 +11,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public TxSize TxSize; public sbyte Skip; public sbyte SegmentId; - public sbyte SegIdPredicted; // Valid only when TemporalUpdate is enabled + public sbyte SegIdPredicted; // Valid only when TemporalUpdate is enabled // Only for Intra blocks public PredictionMode UvMode; @@ -32,10 +32,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types return SbType < BlockSize.Block8x8 ? Bmi[block].Mode : Mode; } - public TxSize GetUvTxSize(ref MacroBlockDPlane pd) + public readonly TxSize GetUvTxSize(ref MacroBlockDPlane pd) { Debug.Assert(SbType < BlockSize.Block8x8 || Luts.SsSizeLookup[(int)SbType][pd.SubsamplingX][pd.SubsamplingY] != BlockSize.BlockInvalid); + return Luts.UvTxsizeLookup[(int)SbType][(int)TxSize][pd.SubsamplingX][pd.SubsamplingY]; } @@ -49,9 +50,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types return RefFrame[1] > Constants.IntraFrame; } - private static readonly int[][] IdxNColumnToSubblock = new int[][] - { - new int[] { 1, 2 }, new int[] { 1, 3 }, new int[] { 3, 2 }, new int[] { 3, 3 } + private static readonly int[][] _idxNColumnToSubblock = { + new[] { 1, 2 }, new[] { 1, 3 }, new[] { 3, 2 }, new[] { 3, 3 }, }; // This function returns either the appropriate sub block or block's mv @@ -59,7 +59,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public Mv GetSubBlockMv(int whichMv, int searchCol, int blockIdx) { return blockIdx >= 0 && SbType < BlockSize.Block8x8 - ? Bmi[IdxNColumnToSubblock[blockIdx][searchCol == 0 ? 1 : 0]].Mv[whichMv] + ? Bmi[_idxNColumnToSubblock[blockIdx][searchCol == 0 ? 1 : 0]].Mv[whichMv] : Mv[whichMv]; } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MotionVectorContext.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MotionVectorContext.cs index 319c8dba8..a9a603bf0 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MotionVectorContext.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/MotionVectorContext.cs @@ -9,6 +9,6 @@ BothNew = 4, IntraPlusNonIntra = 5, BothIntra = 6, - InvalidCase = 9 + InvalidCase = 9, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Mv.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Mv.cs index 815bbb321..c78a80d0d 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Mv.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Mv.cs @@ -51,13 +51,13 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, - 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10 + 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, }; - public bool UseMvHp() + public readonly bool UseMvHp() { - const int kMvRefThresh = 64; // Threshold for use of high-precision 1/8 mv - return Math.Abs(Row) < kMvRefThresh && Math.Abs(Col) < kMvRefThresh; + const int KMvRefThresh = 64; // Threshold for use of high-precision 1/8 mv + return Math.Abs(Row) < KMvRefThresh && Math.Abs(Col) < KMvRefThresh; } public static bool MvJointVertical(MvJointType type) @@ -110,7 +110,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types else { int i; - int b = c + Constants.Class0Bits - 1; // Number of bits + int b = c + Constants.Class0Bits - 1; // Number of bits for (i = 0; i < b; ++i) { counts.Bits[comp][i][((d >> i) & 1)] += (uint)incr; @@ -121,19 +121,17 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types } } - private MvJointType GetMvJoint() + private readonly MvJointType GetMvJoint() { if (Row == 0) { return Col == 0 ? MvJointType.MvJointZero : MvJointType.MvJointHnzvz; } - else - { - return Col == 0 ? MvJointType.MvJointHzvnz : MvJointType.MvJointHnzvnz; - } + + return Col == 0 ? MvJointType.MvJointHzvnz : MvJointType.MvJointHnzvnz; } - internal void IncMv(Ptr counts) + internal readonly void IncMv(Ptr counts) { if (!counts.IsNull) { @@ -158,7 +156,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types Row = (short)Math.Clamp(Row, minRow, maxRow); } - private const int MvBorder = (16 << 3); // Allow 16 pels in 1/8th pel units + private const int MvBorder = (16 << 3); // Allow 16 pels in 1/8th pel units public void ClampMvRef(ref MacroBlockD xd) { diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PartitionType.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PartitionType.cs index 096f9818a..78f4fb260 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PartitionType.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PartitionType.cs @@ -7,6 +7,6 @@ PartitionVert, PartitionSplit, PartitionTypes, - PartitionInvalid = PartitionTypes + PartitionInvalid = PartitionTypes, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PlaneType.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PlaneType.cs index 790aa2a0c..d62594567 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PlaneType.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PlaneType.cs @@ -4,6 +4,6 @@ { Y = 0, Uv = 1, - PlaneTypes + PlaneTypes, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PredictionMode.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PredictionMode.cs index bbb9be9ad..fbf542043 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PredictionMode.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/PredictionMode.cs @@ -2,20 +2,20 @@ { internal enum PredictionMode { - DcPred = 0, // Average of above and left pixels - VPred = 1, // Vertical - HPred = 2, // Horizontal - D45Pred = 3, // Directional 45 deg = round(arctan(1 / 1) * 180 / pi) - D135Pred = 4, // Directional 135 deg = 180 - 45 - D117Pred = 5, // Directional 117 deg = 180 - 63 - D153Pred = 6, // Directional 153 deg = 180 - 27 - D207Pred = 7, // Directional 207 deg = 180 + 27 - D63Pred = 8, // Directional 63 deg = round(arctan(2 / 1) * 180 / pi) - TmPred = 9, // True-motion + DcPred = 0, // Average of above and left pixels + VPred = 1, // Vertical + HPred = 2, // Horizontal + D45Pred = 3, // Directional 45 deg = round(arctan(1 / 1) * 180 / pi) + D135Pred = 4, // Directional 135 deg = 180 - 45 + D117Pred = 5, // Directional 117 deg = 180 - 63 + D153Pred = 6, // Directional 153 deg = 180 - 27 + D207Pred = 7, // Directional 207 deg = 180 + 27 + D63Pred = 8, // Directional 63 deg = round(arctan(2 / 1) * 180 / pi) + TmPred = 9, // True-motion NearestMv = 10, NearMv = 11, ZeroMv = 12, NewMv = 13, - MbModeCount = 14 + MbModeCount = 14, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ReferenceMode.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ReferenceMode.cs index 7cbf9f4ef..5d9f189d2 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ReferenceMode.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ReferenceMode.cs @@ -5,6 +5,6 @@ SingleReference = 0, CompoundReference = 1, ReferenceModeSelect = 2, - ReferenceModes = 3 + ReferenceModes = 3, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ScaleFactors.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ScaleFactors.cs index 970f96801..ba89d6e39 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ScaleFactors.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/ScaleFactors.cs @@ -38,263 +38,255 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types int h, int bd); - private static readonly unsafe ConvolveFn[][][] PredictX16Y16 = new ConvolveFn[][][] - { - new ConvolveFn[][] + private static readonly unsafe ConvolveFn[][][] _predictX16Y16 = { + new[] { new ConvolveFn[] { ConvolveCopy, - ConvolveAvg + ConvolveAvg, }, new ConvolveFn[] { Convolve8Vert, - Convolve8AvgVert - } + Convolve8AvgVert, + }, }, - new ConvolveFn[][] + new[] { new ConvolveFn[] { Convolve8Horiz, - Convolve8AvgHoriz + Convolve8AvgHoriz, }, new ConvolveFn[] { Convolve8, - Convolve8Avg - } - } + Convolve8Avg, + }, + }, }; - private static readonly unsafe ConvolveFn[][][] PredictX16 = new ConvolveFn[][][] - { - new ConvolveFn[][] + private static readonly unsafe ConvolveFn[][][] _predictX16 = { + new[] { new ConvolveFn[] { ScaledVert, - ScaledAvgVert + ScaledAvgVert, }, new ConvolveFn[] { ScaledVert, - ScaledAvgVert - } + ScaledAvgVert, + }, }, - new ConvolveFn[][] + new[] { new ConvolveFn[] { Scaled2D, - ScaledAvg2D + ScaledAvg2D, }, new ConvolveFn[] { Scaled2D, - ScaledAvg2D - } - } + ScaledAvg2D, + }, + }, }; - private static readonly unsafe ConvolveFn[][][] PredictY16 = new ConvolveFn[][][] - { - new ConvolveFn[][] + private static readonly unsafe ConvolveFn[][][] _predictY16 = { + new[] { new ConvolveFn[] { ScaledHoriz, - ScaledAvgHoriz + ScaledAvgHoriz, }, new ConvolveFn[] { Scaled2D, - ScaledAvg2D - } + ScaledAvg2D, + }, }, - new ConvolveFn[][] + new[] { new ConvolveFn[] { ScaledHoriz, - ScaledAvgHoriz + ScaledAvgHoriz, }, new ConvolveFn[] { Scaled2D, - ScaledAvg2D - } - } - }; - - private static readonly unsafe ConvolveFn[][][] Predict = new ConvolveFn[][][] - { - new ConvolveFn[][] - { - new ConvolveFn[] - { - Scaled2D, - ScaledAvg2D + ScaledAvg2D, }, - new ConvolveFn[] - { - Scaled2D, - ScaledAvg2D - } }, - new ConvolveFn[][] + }; + + private static readonly unsafe ConvolveFn[][][] _predict = { + new[] { new ConvolveFn[] { Scaled2D, - ScaledAvg2D + ScaledAvg2D, }, new ConvolveFn[] { Scaled2D, - ScaledAvg2D - } - } + ScaledAvg2D, + }, + }, + new[] + { + new ConvolveFn[] + { + Scaled2D, + ScaledAvg2D, + }, + new ConvolveFn[] + { + Scaled2D, + ScaledAvg2D, + }, + }, }; - private static readonly unsafe HighbdConvolveFn[][][] HighbdPredictX16Y16 = new HighbdConvolveFn[][][] - { - new HighbdConvolveFn[][] + private static readonly unsafe HighbdConvolveFn[][][] _highbdPredictX16Y16 = { + new[] { new HighbdConvolveFn[] { HighbdConvolveCopy, - HighbdConvolveAvg + HighbdConvolveAvg, }, new HighbdConvolveFn[] { HighbdConvolve8Vert, - HighbdConvolve8AvgVert - } + HighbdConvolve8AvgVert, + }, }, - new HighbdConvolveFn[][] + new[] { new HighbdConvolveFn[] { HighbdConvolve8Horiz, - HighbdConvolve8AvgHoriz + HighbdConvolve8AvgHoriz, }, new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg - } - } + HighbdConvolve8Avg, + }, + }, }; - private static readonly unsafe HighbdConvolveFn[][][] HighbdPredictX16 = new HighbdConvolveFn[][][] - { - new HighbdConvolveFn[][] + private static readonly unsafe HighbdConvolveFn[][][] _highbdPredictX16 = { + new[] { new HighbdConvolveFn[] { HighbdConvolve8Vert, - HighbdConvolve8AvgVert + HighbdConvolve8AvgVert, }, new HighbdConvolveFn[] { HighbdConvolve8Vert, - HighbdConvolve8AvgVert - } + HighbdConvolve8AvgVert, + }, }, - new HighbdConvolveFn[][] + new[] { new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg + HighbdConvolve8Avg, }, new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg - } - } + HighbdConvolve8Avg, + }, + }, }; - private static readonly unsafe HighbdConvolveFn[][][] HighbdPredictY16 = new HighbdConvolveFn[][][] - { - new HighbdConvolveFn[][] + private static readonly unsafe HighbdConvolveFn[][][] _highbdPredictY16 = { + new[] { new HighbdConvolveFn[] { HighbdConvolve8Horiz, - HighbdConvolve8AvgHoriz + HighbdConvolve8AvgHoriz, }, new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg - } + HighbdConvolve8Avg, + }, }, - new HighbdConvolveFn[][] + new[] { new HighbdConvolveFn[] { HighbdConvolve8Horiz, - HighbdConvolve8AvgHoriz + HighbdConvolve8AvgHoriz, }, new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg - } - } - }; - - private static readonly unsafe HighbdConvolveFn[][][] HighbdPredict = new HighbdConvolveFn[][][] - { - new HighbdConvolveFn[][] - { - new HighbdConvolveFn[] - { - HighbdConvolve8, - HighbdConvolve8Avg + HighbdConvolve8Avg, }, - new HighbdConvolveFn[] - { - HighbdConvolve8, - HighbdConvolve8Avg - } }, - new HighbdConvolveFn[][] + }; + + private static readonly unsafe HighbdConvolveFn[][][] _highbdPredict = { + new[] { new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg + HighbdConvolve8Avg, }, new HighbdConvolveFn[] { HighbdConvolve8, - HighbdConvolve8Avg - } - } + HighbdConvolve8Avg, + }, + }, + new[] + { + new HighbdConvolveFn[] + { + HighbdConvolve8, + HighbdConvolve8Avg, + }, + new HighbdConvolveFn[] + { + HighbdConvolve8, + HighbdConvolve8Avg, + }, + }, }; - public int XScaleFP; // Horizontal fixed point scale factor - public int YScaleFP; // Vertical fixed point scale factor + public int XScaleFP; // Horizontal fixed point scale factor + public int YScaleFP; // Vertical fixed point scale factor public int XStepQ4; public int YStepQ4; - public int ScaleValueX(int val) + public readonly int ScaleValueX(int val) { return IsScaled() ? ScaledX(val) : val; } - public int ScaleValueY(int val) + public readonly int ScaleValueY(int val) { return IsScaled() ? ScaledY(val) : val; } [MethodImpl(MethodImplOptions.AggressiveInlining)] - public unsafe void InterPredict( + public readonly unsafe void InterPredict( int horiz, int vert, int avg, @@ -315,12 +307,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types if (YStepQ4 == 16) { // No scaling in either direction. - PredictX16Y16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); + _predictX16Y16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); } else { // No scaling in x direction. Must always scale in the y direction. - PredictX16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); + _predictX16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); } } else @@ -328,18 +320,18 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types if (YStepQ4 == 16) { // No scaling in the y direction. Must always scale in the x direction. - PredictY16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); + _predictY16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); } else { // Must always scale in both directions. - Predict[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); + _predict[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h); } } } [MethodImpl(MethodImplOptions.AggressiveInlining)] - public unsafe void HighbdInterPredict( + public readonly unsafe void HighbdInterPredict( int horiz, int vert, int avg, @@ -361,12 +353,12 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types if (YStepQ4 == 16) { // No scaling in either direction. - HighbdPredictX16Y16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); + _highbdPredictX16Y16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); } else { // No scaling in x direction. Must always scale in the y direction. - HighbdPredictX16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); + _highbdPredictX16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); } } else @@ -374,22 +366,22 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types if (YStepQ4 == 16) { // No scaling in the y direction. Must always scale in the x direction. - HighbdPredictY16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); + _highbdPredictY16[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); } else { // Must always scale in both directions. - HighbdPredict[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); + _highbdPredict[horiz][vert][avg](src, srcStride, dst, dstStride, kernel, subpelX, xs, subpelY, ys, w, h, bd); } } } - private int ScaledX(int val) + private readonly int ScaledX(int val) { return (int)((long)val * XScaleFP >> RefScaleShift); } - private int ScaledY(int val) + private readonly int ScaledY(int val) { return (int)((long)val * YScaleFP >> RefScaleShift); } @@ -407,20 +399,21 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types { int xOffQ4 = ScaledX(x << SubpelBits) & SubpelMask; int yOffQ4 = ScaledY(y << SubpelBits) & SubpelMask; - Mv32 res = new Mv32() + Mv32 res = new() { Row = ScaledY(mv.Row) + yOffQ4, - Col = ScaledX(mv.Col) + xOffQ4 + Col = ScaledX(mv.Col) + xOffQ4, }; + return res; } - public bool IsValidScale() + public readonly bool IsValidScale() { return XScaleFP != RefInvalidScale && YScaleFP != RefInvalidScale; } - public bool IsScaled() + public readonly bool IsScaled() { return IsValidScale() && (XScaleFP != RefNoScale || YScaleFP != RefNoScale); } @@ -439,6 +432,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types { XScaleFP = RefInvalidScale; YScaleFP = RefInvalidScale; + return; } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/SegLvlFeatures.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/SegLvlFeatures.cs index c3ea3fd89..8d04d18b8 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/SegLvlFeatures.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/SegLvlFeatures.cs @@ -2,10 +2,10 @@ { internal enum SegLvlFeatures { - SegLvlAltQ = 0, // Use alternate Quantizer .... - SegLvlAltLf = 1, // Use alternate loop filter value... - SegLvlRefFrame = 2, // Optional Segment reference frame - SegLvlSkip = 3, // Optional Segment (0,0) + skip mode - SegLvlMax = 4 // Number of features supported + SegLvlAltQ = 0, // Use alternate Quantizer .... + SegLvlAltLf = 1, // Use alternate loop filter value... + SegLvlRefFrame = 2, // Optional Segment reference frame + SegLvlSkip = 3, // Optional Segment (0,0) + skip mode + SegLvlMax = 4, // Number of features supported } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Segmentation.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Segmentation.cs index 53d1f2ccb..c0fbdc51e 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Segmentation.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Segmentation.cs @@ -6,8 +6,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types { internal struct Segmentation { - private static readonly int[] SegFeatureDataSigned = new int[] { 1, 1, 0, 0 }; - private static readonly int[] SegFeatureDataMax = new int[] { QuantCommon.MaxQ, Vp9.LoopFilter.MaxLoopFilter, 3, 0 }; + private static readonly int[] _segFeatureDataSigned = { 1, 1, 0, 0 }; + private static readonly int[] _segFeatureDataMax = { QuantCommon.MaxQ, Vp9.LoopFilter.MaxLoopFilter, 3, 0 }; public bool Enabled; public bool UpdateMap; @@ -26,8 +26,8 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public void ClearAllSegFeatures() { - MemoryMarshal.CreateSpan(ref FeatureData[0][0], 8 * 4).Fill(0); - MemoryMarshal.CreateSpan(ref FeatureMask[0], 8).Fill(0); + MemoryMarshal.CreateSpan(ref FeatureData[0][0], 8 * 4).Clear(); + MemoryMarshal.CreateSpan(ref FeatureMask[0], 8).Clear(); AqAvOffset = 0; } @@ -38,21 +38,21 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types internal static int FeatureDataMax(SegLvlFeatures featureId) { - return SegFeatureDataMax[(int)featureId]; + return _segFeatureDataMax[(int)featureId]; } internal static int IsSegFeatureSigned(SegLvlFeatures featureId) { - return SegFeatureDataSigned[(int)featureId]; + return _segFeatureDataSigned[(int)featureId]; } internal void SetSegData(int segmentId, SegLvlFeatures featureId, int segData) { - Debug.Assert(segData <= SegFeatureDataMax[(int)featureId]); + Debug.Assert(segData <= _segFeatureDataMax[(int)featureId]); if (segData < 0) { - Debug.Assert(SegFeatureDataSigned[(int)featureId] != 0); - Debug.Assert(-segData <= SegFeatureDataMax[(int)featureId]); + Debug.Assert(_segFeatureDataSigned[(int)featureId] != 0); + Debug.Assert(-segData <= _segFeatureDataMax[(int)featureId]); } FeatureData[segmentId][(int)featureId] = (short)segData; diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Surface.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Surface.cs index d5b51bc2f..7f34faa5b 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Surface.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Surface.cs @@ -11,11 +11,11 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public ArrayPtr UBuffer; public ArrayPtr VBuffer; - public unsafe Plane YPlane => new Plane((IntPtr)YBuffer.ToPointer(), YBuffer.Length); - public unsafe Plane UPlane => new Plane((IntPtr)UBuffer.ToPointer(), UBuffer.Length); - public unsafe Plane VPlane => new Plane((IntPtr)VBuffer.ToPointer(), VBuffer.Length); + public readonly unsafe Plane YPlane => new((IntPtr)YBuffer.ToPointer(), YBuffer.Length); + public readonly unsafe Plane UPlane => new((IntPtr)UBuffer.ToPointer(), UBuffer.Length); + public readonly unsafe Plane VPlane => new((IntPtr)VBuffer.ToPointer(), VBuffer.Length); - public FrameField Field => FrameField.Progressive; + public readonly FrameField Field => FrameField.Progressive; public int Width { get; } public int Height { get; } @@ -27,29 +27,31 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public int UvAlignedWidth { get; } public int UvAlignedHeight { get; } public int UvStride { get; } - public bool HighBd => false; + + public bool HighBd { get; } private readonly IntPtr _pointer; public Surface(int width, int height) { - const int border = 32; - const int ssX = 1; - const int ssY = 1; - const bool highbd = false; + HighBd = false; + + const int Border = 32; + const int SsX = 1; + const int SsY = 1; int alignedWidth = (width + 7) & ~7; int alignedHeight = (height + 7) & ~7; - int yStride = ((alignedWidth + 2 * border) + 31) & ~31; - int yplaneSize = (alignedHeight + 2 * border) * yStride; - int uvWidth = alignedWidth >> ssX; - int uvHeight = alignedHeight >> ssY; - int uvStride = yStride >> ssX; - int uvBorderW = border >> ssX; - int uvBorderH = border >> ssY; + int yStride = ((alignedWidth + 2 * Border) + 31) & ~31; + int yplaneSize = (alignedHeight + 2 * Border) * yStride; + int uvWidth = alignedWidth >> SsX; + int uvHeight = alignedHeight >> SsY; + int uvStride = yStride >> SsX; + int uvBorderW = Border >> SsX; + int uvBorderH = Border >> SsY; int uvplaneSize = (uvHeight + 2 * uvBorderH) * uvStride; - int frameSize = (highbd ? 2 : 1) * (yplaneSize + 2 * uvplaneSize); + int frameSize = (HighBd ? 2 : 1) * (yplaneSize + 2 * uvplaneSize); IntPtr pointer = Marshal.AllocHGlobal(frameSize); _pointer = pointer; @@ -58,23 +60,23 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types AlignedWidth = alignedWidth; AlignedHeight = alignedHeight; Stride = yStride; - UvWidth = (width + ssX) >> ssX; - UvHeight = (height + ssY) >> ssY; + UvWidth = (width + SsX) >> SsX; + UvHeight = (height + SsY) >> SsY; UvAlignedWidth = uvWidth; UvAlignedHeight = uvHeight; UvStride = uvStride; - ArrayPtr NewPlane(int start, int size, int border) + ArrayPtr NewPlane(int start, int size, int planeBorder) { - return new ArrayPtr(pointer + start + border, size - border); + return new ArrayPtr(pointer + start + planeBorder, size - planeBorder); } - YBuffer = NewPlane(0, yplaneSize, (border * yStride) + border); + YBuffer = NewPlane(0, yplaneSize, (Border * yStride) + Border); UBuffer = NewPlane(yplaneSize, uvplaneSize, (uvBorderH * uvStride) + uvBorderW); VBuffer = NewPlane(yplaneSize + uvplaneSize, uvplaneSize, (uvBorderH * uvStride) + uvBorderW); } - public void Dispose() + public readonly void Dispose() { Marshal.FreeHGlobal(_pointer); } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TileInfo.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TileInfo.cs index 67289c47d..232d4ccb2 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TileInfo.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TileInfo.cs @@ -21,6 +21,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types { int sbCols = MiColsAlignedToSb(mis) >> Constants.MiBlockSizeLog2; int offset = ((idx * sbCols) >> log2) << Constants.MiBlockSizeLog2; + return Math.Min(offset, mis); } @@ -44,7 +45,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types // Checks that the given miRow, miCol and search point // are inside the borders of the tile. - public bool IsInside(int miCol, int miRow, int miRows, ref Position miPos) + public readonly bool IsInside(int miCol, int miRow, int miRows, ref Position miPos) { return !(miRow + miPos.Row < 0 || miCol + miPos.Col < MiColStart || diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxMode.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxMode.cs index db914525c..80c963fe0 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxMode.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxMode.cs @@ -2,11 +2,11 @@ { public enum TxMode { - Only4X4 = 0, // Only 4x4 transform used - Allow8X8 = 1, // Allow block transform size up to 8x8 - Allow16X16 = 2, // Allow block transform size up to 16x16 - Allow32X32 = 3, // Allow block transform size up to 32x32 + Only4X4 = 0, // Only 4x4 transform used + Allow8X8 = 1, // Allow block transform size up to 8x8 + Allow16X16 = 2, // Allow block transform size up to 16x16 + Allow32X32 = 3, // Allow block transform size up to 32x32 TxModeSelect = 4, // Transform specified for each block - TxModes = 5 + TxModes = 5, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxSize.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxSize.cs index 994deb2c3..bcc70ebab 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxSize.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxSize.cs @@ -2,10 +2,10 @@ { public enum TxSize { - Tx4x4 = 0, // 4x4 transform - Tx8x8 = 1, // 8x8 transform + Tx4x4 = 0, // 4x4 transform + Tx8x8 = 1, // 8x8 transform Tx16x16 = 2, // 16x16 transform Tx32x32 = 3, // 32x32 transform - TxSizes = 4 + TxSizes = 4, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxType.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxType.cs index dbf7251cd..1ae436e96 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxType.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/TxType.cs @@ -2,10 +2,10 @@ { internal enum TxType { - DctDct = 0, // DCT in both horizontal and vertical - AdstDct = 1, // ADST in vertical, DCT in horizontal - DctAdst = 2, // DCT in vertical, ADST in horizontal + DctDct = 0, // DCT in both horizontal and vertical + AdstDct = 1, // ADST in vertical, DCT in horizontal + DctAdst = 2, // DCT in vertical, ADST in horizontal AdstAdst = 3, // ADST in both directions - TxTypes = 4 + TxTypes = 4, } } diff --git a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Vp9Common.cs b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Vp9Common.cs index faadd3498..8dd0879eb 100644 --- a/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Vp9Common.cs +++ b/src/Ryujinx.Graphics.Nvdec.Vp9/Types/Vp9Common.cs @@ -88,7 +88,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public ArrayPtr AboveSegContext; public ArrayPtr AboveContext; - public bool FrameIsIntraOnly() + public readonly bool FrameIsIntraOnly() { return FrameType == FrameType.KeyFrame || IntraOnly; } @@ -132,7 +132,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types TileWorkerData = allocator.Allocate(tileCols * tileRows + (maxThreads > 1 ? maxThreads : 0)); } - public void FreeTileWorkerData(MemoryAllocator allocator) + public readonly void FreeTileWorkerData(MemoryAllocator allocator) { allocator.Free(TileWorkerData); } @@ -257,7 +257,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types } } - private void SetPartitionProbs(ref MacroBlockD xd) + private readonly void SetPartitionProbs(ref MacroBlockD xd) { xd.PartitionProbs = FrameIsIntraOnly() ? new ArrayPtr>(ref Fc.Value.KfPartitionProb[0], 16) @@ -293,7 +293,7 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types public void SetupSegmentationDequant() { - const BitDepth bitDepth = BitDepth.Bits8; // TODO: Configurable + const BitDepth BitDepth = BitDepth.Bits8; // TODO: Configurable // Build y/uv dequant values based on segmentation. if (Seg.Enabled) { @@ -301,10 +301,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types for (i = 0; i < Constants.MaxSegments; ++i) { int qIndex = QuantCommon.GetQIndex(ref Seg, i, BaseQindex); - YDequant[i][0] = QuantCommon.DcQuant(qIndex, YDcDeltaQ, bitDepth); - YDequant[i][1] = QuantCommon.AcQuant(qIndex, 0, bitDepth); - UvDequant[i][0] = QuantCommon.DcQuant(qIndex, UvDcDeltaQ, bitDepth); - UvDequant[i][1] = QuantCommon.AcQuant(qIndex, UvAcDeltaQ, bitDepth); + YDequant[i][0] = QuantCommon.DcQuant(qIndex, YDcDeltaQ, BitDepth); + YDequant[i][1] = QuantCommon.AcQuant(qIndex, 0, BitDepth); + UvDequant[i][0] = QuantCommon.DcQuant(qIndex, UvDcDeltaQ, BitDepth); + UvDequant[i][1] = QuantCommon.AcQuant(qIndex, UvAcDeltaQ, BitDepth); } } else @@ -312,10 +312,10 @@ namespace Ryujinx.Graphics.Nvdec.Vp9.Types int qIndex = BaseQindex; // When segmentation is disabled, only the first value is used. The // remaining are don't cares. - YDequant[0][0] = QuantCommon.DcQuant(qIndex, YDcDeltaQ, bitDepth); - YDequant[0][1] = QuantCommon.AcQuant(qIndex, 0, bitDepth); - UvDequant[0][0] = QuantCommon.DcQuant(qIndex, UvDcDeltaQ, bitDepth); - UvDequant[0][1] = QuantCommon.AcQuant(qIndex, UvAcDeltaQ, bitDepth); + YDequant[0][0] = QuantCommon.DcQuant(qIndex, YDcDeltaQ, BitDepth); + YDequant[0][1] = QuantCommon.AcQuant(qIndex, 0, BitDepth); + UvDequant[0][0] = QuantCommon.DcQuant(qIndex, UvDcDeltaQ, BitDepth); + UvDequant[0][1] = QuantCommon.AcQuant(qIndex, UvAcDeltaQ, BitDepth); } } From 2cdc82cb910d03e13d36b6a31148b5b87e35fde9 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 28 Jun 2023 09:36:22 +0200 Subject: [PATCH 16/19] nuget: bump Microsoft.NET.Test.Sdk from 17.6.2 to 17.6.3 (#5406) Bumps [Microsoft.NET.Test.Sdk](https://github.com/microsoft/vstest) from 17.6.2 to 17.6.3. - [Release notes](https://github.com/microsoft/vstest/releases) - [Changelog](https://github.com/microsoft/vstest/blob/main/docs/releases.md) - [Commits](https://github.com/microsoft/vstest/compare/v17.6.2...v17.6.3) --- updated-dependencies: - dependency-name: Microsoft.NET.Test.Sdk dependency-type: direct:production update-type: version-update:semver-patch ... Signed-off-by: dependabot[bot] Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> --- Directory.Packages.props | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Directory.Packages.props b/Directory.Packages.props index a100f8261..df917cbab 100644 --- a/Directory.Packages.props +++ b/Directory.Packages.props @@ -21,7 +21,7 @@ - + From 9288ffd26d0b0b831f62cfc0281c71662d251884 Mon Sep 17 00:00:00 2001 From: Ac_K Date: Wed, 28 Jun 2023 17:36:30 +0200 Subject: [PATCH 17/19] Cpu: Implement VCVT (between floating-point and fixed-point) instruction (#5343) * cpu: Implement VCVT (between floating-point and fixed-point) instruction Rebase, fix and superseed of https://github.com/Ryujinx/Ryujinx/pull/2915 (Since I only have little CPU knowledge, I hope I have done everything good) * Update Ptc.cs * Fix wrong cast * Rename tests * Addresses feedback Co-Authored-By: gdkchan <5624669+gdkchan@users.noreply.github.com> * Remove extra empty line --------- Co-authored-by: gdkchan <5624669+gdkchan@users.noreply.github.com> --- .../Decoders/OpCode32SimdCvtFFixed.cs | 23 ++ src/ARMeilleure/Decoders/OpCodeTable.cs | 341 +++++++++--------- .../Instructions/InstEmitSimdCvt32.cs | 29 ++ src/ARMeilleure/Translation/PTC/Ptc.cs | 2 +- src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs | 90 ++++- 5 files changed, 309 insertions(+), 176 deletions(-) create mode 100644 src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs new file mode 100644 index 000000000..f8564d0e5 --- /dev/null +++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtFFixed.cs @@ -0,0 +1,23 @@ +namespace ARMeilleure.Decoders +{ + class OpCode32SimdCvtFFixed : OpCode32Simd + { + public int Fbits { get; protected set; } + + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, false); + public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFFixed(inst, address, opCode, true); + + public OpCode32SimdCvtFFixed(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) + { + Opc = (opCode >> 8) & 0x1; + + Size = Opc == 1 ? 0 : 2; + Fbits = 64 - ((opCode >> 16) & 0x3f); + + if (DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vm)) + { + Instruction = InstDescriptor.Undefined; + } + } + } +} \ No newline at end of file diff --git a/src/ARMeilleure/Decoders/OpCodeTable.cs b/src/ARMeilleure/Decoders/OpCodeTable.cs index d3fc4ca08..5cfd0bb81 100644 --- a/src/ARMeilleure/Decoders/OpCodeTable.cs +++ b/src/ARMeilleure/Decoders/OpCodeTable.cs @@ -883,174 +883,175 @@ namespace ARMeilleure.Decoders SetVfp("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub, InstEmit32.Vsub_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32); // ASIMD - SetAsimd("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V, InstEmit32.Aesd_V, OpCode32Simd.Create, OpCode32Simd.CreateT32); - SetAsimd("111100111x110000xxx0001100x0xxx0", InstName.Aese_V, InstEmit32.Aese_V, OpCode32Simd.Create, OpCode32Simd.CreateT32); - SetAsimd("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, OpCode32Simd.Create, OpCode32Simd.CreateT32); - SetAsimd("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V, InstEmit32.Aesmc_V, OpCode32Simd.Create, OpCode32Simd.CreateT32); - SetAsimd("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V, InstEmit32.Sha256h_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V, InstEmit32.Sha256h2_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create, OpCode32Simd.CreateT32); - SetAsimd("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("1111001x0x<xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); - SetAsimd("111101000x10xxxxxxxx000x<>>xxxxxxx100101x1xxx0", InstName.Vqrshrn, InstEmit32.Vqrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn, InstEmit32.Vqshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun, InstEmit32.Vqshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub, InstEmit32.Vqsub, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32); - SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("111100111x11xx00xxxx000<>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); - SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32); - SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra, InstEmit32.Vrsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); - SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); - SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); - SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding. - SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); - SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); - SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); - SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); - SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); - SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); - SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); - SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create, OpCode32SimdMemPair.CreateT32); // Regs = 1. - SetAsimd("111101000x00xxxxxxxx1010xx<xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); + SetAsimd("111101000x10xxxxxxxx000x<>>xxxxxxx100101x1xxx0", InstName.Vqrshrn, InstEmit32.Vqrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn, InstEmit32.Vqshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun, InstEmit32.Vqshrun, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub, InstEmit32.Vqsub, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); + SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32); + SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); + SetAsimd("111100111x11xx00xxxx000<>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); + SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create, OpCode32SimdSqrte.CreateT32); + SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); + SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra, InstEmit32.Vrsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); + SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); + SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); + SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding. + SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); + SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32); + SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32); + SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); + SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); + SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); + SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create, OpCode32SimdMemSingle.CreateT32); + SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create, OpCode32SimdMemPair.CreateT32); // Regs = 1. + SetAsimd("111101000x00xxxxxxxx1010xx< + { + var scaledValue = context.Multiply(op1, ConstF(MathF.Pow(2f, fracBits))); + MethodInfo info = unsigned ? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToU32)) : typeof(SoftFallback).GetMethod(nameof(SoftFallback.SatF32ToS32)); + + return context.Call(info, scaledValue); + }); + } + else // S32 or U32 (fixed) to F32 + { + EmitVectorUnaryOpI32(context, (op1) => + { + var floatValue = unsigned ? context.ConvertToFPUI(OperandType.FP32, op1) : context.ConvertToFP(OperandType.FP32, op1); + + return context.Multiply(floatValue, ConstF(1f / MathF.Pow(2f, fracBits))); + }, !unsigned); + } + } + public static void Vcvt_FD(ArmEmitterContext context) { OpCode32SimdS op = (OpCode32SimdS)context.CurrOp; diff --git a/src/ARMeilleure/Translation/PTC/Ptc.cs b/src/ARMeilleure/Translation/PTC/Ptc.cs index 72b60fab0..14d4e471f 100644 --- a/src/ARMeilleure/Translation/PTC/Ptc.cs +++ b/src/ARMeilleure/Translation/PTC/Ptc.cs @@ -29,7 +29,7 @@ namespace ARMeilleure.Translation.PTC private const string OuterHeaderMagicString = "PTCohd\0\0"; private const string InnerHeaderMagicString = "PTCihd\0\0"; - private const uint InternalVersion = 5292; //! To be incremented manually for each change to the ARMeilleure project. + private const uint InternalVersion = 5343; //! To be incremented manually for each change to the ARMeilleure project. private const string ActualDir = "0"; private const string BackupDir = "1"; diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs index aa68cded3..e9a8ad590 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs @@ -395,11 +395,11 @@ namespace Ryujinx.Tests.Cpu [Explicit] [Test, Pairwise, Description("VCVT.F.F16 , ")] public void Vcvt_F16_Fx([Values(0u, 1u, 2u, 3u)] uint rd, - [Values(0u, 1u, 2u, 3u)] uint rm, - [ValueSource(nameof(_1D_F_))] ulong d0, - [ValueSource(nameof(_1D_F_))] ulong d1, - [Values] bool top, - [Values] bool sz) + [Values(0u, 1u, 2u, 3u)] uint rm, + [ValueSource(nameof(_1D_F_))] ulong d0, + [ValueSource(nameof(_1D_F_))] ulong d1, + [Values] bool top, + [Values] bool sz) { uint opcode = 0xeeb20a40; // VCVTB.F32.F16 S0, S0 @@ -426,6 +426,86 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + + [Test, Pairwise, Description("VCVT.I32.F32 , , #")] + public void Vcvt_V_Fixed_F32_I32([Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0u, 1u, 2u, 3u)] uint vm, + [ValueSource(nameof(_1S_F_))][Random(RndCnt)] ulong s0, + [ValueSource(nameof(_1S_F_))][Random(RndCnt)] ulong s1, + [ValueSource(nameof(_1S_F_))][Random(RndCnt)] ulong s2, + [ValueSource(nameof(_1S_F_))][Random(RndCnt)] ulong s3, + [Random(32u, 63u, 1)] uint fixImm, + [Values] bool unsigned, + [Values] bool q) + { + uint opcode = 0xF2800F10u; // VCVT.U32.F32 D0, D0, #0 + + if (q) + { + opcode |= 1 << 6; + vm <<= 1; + vd <<= 1; + } + + if (unsigned) + { + opcode |= 1 << 24; + } + + opcode |= ((vm & 0x10) << 1); + opcode |= ((vm & 0xf) << 0); + + opcode |= ((vd & 0x10) << 18); + opcode |= ((vd & 0xf) << 12); + + opcode |= (fixImm & 0x3f) << 16; + + var v0 = new V128((uint)s0, (uint)s1, (uint)s2, (uint)s3); + + SingleOpcode(opcode, v0: v0); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("VCVT.F32.I32 , , #")] + public void Vcvt_V_Fixed_I32_F32([Values(0u, 1u, 2u, 3u)] uint vd, + [Values(0u, 1u, 2u, 3u)] uint vm, + [ValueSource(nameof(_1S_))][Random(RndCnt)] uint s0, + [ValueSource(nameof(_1S_))][Random(RndCnt)] uint s1, + [ValueSource(nameof(_1S_))][Random(RndCnt)] uint s2, + [ValueSource(nameof(_1S_))][Random(RndCnt)] uint s3, + [Range(32u, 63u, 1)] uint fixImm, + [Values] bool unsigned, + [Values] bool q) + { + uint opcode = 0xF2800E10u; // VCVT.F32.U32 D0, D0, #0 + + if (q) + { + opcode |= 1 << 6; + vm <<= 1; + vd <<= 1; + } + + if (unsigned) + { + opcode |= 1 << 24; + } + + opcode |= ((vm & 0x10) << 1); + opcode |= ((vm & 0xf) << 0); + + opcode |= ((vd & 0x10) << 18); + opcode |= ((vd & 0xf) << 12); + + opcode |= (fixImm & 0x3f) << 16; + + var v0 = new V128(s0, s1, s2, s3); + + SingleOpcode(opcode, v0: v0); + + CompareAgainstUnicorn(); + } #endif } } \ No newline at end of file From 40f2bd37e3b025ae3b932d15971d8a8e2f8b9866 Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 18:10:55 +0200 Subject: [PATCH 18/19] [Ryujinx.Graphics.OpenGL] Address dotnet-format issues (#5372) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Address or silence dotnet format IDE1006 warnings * Fix IDE0090 after rebase * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Another rebase, another dotnet format run * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Address review feedback --- .../BackgroundContextWorker.cs | 10 +- src/Ryujinx.Graphics.OpenGL/Debugger.cs | 16 ++- .../DrawTextureEmulation.cs | 8 +- .../Effects/FsrScalingFilter.cs | 4 +- .../Effects/FxaaPostProcessingEffect.cs | 2 +- .../Effects/IPostProcessingEffect.cs | 4 +- .../Effects/IScalingFilter.cs | 2 +- .../Effects/ShaderHelper.cs | 1 - .../Effects/SmaaPostProcessingEffect.cs | 2 +- src/Ryujinx.Graphics.OpenGL/FormatInfo.cs | 42 +++---- src/Ryujinx.Graphics.OpenGL/FormatTable.cs | 8 +- src/Ryujinx.Graphics.OpenGL/Framebuffer.cs | 2 +- src/Ryujinx.Graphics.OpenGL/HwCapabilities.cs | 103 +++++++++--------- .../Image/IntermmediatePool.cs | 2 +- src/Ryujinx.Graphics.OpenGL/Image/Sampler.cs | 4 +- .../Image/TextureBuffer.cs | 4 +- .../Image/TextureCopy.cs | 32 +++--- .../Image/TextureCopyIncompatible.cs | 6 +- .../Image/TextureCopyMS.cs | 6 +- .../Image/TextureStorage.cs | 2 +- .../Image/TextureView.cs | 8 +- src/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs | 10 +- .../PersistentBuffers.cs | 10 +- src/Ryujinx.Graphics.OpenGL/Pipeline.cs | 26 +++-- src/Ryujinx.Graphics.OpenGL/Program.cs | 2 +- .../Queries/BufferedQuery.cs | 8 +- .../Queries/CounterQueue.cs | 25 ++--- .../Queries/CounterQueueEvent.cs | 4 +- .../Queries/Counters.cs | 4 +- src/Ryujinx.Graphics.OpenGL/ResourcePool.cs | 8 +- src/Ryujinx.Graphics.OpenGL/Sync.cs | 22 ++-- src/Ryujinx.Graphics.OpenGL/VertexArray.cs | 4 +- src/Ryujinx.Graphics.OpenGL/Window.cs | 4 +- 33 files changed, 198 insertions(+), 197 deletions(-) diff --git a/src/Ryujinx.Graphics.OpenGL/BackgroundContextWorker.cs b/src/Ryujinx.Graphics.OpenGL/BackgroundContextWorker.cs index 764ea7159..ae647e388 100644 --- a/src/Ryujinx.Graphics.OpenGL/BackgroundContextWorker.cs +++ b/src/Ryujinx.Graphics.OpenGL/BackgroundContextWorker.cs @@ -9,12 +9,12 @@ namespace Ryujinx.Graphics.OpenGL { [ThreadStatic] public static bool InBackground; - private Thread _thread; + private readonly Thread _thread; private bool _running; - private AutoResetEvent _signal; - private Queue _work; - private ObjectPool _invokePool; + private readonly AutoResetEvent _signal; + private readonly Queue _work; + private readonly ObjectPool _invokePool; private readonly IOpenGLContext _backgroundContext; public BackgroundContextWorker(IOpenGLContext backgroundContext) @@ -88,4 +88,4 @@ namespace Ryujinx.Graphics.OpenGL _signal.Dispose(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Debugger.cs b/src/Ryujinx.Graphics.OpenGL/Debugger.cs index 9f67cfc67..7606bdbfd 100644 --- a/src/Ryujinx.Graphics.OpenGL/Debugger.cs +++ b/src/Ryujinx.Graphics.OpenGL/Debugger.cs @@ -63,10 +63,18 @@ namespace Ryujinx.Graphics.OpenGL switch (type) { - case DebugType.DebugTypeError : Logger.Error?.Print(LogClass.Gpu, $"{severity}: {msg}\nCallStack={Environment.StackTrace}", "GLERROR"); break; - case DebugType.DebugTypePerformance: Logger.Warning?.Print(LogClass.Gpu, $"{severity}: {msg}", "GLPERF"); break; - case DebugType.DebugTypePushGroup : Logger.Info?.Print(LogClass.Gpu, $"{{ ({id}) {severity}: {msg}", "GLINFO"); break; - case DebugType.DebugTypePopGroup : Logger.Info?.Print(LogClass.Gpu, $"}} ({id}) {severity}: {msg}", "GLINFO"); break; + case DebugType.DebugTypeError: + Logger.Error?.Print(LogClass.Gpu, $"{severity}: {msg}\nCallStack={Environment.StackTrace}", "GLERROR"); + break; + case DebugType.DebugTypePerformance: + Logger.Warning?.Print(LogClass.Gpu, $"{severity}: {msg}", "GLPERF"); + break; + case DebugType.DebugTypePushGroup: + Logger.Info?.Print(LogClass.Gpu, $"{{ ({id}) {severity}: {msg}", "GLINFO"); + break; + case DebugType.DebugTypePopGroup: + Logger.Info?.Print(LogClass.Gpu, $"}} ({id}) {severity}: {msg}", "GLINFO"); + break; default: if (source == DebugSource.DebugSourceApplication) { diff --git a/src/Ryujinx.Graphics.OpenGL/DrawTextureEmulation.cs b/src/Ryujinx.Graphics.OpenGL/DrawTextureEmulation.cs index 509e20fe2..7a6af95ea 100644 --- a/src/Ryujinx.Graphics.OpenGL/DrawTextureEmulation.cs +++ b/src/Ryujinx.Graphics.OpenGL/DrawTextureEmulation.cs @@ -65,16 +65,12 @@ void main() if (x0 > x1) { - float temp = s0; - s0 = s1; - s1 = temp; + (s1, s0) = (s0, s1); } if (y0 > y1) { - float temp = t0; - t0 = t1; - t1 = temp; + (t1, t0) = (t0, t1); } GL.Uniform1(_uniformSrcX0Location, s0); diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/FsrScalingFilter.cs b/src/Ryujinx.Graphics.OpenGL/Effects/FsrScalingFilter.cs index 16678bb7b..5daaf8c45 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/FsrScalingFilter.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/FsrScalingFilter.cs @@ -37,7 +37,7 @@ namespace Ryujinx.Graphics.OpenGL.Effects } } - public FsrScalingFilter(OpenGLRenderer renderer, IPostProcessingEffect filter) + public FsrScalingFilter(OpenGLRenderer renderer) { Initialize(); @@ -174,4 +174,4 @@ namespace Ryujinx.Graphics.OpenGL.Effects GL.ActiveTexture((TextureUnit)previousUnit); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/FxaaPostProcessingEffect.cs b/src/Ryujinx.Graphics.OpenGL/Effects/FxaaPostProcessingEffect.cs index 3a2d685b7..c8f170846 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/FxaaPostProcessingEffect.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/FxaaPostProcessingEffect.cs @@ -78,4 +78,4 @@ namespace Ryujinx.Graphics.OpenGL.Effects return textureView; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/IPostProcessingEffect.cs b/src/Ryujinx.Graphics.OpenGL/Effects/IPostProcessingEffect.cs index 7a045a021..154e74921 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/IPostProcessingEffect.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/IPostProcessingEffect.cs @@ -3,9 +3,9 @@ using System; namespace Ryujinx.Graphics.OpenGL.Effects { - internal interface IPostProcessingEffect : IDisposable + internal interface IPostProcessingEffect : IDisposable { const int LocalGroupSize = 64; TextureView Run(TextureView view, int width, int height); } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/IScalingFilter.cs b/src/Ryujinx.Graphics.OpenGL/Effects/IScalingFilter.cs index e1e1b2c1d..b5c80878a 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/IScalingFilter.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/IScalingFilter.cs @@ -15,4 +15,4 @@ namespace Ryujinx.Graphics.OpenGL.Effects Extents2D source, Extents2D destination); } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/ShaderHelper.cs b/src/Ryujinx.Graphics.OpenGL/Effects/ShaderHelper.cs index 72c5a98f5..976b3410b 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/ShaderHelper.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/ShaderHelper.cs @@ -1,5 +1,4 @@ using OpenTK.Graphics.OpenGL; -using System; namespace Ryujinx.Graphics.OpenGL.Effects { diff --git a/src/Ryujinx.Graphics.OpenGL/Effects/SmaaPostProcessingEffect.cs b/src/Ryujinx.Graphics.OpenGL/Effects/SmaaPostProcessingEffect.cs index 1ad300c88..eede852f7 100644 --- a/src/Ryujinx.Graphics.OpenGL/Effects/SmaaPostProcessingEffect.cs +++ b/src/Ryujinx.Graphics.OpenGL/Effects/SmaaPostProcessingEffect.cs @@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.OpenGL.Effects.Smaa private int[] _neighbourShaderPrograms; private TextureStorage _edgeOutputTexture; private TextureStorage _blendOutputTexture; - private string[] _qualities; + private readonly string[] _qualities; private int _inputUniform; private int _outputUniform; private int _samplerAreaUniform; diff --git a/src/Ryujinx.Graphics.OpenGL/FormatInfo.cs b/src/Ryujinx.Graphics.OpenGL/FormatInfo.cs index aef4dbad3..c1a97e81a 100644 --- a/src/Ryujinx.Graphics.OpenGL/FormatInfo.cs +++ b/src/Ryujinx.Graphics.OpenGL/FormatInfo.cs @@ -4,42 +4,42 @@ namespace Ryujinx.Graphics.OpenGL { readonly struct FormatInfo { - public int Components { get; } + public int Components { get; } public bool Normalized { get; } - public bool Scaled { get; } + public bool Scaled { get; } public PixelInternalFormat PixelInternalFormat { get; } - public PixelFormat PixelFormat { get; } - public PixelType PixelType { get; } + public PixelFormat PixelFormat { get; } + public PixelType PixelType { get; } public bool IsCompressed { get; } public FormatInfo( - int components, - bool normalized, - bool scaled, - All pixelInternalFormat, + int components, + bool normalized, + bool scaled, + All pixelInternalFormat, PixelFormat pixelFormat, - PixelType pixelType) + PixelType pixelType) { - Components = components; - Normalized = normalized; - Scaled = scaled; + Components = components; + Normalized = normalized; + Scaled = scaled; PixelInternalFormat = (PixelInternalFormat)pixelInternalFormat; - PixelFormat = pixelFormat; - PixelType = pixelType; - IsCompressed = false; + PixelFormat = pixelFormat; + PixelType = pixelType; + IsCompressed = false; } public FormatInfo(int components, bool normalized, bool scaled, All pixelFormat) { - Components = components; - Normalized = normalized; - Scaled = scaled; + Components = components; + Normalized = normalized; + Scaled = scaled; PixelInternalFormat = 0; - PixelFormat = (PixelFormat)pixelFormat; - PixelType = 0; - IsCompressed = true; + PixelFormat = (PixelFormat)pixelFormat; + PixelType = 0; + IsCompressed = true; } } } diff --git a/src/Ryujinx.Graphics.OpenGL/FormatTable.cs b/src/Ryujinx.Graphics.OpenGL/FormatTable.cs index 281f0004f..3dac33b94 100644 --- a/src/Ryujinx.Graphics.OpenGL/FormatTable.cs +++ b/src/Ryujinx.Graphics.OpenGL/FormatTable.cs @@ -4,10 +4,10 @@ using System; namespace Ryujinx.Graphics.OpenGL { - struct FormatTable + readonly struct FormatTable { - private static FormatInfo[] _table; - private static SizedInternalFormat[] _tableImage; + private static readonly FormatInfo[] _table; + private static readonly SizedInternalFormat[] _tableImage; static FormatTable() { @@ -16,6 +16,7 @@ namespace Ryujinx.Graphics.OpenGL _table = new FormatInfo[tableSize]; _tableImage = new SizedInternalFormat[tableSize]; +#pragma warning disable IDE0055 // Disable formatting Add(Format.R8Unorm, new FormatInfo(1, true, false, All.R8, PixelFormat.Red, PixelType.UnsignedByte)); Add(Format.R8Snorm, new FormatInfo(1, true, false, All.R8Snorm, PixelFormat.Red, PixelType.Byte)); Add(Format.R8Uint, new FormatInfo(1, false, false, All.R8ui, PixelFormat.RedInteger, PixelType.UnsignedByte)); @@ -200,6 +201,7 @@ namespace Ryujinx.Graphics.OpenGL Add(Format.R10G10B10A2Unorm, (SizedInternalFormat)All.Rgb10A2); Add(Format.R10G10B10A2Uint, (SizedInternalFormat)All.Rgb10A2ui); Add(Format.R11G11B10Float, (SizedInternalFormat)All.R11fG11fB10f); +#pragma warning restore IDE0055 } private static void Add(Format format, FormatInfo info) diff --git a/src/Ryujinx.Graphics.OpenGL/Framebuffer.cs b/src/Ryujinx.Graphics.OpenGL/Framebuffer.cs index b180b8578..3b79c5d6b 100644 --- a/src/Ryujinx.Graphics.OpenGL/Framebuffer.cs +++ b/src/Ryujinx.Graphics.OpenGL/Framebuffer.cs @@ -105,7 +105,7 @@ namespace Ryujinx.Graphics.OpenGL _colorsCount = colorsCount; } - private void SetDrawBuffersImpl(int colorsCount) + private static void SetDrawBuffersImpl(int colorsCount) { DrawBuffersEnum[] drawBuffers = new DrawBuffersEnum[colorsCount]; diff --git a/src/Ryujinx.Graphics.OpenGL/HwCapabilities.cs b/src/Ryujinx.Graphics.OpenGL/HwCapabilities.cs index dd0b1501f..d7d993459 100644 --- a/src/Ryujinx.Graphics.OpenGL/HwCapabilities.cs +++ b/src/Ryujinx.Graphics.OpenGL/HwCapabilities.cs @@ -5,30 +5,30 @@ namespace Ryujinx.Graphics.OpenGL { static class HwCapabilities { - private static readonly Lazy _supportsAlphaToCoverageDitherControl = new Lazy(() => HasExtension("GL_NV_alpha_to_coverage_dither_control")); - private static readonly Lazy _supportsAstcCompression = new Lazy(() => HasExtension("GL_KHR_texture_compression_astc_ldr")); - private static readonly Lazy _supportsBlendEquationAdvanced = new Lazy(() => HasExtension("GL_NV_blend_equation_advanced")); - private static readonly Lazy _supportsDrawTexture = new Lazy(() => HasExtension("GL_NV_draw_texture")); - private static readonly Lazy _supportsFragmentShaderInterlock = new Lazy(() => HasExtension("GL_ARB_fragment_shader_interlock")); - private static readonly Lazy _supportsFragmentShaderOrdering = new Lazy(() => HasExtension("GL_INTEL_fragment_shader_ordering")); - private static readonly Lazy _supportsGeometryShaderPassthrough = new Lazy(() => HasExtension("GL_NV_geometry_shader_passthrough")); - private static readonly Lazy _supportsImageLoadFormatted = new Lazy(() => HasExtension("GL_EXT_shader_image_load_formatted")); - private static readonly Lazy _supportsIndirectParameters = new Lazy(() => HasExtension("GL_ARB_indirect_parameters")); - private static readonly Lazy _supportsParallelShaderCompile = new Lazy(() => HasExtension("GL_ARB_parallel_shader_compile")); - private static readonly Lazy _supportsPolygonOffsetClamp = new Lazy(() => HasExtension("GL_EXT_polygon_offset_clamp")); - private static readonly Lazy _supportsQuads = new Lazy(SupportsQuadsCheck); - private static readonly Lazy _supportsSeamlessCubemapPerTexture = new Lazy(() => HasExtension("GL_ARB_seamless_cubemap_per_texture")); - private static readonly Lazy _supportsShaderBallot = new Lazy(() => HasExtension("GL_ARB_shader_ballot")); - private static readonly Lazy _supportsShaderViewportLayerArray = new Lazy(() => HasExtension("GL_ARB_shader_viewport_layer_array")); - private static readonly Lazy _supportsViewportArray2 = new Lazy(() => HasExtension("GL_NV_viewport_array2")); - private static readonly Lazy _supportsTextureCompressionBptc = new Lazy(() => HasExtension("GL_EXT_texture_compression_bptc")); - private static readonly Lazy _supportsTextureCompressionRgtc = new Lazy(() => HasExtension("GL_EXT_texture_compression_rgtc")); - private static readonly Lazy _supportsTextureCompressionS3tc = new Lazy(() => HasExtension("GL_EXT_texture_compression_s3tc")); - private static readonly Lazy _supportsTextureShadowLod = new Lazy(() => HasExtension("GL_EXT_texture_shadow_lod")); - private static readonly Lazy _supportsViewportSwizzle = new Lazy(() => HasExtension("GL_NV_viewport_swizzle")); + private static readonly Lazy _supportsAlphaToCoverageDitherControl = new(() => HasExtension("GL_NV_alpha_to_coverage_dither_control")); + private static readonly Lazy _supportsAstcCompression = new(() => HasExtension("GL_KHR_texture_compression_astc_ldr")); + private static readonly Lazy _supportsBlendEquationAdvanced = new(() => HasExtension("GL_NV_blend_equation_advanced")); + private static readonly Lazy _supportsDrawTexture = new(() => HasExtension("GL_NV_draw_texture")); + private static readonly Lazy _supportsFragmentShaderInterlock = new(() => HasExtension("GL_ARB_fragment_shader_interlock")); + private static readonly Lazy _supportsFragmentShaderOrdering = new(() => HasExtension("GL_INTEL_fragment_shader_ordering")); + private static readonly Lazy _supportsGeometryShaderPassthrough = new(() => HasExtension("GL_NV_geometry_shader_passthrough")); + private static readonly Lazy _supportsImageLoadFormatted = new(() => HasExtension("GL_EXT_shader_image_load_formatted")); + private static readonly Lazy _supportsIndirectParameters = new(() => HasExtension("GL_ARB_indirect_parameters")); + private static readonly Lazy _supportsParallelShaderCompile = new(() => HasExtension("GL_ARB_parallel_shader_compile")); + private static readonly Lazy _supportsPolygonOffsetClamp = new(() => HasExtension("GL_EXT_polygon_offset_clamp")); + private static readonly Lazy _supportsQuads = new(SupportsQuadsCheck); + private static readonly Lazy _supportsSeamlessCubemapPerTexture = new(() => HasExtension("GL_ARB_seamless_cubemap_per_texture")); + private static readonly Lazy _supportsShaderBallot = new(() => HasExtension("GL_ARB_shader_ballot")); + private static readonly Lazy _supportsShaderViewportLayerArray = new(() => HasExtension("GL_ARB_shader_viewport_layer_array")); + private static readonly Lazy _supportsViewportArray2 = new(() => HasExtension("GL_NV_viewport_array2")); + private static readonly Lazy _supportsTextureCompressionBptc = new(() => HasExtension("GL_EXT_texture_compression_bptc")); + private static readonly Lazy _supportsTextureCompressionRgtc = new(() => HasExtension("GL_EXT_texture_compression_rgtc")); + private static readonly Lazy _supportsTextureCompressionS3tc = new(() => HasExtension("GL_EXT_texture_compression_s3tc")); + private static readonly Lazy _supportsTextureShadowLod = new(() => HasExtension("GL_EXT_texture_shadow_lod")); + private static readonly Lazy _supportsViewportSwizzle = new(() => HasExtension("GL_NV_viewport_swizzle")); - private static readonly Lazy _maximumComputeSharedMemorySize = new Lazy(() => GetLimit(All.MaxComputeSharedMemorySize)); - private static readonly Lazy _storageBufferOffsetAlignment = new Lazy(() => GetLimit(All.ShaderStorageBufferOffsetAlignment)); + private static readonly Lazy _maximumComputeSharedMemorySize = new(() => GetLimit(All.MaxComputeSharedMemorySize)); + private static readonly Lazy _storageBufferOffsetAlignment = new(() => GetLimit(All.ShaderStorageBufferOffsetAlignment)); public enum GpuVendor { @@ -40,45 +40,44 @@ namespace Ryujinx.Graphics.OpenGL Nvidia } - private static readonly Lazy _gpuVendor = new Lazy(GetGpuVendor); + private static readonly Lazy _gpuVendor = new(GetGpuVendor); - private static bool _isAMD => _gpuVendor.Value == GpuVendor.AmdWindows || _gpuVendor.Value == GpuVendor.AmdUnix; - private static bool _isIntel => _gpuVendor.Value == GpuVendor.IntelWindows || _gpuVendor.Value == GpuVendor.IntelUnix; + private static bool IsIntel => _gpuVendor.Value == GpuVendor.IntelWindows || _gpuVendor.Value == GpuVendor.IntelUnix; public static GpuVendor Vendor => _gpuVendor.Value; - private static Lazy _maxSupportedAnisotropy = new Lazy(GL.GetFloat((GetPName)All.MaxTextureMaxAnisotropy)); + private static readonly Lazy _maxSupportedAnisotropy = new(GL.GetFloat((GetPName)All.MaxTextureMaxAnisotropy)); - public static bool UsePersistentBufferForFlush => _gpuVendor.Value == GpuVendor.AmdWindows || _gpuVendor.Value == GpuVendor.Nvidia; + public static bool UsePersistentBufferForFlush => _gpuVendor.Value == GpuVendor.AmdWindows || _gpuVendor.Value == GpuVendor.Nvidia; public static bool SupportsAlphaToCoverageDitherControl => _supportsAlphaToCoverageDitherControl.Value; - public static bool SupportsAstcCompression => _supportsAstcCompression.Value; - public static bool SupportsBlendEquationAdvanced => _supportsBlendEquationAdvanced.Value; - public static bool SupportsDrawTexture => _supportsDrawTexture.Value; - public static bool SupportsFragmentShaderInterlock => _supportsFragmentShaderInterlock.Value; - public static bool SupportsFragmentShaderOrdering => _supportsFragmentShaderOrdering.Value; - public static bool SupportsGeometryShaderPassthrough => _supportsGeometryShaderPassthrough.Value; - public static bool SupportsImageLoadFormatted => _supportsImageLoadFormatted.Value; - public static bool SupportsIndirectParameters => _supportsIndirectParameters.Value; - public static bool SupportsParallelShaderCompile => _supportsParallelShaderCompile.Value; - public static bool SupportsPolygonOffsetClamp => _supportsPolygonOffsetClamp.Value; - public static bool SupportsQuads => _supportsQuads.Value; - public static bool SupportsSeamlessCubemapPerTexture => _supportsSeamlessCubemapPerTexture.Value; - public static bool SupportsShaderBallot => _supportsShaderBallot.Value; - public static bool SupportsShaderViewportLayerArray => _supportsShaderViewportLayerArray.Value; - public static bool SupportsViewportArray2 => _supportsViewportArray2.Value; - public static bool SupportsTextureCompressionBptc => _supportsTextureCompressionBptc.Value; - public static bool SupportsTextureCompressionRgtc => _supportsTextureCompressionRgtc.Value; - public static bool SupportsTextureCompressionS3tc => _supportsTextureCompressionS3tc.Value; - public static bool SupportsTextureShadowLod => _supportsTextureShadowLod.Value; - public static bool SupportsViewportSwizzle => _supportsViewportSwizzle.Value; + public static bool SupportsAstcCompression => _supportsAstcCompression.Value; + public static bool SupportsBlendEquationAdvanced => _supportsBlendEquationAdvanced.Value; + public static bool SupportsDrawTexture => _supportsDrawTexture.Value; + public static bool SupportsFragmentShaderInterlock => _supportsFragmentShaderInterlock.Value; + public static bool SupportsFragmentShaderOrdering => _supportsFragmentShaderOrdering.Value; + public static bool SupportsGeometryShaderPassthrough => _supportsGeometryShaderPassthrough.Value; + public static bool SupportsImageLoadFormatted => _supportsImageLoadFormatted.Value; + public static bool SupportsIndirectParameters => _supportsIndirectParameters.Value; + public static bool SupportsParallelShaderCompile => _supportsParallelShaderCompile.Value; + public static bool SupportsPolygonOffsetClamp => _supportsPolygonOffsetClamp.Value; + public static bool SupportsQuads => _supportsQuads.Value; + public static bool SupportsSeamlessCubemapPerTexture => _supportsSeamlessCubemapPerTexture.Value; + public static bool SupportsShaderBallot => _supportsShaderBallot.Value; + public static bool SupportsShaderViewportLayerArray => _supportsShaderViewportLayerArray.Value; + public static bool SupportsViewportArray2 => _supportsViewportArray2.Value; + public static bool SupportsTextureCompressionBptc => _supportsTextureCompressionBptc.Value; + public static bool SupportsTextureCompressionRgtc => _supportsTextureCompressionRgtc.Value; + public static bool SupportsTextureCompressionS3tc => _supportsTextureCompressionS3tc.Value; + public static bool SupportsTextureShadowLod => _supportsTextureShadowLod.Value; + public static bool SupportsViewportSwizzle => _supportsViewportSwizzle.Value; - public static bool SupportsMismatchingViewFormat => _gpuVendor.Value != GpuVendor.AmdWindows && _gpuVendor.Value != GpuVendor.IntelWindows; + public static bool SupportsMismatchingViewFormat => _gpuVendor.Value != GpuVendor.AmdWindows && _gpuVendor.Value != GpuVendor.IntelWindows; public static bool SupportsNonConstantTextureOffset => _gpuVendor.Value == GpuVendor.Nvidia; - public static bool RequiresSyncFlush => _gpuVendor.Value == GpuVendor.AmdWindows || _isIntel; + public static bool RequiresSyncFlush => _gpuVendor.Value == GpuVendor.AmdWindows || IsIntel; public static int MaximumComputeSharedMemorySize => _maximumComputeSharedMemorySize.Value; - public static int StorageBufferOffsetAlignment => _storageBufferOffsetAlignment.Value; + public static int StorageBufferOffsetAlignment => _storageBufferOffsetAlignment.Value; public static float MaximumSupportedAnisotropy => _maxSupportedAnisotropy.Value; @@ -139,4 +138,4 @@ namespace Ryujinx.Graphics.OpenGL return GL.GetError() == ErrorCode.NoError; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Image/IntermmediatePool.cs b/src/Ryujinx.Graphics.OpenGL/Image/IntermmediatePool.cs index 4f167e893..1a08f973a 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/IntermmediatePool.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/IntermmediatePool.cs @@ -100,4 +100,4 @@ namespace Ryujinx.Graphics.OpenGL.Image _entries.Clear(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/Image/Sampler.cs b/src/Ryujinx.Graphics.OpenGL/Image/Sampler.cs index f705aa3e7..18dd1b72a 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/Sampler.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/Sampler.cs @@ -39,8 +39,8 @@ namespace Ryujinx.Graphics.OpenGL.Image GL.SamplerParameter(Handle, SamplerParameterName.TextureBorderColor, borderColor); } - GL.SamplerParameter(Handle, SamplerParameterName.TextureMinLod, info.MinLod); - GL.SamplerParameter(Handle, SamplerParameterName.TextureMaxLod, info.MaxLod); + GL.SamplerParameter(Handle, SamplerParameterName.TextureMinLod, info.MinLod); + GL.SamplerParameter(Handle, SamplerParameterName.TextureMaxLod, info.MaxLod); GL.SamplerParameter(Handle, SamplerParameterName.TextureLodBias, info.MipLodBias); GL.SamplerParameter(Handle, SamplerParameterName.TextureMaxAnisotropyExt, info.MaxAnisotropy); diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureBuffer.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureBuffer.cs index 116f70cc7..c177ae9c6 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureBuffer.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureBuffer.cs @@ -7,7 +7,7 @@ namespace Ryujinx.Graphics.OpenGL.Image { class TextureBuffer : TextureBase, ITexture { - private OpenGLRenderer _renderer; + private readonly OpenGLRenderer _renderer; private int _bufferOffset; private int _bufferSize; private int _bufferCount; @@ -58,7 +58,7 @@ namespace Ryujinx.Graphics.OpenGL.Image { var dataSpan = data.AsSpan(); - Buffer.SetData(_buffer, _bufferOffset, dataSpan.Slice(0, Math.Min(dataSpan.Length, _bufferSize))); + Buffer.SetData(_buffer, _bufferOffset, dataSpan[..Math.Min(dataSpan.Length, _bufferSize)]); } public void SetData(SpanOrArray data, int layer, int level) diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopy.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopy.cs index a4b08787b..bb1911e8b 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopy.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopy.cs @@ -26,13 +26,13 @@ namespace Ryujinx.Graphics.OpenGL.Image public void Copy( TextureView src, TextureView dst, - Extents2D srcRegion, - Extents2D dstRegion, - bool linearFilter, - int srcLayer = 0, - int dstLayer = 0, - int srcLevel = 0, - int dstLevel = 0) + Extents2D srcRegion, + Extents2D dstRegion, + bool linearFilter, + int srcLayer = 0, + int dstLayer = 0, + int srcLevel = 0, + int dstLevel = 0) { int levels = Math.Min(src.Info.Levels - srcLevel, dst.Info.Levels - dstLevel); int layers = Math.Min(src.Info.GetLayers() - srcLayer, dst.Info.GetLayers() - dstLayer); @@ -43,15 +43,15 @@ namespace Ryujinx.Graphics.OpenGL.Image public void Copy( TextureView src, TextureView dst, - Extents2D srcRegion, - Extents2D dstRegion, - bool linearFilter, - int srcLayer, - int dstLayer, - int srcLevel, - int dstLevel, - int layers, - int levels) + Extents2D srcRegion, + Extents2D dstRegion, + bool linearFilter, + int srcLayer, + int dstLayer, + int srcLevel, + int dstLevel, + int layers, + int levels) { TextureView srcConverted = src.Format.IsBgr() != dst.Format.IsBgr() ? BgraSwap(src) : src; diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyIncompatible.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyIncompatible.cs index c8fbfbc6a..6b5fb376b 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyIncompatible.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyIncompatible.cs @@ -1,5 +1,4 @@ using OpenTK.Graphics.OpenGL; -using Ryujinx.Graphics.GAL; using System; using System.Collections.Generic; using System.Globalization; @@ -81,9 +80,6 @@ void main() public void CopyIncompatibleFormats(ITextureInfo src, ITextureInfo dst, int srcLayer, int dstLayer, int srcLevel, int dstLevel, int depth, int levels) { - TextureCreateInfo srcInfo = src.Info; - TextureCreateInfo dstInfo = dst.Info; - int srcBpp = src.Info.BytesPerPixel; int dstBpp = dst.Info.BytesPerPixel; @@ -176,7 +172,7 @@ void main() return GetShader(ComputeShaderWidening, _wideningProgramHandles, componentSize, srcComponentsCount, dstComponentsCount); } - private int GetShader( + private static int GetShader( string code, Dictionary programHandles, int componentSize, diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyMS.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyMS.cs index 9963dc661..39f232723 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyMS.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureCopyMS.cs @@ -94,8 +94,8 @@ void main() }"; private readonly OpenGLRenderer _renderer; - private int[] _msToNonMSProgramHandles; - private int[] _nonMSToMSProgramHandles; + private readonly int[] _msToNonMSProgramHandles; + private readonly int[] _nonMSToMSProgramHandles; public TextureCopyMS(OpenGLRenderer renderer) { @@ -219,7 +219,7 @@ void main() return GetShader(ComputeShaderNonMSToMS, _nonMSToMSProgramHandles, bytesPerPixel); } - private int GetShader(string code, int[] programHandles, int bytesPerPixel) + private static int GetShader(string code, int[] programHandles, int bytesPerPixel) { int index = BitOperations.Log2((uint)bytesPerPixel); diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureStorage.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureStorage.cs index c058ac885..d714caf38 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureStorage.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureStorage.cs @@ -21,7 +21,7 @@ namespace Ryujinx.Graphics.OpenGL.Image public TextureStorage(OpenGLRenderer renderer, TextureCreateInfo info, float scaleFactor) { _renderer = renderer; - Info = info; + Info = info; Handle = GL.GenTexture(); ScaleFactor = scaleFactor; diff --git a/src/Ryujinx.Graphics.OpenGL/Image/TextureView.cs b/src/Ryujinx.Graphics.OpenGL/Image/TextureView.cs index 90a2936d0..21d8e449c 100644 --- a/src/Ryujinx.Graphics.OpenGL/Image/TextureView.cs +++ b/src/Ryujinx.Graphics.OpenGL/Image/TextureView.cs @@ -88,9 +88,7 @@ namespace Ryujinx.Graphics.OpenGL.Image { // Swap B <-> R for BGRA formats, as OpenGL has no support for them // and we need to manually swap the components on read/write on the GPU. - int temp = swizzleRgba[0]; - swizzleRgba[0] = swizzleRgba[2]; - swizzleRgba[2] = temp; + (swizzleRgba[2], swizzleRgba[0]) = (swizzleRgba[0], swizzleRgba[2]); } GL.TexParameter(target, TextureParameterName.TextureSwizzleRgba, swizzleRgba); @@ -186,8 +184,8 @@ namespace Ryujinx.Graphics.OpenGL.Image // This approach uses blit, which causes a resolution loss since some samples will be lost // in the process. - Extents2D srcRegion = new Extents2D(0, 0, Width, Height); - Extents2D dstRegion = new Extents2D(0, 0, destinationView.Width, destinationView.Height); + Extents2D srcRegion = new(0, 0, Width, Height); + Extents2D dstRegion = new(0, 0, destinationView.Width, destinationView.Height); if (destinationView.Target.IsMultisample()) { diff --git a/src/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs b/src/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs index c7c01a37b..b4c567a81 100644 --- a/src/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs +++ b/src/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs @@ -21,13 +21,13 @@ namespace Ryujinx.Graphics.OpenGL public IWindow Window => _window; - private TextureCopy _textureCopy; - private TextureCopy _backgroundTextureCopy; + private readonly TextureCopy _textureCopy; + private readonly TextureCopy _backgroundTextureCopy; internal TextureCopy TextureCopy => BackgroundContextWorker.InBackground ? _backgroundTextureCopy : _textureCopy; internal TextureCopyIncompatible TextureCopyIncompatible { get; } internal TextureCopyMS TextureCopyMS { get; } - private Sync _sync; + private readonly Sync _sync; public event EventHandler ScreenCaptured; @@ -222,9 +222,9 @@ namespace Ryujinx.Graphics.OpenGL private void PrintGpuInformation() { - GpuVendor = GL.GetString(StringName.Vendor); + GpuVendor = GL.GetString(StringName.Vendor); GpuRenderer = GL.GetString(StringName.Renderer); - GpuVersion = GL.GetString(StringName.Version); + GpuVersion = GL.GetString(StringName.Version); Logger.Notice.Print(LogClass.Gpu, $"{GpuVendor} {GpuRenderer} ({GpuVersion})"); } diff --git a/src/Ryujinx.Graphics.OpenGL/PersistentBuffers.cs b/src/Ryujinx.Graphics.OpenGL/PersistentBuffers.cs index aac288b7e..ebfe3ad64 100644 --- a/src/Ryujinx.Graphics.OpenGL/PersistentBuffers.cs +++ b/src/Ryujinx.Graphics.OpenGL/PersistentBuffers.cs @@ -11,10 +11,10 @@ namespace Ryujinx.Graphics.OpenGL { class PersistentBuffers : IDisposable { - private PersistentBuffer _main = new PersistentBuffer(); - private PersistentBuffer _background = new PersistentBuffer(); + private readonly PersistentBuffer _main = new(); + private readonly PersistentBuffer _background = new(); - private Dictionary _maps = new Dictionary(); + private readonly Dictionary _maps = new(); public PersistentBuffer Default => BackgroundContextWorker.InBackground ? _background : _main; @@ -91,7 +91,7 @@ namespace Ryujinx.Graphics.OpenGL return _dataMap; } - private void Sync() + private static void Sync() { GL.MemoryBarrier(MemoryBarrierFlags.ClientMappedBufferBarrierBit); @@ -133,7 +133,7 @@ namespace Ryujinx.Graphics.OpenGL Sync(); - return new ReadOnlySpan(_bufferMap.ToPointer(), size).Slice(offset); + return new ReadOnlySpan(_bufferMap.ToPointer(), size)[offset..]; } public unsafe ReadOnlySpan GetBufferData(BufferHandle buffer, int offset, int size) diff --git a/src/Ryujinx.Graphics.OpenGL/Pipeline.cs b/src/Ryujinx.Graphics.OpenGL/Pipeline.cs index 6b6d0289c..df618d5bc 100644 --- a/src/Ryujinx.Graphics.OpenGL/Pipeline.cs +++ b/src/Ryujinx.Graphics.OpenGL/Pipeline.cs @@ -44,11 +44,11 @@ namespace Ryujinx.Graphics.OpenGL private CounterQueueEvent _activeConditionalRender; - private Vector4[] _fpIsBgra = new Vector4[SupportBuffer.FragmentIsBgraCount]; - private Vector4[] _renderScale = new Vector4[73]; + private readonly Vector4[] _fpIsBgra = new Vector4[SupportBuffer.FragmentIsBgraCount]; + private readonly Vector4[] _renderScale = new Vector4[73]; private int _fragmentScaleCount; - private (TextureBase, Format)[] _images; + private readonly (TextureBase, Format)[] _images; private TextureBase _unit0Texture; private Sampler _unit0Sampler; @@ -260,7 +260,7 @@ namespace Ryujinx.Graphics.OpenGL PostDraw(); } - private void DrawQuadsImpl( + private static void DrawQuadsImpl( int vertexCount, int instanceCount, int firstVertex, @@ -285,7 +285,7 @@ namespace Ryujinx.Graphics.OpenGL quadsCount); } - private void DrawQuadStripImpl( + private static void DrawQuadStripImpl( int vertexCount, int instanceCount, int firstVertex, @@ -366,8 +366,12 @@ namespace Ryujinx.Graphics.OpenGL switch (_elementsType) { - case DrawElementsType.UnsignedShort: indexElemSize = 2; break; - case DrawElementsType.UnsignedInt: indexElemSize = 4; break; + case DrawElementsType.UnsignedShort: + indexElemSize = 2; + break; + case DrawElementsType.UnsignedInt: + indexElemSize = 4; + break; } IntPtr indexBaseOffset = _indexBaseOffset + firstIndex * indexElemSize; @@ -1471,7 +1475,7 @@ namespace Ryujinx.Graphics.OpenGL GL.MemoryBarrier(MemoryBarrierFlags.TextureFetchBarrierBit); } - private void SetBuffers(ReadOnlySpan buffers, bool isStorage) + private static void SetBuffers(ReadOnlySpan buffers, bool isStorage) { BufferRangeTarget target = isStorage ? BufferRangeTarget.ShaderStorageBuffer : BufferRangeTarget.UniformBuffer; @@ -1701,11 +1705,9 @@ namespace Ryujinx.Graphics.OpenGL public bool TryHostConditionalRendering(ICounterEvent value, ulong compare, bool isEqual) { - if (value is CounterQueueEvent) + // Compare an event and a constant value. + if (value is CounterQueueEvent evt) { - // Compare an event and a constant value. - CounterQueueEvent evt = (CounterQueueEvent)value; - // Easy host conditional rendering when the check matches what GL can do: // - Event is of type samples passed. // - Result is not a combination of multiple queries. diff --git a/src/Ryujinx.Graphics.OpenGL/Program.cs b/src/Ryujinx.Graphics.OpenGL/Program.cs index a6009108a..cc9120c7c 100644 --- a/src/Ryujinx.Graphics.OpenGL/Program.cs +++ b/src/Ryujinx.Graphics.OpenGL/Program.cs @@ -123,7 +123,7 @@ namespace Ryujinx.Graphics.OpenGL if (log.Length > MaxShaderLogLength) { - log = log.Substring(0, MaxShaderLogLength) + "..."; + log = log[..MaxShaderLogLength] + "..."; } Logger.Warning?.Print(LogClass.Gpu, $"Shader linking failed: \n{log}"); diff --git a/src/Ryujinx.Graphics.OpenGL/Queries/BufferedQuery.cs b/src/Ryujinx.Graphics.OpenGL/Queries/BufferedQuery.cs index 9d43f6c3f..1470f5aaa 100644 --- a/src/Ryujinx.Graphics.OpenGL/Queries/BufferedQuery.cs +++ b/src/Ryujinx.Graphics.OpenGL/Queries/BufferedQuery.cs @@ -14,9 +14,9 @@ namespace Ryujinx.Graphics.OpenGL.Queries public int Query { get; } - private int _buffer; - private IntPtr _bufferMap; - private QueryTarget _type; + private readonly int _buffer; + private readonly IntPtr _bufferMap; + private readonly QueryTarget _type; public BufferedQuery(QueryTarget type) { @@ -64,7 +64,7 @@ namespace Ryujinx.Graphics.OpenGL.Queries } } - private bool WaitingForValue(long data) + private static bool WaitingForValue(long data) { return data == DefaultValue || ((ulong)data & HighMask) == (unchecked((ulong)DefaultValue) & HighMask); diff --git a/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueue.cs b/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueue.cs index 648600bc2..ff7e9a3ee 100644 --- a/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueue.cs +++ b/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueue.cs @@ -15,7 +15,7 @@ namespace Ryujinx.Graphics.OpenGL.Queries private readonly Pipeline _pipeline; - private Queue _events = new Queue(); + private readonly Queue _events = new(); private CounterQueueEvent _current; private ulong _accumulatedCounter; @@ -23,12 +23,12 @@ namespace Ryujinx.Graphics.OpenGL.Queries private readonly object _lock = new(); - private Queue _queryPool; - private AutoResetEvent _queuedEvent = new AutoResetEvent(false); - private AutoResetEvent _wakeSignal = new AutoResetEvent(false); - private AutoResetEvent _eventConsumed = new AutoResetEvent(false); + private readonly Queue _queryPool; + private readonly AutoResetEvent _queuedEvent = new(false); + private readonly AutoResetEvent _wakeSignal = new(false); + private readonly AutoResetEvent _eventConsumed = new(false); - private Thread _consumerThread; + private readonly Thread _consumerThread; internal CounterQueue(Pipeline pipeline, CounterType type) { @@ -148,14 +148,13 @@ namespace Ryujinx.Graphics.OpenGL.Queries private static QueryTarget GetTarget(CounterType type) { - switch (type) + return type switch { - case CounterType.SamplesPassed: return QueryTarget.SamplesPassed; - case CounterType.PrimitivesGenerated: return QueryTarget.PrimitivesGenerated; - case CounterType.TransformFeedbackPrimitivesWritten: return QueryTarget.TransformFeedbackPrimitivesWritten; - } - - return QueryTarget.SamplesPassed; + CounterType.SamplesPassed => QueryTarget.SamplesPassed, + CounterType.PrimitivesGenerated => QueryTarget.PrimitivesGenerated, + CounterType.TransformFeedbackPrimitivesWritten => QueryTarget.TransformFeedbackPrimitivesWritten, + _ => QueryTarget.SamplesPassed, + }; } public void Flush(bool blocking) diff --git a/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueueEvent.cs b/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueueEvent.cs index ffe1f774f..7d2249068 100644 --- a/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueueEvent.cs +++ b/src/Ryujinx.Graphics.OpenGL/Queries/CounterQueueEvent.cs @@ -18,8 +18,8 @@ namespace Ryujinx.Graphics.OpenGL.Queries public ulong DrawIndex { get; } - private CounterQueue _queue; - private BufferedQuery _counter; + private readonly CounterQueue _queue; + private readonly BufferedQuery _counter; private bool _hostAccessReserved = false; private int _refCount = 1; // Starts with a reference from the counter queue. diff --git a/src/Ryujinx.Graphics.OpenGL/Queries/Counters.cs b/src/Ryujinx.Graphics.OpenGL/Queries/Counters.cs index e6c7ab2bd..91554ebad 100644 --- a/src/Ryujinx.Graphics.OpenGL/Queries/Counters.cs +++ b/src/Ryujinx.Graphics.OpenGL/Queries/Counters.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.OpenGL.Queries { class Counters : IDisposable { - private CounterQueue[] _counterQueues; + private readonly CounterQueue[] _counterQueues; public Counters() { @@ -54,4 +54,4 @@ namespace Ryujinx.Graphics.OpenGL.Queries } } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Graphics.OpenGL/ResourcePool.cs b/src/Ryujinx.Graphics.OpenGL/ResourcePool.cs index 69d2a78e1..bba5c5cb7 100644 --- a/src/Ryujinx.Graphics.OpenGL/ResourcePool.cs +++ b/src/Ryujinx.Graphics.OpenGL/ResourcePool.cs @@ -21,7 +21,7 @@ namespace Ryujinx.Graphics.OpenGL private const int DisposedLiveFrames = 2; private readonly object _lock = new(); - private readonly Dictionary> _textures = new Dictionary>(); + private readonly Dictionary> _textures = new(); /// /// Add a texture that is not being used anymore to the resource pool to be used later. @@ -32,8 +32,7 @@ namespace Ryujinx.Graphics.OpenGL { lock (_lock) { - List list; - if (!_textures.TryGetValue(view.Info, out list)) + if (!_textures.TryGetValue(view.Info, out List list)) { list = new List(); _textures.Add(view.Info, list); @@ -59,8 +58,7 @@ namespace Ryujinx.Graphics.OpenGL { lock (_lock) { - List list; - if (!_textures.TryGetValue(info, out list)) + if (!_textures.TryGetValue(info, out List list)) { return null; } diff --git a/src/Ryujinx.Graphics.OpenGL/Sync.cs b/src/Ryujinx.Graphics.OpenGL/Sync.cs index 58818e6a7..54e9c6d3f 100644 --- a/src/Ryujinx.Graphics.OpenGL/Sync.cs +++ b/src/Ryujinx.Graphics.OpenGL/Sync.cs @@ -15,13 +15,13 @@ namespace Ryujinx.Graphics.OpenGL } private ulong _firstHandle = 0; - private ClientWaitSyncFlags _syncFlags => HwCapabilities.RequiresSyncFlush ? ClientWaitSyncFlags.None : ClientWaitSyncFlags.SyncFlushCommandsBit; + private static ClientWaitSyncFlags SyncFlags => HwCapabilities.RequiresSyncFlush ? ClientWaitSyncFlags.None : ClientWaitSyncFlags.SyncFlushCommandsBit; - private List _handles = new List(); + private readonly List _handles = new(); public void Create(ulong id) { - SyncHandle handle = new SyncHandle + SyncHandle handle = new() { ID = id, Handle = GL.FenceSync(SyncCondition.SyncGpuCommandsComplete, WaitSyncFlags.None) @@ -57,7 +57,7 @@ namespace Ryujinx.Graphics.OpenGL if (handle.ID > lastHandle) { - WaitSyncStatus syncResult = GL.ClientWaitSync(handle.Handle, _syncFlags, 0); + WaitSyncStatus syncResult = GL.ClientWaitSync(handle.Handle, SyncFlags, 0); if (syncResult == WaitSyncStatus.AlreadySignaled) { @@ -101,8 +101,8 @@ namespace Ryujinx.Graphics.OpenGL return; } - WaitSyncStatus syncResult = GL.ClientWaitSync(result.Handle, _syncFlags, 1000000000); - + WaitSyncStatus syncResult = GL.ClientWaitSync(result.Handle, SyncFlags, 1000000000); + if (syncResult == WaitSyncStatus.TimeoutExpired) { Logger.Error?.PrintMsg(LogClass.Gpu, $"GL Sync Object {result.ID} failed to signal within 1000ms. Continuing..."); @@ -123,9 +123,12 @@ namespace Ryujinx.Graphics.OpenGL first = _handles.FirstOrDefault(); } - if (first == null) break; + if (first == null) + { + break; + } - WaitSyncStatus syncResult = GL.ClientWaitSync(first.Handle, _syncFlags, 0); + WaitSyncStatus syncResult = GL.ClientWaitSync(first.Handle, SyncFlags, 0); if (syncResult == WaitSyncStatus.AlreadySignaled) { @@ -140,7 +143,8 @@ namespace Ryujinx.Graphics.OpenGL first.Handle = IntPtr.Zero; } } - } else + } + else { // This sync handle and any following have not been reached yet. break; diff --git a/src/Ryujinx.Graphics.OpenGL/VertexArray.cs b/src/Ryujinx.Graphics.OpenGL/VertexArray.cs index 7d22033ec..32211e783 100644 --- a/src/Ryujinx.Graphics.OpenGL/VertexArray.cs +++ b/src/Ryujinx.Graphics.OpenGL/VertexArray.cs @@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.OpenGL private uint _vertexBuffersLimited; private BufferRange _indexBuffer; - private BufferHandle _tempIndexBuffer; + private readonly BufferHandle _tempIndexBuffer; private BufferHandle _tempVertexBuffer; private int _tempVertexBufferSize; @@ -102,7 +102,7 @@ namespace Ryujinx.Graphics.OpenGL } int offset = attrib.Offset; - int size = fmtInfo.Components; + int size = fmtInfo.Components; bool isFloat = fmtInfo.PixelType == PixelType.Float || fmtInfo.PixelType == PixelType.HalfFloat; diff --git a/src/Ryujinx.Graphics.OpenGL/Window.cs b/src/Ryujinx.Graphics.OpenGL/Window.cs index cc9836e06..a928772fd 100644 --- a/src/Ryujinx.Graphics.OpenGL/Window.cs +++ b/src/Ryujinx.Graphics.OpenGL/Window.cs @@ -375,7 +375,7 @@ namespace Ryujinx.Graphics.OpenGL if (_scalingFilter is not FsrScalingFilter) { _scalingFilter?.Dispose(); - _scalingFilter = new FsrScalingFilter(_renderer, _antiAliasing); + _scalingFilter = new FsrScalingFilter(_renderer); } _isLinear = false; _scalingFilter.Level = _scalingFilterLevel; @@ -417,4 +417,4 @@ namespace Ryujinx.Graphics.OpenGL _updateScalingFilter = true; } } -} \ No newline at end of file +} From 46b7c905f5dbb8c7e527281e22d5d2fc36bc666f Mon Sep 17 00:00:00 2001 From: TSRBerry <20988865+TSRBerry@users.noreply.github.com> Date: Wed, 28 Jun 2023 18:23:00 +0200 Subject: [PATCH 19/19] [Ryujinx.Input] Address dotnet-format issues (#5384) * dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Address dotnet format CA1816 warnings * Address or silence dotnet format CA1806 and a few CA1854 warnings * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Remove redundant code, convert to auto-properties and fix naming rule violations * Remove bogus change * Address review feedback --- .../Assigner/GamepadButtonAssigner.cs | 15 +- src/Ryujinx.Input/Assigner/IButtonAssigner.cs | 2 +- .../Assigner/KeyboardKeyAssigner.cs | 4 +- src/Ryujinx.Input/GamepadButtonInputId.cs | 2 +- src/Ryujinx.Input/GamepadFeaturesFlag.cs | 2 +- src/Ryujinx.Input/HLE/InputManager.cs | 3 +- src/Ryujinx.Input/HLE/NpadController.cs | 352 +++++++++--------- src/Ryujinx.Input/HLE/NpadManager.cs | 33 +- src/Ryujinx.Input/HLE/TouchScreenManager.cs | 15 +- src/Ryujinx.Input/IMouse.cs | 4 +- src/Ryujinx.Input/Key.cs | 4 +- src/Ryujinx.Input/KeyboardStateSnapshot.cs | 2 +- src/Ryujinx.Input/Motion/CemuHook/Client.cs | 157 ++++---- .../CemuHook/Protocol/ControllerData.cs | 22 +- .../CemuHook/Protocol/ControllerInfo.cs | 4 +- .../Motion/CemuHook/Protocol/Header.cs | 2 +- .../Motion/CemuHook/Protocol/MessageType.cs | 4 +- .../CemuHook/Protocol/SharedResponse.cs | 18 +- src/Ryujinx.Input/Motion/MotionInput.cs | 14 +- .../Motion/MotionSensorFilter.cs | 14 +- src/Ryujinx.Input/MotionInputId.cs | 2 +- src/Ryujinx.Input/MouseButton.cs | 4 +- src/Ryujinx.Input/MouseStateSnapshot.cs | 6 +- src/Ryujinx.Input/StickInputId.cs | 2 +- 24 files changed, 344 insertions(+), 343 deletions(-) diff --git a/src/Ryujinx.Input/Assigner/GamepadButtonAssigner.cs b/src/Ryujinx.Input/Assigner/GamepadButtonAssigner.cs index 8621b3a52..388ebcc07 100644 --- a/src/Ryujinx.Input/Assigner/GamepadButtonAssigner.cs +++ b/src/Ryujinx.Input/Assigner/GamepadButtonAssigner.cs @@ -10,15 +10,15 @@ namespace Ryujinx.Input.Assigner /// public class GamepadButtonAssigner : IButtonAssigner { - private IGamepad _gamepad; + private readonly IGamepad _gamepad; private GamepadStateSnapshot _currState; private GamepadStateSnapshot _prevState; - private JoystickButtonDetector _detector; + private readonly JoystickButtonDetector _detector; - private bool _forStick; + private readonly bool _forStick; public GamepadButtonAssigner(IGamepad gamepad, float triggerThreshold, bool forStick) { @@ -35,7 +35,7 @@ namespace Ryujinx.Input.Assigner { _currState = _gamepad.GetStateSnapshot(); _prevState = _currState; - } + } } public void ReadInput() @@ -116,7 +116,7 @@ namespace Ryujinx.Input.Assigner private class JoystickButtonDetector { - private Dictionary _stats; + private readonly Dictionary _stats; public JoystickButtonDetector() { @@ -135,9 +135,8 @@ namespace Ryujinx.Input.Assigner public void AddInput(GamepadButtonInputId button, float value) { - InputSummary inputSummary; - if (!_stats.TryGetValue(button, out inputSummary)) + if (!_stats.TryGetValue(button, out InputSummary inputSummary)) { inputSummary = new InputSummary(); _stats.Add(button, inputSummary); @@ -148,7 +147,7 @@ namespace Ryujinx.Input.Assigner public override string ToString() { - StringWriter writer = new StringWriter(); + StringWriter writer = new(); foreach (var kvp in _stats) { diff --git a/src/Ryujinx.Input/Assigner/IButtonAssigner.cs b/src/Ryujinx.Input/Assigner/IButtonAssigner.cs index 021736df4..76a9fece4 100644 --- a/src/Ryujinx.Input/Assigner/IButtonAssigner.cs +++ b/src/Ryujinx.Input/Assigner/IButtonAssigner.cs @@ -33,4 +33,4 @@ namespace Ryujinx.Input.Assigner /// The pressed button that was read string GetPressedButton(); } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Assigner/KeyboardKeyAssigner.cs b/src/Ryujinx.Input/Assigner/KeyboardKeyAssigner.cs index 23ae3655d..e52ef4a2c 100644 --- a/src/Ryujinx.Input/Assigner/KeyboardKeyAssigner.cs +++ b/src/Ryujinx.Input/Assigner/KeyboardKeyAssigner.cs @@ -5,7 +5,7 @@ namespace Ryujinx.Input.Assigner /// public class KeyboardKeyAssigner : IButtonAssigner { - private IKeyboard _keyboard; + private readonly IKeyboard _keyboard; private KeyboardStateSnapshot _keyboardState; @@ -47,4 +47,4 @@ namespace Ryujinx.Input.Assigner return !ShouldCancel() ? keyPressed : ""; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/GamepadButtonInputId.cs b/src/Ryujinx.Input/GamepadButtonInputId.cs index d1e4b9ac0..618f8d0a0 100644 --- a/src/Ryujinx.Input/GamepadButtonInputId.cs +++ b/src/Ryujinx.Input/GamepadButtonInputId.cs @@ -52,6 +52,6 @@ SingleLeftTrigger1, SingleRightTrigger1, - Count + Count, } } diff --git a/src/Ryujinx.Input/GamepadFeaturesFlag.cs b/src/Ryujinx.Input/GamepadFeaturesFlag.cs index 87310a322..206b4ea11 100644 --- a/src/Ryujinx.Input/GamepadFeaturesFlag.cs +++ b/src/Ryujinx.Input/GamepadFeaturesFlag.cs @@ -23,6 +23,6 @@ namespace Ryujinx.Input /// Motion /// Also named sixaxis /// - Motion + Motion, } } diff --git a/src/Ryujinx.Input/HLE/InputManager.cs b/src/Ryujinx.Input/HLE/InputManager.cs index bc38cf5a2..6dba839b9 100644 --- a/src/Ryujinx.Input/HLE/InputManager.cs +++ b/src/Ryujinx.Input/HLE/InputManager.cs @@ -25,7 +25,7 @@ namespace Ryujinx.Input.HLE { return new NpadManager(KeyboardDriver, GamepadDriver, MouseDriver); } - + public TouchScreenManager CreateTouchScreenManager() { if (MouseDriver == null) @@ -48,6 +48,7 @@ namespace Ryujinx.Input.HLE public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } } diff --git a/src/Ryujinx.Input/HLE/NpadController.cs b/src/Ryujinx.Input/HLE/NpadController.cs index 46c0fc33a..c193b45c2 100644 --- a/src/Ryujinx.Input/HLE/NpadController.cs +++ b/src/Ryujinx.Input/HLE/NpadController.cs @@ -8,7 +8,6 @@ using System; using System.Collections.Concurrent; using System.Numerics; using System.Runtime.CompilerServices; - using CemuHookClient = Ryujinx.Input.Motion.CemuHook.Client; using ConfigControllerType = Ryujinx.Common.Configuration.Hid.ControllerType; @@ -28,29 +27,28 @@ namespace Ryujinx.Input.HLE } } - private static readonly HLEButtonMappingEntry[] _hleButtonMapping = new HLEButtonMappingEntry[] - { - new HLEButtonMappingEntry(GamepadButtonInputId.A, ControllerKeys.A), - new HLEButtonMappingEntry(GamepadButtonInputId.B, ControllerKeys.B), - new HLEButtonMappingEntry(GamepadButtonInputId.X, ControllerKeys.X), - new HLEButtonMappingEntry(GamepadButtonInputId.Y, ControllerKeys.Y), - new HLEButtonMappingEntry(GamepadButtonInputId.LeftStick, ControllerKeys.LStick), - new HLEButtonMappingEntry(GamepadButtonInputId.RightStick, ControllerKeys.RStick), - new HLEButtonMappingEntry(GamepadButtonInputId.LeftShoulder, ControllerKeys.L), - new HLEButtonMappingEntry(GamepadButtonInputId.RightShoulder, ControllerKeys.R), - new HLEButtonMappingEntry(GamepadButtonInputId.LeftTrigger, ControllerKeys.Zl), - new HLEButtonMappingEntry(GamepadButtonInputId.RightTrigger, ControllerKeys.Zr), - new HLEButtonMappingEntry(GamepadButtonInputId.DpadUp, ControllerKeys.DpadUp), - new HLEButtonMappingEntry(GamepadButtonInputId.DpadDown, ControllerKeys.DpadDown), - new HLEButtonMappingEntry(GamepadButtonInputId.DpadLeft, ControllerKeys.DpadLeft), - new HLEButtonMappingEntry(GamepadButtonInputId.DpadRight, ControllerKeys.DpadRight), - new HLEButtonMappingEntry(GamepadButtonInputId.Minus, ControllerKeys.Minus), - new HLEButtonMappingEntry(GamepadButtonInputId.Plus, ControllerKeys.Plus), + private static readonly HLEButtonMappingEntry[] _hleButtonMapping = { + new(GamepadButtonInputId.A, ControllerKeys.A), + new(GamepadButtonInputId.B, ControllerKeys.B), + new(GamepadButtonInputId.X, ControllerKeys.X), + new(GamepadButtonInputId.Y, ControllerKeys.Y), + new(GamepadButtonInputId.LeftStick, ControllerKeys.LStick), + new(GamepadButtonInputId.RightStick, ControllerKeys.RStick), + new(GamepadButtonInputId.LeftShoulder, ControllerKeys.L), + new(GamepadButtonInputId.RightShoulder, ControllerKeys.R), + new(GamepadButtonInputId.LeftTrigger, ControllerKeys.Zl), + new(GamepadButtonInputId.RightTrigger, ControllerKeys.Zr), + new(GamepadButtonInputId.DpadUp, ControllerKeys.DpadUp), + new(GamepadButtonInputId.DpadDown, ControllerKeys.DpadDown), + new(GamepadButtonInputId.DpadLeft, ControllerKeys.DpadLeft), + new(GamepadButtonInputId.DpadRight, ControllerKeys.DpadRight), + new(GamepadButtonInputId.Minus, ControllerKeys.Minus), + new(GamepadButtonInputId.Plus, ControllerKeys.Plus), - new HLEButtonMappingEntry(GamepadButtonInputId.SingleLeftTrigger0, ControllerKeys.SlLeft), - new HLEButtonMappingEntry(GamepadButtonInputId.SingleRightTrigger0, ControllerKeys.SrLeft), - new HLEButtonMappingEntry(GamepadButtonInputId.SingleLeftTrigger1, ControllerKeys.SlRight), - new HLEButtonMappingEntry(GamepadButtonInputId.SingleRightTrigger1, ControllerKeys.SrRight), + new(GamepadButtonInputId.SingleLeftTrigger0, ControllerKeys.SlLeft), + new(GamepadButtonInputId.SingleRightTrigger0, ControllerKeys.SrLeft), + new(GamepadButtonInputId.SingleLeftTrigger1, ControllerKeys.SlRight), + new(GamepadButtonInputId.SingleRightTrigger1, ControllerKeys.SrRight), }; private class HLEKeyboardMappingEntry @@ -65,150 +63,147 @@ namespace Ryujinx.Input.HLE } } - private static readonly HLEKeyboardMappingEntry[] KeyMapping = new HLEKeyboardMappingEntry[] - { - new HLEKeyboardMappingEntry(Key.A, 0x4), - new HLEKeyboardMappingEntry(Key.B, 0x5), - new HLEKeyboardMappingEntry(Key.C, 0x6), - new HLEKeyboardMappingEntry(Key.D, 0x7), - new HLEKeyboardMappingEntry(Key.E, 0x8), - new HLEKeyboardMappingEntry(Key.F, 0x9), - new HLEKeyboardMappingEntry(Key.G, 0xA), - new HLEKeyboardMappingEntry(Key.H, 0xB), - new HLEKeyboardMappingEntry(Key.I, 0xC), - new HLEKeyboardMappingEntry(Key.J, 0xD), - new HLEKeyboardMappingEntry(Key.K, 0xE), - new HLEKeyboardMappingEntry(Key.L, 0xF), - new HLEKeyboardMappingEntry(Key.M, 0x10), - new HLEKeyboardMappingEntry(Key.N, 0x11), - new HLEKeyboardMappingEntry(Key.O, 0x12), - new HLEKeyboardMappingEntry(Key.P, 0x13), - new HLEKeyboardMappingEntry(Key.Q, 0x14), - new HLEKeyboardMappingEntry(Key.R, 0x15), - new HLEKeyboardMappingEntry(Key.S, 0x16), - new HLEKeyboardMappingEntry(Key.T, 0x17), - new HLEKeyboardMappingEntry(Key.U, 0x18), - new HLEKeyboardMappingEntry(Key.V, 0x19), - new HLEKeyboardMappingEntry(Key.W, 0x1A), - new HLEKeyboardMappingEntry(Key.X, 0x1B), - new HLEKeyboardMappingEntry(Key.Y, 0x1C), - new HLEKeyboardMappingEntry(Key.Z, 0x1D), + private static readonly HLEKeyboardMappingEntry[] _keyMapping = { + new(Key.A, 0x4), + new(Key.B, 0x5), + new(Key.C, 0x6), + new(Key.D, 0x7), + new(Key.E, 0x8), + new(Key.F, 0x9), + new(Key.G, 0xA), + new(Key.H, 0xB), + new(Key.I, 0xC), + new(Key.J, 0xD), + new(Key.K, 0xE), + new(Key.L, 0xF), + new(Key.M, 0x10), + new(Key.N, 0x11), + new(Key.O, 0x12), + new(Key.P, 0x13), + new(Key.Q, 0x14), + new(Key.R, 0x15), + new(Key.S, 0x16), + new(Key.T, 0x17), + new(Key.U, 0x18), + new(Key.V, 0x19), + new(Key.W, 0x1A), + new(Key.X, 0x1B), + new(Key.Y, 0x1C), + new(Key.Z, 0x1D), - new HLEKeyboardMappingEntry(Key.Number1, 0x1E), - new HLEKeyboardMappingEntry(Key.Number2, 0x1F), - new HLEKeyboardMappingEntry(Key.Number3, 0x20), - new HLEKeyboardMappingEntry(Key.Number4, 0x21), - new HLEKeyboardMappingEntry(Key.Number5, 0x22), - new HLEKeyboardMappingEntry(Key.Number6, 0x23), - new HLEKeyboardMappingEntry(Key.Number7, 0x24), - new HLEKeyboardMappingEntry(Key.Number8, 0x25), - new HLEKeyboardMappingEntry(Key.Number9, 0x26), - new HLEKeyboardMappingEntry(Key.Number0, 0x27), + new(Key.Number1, 0x1E), + new(Key.Number2, 0x1F), + new(Key.Number3, 0x20), + new(Key.Number4, 0x21), + new(Key.Number5, 0x22), + new(Key.Number6, 0x23), + new(Key.Number7, 0x24), + new(Key.Number8, 0x25), + new(Key.Number9, 0x26), + new(Key.Number0, 0x27), - new HLEKeyboardMappingEntry(Key.Enter, 0x28), - new HLEKeyboardMappingEntry(Key.Escape, 0x29), - new HLEKeyboardMappingEntry(Key.BackSpace, 0x2A), - new HLEKeyboardMappingEntry(Key.Tab, 0x2B), - new HLEKeyboardMappingEntry(Key.Space, 0x2C), - new HLEKeyboardMappingEntry(Key.Minus, 0x2D), - new HLEKeyboardMappingEntry(Key.Plus, 0x2E), - new HLEKeyboardMappingEntry(Key.BracketLeft, 0x2F), - new HLEKeyboardMappingEntry(Key.BracketRight, 0x30), - new HLEKeyboardMappingEntry(Key.BackSlash, 0x31), - new HLEKeyboardMappingEntry(Key.Tilde, 0x32), - new HLEKeyboardMappingEntry(Key.Semicolon, 0x33), - new HLEKeyboardMappingEntry(Key.Quote, 0x34), - new HLEKeyboardMappingEntry(Key.Grave, 0x35), - new HLEKeyboardMappingEntry(Key.Comma, 0x36), - new HLEKeyboardMappingEntry(Key.Period, 0x37), - new HLEKeyboardMappingEntry(Key.Slash, 0x38), - new HLEKeyboardMappingEntry(Key.CapsLock, 0x39), + new(Key.Enter, 0x28), + new(Key.Escape, 0x29), + new(Key.BackSpace, 0x2A), + new(Key.Tab, 0x2B), + new(Key.Space, 0x2C), + new(Key.Minus, 0x2D), + new(Key.Plus, 0x2E), + new(Key.BracketLeft, 0x2F), + new(Key.BracketRight, 0x30), + new(Key.BackSlash, 0x31), + new(Key.Tilde, 0x32), + new(Key.Semicolon, 0x33), + new(Key.Quote, 0x34), + new(Key.Grave, 0x35), + new(Key.Comma, 0x36), + new(Key.Period, 0x37), + new(Key.Slash, 0x38), + new(Key.CapsLock, 0x39), - new HLEKeyboardMappingEntry(Key.F1, 0x3a), - new HLEKeyboardMappingEntry(Key.F2, 0x3b), - new HLEKeyboardMappingEntry(Key.F3, 0x3c), - new HLEKeyboardMappingEntry(Key.F4, 0x3d), - new HLEKeyboardMappingEntry(Key.F5, 0x3e), - new HLEKeyboardMappingEntry(Key.F6, 0x3f), - new HLEKeyboardMappingEntry(Key.F7, 0x40), - new HLEKeyboardMappingEntry(Key.F8, 0x41), - new HLEKeyboardMappingEntry(Key.F9, 0x42), - new HLEKeyboardMappingEntry(Key.F10, 0x43), - new HLEKeyboardMappingEntry(Key.F11, 0x44), - new HLEKeyboardMappingEntry(Key.F12, 0x45), + new(Key.F1, 0x3a), + new(Key.F2, 0x3b), + new(Key.F3, 0x3c), + new(Key.F4, 0x3d), + new(Key.F5, 0x3e), + new(Key.F6, 0x3f), + new(Key.F7, 0x40), + new(Key.F8, 0x41), + new(Key.F9, 0x42), + new(Key.F10, 0x43), + new(Key.F11, 0x44), + new(Key.F12, 0x45), - new HLEKeyboardMappingEntry(Key.PrintScreen, 0x46), - new HLEKeyboardMappingEntry(Key.ScrollLock, 0x47), - new HLEKeyboardMappingEntry(Key.Pause, 0x48), - new HLEKeyboardMappingEntry(Key.Insert, 0x49), - new HLEKeyboardMappingEntry(Key.Home, 0x4A), - new HLEKeyboardMappingEntry(Key.PageUp, 0x4B), - new HLEKeyboardMappingEntry(Key.Delete, 0x4C), - new HLEKeyboardMappingEntry(Key.End, 0x4D), - new HLEKeyboardMappingEntry(Key.PageDown, 0x4E), - new HLEKeyboardMappingEntry(Key.Right, 0x4F), - new HLEKeyboardMappingEntry(Key.Left, 0x50), - new HLEKeyboardMappingEntry(Key.Down, 0x51), - new HLEKeyboardMappingEntry(Key.Up, 0x52), + new(Key.PrintScreen, 0x46), + new(Key.ScrollLock, 0x47), + new(Key.Pause, 0x48), + new(Key.Insert, 0x49), + new(Key.Home, 0x4A), + new(Key.PageUp, 0x4B), + new(Key.Delete, 0x4C), + new(Key.End, 0x4D), + new(Key.PageDown, 0x4E), + new(Key.Right, 0x4F), + new(Key.Left, 0x50), + new(Key.Down, 0x51), + new(Key.Up, 0x52), - new HLEKeyboardMappingEntry(Key.NumLock, 0x53), - new HLEKeyboardMappingEntry(Key.KeypadDivide, 0x54), - new HLEKeyboardMappingEntry(Key.KeypadMultiply, 0x55), - new HLEKeyboardMappingEntry(Key.KeypadSubtract, 0x56), - new HLEKeyboardMappingEntry(Key.KeypadAdd, 0x57), - new HLEKeyboardMappingEntry(Key.KeypadEnter, 0x58), - new HLEKeyboardMappingEntry(Key.Keypad1, 0x59), - new HLEKeyboardMappingEntry(Key.Keypad2, 0x5A), - new HLEKeyboardMappingEntry(Key.Keypad3, 0x5B), - new HLEKeyboardMappingEntry(Key.Keypad4, 0x5C), - new HLEKeyboardMappingEntry(Key.Keypad5, 0x5D), - new HLEKeyboardMappingEntry(Key.Keypad6, 0x5E), - new HLEKeyboardMappingEntry(Key.Keypad7, 0x5F), - new HLEKeyboardMappingEntry(Key.Keypad8, 0x60), - new HLEKeyboardMappingEntry(Key.Keypad9, 0x61), - new HLEKeyboardMappingEntry(Key.Keypad0, 0x62), - new HLEKeyboardMappingEntry(Key.KeypadDecimal, 0x63), + new(Key.NumLock, 0x53), + new(Key.KeypadDivide, 0x54), + new(Key.KeypadMultiply, 0x55), + new(Key.KeypadSubtract, 0x56), + new(Key.KeypadAdd, 0x57), + new(Key.KeypadEnter, 0x58), + new(Key.Keypad1, 0x59), + new(Key.Keypad2, 0x5A), + new(Key.Keypad3, 0x5B), + new(Key.Keypad4, 0x5C), + new(Key.Keypad5, 0x5D), + new(Key.Keypad6, 0x5E), + new(Key.Keypad7, 0x5F), + new(Key.Keypad8, 0x60), + new(Key.Keypad9, 0x61), + new(Key.Keypad0, 0x62), + new(Key.KeypadDecimal, 0x63), - new HLEKeyboardMappingEntry(Key.F13, 0x68), - new HLEKeyboardMappingEntry(Key.F14, 0x69), - new HLEKeyboardMappingEntry(Key.F15, 0x6A), - new HLEKeyboardMappingEntry(Key.F16, 0x6B), - new HLEKeyboardMappingEntry(Key.F17, 0x6C), - new HLEKeyboardMappingEntry(Key.F18, 0x6D), - new HLEKeyboardMappingEntry(Key.F19, 0x6E), - new HLEKeyboardMappingEntry(Key.F20, 0x6F), - new HLEKeyboardMappingEntry(Key.F21, 0x70), - new HLEKeyboardMappingEntry(Key.F22, 0x71), - new HLEKeyboardMappingEntry(Key.F23, 0x72), - new HLEKeyboardMappingEntry(Key.F24, 0x73), + new(Key.F13, 0x68), + new(Key.F14, 0x69), + new(Key.F15, 0x6A), + new(Key.F16, 0x6B), + new(Key.F17, 0x6C), + new(Key.F18, 0x6D), + new(Key.F19, 0x6E), + new(Key.F20, 0x6F), + new(Key.F21, 0x70), + new(Key.F22, 0x71), + new(Key.F23, 0x72), + new(Key.F24, 0x73), - new HLEKeyboardMappingEntry(Key.ControlLeft, 0xE0), - new HLEKeyboardMappingEntry(Key.ShiftLeft, 0xE1), - new HLEKeyboardMappingEntry(Key.AltLeft, 0xE2), - new HLEKeyboardMappingEntry(Key.WinLeft, 0xE3), - new HLEKeyboardMappingEntry(Key.ControlRight, 0xE4), - new HLEKeyboardMappingEntry(Key.ShiftRight, 0xE5), - new HLEKeyboardMappingEntry(Key.AltRight, 0xE6), - new HLEKeyboardMappingEntry(Key.WinRight, 0xE7), + new(Key.ControlLeft, 0xE0), + new(Key.ShiftLeft, 0xE1), + new(Key.AltLeft, 0xE2), + new(Key.WinLeft, 0xE3), + new(Key.ControlRight, 0xE4), + new(Key.ShiftRight, 0xE5), + new(Key.AltRight, 0xE6), + new(Key.WinRight, 0xE7), }; - private static readonly HLEKeyboardMappingEntry[] KeyModifierMapping = new HLEKeyboardMappingEntry[] - { - new HLEKeyboardMappingEntry(Key.ControlLeft, 0), - new HLEKeyboardMappingEntry(Key.ShiftLeft, 1), - new HLEKeyboardMappingEntry(Key.AltLeft, 2), - new HLEKeyboardMappingEntry(Key.WinLeft, 3), - new HLEKeyboardMappingEntry(Key.ControlRight, 4), - new HLEKeyboardMappingEntry(Key.ShiftRight, 5), - new HLEKeyboardMappingEntry(Key.AltRight, 6), - new HLEKeyboardMappingEntry(Key.WinRight, 7), - new HLEKeyboardMappingEntry(Key.CapsLock, 8), - new HLEKeyboardMappingEntry(Key.ScrollLock, 9), - new HLEKeyboardMappingEntry(Key.NumLock, 10), + private static readonly HLEKeyboardMappingEntry[] _keyModifierMapping = { + new(Key.ControlLeft, 0), + new(Key.ShiftLeft, 1), + new(Key.AltLeft, 2), + new(Key.WinLeft, 3), + new(Key.ControlRight, 4), + new(Key.ShiftRight, 5), + new(Key.AltRight, 6), + new(Key.WinRight, 7), + new(Key.CapsLock, 8), + new(Key.ScrollLock, 9), + new(Key.NumLock, 10), }; private bool _isValid; - private string _id; private MotionInput _leftMotionInput; private MotionInput _rightMotionInput; @@ -219,14 +214,14 @@ namespace Ryujinx.Input.HLE public IGamepadDriver GamepadDriver { get; private set; } public GamepadStateSnapshot State { get; private set; } - public string Id => _id; + public string Id { get; private set; } - private CemuHookClient _cemuHookClient; + private readonly CemuHookClient _cemuHookClient; public NpadController(CemuHookClient cemuHookClient) { State = default; - _id = null; + Id = null; _isValid = false; _cemuHookClient = cemuHookClient; } @@ -237,8 +232,8 @@ namespace Ryujinx.Input.HLE _gamepad?.Dispose(); - _id = config.Id; - _gamepad = GamepadDriver.GetGamepad(_id); + Id = config.Id; + _gamepad = GamepadDriver.GetGamepad(Id); _isValid = _gamepad != null; UpdateUserConfiguration(config); @@ -278,7 +273,7 @@ namespace Ryujinx.Input.HLE if (motionConfig.MotionBackend != MotionInputBackendType.CemuHook) { _leftMotionInput = new MotionInput(); - } + } else { _leftMotionInput = null; @@ -347,7 +342,7 @@ namespace Ryujinx.Input.HLE public GamepadInput GetHLEInputState() { - GamepadInput state = new GamepadInput(); + GamepadInput state = new(); // First update all buttons foreach (HLEButtonMappingEntry entry in _hleButtonMapping) @@ -366,13 +361,13 @@ namespace Ryujinx.Input.HLE state.LStick = new JoystickPosition { Dx = ClampAxis(leftAxisX), - Dy = ClampAxis(leftAxisY) + Dy = ClampAxis(leftAxisY), }; state.RStick = new JoystickPosition { Dx = ClampAxis(rightAxisX), - Dy = ClampAxis(rightAxisY) + Dy = ClampAxis(rightAxisY), }; } else if (_config is StandardControllerInputConfig controllerConfig) @@ -391,16 +386,16 @@ namespace Ryujinx.Input.HLE private static JoystickPosition ApplyDeadzone(float x, float y, float deadzone) { float magnitudeClamped = Math.Min(MathF.Sqrt(x * x + y * y), 1f); - + if (magnitudeClamped <= deadzone) { - return new JoystickPosition() {Dx = 0, Dy = 0}; + return new JoystickPosition { Dx = 0, Dy = 0 }; } - - return new JoystickPosition() + + return new JoystickPosition { Dx = ClampAxis((x / magnitudeClamped) * ((magnitudeClamped - deadzone) / (1 - deadzone))), - Dy = ClampAxis((y / magnitudeClamped) * ((magnitudeClamped - deadzone) / (1 - deadzone))) + Dy = ClampAxis((y / magnitudeClamped) * ((magnitudeClamped - deadzone) / (1 - deadzone))), }; } @@ -428,7 +423,7 @@ namespace Ryujinx.Input.HLE return new JoystickPosition { Dx = (int)point.X, - Dy = (int)point.Y + Dy = (int)point.Y, }; } @@ -476,12 +471,12 @@ namespace Ryujinx.Input.HLE rotation = new Vector3(); } - return new SixAxisInput() + return new SixAxisInput { Accelerometer = accelerometer, - Gyroscope = gyroscope, - Rotation = rotation, - Orientation = orientationForHLE + Gyroscope = gyroscope, + Rotation = rotation, + Orientation = orientationForHLE, }; } @@ -502,20 +497,20 @@ namespace Ryujinx.Input.HLE { KeyboardStateSnapshot keyboardState = keyboard.GetKeyboardStateSnapshot(); - KeyboardInput hidKeyboard = new KeyboardInput + KeyboardInput hidKeyboard = new() { Modifier = 0, - Keys = new ulong[0x4] + Keys = new ulong[0x4], }; - foreach (HLEKeyboardMappingEntry entry in KeyMapping) + foreach (HLEKeyboardMappingEntry entry in _keyMapping) { ulong value = keyboardState.IsPressed(entry.TargetKey) ? 1UL : 0UL; hidKeyboard.Keys[entry.Target / 0x40] |= (value << (entry.Target % 0x40)); } - foreach (HLEKeyboardMappingEntry entry in KeyModifierMapping) + foreach (HLEKeyboardMappingEntry entry in _keyModifierMapping) { int value = keyboardState.IsPressed(entry.TargetKey) ? 1 : 0; @@ -539,6 +534,7 @@ namespace Ryujinx.Input.HLE public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } diff --git a/src/Ryujinx.Input/HLE/NpadManager.cs b/src/Ryujinx.Input/HLE/NpadManager.cs index 89a2f585b..25887748f 100644 --- a/src/Ryujinx.Input/HLE/NpadManager.cs +++ b/src/Ryujinx.Input/HLE/NpadManager.cs @@ -7,13 +7,15 @@ using System.Collections.Generic; using System.Diagnostics; using System.Runtime.CompilerServices; using CemuHookClient = Ryujinx.Input.Motion.CemuHook.Client; +using ControllerType = Ryujinx.Common.Configuration.Hid.ControllerType; +using PlayerIndex = Ryujinx.HLE.HOS.Services.Hid.PlayerIndex; using Switch = Ryujinx.HLE.Switch; namespace Ryujinx.Input.HLE { public class NpadManager : IDisposable { - private CemuHookClient _cemuHookClient; + private readonly CemuHookClient _cemuHookClient; private readonly object _lock = new(); @@ -21,7 +23,7 @@ namespace Ryujinx.Input.HLE private const int MaxControllers = 9; - private NpadController[] _controllers; + private readonly NpadController[] _controllers; private readonly IGamepadDriver _keyboardDriver; private readonly IGamepadDriver _gamepadDriver; @@ -51,7 +53,7 @@ namespace Ryujinx.Input.HLE { lock (_lock) { - List validInputs = new List(); + List validInputs = new(); foreach (var inputConfigEntry in _inputConfig) { if (_controllers[(int)inputConfigEntry.PlayerIndex] != null) @@ -96,10 +98,8 @@ namespace Ryujinx.Input.HLE { return controller.UpdateDriverConfiguration(targetDriver, config); } - else - { - return controller.GamepadDriver != null; - } + + return controller.GamepadDriver != null; } public void ReloadConfiguration(List inputConfig, bool enableKeyboard, bool enableMouse) @@ -112,11 +112,11 @@ namespace Ryujinx.Input.HLE _controllers[i] = null; } - List validInputs = new List(); + List validInputs = new(); foreach (InputConfig inputConfigEntry in inputConfig) { - NpadController controller = new NpadController(_cemuHookClient); + NpadController controller = new(_cemuHookClient); bool isValid = DriverConfigurationUpdate(ref controller, inputConfigEntry); @@ -131,9 +131,9 @@ namespace Ryujinx.Input.HLE } } - _inputConfig = inputConfig; + _inputConfig = inputConfig; _enableKeyboard = enableKeyboard; - _enableMouse = enableMouse; + _enableMouse = enableMouse; _device.Hid.RefreshInputConfig(validInputs); } @@ -167,8 +167,8 @@ namespace Ryujinx.Input.HLE { lock (_lock) { - List hleInputStates = new List(); - List hleMotionStates = new List(NpadDevices.MaxControllers); + List hleInputStates = new(); + List hleMotionStates = new(NpadDevices.MaxControllers); KeyboardInput? hleKeyboardInput = null; @@ -178,7 +178,7 @@ namespace Ryujinx.Input.HLE (SixAxisInput, SixAxisInput) motionState = default; NpadController controller = _controllers[(int)inputConfig.PlayerIndex]; - Ryujinx.HLE.HOS.Services.Hid.PlayerIndex playerIndex = (Ryujinx.HLE.HOS.Services.Hid.PlayerIndex)inputConfig.PlayerIndex; + PlayerIndex playerIndex = (PlayerIndex)inputConfig.PlayerIndex; bool isJoyconPair = false; @@ -195,7 +195,7 @@ namespace Ryujinx.Input.HLE inputState.Buttons |= _device.Hid.UpdateStickButtons(inputState.LStick, inputState.RStick); - isJoyconPair = inputConfig.ControllerType == Common.Configuration.Hid.ControllerType.JoyconPair; + isJoyconPair = inputConfig.ControllerType == ControllerType.JoyconPair; var altMotionState = isJoyconPair ? controller.GetHLEMotionState(true) : default; @@ -284,7 +284,7 @@ namespace Ryujinx.Input.HLE { lock (_lock) { - return _inputConfig.Find(x => x.PlayerIndex == (Ryujinx.Common.Configuration.Hid.PlayerIndex)index); + return _inputConfig.Find(x => x.PlayerIndex == (Common.Configuration.Hid.PlayerIndex)index); } } @@ -314,6 +314,7 @@ namespace Ryujinx.Input.HLE public void Dispose() { + GC.SuppressFinalize(this); Dispose(true); } } diff --git a/src/Ryujinx.Input/HLE/TouchScreenManager.cs b/src/Ryujinx.Input/HLE/TouchScreenManager.cs index e4b0f8fc7..c613f9281 100644 --- a/src/Ryujinx.Input/HLE/TouchScreenManager.cs +++ b/src/Ryujinx.Input/HLE/TouchScreenManager.cs @@ -31,7 +31,7 @@ namespace Ryujinx.Input.HLE MouseStateSnapshot snapshot = IMouse.GetMouseStateSnapshot(_mouse); var touchPosition = IMouse.GetScreenPosition(snapshot.Position, _mouse.ClientSize, aspectRatio); - TouchPoint currentPoint = new TouchPoint + TouchPoint currentPoint = new() { Attribute = TouchAttribute.End, @@ -41,7 +41,7 @@ namespace Ryujinx.Input.HLE // Placeholder values till more data is acquired DiameterX = 10, DiameterY = 10, - Angle = 90 + Angle = 90, }; _device.Hid.Touchscreen.Update(currentPoint); @@ -71,7 +71,7 @@ namespace Ryujinx.Input.HLE attribute = TouchAttribute.End; } - TouchPoint currentPoint = new TouchPoint + TouchPoint currentPoint = new() { Attribute = attribute, @@ -81,7 +81,7 @@ namespace Ryujinx.Input.HLE // Placeholder values till more data is acquired DiameterX = 10, DiameterY = 10, - Angle = 90 + Angle = 90, }; _device.Hid.Touchscreen.Update(currentPoint); @@ -94,6 +94,9 @@ namespace Ryujinx.Input.HLE return false; } - public void Dispose() { } + public void Dispose() + { + GC.SuppressFinalize(this); + } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/IMouse.cs b/src/Ryujinx.Input/IMouse.cs index fde150fc2..e20e7798d 100644 --- a/src/Ryujinx.Input/IMouse.cs +++ b/src/Ryujinx.Input/IMouse.cs @@ -8,7 +8,9 @@ namespace Ryujinx.Input /// public interface IMouse : IGamepad { +#pragma warning disable IDE0051 // Remove unused private member private const int SwitchPanelWidth = 1280; +#pragma warning restore IDE0051 private const int SwitchPanelHeight = 720; /// @@ -101,4 +103,4 @@ namespace Ryujinx.Input return new Vector2(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Key.cs b/src/Ryujinx.Input/Key.cs index 5fa044847..b4229e059 100644 --- a/src/Ryujinx.Input/Key.cs +++ b/src/Ryujinx.Input/Key.cs @@ -137,6 +137,6 @@ BackSlash, Unbound, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/KeyboardStateSnapshot.cs b/src/Ryujinx.Input/KeyboardStateSnapshot.cs index da77a461f..abf85666b 100644 --- a/src/Ryujinx.Input/KeyboardStateSnapshot.cs +++ b/src/Ryujinx.Input/KeyboardStateSnapshot.cs @@ -7,7 +7,7 @@ namespace Ryujinx.Input /// public class KeyboardStateSnapshot { - private bool[] _keysState; + private readonly bool[] _keysState; /// /// Create a new . diff --git a/src/Ryujinx.Input/Motion/CemuHook/Client.cs b/src/Ryujinx.Input/Motion/CemuHook/Client.cs index a79412a17..b8b936c1e 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Client.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Client.cs @@ -19,7 +19,7 @@ namespace Ryujinx.Input.Motion.CemuHook { public class Client : IDisposable { - public const uint Magic = 0x43555344; // DSUC + public const uint Magic = 0x43555344; // DSUC public const ushort Version = 1001; private bool _active; @@ -29,15 +29,15 @@ namespace Ryujinx.Input.Motion.CemuHook private readonly Dictionary _clients; private readonly bool[] _clientErrorStatus = new bool[Enum.GetValues().Length]; - private readonly long[] _clientRetryTimer = new long[Enum.GetValues().Length]; - private NpadManager _npadManager; + private readonly long[] _clientRetryTimer = new long[Enum.GetValues().Length]; + private readonly NpadManager _npadManager; public Client(NpadManager npadManager) { _npadManager = npadManager; - _hosts = new Dictionary(); - _motionData = new Dictionary>(); - _clients = new Dictionary(); + _hosts = new Dictionary(); + _motionData = new Dictionary>(); + _clients = new Dictionary(); CloseClients(); } @@ -84,7 +84,7 @@ namespace Ryujinx.Input.Motion.CemuHook try { - IPEndPoint endPoint = new IPEndPoint(IPAddress.Parse(host), port); + IPEndPoint endPoint = new(IPAddress.Parse(host), port); client = new UdpClient(host, port); @@ -141,9 +141,9 @@ namespace Ryujinx.Input.Motion.CemuHook { lock (_motionData) { - if (_motionData.ContainsKey(player)) + if (_motionData.TryGetValue(player, out Dictionary value)) { - if (_motionData[player].TryGetValue(slot, out input)) + if (value.TryGetValue(slot, out input)) { return true; } @@ -164,26 +164,26 @@ namespace Ryujinx.Input.Motion.CemuHook private void Send(byte[] data, int clientId) { - if (_clients.TryGetValue(clientId, out UdpClient _client)) + if (_clients.TryGetValue(clientId, out UdpClient client)) { - if (_client != null && _client.Client != null && _client.Client.Connected) + if (client != null && client.Client != null && client.Client.Connected) { try { - _client?.Send(data, data.Length); + client?.Send(data, data.Length); } catch (SocketException socketException) { if (!_clientErrorStatus[clientId]) { - Logger.Warning?.PrintMsg(LogClass.Hid, $"Unable to send data request to motion source at {_client.Client.RemoteEndPoint}. Error: {socketException.ErrorCode}"); + Logger.Warning?.PrintMsg(LogClass.Hid, $"Unable to send data request to motion source at {client.Client.RemoteEndPoint}. Error: {socketException.ErrorCode}"); } _clientErrorStatus[clientId] = true; RemoveClient(clientId); - _client?.Dispose(); + client?.Dispose(); SetRetryTimer(clientId); } @@ -193,7 +193,7 @@ namespace Ryujinx.Input.Motion.CemuHook RemoveClient(clientId); - _client?.Dispose(); + client?.Dispose(); SetRetryTimer(clientId); } @@ -203,13 +203,13 @@ namespace Ryujinx.Input.Motion.CemuHook private byte[] Receive(int clientId, int timeout = 0) { - if (_hosts.TryGetValue(clientId, out IPEndPoint endPoint) && _clients.TryGetValue(clientId, out UdpClient _client)) + if (_hosts.TryGetValue(clientId, out IPEndPoint endPoint) && _clients.TryGetValue(clientId, out UdpClient client)) { - if (_client != null && _client.Client != null && _client.Client.Connected) + if (client != null && client.Client != null && client.Client.Connected) { - _client.Client.ReceiveTimeout = timeout; + client.Client.ReceiveTimeout = timeout; - var result = _client?.Receive(ref endPoint); + var result = client?.Receive(ref endPoint); if (result.Length > 0) { @@ -242,9 +242,9 @@ namespace Ryujinx.Input.Motion.CemuHook public void ReceiveLoop(int clientId) { - if (_hosts.TryGetValue(clientId, out IPEndPoint endPoint) && _clients.TryGetValue(clientId, out UdpClient _client)) + if (_hosts.TryGetValue(clientId, out IPEndPoint endPoint) && _clients.TryGetValue(clientId, out UdpClient client)) { - if (_client != null && _client.Client != null && _client.Client.Connected) + if (client != null && client.Client != null && client.Client.Connected) { try { @@ -271,7 +271,7 @@ namespace Ryujinx.Input.Motion.CemuHook RemoveClient(clientId); - _client?.Dispose(); + client?.Dispose(); SetRetryTimer(clientId); } @@ -281,7 +281,7 @@ namespace Ryujinx.Input.Motion.CemuHook RemoveClient(clientId); - _client?.Dispose(); + client?.Dispose(); SetRetryTimer(clientId); } @@ -297,8 +297,8 @@ namespace Ryujinx.Input.Motion.CemuHook data = data.AsSpan()[16..].ToArray(); - using MemoryStream stream = new MemoryStream(data); - using BinaryReader reader = new BinaryReader(stream); + using MemoryStream stream = new(data); + using BinaryReader reader = new(stream); switch (type) { @@ -310,18 +310,18 @@ namespace Ryujinx.Input.Motion.CemuHook case MessageType.Data: ControllerDataResponse inputData = reader.ReadStruct(); - Vector3 accelerometer = new Vector3() + Vector3 accelerometer = new() { X = -inputData.AccelerometerX, Y = inputData.AccelerometerZ, - Z = -inputData.AccelerometerY + Z = -inputData.AccelerometerY, }; - Vector3 gyroscrope = new Vector3() + Vector3 gyroscrope = new() { X = inputData.GyroscopePitch, Y = inputData.GyroscopeRoll, - Z = -inputData.GyroscopeYaw + Z = -inputData.GyroscopeYaw, }; ulong timestamp = inputData.MotionTimestamp; @@ -346,7 +346,7 @@ namespace Ryujinx.Input.Motion.CemuHook } else { - MotionInput input = new MotionInput(); + MotionInput input = new(); input.Update(accelerometer, gyroscrope, timestamp, cemuHookConfig.Sensitivity, (float)cemuHookConfig.GyroDeadzone); @@ -355,11 +355,11 @@ namespace Ryujinx.Input.Motion.CemuHook } else { - MotionInput input = new MotionInput(); + MotionInput input = new(); input.Update(accelerometer, gyroscrope, timestamp, cemuHookConfig.Sensitivity, (float)cemuHookConfig.GyroDeadzone); - _motionData.Add(clientId, new Dictionary() { { slot, input } }); + _motionData.Add(clientId, new Dictionary { { slot, input } }); } } else @@ -380,38 +380,37 @@ namespace Ryujinx.Input.Motion.CemuHook Header header = GenerateHeader(clientId); - using (MemoryStream stream = MemoryStreamManager.Shared.GetStream()) - using (BinaryWriter writer = new BinaryWriter(stream)) + using MemoryStream stream = MemoryStreamManager.Shared.GetStream(); + using BinaryWriter writer = new(stream); + + writer.WriteStruct(header); + + ControllerInfoRequest request = new() { - writer.WriteStruct(header); + Type = MessageType.Info, + PortsCount = 4, + }; - ControllerInfoRequest request = new ControllerInfoRequest() - { - Type = MessageType.Info, - PortsCount = 4 - }; + request.PortIndices[0] = (byte)slot; - request.PortIndices[0] = (byte)slot; + writer.WriteStruct(request); - writer.WriteStruct(request); + header.Length = (ushort)(stream.Length - 16); - header.Length = (ushort)(stream.Length - 16); + writer.Seek(6, SeekOrigin.Begin); + writer.Write(header.Length); - writer.Seek(6, SeekOrigin.Begin); - writer.Write(header.Length); + Crc32.Hash(stream.ToArray(), header.Crc32.AsSpan()); - Crc32.Hash(stream.ToArray(), header.Crc32.AsSpan()); + writer.Seek(8, SeekOrigin.Begin); + writer.Write(header.Crc32.AsSpan()); - writer.Seek(8, SeekOrigin.Begin); - writer.Write(header.Crc32.AsSpan()); + byte[] data = stream.ToArray(); - byte[] data = stream.ToArray(); - - Send(data, clientId); - } + Send(data, clientId); } - public unsafe void RequestData(int clientId, int slot) + public void RequestData(int clientId, int slot) { if (!_active) { @@ -420,44 +419,43 @@ namespace Ryujinx.Input.Motion.CemuHook Header header = GenerateHeader(clientId); - using (MemoryStream stream = MemoryStreamManager.Shared.GetStream()) - using (BinaryWriter writer = new BinaryWriter(stream)) + using MemoryStream stream = MemoryStreamManager.Shared.GetStream(); + using BinaryWriter writer = new(stream); + + writer.WriteStruct(header); + + ControllerDataRequest request = new() { - writer.WriteStruct(header); + Type = MessageType.Data, + Slot = (byte)slot, + SubscriberType = SubscriberType.Slot, + }; - ControllerDataRequest request = new ControllerDataRequest() - { - Type = MessageType.Data, - Slot = (byte)slot, - SubscriberType = SubscriberType.Slot - }; + writer.WriteStruct(request); - writer.WriteStruct(request); + header.Length = (ushort)(stream.Length - 16); - header.Length = (ushort)(stream.Length - 16); + writer.Seek(6, SeekOrigin.Begin); + writer.Write(header.Length); - writer.Seek(6, SeekOrigin.Begin); - writer.Write(header.Length); + Crc32.Hash(stream.ToArray(), header.Crc32.AsSpan()); - Crc32.Hash(stream.ToArray(), header.Crc32.AsSpan()); + writer.Seek(8, SeekOrigin.Begin); + writer.Write(header.Crc32.AsSpan()); - writer.Seek(8, SeekOrigin.Begin); - writer.Write(header.Crc32.AsSpan()); + byte[] data = stream.ToArray(); - byte[] data = stream.ToArray(); - - Send(data, clientId); - } + Send(data, clientId); } - private Header GenerateHeader(int clientId) + private static Header GenerateHeader(int clientId) { - Header header = new Header() + Header header = new() { - Id = (uint)clientId, + Id = (uint)clientId, MagicString = Magic, - Version = Version, - Length = 0 + Version = Version, + Length = 0, }; return header; @@ -465,9 +463,10 @@ namespace Ryujinx.Input.Motion.CemuHook public void Dispose() { + GC.SuppressFinalize(this); _active = false; CloseClients(); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerData.cs b/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerData.cs index 7fb72344c..4eee2e8e0 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerData.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerData.cs @@ -16,15 +16,15 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol public struct ControllerDataResponse { public SharedResponse Shared; - public byte Connected; - public uint PacketId; - public byte ExtraButtons; - public byte MainButtons; - public ushort PSExtraInput; - public ushort LeftStickXY; - public ushort RightStickXY; - public uint DPadAnalog; - public ulong MainButtonsAnalog; + public byte Connected; + public uint PacketId; + public byte ExtraButtons; + public byte MainButtons; + public ushort PSExtraInput; + public ushort LeftStickXY; + public ushort RightStickXY; + public uint DPadAnalog; + public ulong MainButtonsAnalog; public Array6 Touch1; public Array6 Touch2; @@ -42,6 +42,6 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol { All, Slot, - Mac + Mac, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerInfo.cs b/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerInfo.cs index 63d4524a8..3e51c2915 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerInfo.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Protocol/ControllerInfo.cs @@ -7,7 +7,7 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol public struct ControllerInfoResponse { public SharedResponse Shared; - private byte _zero; + private readonly byte _zero; } [StructLayout(LayoutKind.Sequential, Pack = 1)] @@ -17,4 +17,4 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol public int PortsCount; public Array4 PortIndices; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/CemuHook/Protocol/Header.cs b/src/Ryujinx.Input/Motion/CemuHook/Protocol/Header.cs index 57f58ff03..142006d17 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Protocol/Header.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Protocol/Header.cs @@ -12,4 +12,4 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol public Array4 Crc32; public uint Id; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/CemuHook/Protocol/MessageType.cs b/src/Ryujinx.Input/Motion/CemuHook/Protocol/MessageType.cs index de1e5e90d..5ef15a7a3 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Protocol/MessageType.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Protocol/MessageType.cs @@ -4,6 +4,6 @@ { Protocol = 0x100000, Info, - Data + Data, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/CemuHook/Protocol/SharedResponse.cs b/src/Ryujinx.Input/Motion/CemuHook/Protocol/SharedResponse.cs index e2e1ee9b4..be37f53b6 100644 --- a/src/Ryujinx.Input/Motion/CemuHook/Protocol/SharedResponse.cs +++ b/src/Ryujinx.Input/Motion/CemuHook/Protocol/SharedResponse.cs @@ -6,11 +6,11 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol [StructLayout(LayoutKind.Sequential, Pack = 1)] public struct SharedResponse { - public MessageType Type; - public byte Slot; - public SlotState State; + public MessageType Type; + public byte Slot; + public SlotState State; public DeviceModelType ModelType; - public ConnectionType ConnectionType; + public ConnectionType ConnectionType; public Array6 MacAddress; public BatteryStatus BatteryStatus; @@ -20,21 +20,21 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol { Disconnected, Reserved, - Connected + Connected, } public enum DeviceModelType : byte { None, PartialGyro, - FullGyro + FullGyro, } public enum ConnectionType : byte { None, USB, - Bluetooth + Bluetooth, } public enum BatteryStatus : byte @@ -46,6 +46,6 @@ namespace Ryujinx.Input.Motion.CemuHook.Protocol High, Full, Charging, - Charged + Charged, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/MotionInput.cs b/src/Ryujinx.Input/Motion/MotionInput.cs index 1923d9cbe..2c7af58f6 100644 --- a/src/Ryujinx.Input/Motion/MotionInput.cs +++ b/src/Ryujinx.Input/Motion/MotionInput.cs @@ -6,19 +6,19 @@ namespace Ryujinx.Input { public class MotionInput { - public ulong TimeStamp { get; set; } + public ulong TimeStamp { get; set; } public Vector3 Accelerometer { get; set; } - public Vector3 Gyroscrope { get; set; } - public Vector3 Rotation { get; set; } + public Vector3 Gyroscrope { get; set; } + public Vector3 Rotation { get; set; } private readonly MotionSensorFilter _filter; public MotionInput() { - TimeStamp = 0; + TimeStamp = 0; Accelerometer = new Vector3(); - Gyroscrope = new Vector3(); - Rotation = new Vector3(); + Gyroscrope = new Vector3(); + Rotation = new Vector3(); // TODO: RE the correct filter. _filter = new MotionSensorFilter(0f); @@ -62,4 +62,4 @@ namespace Ryujinx.Input return degree * (MathF.PI / 180); } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/Motion/MotionSensorFilter.cs b/src/Ryujinx.Input/Motion/MotionSensorFilter.cs index 440fa7ac5..1a9749682 100644 --- a/src/Ryujinx.Input/Motion/MotionSensorFilter.cs +++ b/src/Ryujinx.Input/Motion/MotionSensorFilter.cs @@ -106,19 +106,19 @@ namespace Ryujinx.Input.Motion float q1 = Quaternion.W; // Estimated direction of gravity. - Vector3 gravity = new Vector3() + Vector3 gravity = new() { X = 2f * (q2 * q4 - q1 * q3), Y = 2f * (q1 * q2 + q3 * q4), - Z = q1 * q1 - q2 * q2 - q3 * q3 + q4 * q4 + Z = q1 * q1 - q2 * q2 - q3 * q3 + q4 * q4, }; // Error is cross product between estimated direction and measured direction of gravity. - Vector3 error = new Vector3() + Vector3 error = new() { X = accel.Y * gravity.Z - accel.Z * gravity.Y, Y = accel.Z * gravity.X - accel.X * gravity.Z, - Z = accel.X * gravity.Y - accel.Y * gravity.X + Z = accel.X * gravity.Y - accel.Y * gravity.X, }; if (Ki > 0f) @@ -134,7 +134,7 @@ namespace Ryujinx.Input.Motion gyro += (Kp * error) + (Ki * _intergralError); // Integrate rate of change of quaternion. - Vector3 delta = new Vector3(q2, q3, q4); + Vector3 delta = new(q2, q3, q4); q1 += (-q2 * gyro.X - q3 * gyro.Y - q4 * gyro.Z) * (SampleRateCoefficient * SamplePeriod); q2 += (q1 * gyro.X + delta.Y * gyro.Z - delta.Z * gyro.Y) * (SampleRateCoefficient * SamplePeriod); @@ -142,7 +142,7 @@ namespace Ryujinx.Input.Motion q4 += (q1 * gyro.Z + delta.X * gyro.Y - delta.Y * gyro.X) * (SampleRateCoefficient * SamplePeriod); // Normalise quaternion. - Quaternion quaternion = new Quaternion(q2, q3, q4, q1); + Quaternion quaternion = new(q2, q3, q4, q1); norm = 1f / quaternion.Length(); @@ -159,4 +159,4 @@ namespace Ryujinx.Input.Motion Quaternion = Quaternion.Identity; } } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/MotionInputId.cs b/src/Ryujinx.Input/MotionInputId.cs index 3176a987a..61c7d305c 100644 --- a/src/Ryujinx.Input/MotionInputId.cs +++ b/src/Ryujinx.Input/MotionInputId.cs @@ -20,6 +20,6 @@ /// Gyroscope. /// /// Values are in degrees - Gyroscope + Gyroscope, } } diff --git a/src/Ryujinx.Input/MouseButton.cs b/src/Ryujinx.Input/MouseButton.cs index ab7642167..a29910027 100644 --- a/src/Ryujinx.Input/MouseButton.cs +++ b/src/Ryujinx.Input/MouseButton.cs @@ -11,6 +11,6 @@ namespace Ryujinx.Input Button7, Button8, Button9, - Count + Count, } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/MouseStateSnapshot.cs b/src/Ryujinx.Input/MouseStateSnapshot.cs index ddfdebc6f..9efc9f9c7 100644 --- a/src/Ryujinx.Input/MouseStateSnapshot.cs +++ b/src/Ryujinx.Input/MouseStateSnapshot.cs @@ -8,7 +8,7 @@ namespace Ryujinx.Input /// public class MouseStateSnapshot { - private bool[] _buttonState; + private readonly bool[] _buttonState; /// /// The position of the mouse cursor @@ -31,7 +31,7 @@ namespace Ryujinx.Input _buttonState = buttonState; Position = position; - Scroll = scroll; + Scroll = scroll; } /// @@ -42,4 +42,4 @@ namespace Ryujinx.Input [MethodImpl(MethodImplOptions.AggressiveInlining)] public bool IsPressed(MouseButton button) => _buttonState[(int)button]; } -} \ No newline at end of file +} diff --git a/src/Ryujinx.Input/StickInputId.cs b/src/Ryujinx.Input/StickInputId.cs index fc9d80434..94c0f25e8 100644 --- a/src/Ryujinx.Input/StickInputId.cs +++ b/src/Ryujinx.Input/StickInputId.cs @@ -9,6 +9,6 @@ Left, Right, - Count + Count, } }