mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2024-12-26 10:33:05 +00:00
Update tests to work with the new Vector128 type and intrinsics
This commit is contained in:
gdkchan
parent
228c4eac74
commit
9f40cdd85e
19 changed files with 439 additions and 411 deletions
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@ -37,14 +37,7 @@ namespace ChocolArm64.Instruction
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public static void Add_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.AddScalar));
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}
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else
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{
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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}
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
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}
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public static void Add_V(AILEmitterCtx Context)
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@ -1132,14 +1125,7 @@ namespace ChocolArm64.Instruction
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public static void Sub_S(AILEmitterCtx Context)
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{
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if (AOptimizations.UseSse2)
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{
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EmitSse2Call(Context, nameof(Sse2.SubtractScalar));
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}
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else
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{
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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}
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EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
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}
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public static void Sub_V(AILEmitterCtx Context)
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@ -334,10 +334,10 @@ namespace ChocolArm64.Instruction
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switch (Size)
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{
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case 0:
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return Sse41.Extract(Sse.StaticCast<float, sbyte>(Vector), Index);
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return ExtractSByte(Vector, Index);
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case 1:
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return Sse2.Extract(Sse.StaticCast<float, short>(Vector), Index);
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return ExtractShort(Vector, Index);
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case 2:
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return Sse41.Extract(Sse.StaticCast<float, int>(Vector), Index);
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@ -352,6 +352,22 @@ namespace ChocolArm64.Instruction
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throw new PlatformNotSupportedException();
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}
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[MethodImpl(MethodImplOptions.NoInlining)]
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private static sbyte ExtractSByte(Vector128<float> Vector, byte Index)
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{
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//Workaround to JIT bug.
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//https://github.com/dotnet/coreclr/issues/17957
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return Sse41.Extract(Sse.StaticCast<float, sbyte>(Vector), Index);
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}
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[MethodImpl(MethodImplOptions.NoInlining)]
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private static short ExtractShort(Vector128<float> Vector, byte Index)
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{
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//Workaround to JIT bug.
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//https://github.com/dotnet/coreclr/issues/17957
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return Sse2.Extract(Sse.StaticCast<float, short>(Vector), Index);
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}
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[MethodImpl(MethodImplOptions.AggressiveInlining)]
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public static float VectorExtractSingle(Vector128<float> Vector, byte Index)
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{
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@ -4,7 +4,10 @@ using ChocolArm64.State;
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using NUnit.Framework;
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using System;
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using System.Threading;
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using System.Runtime.Intrinsics;
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using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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{
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@ -54,7 +57,9 @@ namespace Ryujinx.Tests.Cpu
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}
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protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
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AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
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Vector128<float> V0 = default(Vector128<float>),
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Vector128<float> V1 = default(Vector128<float>),
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Vector128<float> V2 = default(Vector128<float>),
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bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false,
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int Fpcr = 0x0, int Fpsr = 0x0)
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{
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@ -93,7 +98,9 @@ namespace Ryujinx.Tests.Cpu
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protected AThreadState SingleOpcode(uint Opcode,
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ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
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AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec),
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Vector128<float> V0 = default(Vector128<float>),
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Vector128<float> V1 = default(Vector128<float>),
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Vector128<float> V2 = default(Vector128<float>),
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bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false,
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int Fpcr = 0x0, int Fpsr = 0x0)
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{
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@ -105,5 +112,42 @@ namespace Ryujinx.Tests.Cpu
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return GetThreadState();
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}
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protected static double VectorExtractDouble(Vector128<float> Vector, byte Index)
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{
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long Value = Sse41.Extract(Sse.StaticCast<float, long>(Vector), Index);
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return BitConverter.Int64BitsToDouble(Value);
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}
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protected static Vector128<float> MakeVectorE0(double A)
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{
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return Sse.StaticCast<long, float>(Sse2.SetVector128(0, BitConverter.DoubleToInt64Bits(A)));
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}
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protected static Vector128<float> MakeVectorE0(ulong A)
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{
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A));
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}
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protected static Vector128<float> MakeVectorE0E1(ulong A, ulong B)
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{
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(B, A));
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}
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protected static Vector128<float> MakeVectorE1(ulong B)
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{
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return Sse.StaticCast<ulong, float>(Sse2.SetVector128(B, 0));
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}
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protected static ulong GetVectorE0(Vector128<float> Vector)
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{
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), 0);
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}
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protected static ulong GetVectorE1(Vector128<float> Vector)
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{
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return Sse41.Extract(Sse.StaticCast<float, ulong>(Vector), 1);
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}
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}
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}
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@ -1,14 +1,9 @@
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//#define Alu
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Alu"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestAlu : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define AluImm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("AluImm"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestAluImm : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define AluRs
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("AluRs"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestAluRs : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define AluRx
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("AluRx"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestAluRx : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define Bfm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Bfm"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestBfm : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define CcmpImm
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("CcmpImm"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestCcmpImm : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define CcmpReg
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("CcmpReg"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestCcmpReg : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define Csel
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Csel"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestCsel : CpuTest
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{
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@ -2,6 +2,8 @@ using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Misc"), Explicit]
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@ -73,7 +75,9 @@ namespace Ryujinx.Tests.Cpu
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RET
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*/
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SetThreadState(V0: new AVec { S0 = A }, V1: new AVec { S0 = B });
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SetThreadState(
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V0: Sse.SetScalarVector128(A),
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V1: Sse.SetScalarVector128(B));
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Opcode(0x1E2E1002);
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Opcode(0x1E201840);
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Opcode(0x1E211841);
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@ -84,7 +88,7 @@ namespace Ryujinx.Tests.Cpu
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().V0.S0, Is.EqualTo(16f));
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Assert.That(Sse41.Extract(GetThreadState().V0, 0), Is.EqualTo(16f));
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}
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[TestCase(-20d, -5d)] // 18 integer solutions.
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@ -120,7 +124,9 @@ namespace Ryujinx.Tests.Cpu
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RET
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*/
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SetThreadState(V0: new AVec { D0 = A }, V1: new AVec { D0 = B });
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SetThreadState(
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V0: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(A)),
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V1: Sse.StaticCast<double, float>(Sse2.SetScalarVector128(B)));
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Opcode(0x1E6E1002);
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Opcode(0x1E601840);
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Opcode(0x1E611841);
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@ -131,7 +137,7 @@ namespace Ryujinx.Tests.Cpu
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.That(GetThreadState().V0.D0, Is.EqualTo(16d));
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Assert.That(VectorExtractDouble(GetThreadState().V0, 0), Is.EqualTo(16d));
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}
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[Test]
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@ -1,14 +1,9 @@
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//#define Mov
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Mov"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestMov : CpuTest
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{
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@ -1,14 +1,9 @@
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//#define Mul
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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using Tester.Types;
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[Category("Mul"), Ignore("Tested: first half of 2018.")]
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public sealed class CpuTestMul : CpuTest
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{
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@ -1,6 +1,9 @@
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics.X86;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestScalar : CpuTest
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@ -25,8 +28,10 @@ namespace Ryujinx.Tests.Cpu
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public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMAX S0, S1, S2
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AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B });
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Assert.AreEqual(Result, ThreadState.V0.X0);
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AThreadState ThreadState = SingleOpcode(Opcode,
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V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
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V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
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Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
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}
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[TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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@ -49,8 +54,10 @@ namespace Ryujinx.Tests.Cpu
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public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMIN S0, S1, S2
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AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B });
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Assert.AreEqual(Result, ThreadState.V0.X0);
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AThreadState ThreadState = SingleOpcode(Opcode,
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V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
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V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
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Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
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}
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}
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}
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@ -4,6 +4,8 @@ using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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using Tester;
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@ -74,8 +76,8 @@ namespace Ryujinx.Tests.Cpu
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uint Opcode = 0x5EE0B820; // ABS D0, D1
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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@ -83,8 +85,8 @@ namespace Ryujinx.Tests.Cpu
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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@ -96,8 +98,8 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
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AVec V1 = new AVec { X0 = A };
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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@ -105,8 +107,8 @@ namespace Ryujinx.Tests.Cpu
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Assert.Multiple(() =>
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{
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Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(ThreadState.V0.X1, Is.Zero);
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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@ -119,7 +121,7 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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AVec V1 = new AVec { X0 = A0, X1 = A1 };
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -128,8 +130,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -140,8 +142,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x5EF1B820; // ADDP D0, V1.2D
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -150,8 +152,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -163,9 +165,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(),
|
||||
X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
|
||||
|
|
@ -174,8 +176,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -188,9 +190,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(),
|
||||
X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
|
||||
|
|
@ -200,8 +202,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -213,8 +215,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -222,8 +224,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -236,7 +238,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -245,8 +247,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -258,8 +260,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -267,8 +269,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -281,7 +283,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -290,8 +292,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -301,8 +303,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x7EE0B820; // NEG D0, D1
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -310,8 +312,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -323,8 +325,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -332,8 +334,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -346,7 +348,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -355,8 +357,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -368,9 +370,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(),
|
||||
X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
|
||||
|
|
@ -379,8 +381,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
@ -394,8 +396,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -404,8 +406,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
@ -420,8 +422,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -430,8 +432,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
@ -444,9 +446,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = TestContext.CurrentContext.Random.NextULong(),
|
||||
X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V0 = MakeVectorE0E1(TestContext.CurrentContext.Random.NextULong(),
|
||||
TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(TestContext.CurrentContext.Random.NextULong()));
|
||||
|
|
@ -455,8 +457,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
@ -470,8 +472,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -480,8 +482,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
@ -496,8 +498,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -506,8 +508,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); // FIXME: Temporary solution.
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
using ChocolArm64.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
public class CpuTestSimdArithmetic : CpuTest
|
||||
|
|
@ -35,13 +39,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
[TestCase(0x4EE28420u, 0x0102030405060708ul, 0xAAAAAAAAAAAAAAAAul, 0x0807060504030201ul, 0x2222222222222222ul, 0x0909090909090909ul, 0xCCCCCCCCCCCCCCCCul)]
|
||||
public void Add_V(uint Opcode, ulong A0, ulong A1, ulong B0, ulong B1, ulong Result0, ulong Result1)
|
||||
{
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -61,13 +65,13 @@ namespace Ryujinx.Tests.Cpu
|
|||
public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
|
||||
{
|
||||
uint Opcode = 0x4E22F420;
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
AVec V2 = new AVec { X0 = C, X1 = D };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
Vector128<float> V2 = MakeVectorE0E1(C, D);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -87,63 +91,68 @@ namespace Ryujinx.Tests.Cpu
|
|||
public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
|
||||
{
|
||||
uint Opcode = 0x4EA2F420;
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
AVec V2 = new AVec { X0 = C, X1 = D };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
Vector128<float> V2 = MakeVectorE0E1(C, D);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Description("fmul s6, s1, v0.s[2]")]
|
||||
public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x5F809826, V1: new AVec { S0 = A }, V0: new AVec { S2 = B });
|
||||
AThreadState ThreadState = SingleOpcode(0x5F809826,
|
||||
V1: Sse.SetVector128(0, 0, 0, A),
|
||||
V0: Sse.SetVector128(0, B, 0, 0));
|
||||
|
||||
Assert.That(ThreadState.V6.S0, Is.EqualTo(A * B));
|
||||
Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B));
|
||||
}
|
||||
|
||||
[Test, Description("frecpe v2.4s, v0.4s")]
|
||||
public void Frecpe_V([Random(100)] float A)
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: new AVec { S0 = A, S1 = A, S2 = A, S3 = A });
|
||||
AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A));
|
||||
|
||||
Assert.That(ThreadState.V2.S0, Is.EqualTo(1 / A));
|
||||
Assert.That(ThreadState.V2.S1, Is.EqualTo(1 / A));
|
||||
Assert.That(ThreadState.V2.S2, Is.EqualTo(1 / A));
|
||||
Assert.That(ThreadState.V2.S3, Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A));
|
||||
Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
|
||||
}
|
||||
|
||||
[Test, Description("frecpe d0, d1")]
|
||||
public void Frecpe_S([Random(100)] double A)
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: new AVec { D0 = A });
|
||||
AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: MakeVectorE0(A));
|
||||
|
||||
Assert.That(ThreadState.V0.D0, Is.EqualTo(1 / A));
|
||||
Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(1 / A));
|
||||
}
|
||||
|
||||
[Test, Description("frecps v4.4s, v2.4s, v0.4s")]
|
||||
public void Frecps_V([Random(10)] float A, [Random(10)] float B)
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x4E20FC44, V2: new AVec { S0 = A, S1 = A, S2 = A, S3 = A },
|
||||
V0: new AVec { S0 = B, S1 = B, S2 = B, S3 = B });
|
||||
AThreadState ThreadState = SingleOpcode(0x4E20FC44,
|
||||
V2: Sse.SetAllVector128(A),
|
||||
V0: Sse.SetAllVector128(B));
|
||||
|
||||
Assert.That(ThreadState.V4.S0, Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(ThreadState.V4.S1, Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(ThreadState.V4.S2, Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(ThreadState.V4.S3, Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
|
||||
}
|
||||
|
||||
[Test, Description("frecps d0, d1, d2")]
|
||||
public void Frecps_S([Random(10)] double A, [Random(10)] double B)
|
||||
{
|
||||
AThreadState ThreadState = SingleOpcode(0x5E62FC20, V1: new AVec { D0 = A }, V2: new AVec { D0 = B });
|
||||
AThreadState ThreadState = SingleOpcode(0x5E62FC20,
|
||||
V1: MakeVectorE0(A),
|
||||
V2: MakeVectorE0(B));
|
||||
|
||||
Assert.That(ThreadState.V0.D0, Is.EqualTo(2 - (A * B)));
|
||||
Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B)));
|
||||
}
|
||||
|
||||
|
||||
[TestCase(0x3FE66666u, false, 0x40000000u)]
|
||||
[TestCase(0x3F99999Au, false, 0x3F800000u)]
|
||||
[TestCase(0x404CCCCDu, false, 0x40400000u)]
|
||||
|
|
@ -189,17 +198,17 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x6E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
|
||||
|
|
@ -212,12 +221,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -286,9 +295,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E27C020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
|
|
@ -300,11 +309,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
|
||||
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
|
|
@ -348,12 +357,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -402,15 +411,15 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E254020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x4E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
|
||||
|
|
@ -422,12 +431,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -476,17 +485,17 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x4E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
|
||||
[TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xE218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
|
||||
|
|
@ -499,12 +508,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -553,15 +562,15 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E24C020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4EE18820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
|
||||
[TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
|
||||
|
|
@ -573,12 +582,12 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp = 0x2000000;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -647,9 +656,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
|
|
@ -661,11 +670,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
|
||||
[TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
|
||||
|
|
@ -709,21 +718,21 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
FpcrTemp |= 1 << 25;
|
||||
}
|
||||
AVec V1 = new AVec { X0 = A, X1 = B };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.AreEqual(Result0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
|
||||
});
|
||||
}
|
||||
|
||||
[TestCase(0x41200000u, 0x3EA18000u)]
|
||||
public void Frsqrte_S(uint A, uint Result)
|
||||
{
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(0x7EA1D820, V1: V1);
|
||||
Assert.AreEqual(Result, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,10 @@
|
|||
using ChocolArm64.State;
|
||||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
public class CpuTestSimdMove : CpuTest
|
||||
|
|
@ -10,15 +14,17 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
|
||||
{
|
||||
uint Opcode = 0x4E822820;
|
||||
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
|
||||
AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 };
|
||||
Vector128<float> V1 = Sse.StaticCast<uint, float>(Sse2.SetVector128(A3, A2, A1, A0));
|
||||
Vector128<float> V2 = Sse.StaticCast<uint, float>(Sse2.SetVector128(B3, B2, B1, B0));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(ThreadState.V0.W0, Is.EqualTo(A0));
|
||||
Assert.That(ThreadState.V0.W1, Is.EqualTo(B0));
|
||||
Assert.That(ThreadState.V0.W2, Is.EqualTo(A2));
|
||||
Assert.That(ThreadState.V0.W3, Is.EqualTo(B2));
|
||||
Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0);
|
||||
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
}
|
||||
|
||||
[Test, Description("trn1 v0.8b, v1.8b, v2.8b")]
|
||||
|
|
@ -28,19 +34,19 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Random(2)] byte B4, [Random(1)] byte B5, [Random(2)] byte B6, [Random(1)] byte B7)
|
||||
{
|
||||
uint Opcode = 0x0E022820;
|
||||
AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 };
|
||||
AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 };
|
||||
Vector128<float> V1 = Sse.StaticCast<byte, float>(Sse2.SetVector128(0, 0, 0, 0, 0, 0, 0, 0, A7, A6, A5, A4, A3, A2, A1, A0));
|
||||
Vector128<float> V2 = Sse.StaticCast<byte, float>(Sse2.SetVector128(0, 0, 0, 0, 0, 0, 0, 0, B7, B6, B5, B4, B3, B2, B1, B0));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(ThreadState.V0.B0, Is.EqualTo(A0));
|
||||
Assert.That(ThreadState.V0.B1, Is.EqualTo(B0));
|
||||
Assert.That(ThreadState.V0.B2, Is.EqualTo(A2));
|
||||
Assert.That(ThreadState.V0.B3, Is.EqualTo(B2));
|
||||
Assert.That(ThreadState.V0.B4, Is.EqualTo(A4));
|
||||
Assert.That(ThreadState.V0.B5, Is.EqualTo(B4));
|
||||
Assert.That(ThreadState.V0.B6, Is.EqualTo(A6));
|
||||
Assert.That(ThreadState.V0.B7, Is.EqualTo(B6));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B0));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B2));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B4));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A6));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B6));
|
||||
}
|
||||
|
||||
[Test, Description("trn2 v0.4s, v1.4s, v2.4s")]
|
||||
|
|
@ -48,15 +54,15 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
|
||||
{
|
||||
uint Opcode = 0x4E826820;
|
||||
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
|
||||
AVec V2 = new AVec { W0 = B0, W1 = B1, W2 = B2, W3 = B3 };
|
||||
Vector128<float> V1 = Sse.StaticCast<uint, float>(Sse2.SetVector128(A3, A2, A1, A0));
|
||||
Vector128<float> V2 = Sse.StaticCast<uint, float>(Sse2.SetVector128(B3, B2, B1, B0));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(ThreadState.V0.W0, Is.EqualTo(A1));
|
||||
Assert.That(ThreadState.V0.W1, Is.EqualTo(B1));
|
||||
Assert.That(ThreadState.V0.W2, Is.EqualTo(A3));
|
||||
Assert.That(ThreadState.V0.W3, Is.EqualTo(B3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
}
|
||||
|
||||
[Test, Description("trn2 v0.8b, v1.8b, v2.8b")]
|
||||
|
|
@ -66,19 +72,19 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Random(1)] byte B4, [Random(2)] byte B5, [Random(1)] byte B6, [Random(2)] byte B7)
|
||||
{
|
||||
uint Opcode = 0x0E026820;
|
||||
AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 };
|
||||
AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 };
|
||||
Vector128<float> V1 = Sse.StaticCast<byte, float>(Sse2.SetVector128(0, 0, 0, 0, 0, 0, 0, 0, A7, A6, A5, A4, A3, A2, A1, A0));
|
||||
Vector128<float> V2 = Sse.StaticCast<byte, float>(Sse2.SetVector128(0, 0, 0, 0, 0, 0, 0, 0, B7, B6, B5, B4, B3, B2, B1, B0));
|
||||
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
Assert.That(ThreadState.V0.B0, Is.EqualTo(A1));
|
||||
Assert.That(ThreadState.V0.B1, Is.EqualTo(B1));
|
||||
Assert.That(ThreadState.V0.B2, Is.EqualTo(A3));
|
||||
Assert.That(ThreadState.V0.B3, Is.EqualTo(B3));
|
||||
Assert.That(ThreadState.V0.B4, Is.EqualTo(A5));
|
||||
Assert.That(ThreadState.V0.B5, Is.EqualTo(B5));
|
||||
Assert.That(ThreadState.V0.B6, Is.EqualTo(A7));
|
||||
Assert.That(ThreadState.V0.B7, Is.EqualTo(B7));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)0), Is.EqualTo(A1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)1), Is.EqualTo(B1));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)2), Is.EqualTo(A3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)3), Is.EqualTo(B3));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)4), Is.EqualTo(A5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)5), Is.EqualTo(B5));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)6), Is.EqualTo(A7));
|
||||
Assert.That(Sse41.Extract(Sse.StaticCast<float, byte>(ThreadState.V0), (byte)7), Is.EqualTo(B7));
|
||||
}
|
||||
|
||||
[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
|
||||
|
|
@ -92,11 +98,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
// ZIP1 V0.<T>, V1.<T>, V2.<T>
|
||||
uint Opcode = 0x0E023820 | (Q << 30) | (size << 22);
|
||||
AVec V1 = new AVec { X0 = 0x1716151413121110, X1 = 0x1F1E1D1C1B1A1918 };
|
||||
AVec V2 = new AVec { X0 = 0x2726252423222120, X1 = 0x2F2E2D2C2B2A2928 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(0x1716151413121110, 0x1F1E1D1C1B1A1918);
|
||||
Vector128<float> V2 = MakeVectorE0E1(0x2726252423222120, 0x2F2E2D2C2B2A2928);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
Assert.AreEqual(Result_0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result_1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result_0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result_1, GetVectorE1(ThreadState.V0));
|
||||
}
|
||||
|
||||
[TestCase(0u, 0u, 0x2717261625152414ul, 0x0000000000000000ul)]
|
||||
|
|
@ -110,11 +116,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
{
|
||||
// ZIP2 V0.<T>, V1.<T>, V2.<T>
|
||||
uint Opcode = 0x0E027820 | (Q << 30) | (size << 22);
|
||||
AVec V1 = new AVec { X0 = 0x1716151413121110, X1 = 0x1F1E1D1C1B1A1918 };
|
||||
AVec V2 = new AVec { X0 = 0x2726252423222120, X1 = 0x2F2E2D2C2B2A2928 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(0x1716151413121110, 0x1F1E1D1C1B1A1918);
|
||||
Vector128<float> V2 = MakeVectorE0E1(0x2726252423222120, 0x2F2E2D2C2B2A2928);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
Assert.AreEqual(Result_0, ThreadState.V0.X0);
|
||||
Assert.AreEqual(Result_1, ThreadState.V0.X1);
|
||||
Assert.AreEqual(Result_0, GetVectorE0(ThreadState.V0));
|
||||
Assert.AreEqual(Result_1, GetVectorE1(ThreadState.V0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@ using ChocolArm64.State;
|
|||
|
||||
using NUnit.Framework;
|
||||
|
||||
using System.Runtime.Intrinsics;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
using Tester;
|
||||
|
|
@ -65,9 +67,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x5EE28420; // ADD D0, D1, D2
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -76,8 +78,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -90,9 +92,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -101,8 +103,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -117,8 +119,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -129,8 +131,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -145,9 +147,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -158,8 +160,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -175,9 +177,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -188,8 +190,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -202,9 +204,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -213,8 +215,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -229,8 +231,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -241,8 +243,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -253,9 +255,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x0E221C20; // AND V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -264,8 +266,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -278,8 +280,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x4E221C20; // AND V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -290,8 +292,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -302,9 +304,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x0E621C20; // BIC V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -313,8 +315,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -327,8 +329,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x4E621C20; // BIC V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -339,8 +341,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -352,9 +354,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x2EE21C20; // BIF V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z, TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
|
|
@ -364,8 +366,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -380,9 +382,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x6EE21C20; // BIF V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
|
|
@ -395,8 +397,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -408,9 +410,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x2EA21C20; // BIT V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z, TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
|
|
@ -420,8 +422,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -436,9 +438,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x6EA21C20; // BIT V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
|
|
@ -451,8 +453,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -464,9 +466,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x2E621C20; // BSL V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z, X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z, TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z));
|
||||
|
|
@ -476,8 +478,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -492,9 +494,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x6E621C20; // BSL V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X0 = _Z0, X1 = _Z1 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0E1(_Z0, _Z1);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(_Z0));
|
||||
|
|
@ -507,8 +509,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -519,9 +521,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x0EE21C20; // ORN V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -530,8 +532,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -544,8 +546,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x4EE21C20; // ORN V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -556,8 +558,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -568,9 +570,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x0EA21C20; // ORR V0.8B, V1.8B, V2.8B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -579,8 +581,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -593,8 +595,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x4EA21C20; // ORR V0.16B, V1.16B, V2.16B
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -605,8 +607,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -621,9 +623,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -634,8 +636,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -651,9 +653,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -664,8 +666,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -680,9 +682,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -693,8 +695,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -710,9 +712,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -723,8 +725,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -735,9 +737,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
uint Opcode = 0x7EE28420; // SUB D0, D1, D2
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -746,8 +748,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -760,9 +762,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A };
|
||||
AVec V2 = new AVec { X0 = B };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.V(1, new Bits(A));
|
||||
|
|
@ -771,8 +773,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -787,8 +789,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -799,8 +801,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -815,9 +817,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -828,8 +830,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(ThreadState.V0.X1, Is.Zero);
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
|
||||
});
|
||||
}
|
||||
|
||||
|
|
@ -845,9 +847,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
Bits Op = new Bits(Opcode);
|
||||
|
||||
ulong _X0 = TestContext.CurrentContext.Random.NextULong();
|
||||
AVec V0 = new AVec { X0 = _X0 };
|
||||
AVec V1 = new AVec { X0 = A0, X1 = A1 };
|
||||
AVec V2 = new AVec { X0 = B0, X1 = B1 };
|
||||
Vector128<float> V0 = MakeVectorE0(_X0);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A0, A1);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B0, B1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
|
||||
|
||||
AArch64.Vpart(1, 0, new Bits(A0));
|
||||
|
|
@ -858,8 +860,8 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(ThreadState.V0.X0, Is.EqualTo(_X0));
|
||||
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue