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https://git.naxdy.org/Mirror/Ryujinx.git
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Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdLogical.cs * Update AVectorHelper.cs * Update ASoftFallback.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Improve CountSetBits8() algorithm. * Improve CountSetBits8() algorithm.
This commit is contained in:
LDj3SNuD
gdkchan
parent
d24ea0d51b
commit
c228cf320d
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@ -348,6 +348,7 @@ namespace ChocolArm64
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SetA64("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg));
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SetA64("0x00111100000xxx<<x101xxxxxxxxxx", AInstEmit.Orr_Vi, typeof(AOpCodeSimdImm));
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SetA64("0x101110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Raddhn_V, typeof(AOpCodeSimdReg));
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SetA64("0x10111001100000010110xxxxxxxxxx", AInstEmit.Rbit_V, typeof(AOpCodeSimd));
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SetA64("0x00111000100000000110xxxxxxxxxx", AInstEmit.Rev16_V, typeof(AOpCodeSimd));
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SetA64("0x1011100x100000000010xxxxxxxxxx", AInstEmit.Rev32_V, typeof(AOpCodeSimd));
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SetA64("0x001110<<100000000010xxxxxxxxxx", AInstEmit.Rev64_V, typeof(AOpCodeSimd));
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@ -151,9 +151,9 @@ namespace ChocolArm64.Instruction
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, 0);
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Context.Emit(OpCodes.Conv_U1);
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Context.Emit(OpCodes.Conv_U4);
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AVectorHelper.EmitCall(Context, nameof(AVectorHelper.CountSetBits8));
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.CountSetBits8));
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Context.Emit(OpCodes.Conv_U8);
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@ -56,8 +56,9 @@ namespace ChocolArm64.Instruction
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
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EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
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@ -145,6 +146,31 @@ namespace ChocolArm64.Instruction
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EmitVectorImmBinaryOp(Context, () => Context.Emit(OpCodes.Or));
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}
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public static void Rbit_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Elems = Op.RegisterSize == ARegisterSize.SIMD128 ? 16 : 8;
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for (int Index = 0; Index < Elems; Index++)
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{
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EmitVectorExtractZx(Context, Op.Rn, Index, 0);
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Context.Emit(OpCodes.Conv_U4);
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.ReverseBits8));
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Context.Emit(OpCodes.Conv_U8);
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EmitVectorInsert(Context, Op.Rd, Index, 0);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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public static void Rev16_V(AILEmitterCtx Context)
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{
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EmitRev_V(Context, ContainerSize: 1);
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@ -164,18 +190,17 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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if (Op.Size >= ContainerSize)
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{
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throw new InvalidOperationException();
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}
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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int Elems = Bytes >> Op.Size;
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int ContainerMask = (1 << (ContainerSize - Op.Size)) - 1;
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for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
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for (int Index = 0; Index < Elems; Index++)
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{
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int RevIndex = Index ^ ContainerMask;
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@ -30,6 +30,14 @@ namespace ChocolArm64.Instruction
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return (ulong)Size;
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}
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public static uint CountSetBits8(uint Value)
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{
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Value = ((Value >> 1) & 0x55) + (Value & 0x55);
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Value = ((Value >> 2) & 0x33) + (Value & 0x33);
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return (Value >> 4) + (Value & 0x0f);
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}
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private const uint Crc32RevPoly = 0xedb88320;
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private const uint Crc32cRevPoly = 0x82f63b78;
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@ -89,6 +97,14 @@ namespace ChocolArm64.Instruction
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return Crc;
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}
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public static uint ReverseBits8(uint Value)
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{
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Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1);
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Value = ((Value & 0xcc) >> 2) | ((Value & 0x33) << 2);
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return (Value >> 4) | ((Value & 0x0f) << 4);
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}
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public static uint ReverseBits32(uint Value)
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{
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Value = ((Value & 0xaaaaaaaa) >> 1) | ((Value & 0x55555555) << 1);
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@ -93,14 +93,6 @@ namespace ChocolArm64.Instruction
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Value < ulong.MinValue ? ulong.MinValue : (ulong)Value;
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}
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public static int CountSetBits8(byte Value)
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{
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return ((Value >> 0) & 1) + ((Value >> 1) & 1) +
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((Value >> 2) & 1) + ((Value >> 3) & 1) +
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((Value >> 4) & 1) + ((Value >> 5) & 1) +
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((Value >> 6) & 1) + (Value >> 7);
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}
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public static double Max(double LHS, double RHS)
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{
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if (LHS == 0.0 && RHS == 0.0)
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@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu
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using Tester;
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using Tester.Types;
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[Category("Simd")/*, Ignore("Tested: first half of 2018.")*/]
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[Category("Simd")/*, Ignore("Tested: second half of 2018.")*/]
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public sealed class CpuTestSimd : CpuTest
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{
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#if Simd
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@ -775,6 +775,178 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
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public void Rbit_V_8B([ValueSource("_8B_")] [Random(1)] ulong A)
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{
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uint Opcode = 0x2E605820; // RBIT V0.8B, V1.8B
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("RBIT <Vd>.<T>, <Vn>.<T>")]
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public void Rbit_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1)
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{
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uint Opcode = 0x6E605820; // RBIT V0.16B, V1.16B
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
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public void Rev16_V_8B([ValueSource("_8B_")] [Random(1)] ulong A)
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{
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uint Opcode = 0x0E201820; // REV16 V0.8B, V1.8B
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV16 <Vd>.<T>, <Vn>.<T>")]
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public void Rev16_V_16B([ValueSource("_8B_")] [Random(1)] ulong A0,
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[ValueSource("_8B_")] [Random(1)] ulong A1)
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{
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uint Opcode = 0x4E201820; // REV16 V0.16B, V1.16B
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
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public void Rev32_V_8B_4H([ValueSource("_8B4H_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u)] uint size) // <8B, 4H>
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{
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uint Opcode = 0x2E200820; // REV32 V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV32 <Vd>.<T>, <Vn>.<T>")]
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public void Rev32_V_16B_8H([ValueSource("_8B4H_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u)] uint size) // <16B, 8H>
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{
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uint Opcode = 0x6E200820; // REV32 V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
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public void Rev64_V_8B_4H_2S([ValueSource("_8B4H2S_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E200820; // REV64 V0.8B, V1.8B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V0 = MakeVectorE1(TestContext.CurrentContext.Random.NextULong());
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AArch64.V(1, new Bits(A));
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SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.Zero);
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});
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}
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[Test, Pairwise, Description("REV64 <Vd>.<T>, <Vn>.<T>")]
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public void Rev64_V_16B_8H_4S([ValueSource("_8B4H2S_")] [Random(1)] ulong A0,
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[ValueSource("_8B4H2S_")] [Random(1)] ulong A1,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
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{
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uint Opcode = 0x4E200820; // REV64 V0.16B, V1.16B
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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Vector128<float> V1 = MakeVectorE0E1(A0, A1);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
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AArch64.Vpart(1, 0, new Bits(A0));
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AArch64.Vpart(1, 1, new Bits(A1));
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SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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}
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[Test, Description("SQXTN <Vb><d>, <Va><n>")]
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public void Sqxtn_S_HB_SH_DS([ValueSource("_1H1S1D_")] [Random(1)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <HB, SH, DS>
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@ -11,7 +11,7 @@ namespace Ryujinx.Tests.Cpu
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using Tester;
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using Tester.Types;
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[Category("SimdReg")/*, Ignore("Tested: first half of 2018.")*/]
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[Category("SimdReg")/*, Ignore("Tested: second half of 2018.")*/]
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public sealed class CpuTestSimdReg : CpuTest
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{
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#if SimdReg
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@ -1974,13 +1974,13 @@ namespace Ryujinx.Tests.Cpu.Tester
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switch (Bits.Concat(op, U))
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{
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default:
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case Bits bits when bits == "00":
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comparison = CompareOp.CompareOp_GT;
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break;
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case Bits bits when bits == "01":
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comparison = CompareOp.CompareOp_GE;
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break;
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default:
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case Bits bits when bits == "10":
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comparison = CompareOp.CompareOp_EQ;
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break;
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@ -2004,13 +2004,13 @@ namespace Ryujinx.Tests.Cpu.Tester
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switch (comparison)
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{
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default:
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case CompareOp.CompareOp_GT:
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test_passed = (element > (BigInteger)0);
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break;
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case CompareOp.CompareOp_GE:
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test_passed = (element >= (BigInteger)0);
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break;
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default:
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case CompareOp.CompareOp_EQ:
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test_passed = (element == (BigInteger)0);
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break;
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@ -2048,13 +2048,13 @@ namespace Ryujinx.Tests.Cpu.Tester
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switch (Bits.Concat(op, U))
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{
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default:
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case Bits bits when bits == "00":
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comparison = CompareOp.CompareOp_GT;
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break;
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case Bits bits when bits == "01":
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comparison = CompareOp.CompareOp_GE;
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break;
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default:
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case Bits bits when bits == "10":
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comparison = CompareOp.CompareOp_EQ;
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break;
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@ -2078,13 +2078,13 @@ namespace Ryujinx.Tests.Cpu.Tester
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switch (comparison)
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{
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default:
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case CompareOp.CompareOp_GT:
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test_passed = (element > (BigInteger)0);
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break;
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case CompareOp.CompareOp_GE:
|
||||
test_passed = (element >= (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_EQ:
|
||||
test_passed = (element == (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2122,10 +2122,10 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (Bits.Concat(op, U))
|
||||
{
|
||||
default:
|
||||
case Bits bits when bits == "00":
|
||||
comparison = CompareOp.CompareOp_GT;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "01":
|
||||
comparison = CompareOp.CompareOp_GE;
|
||||
break;
|
||||
|
|
@ -2152,10 +2152,10 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_GE:
|
||||
test_passed = (element >= (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2196,10 +2196,10 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (Bits.Concat(op, U))
|
||||
{
|
||||
default:
|
||||
case Bits bits when bits == "00":
|
||||
comparison = CompareOp.CompareOp_GT;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "01":
|
||||
comparison = CompareOp.CompareOp_GE;
|
||||
break;
|
||||
|
|
@ -2226,10 +2226,10 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_GE:
|
||||
test_passed = (element >= (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2418,7 +2418,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (Bits.Concat(op, U))
|
||||
{
|
||||
default:
|
||||
case Bits bits when bits == "00":
|
||||
comparison = CompareOp.CompareOp_GT;
|
||||
break;
|
||||
|
|
@ -2428,6 +2427,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case Bits bits when bits == "10":
|
||||
comparison = CompareOp.CompareOp_EQ;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "11":
|
||||
comparison = CompareOp.CompareOp_LE;
|
||||
break;
|
||||
|
|
@ -2448,7 +2448,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2458,6 +2457,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case CompareOp.CompareOp_EQ:
|
||||
test_passed = (element == (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_LE:
|
||||
test_passed = (element <= (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2492,7 +2492,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (Bits.Concat(op, U))
|
||||
{
|
||||
default:
|
||||
case Bits bits when bits == "00":
|
||||
comparison = CompareOp.CompareOp_GT;
|
||||
break;
|
||||
|
|
@ -2502,6 +2501,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case Bits bits when bits == "10":
|
||||
comparison = CompareOp.CompareOp_EQ;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "11":
|
||||
comparison = CompareOp.CompareOp_LE;
|
||||
break;
|
||||
|
|
@ -2522,7 +2522,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2532,6 +2531,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case CompareOp.CompareOp_EQ:
|
||||
test_passed = (element == (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_LE:
|
||||
test_passed = (element <= (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2576,7 +2576,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2589,6 +2588,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case CompareOp.CompareOp_LE:
|
||||
test_passed = (element <= (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_LT:
|
||||
test_passed = (element < (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2630,7 +2630,6 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
|
||||
switch (comparison)
|
||||
{
|
||||
default:
|
||||
case CompareOp.CompareOp_GT:
|
||||
test_passed = (element > (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2643,6 +2642,7 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
case CompareOp.CompareOp_LE:
|
||||
test_passed = (element <= (BigInteger)0);
|
||||
break;
|
||||
default:
|
||||
case CompareOp.CompareOp_LT:
|
||||
test_passed = (element < (BigInteger)0);
|
||||
break;
|
||||
|
|
@ -2801,6 +2801,265 @@ namespace Ryujinx.Tests.Cpu.Tester
|
|||
V(d, result);
|
||||
}
|
||||
|
||||
// rbit_advsimd.html
|
||||
public static void Rbit_V(bool Q, Bits Rn, Bits Rd)
|
||||
{
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
int esize = 8;
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / 8;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
Bits element;
|
||||
Bits rev = new Bits(esize);
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = Elem(operand, e, esize);
|
||||
|
||||
for (int i = 0; i <= esize - 1; i++)
|
||||
{
|
||||
rev[esize - 1 - i] = element[i];
|
||||
}
|
||||
|
||||
Elem(result, e, esize, rev);
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// rev16_advsimd.html
|
||||
public static void Rev16_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool o0 = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
// size=esize: B(0), H(1), S(1), D(S)
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
// op=REVx: 64(0), 32(1), 16(2)
|
||||
Bits op = Bits.Concat(o0, U);
|
||||
|
||||
// => op+size:
|
||||
// 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X
|
||||
// 32+B = 1, 32+H = 2, 32+S = X, 32+D = X
|
||||
// 16+B = 2, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
// => 3-(op+size) (index bits in group)
|
||||
// 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X
|
||||
// 32+B = 2, 32+H = 1, 32+S = X, 32+D = X
|
||||
// 16+B = 1, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
|
||||
// index bits within group: 1, 2, 3
|
||||
/* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */
|
||||
|
||||
int container_size;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
default:
|
||||
case Bits bits when bits == "10":
|
||||
container_size = 16;
|
||||
break;
|
||||
case Bits bits when bits == "01":
|
||||
container_size = 32;
|
||||
break;
|
||||
case Bits bits when bits == "00":
|
||||
container_size = 64;
|
||||
break;
|
||||
}
|
||||
|
||||
int containers = datasize / container_size;
|
||||
int elements_per_container = container_size / esize;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
int element = 0;
|
||||
int rev_element;
|
||||
|
||||
for (int c = 0; c <= containers - 1; c++)
|
||||
{
|
||||
rev_element = element + elements_per_container - 1;
|
||||
|
||||
for (int e = 0; e <= elements_per_container - 1; e++)
|
||||
{
|
||||
Elem(result, rev_element, esize, Elem(operand, element, esize));
|
||||
|
||||
element = element + 1;
|
||||
rev_element = rev_element - 1;
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// rev32_advsimd.html
|
||||
public static void Rev32_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
const bool o0 = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
// size=esize: B(0), H(1), S(1), D(S)
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
// op=REVx: 64(0), 32(1), 16(2)
|
||||
Bits op = Bits.Concat(o0, U);
|
||||
|
||||
// => op+size:
|
||||
// 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X
|
||||
// 32+B = 1, 32+H = 2, 32+S = X, 32+D = X
|
||||
// 16+B = 2, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
// => 3-(op+size) (index bits in group)
|
||||
// 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X
|
||||
// 32+B = 2, 32+H = 1, 32+S = X, 32+D = X
|
||||
// 16+B = 1, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
|
||||
// index bits within group: 1, 2, 3
|
||||
/* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */
|
||||
|
||||
int container_size;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case Bits bits when bits == "10":
|
||||
container_size = 16;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "01":
|
||||
container_size = 32;
|
||||
break;
|
||||
case Bits bits when bits == "00":
|
||||
container_size = 64;
|
||||
break;
|
||||
}
|
||||
|
||||
int containers = datasize / container_size;
|
||||
int elements_per_container = container_size / esize;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
int element = 0;
|
||||
int rev_element;
|
||||
|
||||
for (int c = 0; c <= containers - 1; c++)
|
||||
{
|
||||
rev_element = element + elements_per_container - 1;
|
||||
|
||||
for (int e = 0; e <= elements_per_container - 1; e++)
|
||||
{
|
||||
Elem(result, rev_element, esize, Elem(operand, element, esize));
|
||||
|
||||
element = element + 1;
|
||||
rev_element = rev_element - 1;
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// rev64_advsimd.html
|
||||
public static void Rev64_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
const bool o0 = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
// size=esize: B(0), H(1), S(1), D(S)
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
|
||||
// op=REVx: 64(0), 32(1), 16(2)
|
||||
Bits op = Bits.Concat(o0, U);
|
||||
|
||||
// => op+size:
|
||||
// 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X
|
||||
// 32+B = 1, 32+H = 2, 32+S = X, 32+D = X
|
||||
// 16+B = 2, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
// => 3-(op+size) (index bits in group)
|
||||
// 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X
|
||||
// 32+B = 2, 32+H = 1, 32+S = X, 32+D = X
|
||||
// 16+B = 1, 16+H = X, 16+S = X, 16+D = X
|
||||
// 8+B = X, 8+H = X, 8+S = X, 8+D = X
|
||||
|
||||
// index bits within group: 1, 2, 3
|
||||
/* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */
|
||||
|
||||
int container_size;
|
||||
|
||||
switch (op)
|
||||
{
|
||||
case Bits bits when bits == "10":
|
||||
container_size = 16;
|
||||
break;
|
||||
case Bits bits when bits == "01":
|
||||
container_size = 32;
|
||||
break;
|
||||
default:
|
||||
case Bits bits when bits == "00":
|
||||
container_size = 64;
|
||||
break;
|
||||
}
|
||||
|
||||
int containers = datasize / container_size;
|
||||
int elements_per_container = container_size / esize;
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
|
||||
int element = 0;
|
||||
int rev_element;
|
||||
|
||||
for (int c = 0; c <= containers - 1; c++)
|
||||
{
|
||||
rev_element = element + elements_per_container - 1;
|
||||
|
||||
for (int e = 0; e <= elements_per_container - 1; e++)
|
||||
{
|
||||
Elem(result, rev_element, esize, Elem(operand, element, esize));
|
||||
|
||||
element = element + 1;
|
||||
rev_element = rev_element - 1;
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqxtn_advsimd.html#SQXTN_asisdmisc_N
|
||||
public static void Sqxtn_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue