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Fix output component register on pixel shaders (#1613)
* Fix output component register on pixel shaders * Clean up usings * Do not advance if no component is enabled for the target, this keeps the previous behavior
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6a51b628f9
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@ -1,4 +1,3 @@
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using Ryujinx.Common;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.Decoders;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using Ryujinx.Graphics.Shader.IntermediateRepresentation;
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using System.Collections.Generic;
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using System.Collections.Generic;
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@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Translation
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this.Copy(dest, src);
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this.Copy(dest, src);
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}
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}
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int regIndex = 0;
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int regIndexBase = 0;
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for (int rtIndex = 0; rtIndex < 8; rtIndex++)
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for (int rtIndex = 0; rtIndex < 8; rtIndex++)
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{
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{
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@ -100,7 +99,7 @@ namespace Ryujinx.Graphics.Shader.Translation
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int fragmentOutputColorAttr = AttributeConsts.FragmentOutputColorBase + rtIndex * 16;
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int fragmentOutputColorAttr = AttributeConsts.FragmentOutputColorBase + rtIndex * 16;
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Operand src = Register(regIndex, RegisterType.Gpr);
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Operand src = Register(regIndexBase + component, RegisterType.Gpr);
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// Perform B <-> R swap if needed, for BGRA formats (not supported on OpenGL).
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// Perform B <-> R swap if needed, for BGRA formats (not supported on OpenGL).
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if (component == 0 || component == 2)
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if (component == 0 || component == 2)
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@ -125,11 +124,12 @@ namespace Ryujinx.Graphics.Shader.Translation
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{
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{
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this.Copy(Attribute(fragmentOutputColorAttr + component * 4), src);
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this.Copy(Attribute(fragmentOutputColorAttr + component * 4), src);
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}
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}
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regIndex++;
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}
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}
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regIndex = BitUtils.AlignUp(regIndex, 4);
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if (target.Enabled)
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{
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regIndexBase += 4;
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}
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}
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}
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}
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}
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}
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}
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