diff --git a/ChocolArm64/ABitUtils.cs b/ChocolArm64/ABitUtils.cs index 357dd45d1..dd4162356 100644 --- a/ChocolArm64/ABitUtils.cs +++ b/ChocolArm64/ABitUtils.cs @@ -27,6 +27,10 @@ namespace ChocolArm64 return -1; } + private static readonly sbyte[] HbsNibbleTbl = { -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 }; + + public static int HighestBitSetNibble(int Value) => HbsNibbleTbl[Value & 0b1111]; + public static long Replicate(long Bits, int Size) { long Output = 0; @@ -54,4 +58,4 @@ namespace ChocolArm64 return Value != 0 && (Value & (Value - 1)) == 0; } } -} \ No newline at end of file +} diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index a73466ae1..b053334f3 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -343,6 +343,7 @@ namespace ChocolArm64 SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg)); SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem)); SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg)); + SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", AInstEmit.Mls_Ve, typeof(AOpCodeSimdRegElem)); SetA64("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); SetA64("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); SetA64("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); @@ -380,8 +381,9 @@ namespace ChocolArm64 SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd)); SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg)); SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg)); - SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm)); - SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm)); + SetA64("0101111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm)); + SetA64("0x00111100>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm)); + SetA64("0100111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm)); SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd)); SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm)); SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg)); @@ -415,13 +417,18 @@ namespace ChocolArm64 SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd)); SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd)); SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg)); + SetA64("0101111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_S, typeof(AOpCodeSimdShImm)); SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm)); SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm)); + SetA64("0101111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_S, typeof(AOpCodeSimdShImm)); + SetA64("0x00111100>>>xxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm)); + SetA64("0100111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm)); SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg)); SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm)); SetA64("0101111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm)); SetA64("0x00111100>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm)); SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm)); + SetA64("0101111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_S, typeof(AOpCodeSimdShImm)); SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm)); SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm)); SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V, typeof(AOpCodeSimdReg)); @@ -474,6 +481,12 @@ namespace ChocolArm64 SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd)); SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd)); SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg)); + SetA64("0111111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_S, typeof(AOpCodeSimdShImm)); + SetA64("0x10111100>>>xxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm)); + SetA64("0110111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm)); + SetA64("0111111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_S, typeof(AOpCodeSimdShImm)); + SetA64("0x10111100>>>xxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm)); + SetA64("0110111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm)); SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg)); SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm)); SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm)); @@ -481,6 +494,7 @@ namespace ChocolArm64 SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm)); SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd)); SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd)); + SetA64("0111111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_S, typeof(AOpCodeSimdShImm)); SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm)); SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm)); SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V, typeof(AOpCodeSimdReg)); diff --git a/ChocolArm64/Decoder/AOpCodeSimdShImm.cs b/ChocolArm64/Decoder/AOpCodeSimdShImm.cs index 6c8398817..e6d5210f2 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdShImm.cs +++ b/ChocolArm64/Decoder/AOpCodeSimdShImm.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder { Imm = (OpCode >> 16) & 0x7f; - Size = ABitUtils.HighestBitSet32(Imm >> 3); + Size = ABitUtils.HighestBitSetNibble(Imm >> 3); } } -} \ No newline at end of file +} diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs index a291a7e51..b9aedd07b 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs @@ -957,6 +957,15 @@ namespace ChocolArm64.Instruction }); } + public static void Mls_Ve(AILEmitterCtx Context) + { + EmitVectorTernaryOpByElemZx(Context, () => + { + Context.Emit(OpCodes.Mul); + Context.Emit(OpCodes.Sub); + }); + } + public static void Mul_V(AILEmitterCtx Context) { EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index 4ecfdae30..cb884c1ac 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -626,6 +626,9 @@ namespace ChocolArm64.Instruction int Bytes = Op.GetBitsCount() >> 3; int Elems = Bytes >> Op.Size; + EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed); + Context.EmitSttmp(); + for (int Index = 0; Index < Elems; Index++) { if (Ternary) @@ -634,7 +637,7 @@ namespace ChocolArm64.Instruction } EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed); - EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed); + Context.EmitLdtmp(); Emit(); diff --git a/ChocolArm64/Instruction/AInstEmitSimdShift.cs b/ChocolArm64/Instruction/AInstEmitSimdShift.cs index 6f6b56068..4dee53b9b 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdShift.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdShift.cs @@ -14,20 +14,24 @@ namespace ChocolArm64.Instruction { AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; - EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size); + EmitScalarUnaryOpZx(Context, () => + { + Context.EmitLdc_I4(GetImmShl(Op)); - Context.EmitLdc_I4(GetImmShl(Op)); - - Context.Emit(OpCodes.Shl); - - EmitScalarSet(Context, Op.Rd, Op.Size); + Context.Emit(OpCodes.Shl); + }); } public static void Shl_V(AILEmitterCtx Context) { AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; - EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op)); + EmitVectorUnaryOpZx(Context, () => + { + Context.EmitLdc_I4(GetImmShl(Op)); + + Context.Emit(OpCodes.Shl); + }); } public static void Shll_V(AILEmitterCtx Context) @@ -103,15 +107,24 @@ namespace ChocolArm64.Instruction EmitVectorSaturatingNarrowOpSxSx(Context, Emit); } + public static void Srshr_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpSx(Context, ShrImmFlags.Round); + } + public static void Srshr_V(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; + EmitVectorShrImmOpSx(Context, ShrImmFlags.Round); + } - int Shift = GetImmShr(Op); + public static void Srsra_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate); + } - long RoundConst = 1L << (Shift - 1); - - EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst); + public static void Srsra_V(AILEmitterCtx Context) + { + EmitVectorShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate); } public static void Sshl_V(AILEmitterCtx Context) @@ -128,35 +141,42 @@ namespace ChocolArm64.Instruction public static void Sshr_S(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; - - EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size); - - Context.EmitLdc_I4(GetImmShr(Op)); - - Context.Emit(OpCodes.Shr); - - EmitScalarSet(Context, Op.Rd, Op.Size); + EmitShrImmOp(Context, ShrImmFlags.ScalarSx); } public static void Sshr_V(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; + EmitShrImmOp(Context, ShrImmFlags.VectorSx); + } - EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), GetImmShr(Op)); + public static void Ssra_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate); } public static void Ssra_V(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; + EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate); + } - Action Emit = () => - { - Context.Emit(OpCodes.Shr); - Context.Emit(OpCodes.Add); - }; + public static void Urshr_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpZx(Context, ShrImmFlags.Round); + } - EmitVectorShImmTernarySx(Context, Emit, GetImmShr(Op)); + public static void Urshr_V(AILEmitterCtx Context) + { + EmitVectorShrImmOpZx(Context, ShrImmFlags.Round); + } + + public static void Ursra_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate); + } + + public static void Ursra_V(AILEmitterCtx Context) + { + EmitVectorShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate); } public static void Ushl_V(AILEmitterCtx Context) @@ -173,41 +193,22 @@ namespace ChocolArm64.Instruction public static void Ushr_S(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; - - EmitScalarUnaryOpZx(Context, () => - { - Context.EmitLdc_I4(GetImmShr(Op)); - - Context.Emit(OpCodes.Shr_Un); - }); + EmitShrImmOp(Context, ShrImmFlags.ScalarZx); } public static void Ushr_V(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; + EmitShrImmOp(Context, ShrImmFlags.VectorZx); + } - EmitVectorUnaryOpZx(Context, () => - { - Context.EmitLdc_I4(GetImmShr(Op)); - - Context.Emit(OpCodes.Shr_Un); - }); + public static void Usra_S(AILEmitterCtx Context) + { + EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate); } public static void Usra_V(AILEmitterCtx Context) { - AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; - - Action Emit = () => - { - Context.EmitLdc_I4(GetImmShr(Op)); - - Context.Emit(OpCodes.Shr_Un); - Context.Emit(OpCodes.Add); - }; - - EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false); + EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate); } private static void EmitVectorShl(AILEmitterCtx Context, bool Signed) @@ -274,78 +275,118 @@ namespace ChocolArm64.Instruction } [Flags] - private enum ShImmFlags + private enum ShrImmFlags { - None = 0, + Scalar = 1 << 0, + Signed = 1 << 1, - Signed = 1 << 0, - Ternary = 1 << 1, - Rounded = 1 << 2, + Round = 1 << 2, + Accumulate = 1 << 3, - SignedTernary = Signed | Ternary, - SignedRounded = Signed | Rounded + ScalarSx = Scalar | Signed, + ScalarZx = Scalar, + + VectorSx = Signed, + VectorZx = 0 } - private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm) + private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags) { - EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.Signed); + EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags); } - private static void EmitVectorShImmTernarySx(AILEmitterCtx Context, Action Emit, int Imm) + private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags) { - EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedTernary); + EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags); } - private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm) + private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags) { - EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.None); + EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags); } - private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc) + private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags) { - EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedRounded, Rc); + EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags); } - private static void EmitVectorShImmOp(AILEmitterCtx Context, Action Emit, int Imm, ShImmFlags Flags, long Rc = 0) + private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags) { - AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp; + + bool Scalar = (Flags & ShrImmFlags.Scalar) != 0; + bool Signed = (Flags & ShrImmFlags.Signed) != 0; + bool Round = (Flags & ShrImmFlags.Round) != 0; + bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0; + + int Shift = GetImmShr(Op); + + long RoundConst = 1L << (Shift - 1); int Bytes = Op.GetBitsCount() >> 3; - int Elems = Bytes >> Op.Size; - - bool Signed = (Flags & ShImmFlags.Signed) != 0; - bool Ternary = (Flags & ShImmFlags.Ternary) != 0; - bool Rounded = (Flags & ShImmFlags.Rounded) != 0; + int Elems = !Scalar ? Bytes >> Op.Size : 1; for (int Index = 0; Index < Elems; Index++) { - if (Ternary) - { - EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed); - } - EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed); - if (Rounded) + if (Op.Size <= 2) { - Context.EmitLdc_I8(Rc); + if (Round) + { + Context.EmitLdc_I8(RoundConst); + + Context.Emit(OpCodes.Add); + } + + Context.EmitLdc_I4(Shift); + + Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un); + } + else /* if (Op.Size == 3) */ + { + EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift); + } + + if (Accumulate) + { + EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed); Context.Emit(OpCodes.Add); } - Context.EmitLdc_I4(Imm); - - Emit(); - - EmitVectorInsert(Context, Op.Rd, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); } - if (Op.RegisterSize == ARegisterSize.SIMD64) + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + + if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar) { EmitVectorZeroUpper(Context, Op.Rd); } } + // Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift; + private static void EmitShrImm_64( + AILEmitterCtx Context, + bool Signed, + long RoundConst, + int Shift) + { + if (((AOpCodeSimd)Context.CurrOp).Size < 3) + { + throw new InvalidOperationException(); + } + + Context.EmitLdc_I8(RoundConst); + Context.EmitLdc_I4(Shift); + + ASoftFallback.EmitCall(Context, Signed + ? nameof(ASoftFallback.SignedShrImm_64) + : nameof(ASoftFallback.UnsignedShrImm_64)); + } + private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm) { EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true); @@ -414,4 +455,4 @@ namespace ChocolArm64.Instruction Context.EmitStvec(Op.Rd); } } -} \ No newline at end of file +} diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs index 0ae84ab2d..a7bc10859 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/ASoftFallback.cs @@ -16,6 +16,92 @@ namespace ChocolArm64.Instruction Context.EmitCall(typeof(ASoftFallback), MthdName); } +#region "ShrImm_64" + public static long SignedShrImm_64(long Value, long RoundConst, int Shift) + { + if (RoundConst == 0L) + { + if (Shift <= 63) + { + return Value >> Shift; + } + else /* if (Shift == 64) */ + { + if (Value < 0L) + { + return -1L; + } + else + { + return 0L; + } + } + } + else /* if (RoundConst == 1L << (Shift - 1)) */ + { + if (Shift <= 63) + { + long Add = Value + RoundConst; + + if ((~Value & (Value ^ Add)) < 0L) + { + return (long)((ulong)Add >> Shift); + } + else + { + return Add >> Shift; + } + } + else /* if (Shift == 64) */ + { + return 0L; + } + } + } + + public static ulong UnsignedShrImm_64(ulong Value, long RoundConst, int Shift) + { + if (RoundConst == 0L) + { + if (Shift <= 63) + { + return Value >> Shift; + } + else /* if (Shift == 64) */ + { + return 0UL; + } + } + else /* if (RoundConst == 1L << (Shift - 1)) */ + { + ulong Add = Value + (ulong)RoundConst; + + if ((Add < Value) && (Add < (ulong)RoundConst)) + { + if (Shift <= 63) + { + return (Add >> Shift) | (0x8000000000000000UL >> (Shift - 1)); + } + else /* if (Shift == 64) */ + { + return 1UL; + } + } + else + { + if (Shift <= 63) + { + return Add >> Shift; + } + else /* if (Shift == 64) */ + { + return 0UL; + } + } + } + } +#endregion + #region "Saturating" public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State) { diff --git a/KEYS.md b/KEYS.md new file mode 100644 index 000000000..a2867ddca --- /dev/null +++ b/KEYS.md @@ -0,0 +1,104 @@ +# Keys + +Keys are required for decrypting most of the file formats used by the Nintendo Switch. + +Keysets are stored as text files. These 3 filenames are automatically read: +`prod.keys` - Contains common keys usedy by all Switch devices. +`console.keys` - Contains console-unique keys. +`title.keys` - Contains game-specific keys. + +Ryujinx will first look for keys in `RyuFS/system`, and if it doesn't find any there it will look in `$HOME/.switch`. + +A guide to assist with dumping your own keys can be found [here](https://gist.github.com/roblabla/d8358ab058bbe3b00614740dcba4f208). + +## Common keys + +Here is a template for a key file containing the main keys Ryujinx uses to read content files. +Both `prod.keys` and `console.keys` use this format. + +``` +master_key_00 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +master_key_01 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +master_key_02 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +master_key_03 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +master_key_04 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +master_key_05 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +titlekek_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +key_area_key_application_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +key_area_key_ocean_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +key_area_key_system_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +aes_kek_generation_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +aes_key_generation_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +header_kek_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +header_key_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +``` + +## Title keys + +Title keys are stored in the format `rights_id,key`. + +For example: + +``` +01000000000100000000000000000003,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +01000000000108000000000000000003,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +01000000000108000000000000000004,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +``` + +## Complete key list +Below is a complete list of keys that are currently recognized. +\## represents a hexadecimal number between 00 and 1F +@@ represents a hexadecimal number between 00 and 03 + +### Common keys + +``` +master_key_source +keyblob_mac_key_source +package2_key_source +aes_kek_generation_source +aes_key_generation_source +key_area_key_application_source +key_area_key_ocean_source +key_area_key_system_source +titlekek_source +header_kek_source +header_key_source +sd_card_kek_source +sd_card_nca_key_source +sd_card_save_key_source +retail_specific_aes_key_source +per_console_key_source +bis_kek_source +bis_key_source_@@ + +header_key +xci_header_key +eticket_rsa_kek + +master_key_## +package1_key_## +package2_key_## +titlekek_## +key_area_key_application_## +key_area_key_ocean_## +key_area_key_system_## +keyblob_key_source_## +keyblob_## +``` + +### Console-unique keys + +``` +secure_boot_key +tsec_key +device_key +bis_key_@@ + +keyblob_key_## +keyblob_mac_key_## +encrypted_keyblob_## + +sd_seed +``` diff --git a/Ryujinx.Graphics/Gal/GalFrameBufferFormat.cs b/Ryujinx.Graphics/Gal/GalFrameBufferFormat.cs index 3180aeff9..08bd622b3 100644 --- a/Ryujinx.Graphics/Gal/GalFrameBufferFormat.cs +++ b/Ryujinx.Graphics/Gal/GalFrameBufferFormat.cs @@ -1,6 +1,6 @@ namespace Ryujinx.Graphics.Gal { - public enum GalFrameBufferFormat + public enum GalSurfaceFormat { Bitmap = 0x1c, Unknown1D = 0x1d, diff --git a/Ryujinx.Graphics/Gal/GalImageFormat.cs b/Ryujinx.Graphics/Gal/GalImageFormat.cs index 4e84067bb..ba555684f 100644 --- a/Ryujinx.Graphics/Gal/GalImageFormat.cs +++ b/Ryujinx.Graphics/Gal/GalImageFormat.cs @@ -1,204 +1,93 @@ -namespace Ryujinx.Graphics.Gal +using System; + +namespace Ryujinx.Graphics.Gal { - //These are Vulkan-based enumerations, do not take them as Tegra values + [Flags] public enum GalImageFormat { - Undefined = 0, + Snorm = 1 << 27, + Unorm = 1 << 28, + Sint = 1 << 29, + Uint = 1 << 30, + Sfloat = 1 << 31, - R4G4_UNORM_PACK8 = 1, - R4G4B4A4_UNORM_PACK16 = 2, - B4G4R4A4_UNORM_PACK16 = 3, - R5G6B5_UNORM_PACK16 = 4, - B5G6R5_UNORM_PACK16 = 5, - R5G5B5A1_UNORM_PACK16 = 6, - B5G5R5A1_UNORM_PACK16 = 7, - A1R5G5B5_UNORM_PACK16 = 8, - R8_UNORM = 9, - R8_SNORM = 10, - R8_USCALED = 11, - R8_SSCALED = 12, - R8_UINT = 13, - R8_SINT = 14, - R8_SRGB = 15, - R8G8_UNORM = 16, - R8G8_SNORM = 17, - R8G8_USCALED = 18, - R8G8_SSCALED = 19, - R8G8_UINT = 20, - R8G8_SINT = 21, - R8G8_SRGB = 22, - R8G8B8_UNORM = 23, - R8G8B8_SNORM = 24, - R8G8B8_USCALED = 25, - R8G8B8_SSCALED = 26, - R8G8B8_UINT = 27, - R8G8B8_SINT = 28, - R8G8B8_SRGB = 29, - B8G8R8_UNORM = 30, - B8G8R8_SNORM = 31, - B8G8R8_USCALED = 32, - B8G8R8_SSCALED = 33, - B8G8R8_UINT = 34, - B8G8R8_SINT = 35, - B8G8R8_SRGB = 36, - R8G8B8A8_UNORM = 37, - R8G8B8A8_SNORM = 38, - R8G8B8A8_USCALED = 39, - R8G8B8A8_SSCALED = 40, - R8G8B8A8_UINT = 41, - R8G8B8A8_SINT = 42, - R8G8B8A8_SRGB = 43, - B8G8R8A8_UNORM = 44, - B8G8R8A8_SNORM = 45, - B8G8R8A8_USCALED = 46, - B8G8R8A8_SSCALED = 47, - B8G8R8A8_UINT = 48, - B8G8R8A8_SINT = 49, - B8G8R8A8_SRGB = 50, - A8B8G8R8_UNORM_PACK32 = 51, - A8B8G8R8_SNORM_PACK32 = 52, - A8B8G8R8_USCALED_PACK32 = 53, - A8B8G8R8_SSCALED_PACK32 = 54, - A8B8G8R8_UINT_PACK32 = 55, - A8B8G8R8_SINT_PACK32 = 56, - A8B8G8R8_SRGB_PACK32 = 57, - A2R10G10B10_UNORM_PACK32 = 58, - A2R10G10B10_SNORM_PACK32 = 59, - A2R10G10B10_USCALED_PACK32 = 60, - A2R10G10B10_SSCALED_PACK32 = 61, - A2R10G10B10_UINT_PACK32 = 62, - A2R10G10B10_SINT_PACK32 = 63, - A2B10G10R10_UNORM_PACK32 = 64, - A2B10G10R10_SNORM_PACK32 = 65, - A2B10G10R10_USCALED_PACK32 = 66, - A2B10G10R10_SSCALED_PACK32 = 67, - A2B10G10R10_UINT_PACK32 = 68, - A2B10G10R10_SINT_PACK32 = 69, - R16_UNORM = 70, - R16_SNORM = 71, - R16_USCALED = 72, - R16_SSCALED = 73, - R16_UINT = 74, - R16_SINT = 75, - R16_SFLOAT = 76, - R16G16_UNORM = 77, - R16G16_SNORM = 78, - R16G16_USCALED = 79, - R16G16_SSCALED = 80, - R16G16_UINT = 81, - R16G16_SINT = 82, - R16G16_SFLOAT = 83, - R16G16B16_UNORM = 84, - R16G16B16_SNORM = 85, - R16G16B16_USCALED = 86, - R16G16B16_SSCALED = 87, - R16G16B16_UINT = 88, - R16G16B16_SINT = 89, - R16G16B16_SFLOAT = 90, - R16G16B16A16_UNORM = 91, - R16G16B16A16_SNORM = 92, - R16G16B16A16_USCALED = 93, - R16G16B16A16_SSCALED = 94, - R16G16B16A16_UINT = 95, - R16G16B16A16_SINT = 96, - R16G16B16A16_SFLOAT = 97, - R32_UINT = 98, - R32_SINT = 99, - R32_SFLOAT = 100, - R32G32_UINT = 101, - R32G32_SINT = 102, - R32G32_SFLOAT = 103, - R32G32B32_UINT = 104, - R32G32B32_SINT = 105, - R32G32B32_SFLOAT = 106, - R32G32B32A32_UINT = 107, - R32G32B32A32_SINT = 108, - R32G32B32A32_SFLOAT = 109, - R64_UINT = 110, - R64_SINT = 111, - R64_SFLOAT = 112, - R64G64_UINT = 113, - R64G64_SINT = 114, - R64G64_SFLOAT = 115, - R64G64B64_UINT = 116, - R64G64B64_SINT = 117, - R64G64B64_SFLOAT = 118, - R64G64B64A64_UINT = 119, - R64G64B64A64_SINT = 120, - R64G64B64A64_SFLOAT = 121, - B10G11R11_UFLOAT_PACK32 = 122, - E5B9G9R9_UFLOAT_PACK32 = 123, - D16_UNORM = 124, - X8_D24_UNORM_PACK32 = 125, - D32_SFLOAT = 126, - S8_UINT = 127, - D16_UNORM_S8_UINT = 128, - D24_UNORM_S8_UINT = 129, - D32_SFLOAT_S8_UINT = 130, - BC1_RGB_UNORM_BLOCK = 131, - BC1_RGB_SRGB_BLOCK = 132, - BC1_RGBA_UNORM_BLOCK = 133, - BC1_RGBA_SRGB_BLOCK = 134, - BC2_UNORM_BLOCK = 135, - BC2_SRGB_BLOCK = 136, - BC3_UNORM_BLOCK = 137, - BC3_SRGB_BLOCK = 138, - BC4_UNORM_BLOCK = 139, - BC4_SNORM_BLOCK = 140, - BC5_UNORM_BLOCK = 141, - BC5_SNORM_BLOCK = 142, - BC6H_UFLOAT_BLOCK = 143, - BC6H_SFLOAT_BLOCK = 144, - BC7_UNORM_BLOCK = 145, - BC7_SRGB_BLOCK = 146, - ETC2_R8G8B8_UNORM_BLOCK = 147, - ETC2_R8G8B8_SRGB_BLOCK = 148, - ETC2_R8G8B8A1_UNORM_BLOCK = 149, - ETC2_R8G8B8A1_SRGB_BLOCK = 150, - ETC2_R8G8B8A8_UNORM_BLOCK = 151, - ETC2_R8G8B8A8_SRGB_BLOCK = 152, - EAC_R11_UNORM_BLOCK = 153, - EAC_R11_SNORM_BLOCK = 154, - EAC_R11G11_UNORM_BLOCK = 155, - EAC_R11G11_SNORM_BLOCK = 156, + TypeMask = Snorm | Unorm | Sint | Uint | Sfloat, - ASTC_BEGIN = ASTC_4x4_UNORM_BLOCK, + FormatMask = ~TypeMask, - ASTC_4x4_UNORM_BLOCK = 157, - ASTC_4x4_SRGB_BLOCK = 158, - ASTC_5x4_UNORM_BLOCK = 159, - ASTC_5x4_SRGB_BLOCK = 160, - ASTC_5x5_UNORM_BLOCK = 161, - ASTC_5x5_SRGB_BLOCK = 162, - ASTC_6x5_UNORM_BLOCK = 163, - ASTC_6x5_SRGB_BLOCK = 164, - ASTC_6x6_UNORM_BLOCK = 165, - ASTC_6x6_SRGB_BLOCK = 166, - ASTC_8x5_UNORM_BLOCK = 167, - ASTC_8x5_SRGB_BLOCK = 168, - ASTC_8x6_UNORM_BLOCK = 169, - ASTC_8x6_SRGB_BLOCK = 170, - ASTC_8x8_UNORM_BLOCK = 171, - ASTC_8x8_SRGB_BLOCK = 172, - ASTC_10x5_UNORM_BLOCK = 173, - ASTC_10x5_SRGB_BLOCK = 174, - ASTC_10x6_UNORM_BLOCK = 175, - ASTC_10x6_SRGB_BLOCK = 176, - ASTC_10x8_UNORM_BLOCK = 177, - ASTC_10x8_SRGB_BLOCK = 178, - ASTC_10x10_UNORM_BLOCK = 179, - ASTC_10x10_SRGB_BLOCK = 180, - ASTC_12x10_UNORM_BLOCK = 181, - ASTC_12x10_SRGB_BLOCK = 182, - ASTC_12x12_UNORM_BLOCK = 183, - ASTC_12x12_SRGB_BLOCK = 184, + ASTC_BEGIN = ASTC_4x4, - ASTC_END = ASTC_12x12_SRGB_BLOCK, + ASTC_4x4 = 1, + ASTC_5x4, + ASTC_5x5, + ASTC_6x5, + ASTC_6x6, + ASTC_8x5, + ASTC_8x6, + ASTC_8x8, + ASTC_10x5, + ASTC_10x6, + ASTC_10x8, + ASTC_10x10, + ASTC_12x10, + ASTC_12x12, - REVERSED_BEGIN, + ASTC_END = ASTC_12x12, - R4G4B4A4_UNORM_PACK16_REVERSED = REVERSED_BEGIN, - - REVERSED_END + R4G4, + R4G4B4A4, + B4G4R4A4, + A4B4G4R4, + R5G6B5, + B5G6R5, + R5G5B5A1, + B5G5R5A1, + A1R5G5B5, + R8, + R8G8, + G8R8, + R8G8B8, + B8G8R8, + R8G8B8A8, + B8G8R8A8, + A8B8G8R8, + A8B8G8R8_SRGB, + A2R10G10B10, + A2B10G10R10, + R16, + R16G16, + R16G16B16, + R16G16B16A16, + R32, + R32G32, + R32G32B32, + R32G32B32A32, + R64, + R64G64, + R64G64B64, + R64G64B64A64, + B10G11R11, + E5B9G9R9, + D16, + X8_D24, + D32, + S8, + D16_S8, + D24_S8, + D32_S8, + BC1_RGB, + BC1_RGBA, + BC2, + BC3, + BC4, + BC5, + BC6H_SF16, + BC6H_UF16, + BC7, + ETC2_R8G8B8, + ETC2_R8G8B8A1, + ETC2_R8G8B8A8, + EAC_R11, + EAC_R11G11, } } \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/IGalFrameBuffer.cs b/Ryujinx.Graphics/Gal/IGalRenderTarget.cs similarity index 96% rename from Ryujinx.Graphics/Gal/IGalFrameBuffer.cs rename to Ryujinx.Graphics/Gal/IGalRenderTarget.cs index 108d3d9b1..c44434ef6 100644 --- a/Ryujinx.Graphics/Gal/IGalFrameBuffer.cs +++ b/Ryujinx.Graphics/Gal/IGalRenderTarget.cs @@ -2,7 +2,7 @@ using System; namespace Ryujinx.Graphics.Gal { - public interface IGalFrameBuffer + public interface IGalRenderTarget { void BindColor(long Key, int Attachment); diff --git a/Ryujinx.Graphics/Gal/IGalRenderer.cs b/Ryujinx.Graphics/Gal/IGalRenderer.cs index b47ac71d0..41e95a878 100644 --- a/Ryujinx.Graphics/Gal/IGalRenderer.cs +++ b/Ryujinx.Graphics/Gal/IGalRenderer.cs @@ -10,7 +10,7 @@ namespace Ryujinx.Graphics.Gal IGalConstBuffer Buffer { get; } - IGalFrameBuffer FrameBuffer { get; } + IGalRenderTarget RenderTarget { get; } IGalRasterizer Rasterizer { get; } diff --git a/Ryujinx.Graphics/Gal/ImageFormatConverter.cs b/Ryujinx.Graphics/Gal/ImageFormatConverter.cs deleted file mode 100644 index 7aa39f5fb..000000000 --- a/Ryujinx.Graphics/Gal/ImageFormatConverter.cs +++ /dev/null @@ -1,279 +0,0 @@ -using System; - -namespace Ryujinx.Graphics.Gal -{ - public static class ImageFormatConverter - { - public static GalImageFormat ConvertTexture( - GalTextureFormat Format, - GalTextureType RType, - GalTextureType GType, - GalTextureType BType, - GalTextureType AType) - { - if (RType != GType || RType != BType || RType != AType) - { - throw new NotImplementedException("Per component types are not implemented"); - } - - GalTextureType Type = RType; - - switch (Type) - { - case GalTextureType.Snorm: - switch (Format) - { - case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SNORM; - case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_SNORM_PACK32; - case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_SNORM_PACK32; - case GalTextureFormat.G8R8: return GalImageFormat.R8G8_SNORM; - case GalTextureFormat.R16: return GalImageFormat.R16_SNORM; - case GalTextureFormat.R8: return GalImageFormat.R8_SNORM; - case GalTextureFormat.BC4: return GalImageFormat.BC4_SNORM_BLOCK; - case GalTextureFormat.BC5: return GalImageFormat.BC5_SNORM_BLOCK; - } - break; - - case GalTextureType.Unorm: - switch (Format) - { - case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_UNORM; - case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_UNORM_PACK32; - case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_UNORM_PACK32; - case GalTextureFormat.A4B4G4R4: return GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED; - case GalTextureFormat.A1B5G5R5: return GalImageFormat.A1R5G5B5_UNORM_PACK16; - case GalTextureFormat.B5G6R5: return GalImageFormat.B5G6R5_UNORM_PACK16; - case GalTextureFormat.BC7U: return GalImageFormat.BC7_UNORM_BLOCK; - case GalTextureFormat.G8R8: return GalImageFormat.R8G8_UNORM; - case GalTextureFormat.R16: return GalImageFormat.R16_UNORM; - case GalTextureFormat.R8: return GalImageFormat.R8_UNORM; - case GalTextureFormat.BC1: return GalImageFormat.BC1_RGBA_UNORM_BLOCK; - case GalTextureFormat.BC2: return GalImageFormat.BC2_UNORM_BLOCK; - case GalTextureFormat.BC3: return GalImageFormat.BC3_UNORM_BLOCK; - case GalTextureFormat.BC4: return GalImageFormat.BC4_UNORM_BLOCK; - case GalTextureFormat.BC5: return GalImageFormat.BC5_UNORM_BLOCK; - case GalTextureFormat.Z24S8: return GalImageFormat.D24_UNORM_S8_UINT; - case GalTextureFormat.ZF32_X24S8: return GalImageFormat.D32_SFLOAT_S8_UINT; - case GalTextureFormat.Astc2D4x4: return GalImageFormat.ASTC_4x4_UNORM_BLOCK; - case GalTextureFormat.Astc2D5x5: return GalImageFormat.ASTC_5x5_UNORM_BLOCK; - case GalTextureFormat.Astc2D6x6: return GalImageFormat.ASTC_6x6_UNORM_BLOCK; - case GalTextureFormat.Astc2D8x8: return GalImageFormat.ASTC_8x8_UNORM_BLOCK; - case GalTextureFormat.Astc2D10x10: return GalImageFormat.ASTC_10x10_UNORM_BLOCK; - case GalTextureFormat.Astc2D12x12: return GalImageFormat.ASTC_12x12_UNORM_BLOCK; - case GalTextureFormat.Astc2D5x4: return GalImageFormat.ASTC_5x4_UNORM_BLOCK; - case GalTextureFormat.Astc2D6x5: return GalImageFormat.ASTC_6x5_UNORM_BLOCK; - case GalTextureFormat.Astc2D8x6: return GalImageFormat.ASTC_8x6_UNORM_BLOCK; - case GalTextureFormat.Astc2D10x8: return GalImageFormat.ASTC_10x8_UNORM_BLOCK; - case GalTextureFormat.Astc2D12x10: return GalImageFormat.ASTC_12x10_UNORM_BLOCK; - case GalTextureFormat.Astc2D8x5: return GalImageFormat.ASTC_8x5_UNORM_BLOCK; - case GalTextureFormat.Astc2D10x5: return GalImageFormat.ASTC_10x5_UNORM_BLOCK; - case GalTextureFormat.Astc2D10x6: return GalImageFormat.ASTC_10x6_UNORM_BLOCK; - } - break; - - case GalTextureType.Sint: - switch (Format) - { - case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_SINT; - case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SINT; - case GalTextureFormat.R32G32: return GalImageFormat.R32G32_SINT; - case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_SINT_PACK32; - case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_SINT_PACK32; - case GalTextureFormat.R32: return GalImageFormat.R32_SINT; - case GalTextureFormat.G8R8: return GalImageFormat.R8G8_SINT; - case GalTextureFormat.R16: return GalImageFormat.R16_SINT; - case GalTextureFormat.R8: return GalImageFormat.R8_SINT; - } - break; - - case GalTextureType.Uint: - switch (Format) - { - case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_UINT; - case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_UINT; - case GalTextureFormat.R32G32: return GalImageFormat.R32G32_UINT; - case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_UINT_PACK32; - case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_UINT_PACK32; - case GalTextureFormat.R32: return GalImageFormat.R32_UINT; - case GalTextureFormat.G8R8: return GalImageFormat.R8G8_UINT; - case GalTextureFormat.R16: return GalImageFormat.R16_UINT; - case GalTextureFormat.R8: return GalImageFormat.R8_UINT; - } - break; - - case GalTextureType.Snorm_Force_Fp16: - //TODO - break; - - case GalTextureType.Unorm_Force_Fp16: - //TODO - break; - - case GalTextureType.Float: - switch (Format) - { - case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_SFLOAT; - case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SFLOAT; - case GalTextureFormat.R32G32: return GalImageFormat.R32G32_SFLOAT; - case GalTextureFormat.R32: return GalImageFormat.R32_SFLOAT; - case GalTextureFormat.BC6H_SF16: return GalImageFormat.BC6H_SFLOAT_BLOCK; - case GalTextureFormat.BC6H_UF16: return GalImageFormat.BC6H_UFLOAT_BLOCK; - case GalTextureFormat.R16: return GalImageFormat.R16_SFLOAT; - case GalTextureFormat.BF10GF11RF11: return GalImageFormat.B10G11R11_UFLOAT_PACK32; - case GalTextureFormat.ZF32: return GalImageFormat.D32_SFLOAT; - } - break; - } - - throw new NotImplementedException("0x" + ((int)Format).ToString("x2") + " " + Type.ToString()); - } - - public static GalImageFormat ConvertFrameBuffer(GalFrameBufferFormat Format) - { - switch (Format) - { - case GalFrameBufferFormat.R32Float: return GalImageFormat.R32_SFLOAT; - case GalFrameBufferFormat.RGB10A2Unorm: return GalImageFormat.A2B10G10R10_UNORM_PACK32; - case GalFrameBufferFormat.RGBA8Srgb: return GalImageFormat.A8B8G8R8_SRGB_PACK32; - case GalFrameBufferFormat.RGBA16Float: return GalImageFormat.R16G16B16A16_SFLOAT; - case GalFrameBufferFormat.R16Float: return GalImageFormat.R16_SFLOAT; - case GalFrameBufferFormat.R8Unorm: return GalImageFormat.R8_UNORM; - case GalFrameBufferFormat.RGBA8Unorm: return GalImageFormat.A8B8G8R8_UNORM_PACK32; - case GalFrameBufferFormat.R11G11B10Float: return GalImageFormat.B10G11R11_UFLOAT_PACK32; - case GalFrameBufferFormat.RGBA32Float: return GalImageFormat.R32G32B32A32_SFLOAT; - case GalFrameBufferFormat.RG16Snorm: return GalImageFormat.R16G16_SNORM; - case GalFrameBufferFormat.RG16Float: return GalImageFormat.R16G16_SFLOAT; - case GalFrameBufferFormat.RG8Snorm: return GalImageFormat.R8_SNORM; - case GalFrameBufferFormat.RGBA8Snorm: return GalImageFormat.A8B8G8R8_SNORM_PACK32; - case GalFrameBufferFormat.RG8Unorm: return GalImageFormat.R8G8_UNORM; - case GalFrameBufferFormat.BGRA8Unorm: return GalImageFormat.A8B8G8R8_UNORM_PACK32; - case GalFrameBufferFormat.BGRA8Srgb: return GalImageFormat.A8B8G8R8_SRGB_PACK32; - case GalFrameBufferFormat.RG32Float: return GalImageFormat.R32G32_SFLOAT; - case GalFrameBufferFormat.RG32Sint: return GalImageFormat.R32G32_SINT; - case GalFrameBufferFormat.RG32Uint: return GalImageFormat.R32G32_UINT; - } - - throw new NotImplementedException(Format.ToString()); - } - - public static GalImageFormat ConvertZeta(GalZetaFormat Format) - { - switch (Format) - { - case GalZetaFormat.Z32Float: return GalImageFormat.D32_SFLOAT; - case GalZetaFormat.S8Z24Unorm: return GalImageFormat.D24_UNORM_S8_UINT; - case GalZetaFormat.Z16Unorm: return GalImageFormat.D16_UNORM; - case GalZetaFormat.Z32S8X24Float: return GalImageFormat.D32_SFLOAT_S8_UINT; - } - - throw new NotImplementedException(Format.ToString()); - } - - public static bool HasColor(GalImageFormat Format) - { - switch (Format) - { - case GalImageFormat.R32G32B32A32_SFLOAT: - case GalImageFormat.R32G32B32A32_SINT: - case GalImageFormat.R32G32B32A32_UINT: - case GalImageFormat.R16G16B16A16_SFLOAT: - case GalImageFormat.R16G16B16A16_SINT: - case GalImageFormat.R16G16B16A16_UINT: - case GalImageFormat.R32G32_SFLOAT: - case GalImageFormat.R32G32_SINT: - case GalImageFormat.R32G32_UINT: - case GalImageFormat.A8B8G8R8_SNORM_PACK32: - case GalImageFormat.A8B8G8R8_UNORM_PACK32: - case GalImageFormat.A8B8G8R8_SINT_PACK32: - case GalImageFormat.A8B8G8R8_UINT_PACK32: - case GalImageFormat.A2B10G10R10_SINT_PACK32: - case GalImageFormat.A2B10G10R10_SNORM_PACK32: - case GalImageFormat.A2B10G10R10_UINT_PACK32: - case GalImageFormat.A2B10G10R10_UNORM_PACK32: - case GalImageFormat.R32_SFLOAT: - case GalImageFormat.R32_SINT: - case GalImageFormat.R32_UINT: - case GalImageFormat.BC6H_SFLOAT_BLOCK: - case GalImageFormat.BC6H_UFLOAT_BLOCK: - case GalImageFormat.A1R5G5B5_UNORM_PACK16: - case GalImageFormat.B5G6R5_UNORM_PACK16: - case GalImageFormat.BC7_UNORM_BLOCK: - case GalImageFormat.R16G16_SFLOAT: - case GalImageFormat.R16G16_SINT: - case GalImageFormat.R16G16_SNORM: - case GalImageFormat.R16G16_UNORM: - case GalImageFormat.R8G8_SINT: - case GalImageFormat.R8G8_SNORM: - case GalImageFormat.R8G8_UINT: - case GalImageFormat.R8G8_UNORM: - case GalImageFormat.R16_SFLOAT: - case GalImageFormat.R16_SINT: - case GalImageFormat.R16_SNORM: - case GalImageFormat.R16_UINT: - case GalImageFormat.R16_UNORM: - case GalImageFormat.R8_SINT: - case GalImageFormat.R8_SNORM: - case GalImageFormat.R8_UINT: - case GalImageFormat.R8_UNORM: - case GalImageFormat.B10G11R11_UFLOAT_PACK32: - case GalImageFormat.BC1_RGBA_UNORM_BLOCK: - case GalImageFormat.BC2_UNORM_BLOCK: - case GalImageFormat.BC3_UNORM_BLOCK: - case GalImageFormat.BC4_UNORM_BLOCK: - case GalImageFormat.BC5_UNORM_BLOCK: - case GalImageFormat.ASTC_4x4_UNORM_BLOCK: - case GalImageFormat.ASTC_5x5_UNORM_BLOCK: - case GalImageFormat.ASTC_6x6_UNORM_BLOCK: - case GalImageFormat.ASTC_8x8_UNORM_BLOCK: - case GalImageFormat.ASTC_10x10_UNORM_BLOCK: - case GalImageFormat.ASTC_12x12_UNORM_BLOCK: - case GalImageFormat.ASTC_5x4_UNORM_BLOCK: - case GalImageFormat.ASTC_6x5_UNORM_BLOCK: - case GalImageFormat.ASTC_8x6_UNORM_BLOCK: - case GalImageFormat.ASTC_10x8_UNORM_BLOCK: - case GalImageFormat.ASTC_12x10_UNORM_BLOCK: - case GalImageFormat.ASTC_8x5_UNORM_BLOCK: - case GalImageFormat.ASTC_10x5_UNORM_BLOCK: - case GalImageFormat.ASTC_10x6_UNORM_BLOCK: - case GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED: - return true; - - case GalImageFormat.D24_UNORM_S8_UINT: - case GalImageFormat.D32_SFLOAT: - case GalImageFormat.D16_UNORM: - case GalImageFormat.D32_SFLOAT_S8_UINT: - return false; - } - - throw new NotImplementedException(Format.ToString()); - } - - public static bool HasDepth(GalImageFormat Format) - { - switch (Format) - { - case GalImageFormat.D24_UNORM_S8_UINT: - case GalImageFormat.D32_SFLOAT: - case GalImageFormat.D16_UNORM: - case GalImageFormat.D32_SFLOAT_S8_UINT: - return true; - } - - //Depth formats are fewer than colors, so it's harder to miss one - //Instead of checking for individual formats, return false - return false; - } - - public static bool HasStencil(GalImageFormat Format) - { - switch (Format) - { - case GalImageFormat.D24_UNORM_S8_UINT: - case GalImageFormat.D32_SFLOAT_S8_UINT: - return true; - } - - return false; - } - } -} \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/OpenGL/ImageHandler.cs b/Ryujinx.Graphics/Gal/OpenGL/ImageHandler.cs index 74f18dcd3..dda825385 100644 --- a/Ryujinx.Graphics/Gal/OpenGL/ImageHandler.cs +++ b/Ryujinx.Graphics/Gal/OpenGL/ImageHandler.cs @@ -1,13 +1,11 @@ using OpenTK.Graphics.OpenGL; +using Ryujinx.Graphics.Texture; using System; namespace Ryujinx.Graphics.Gal.OpenGL { class ImageHandler { - //TODO: Use a variable value here - public const int MaxBpp = 16; - private static int CopyBuffer = 0; private static int CopyBufferSize = 0; @@ -38,87 +36,124 @@ namespace Ryujinx.Graphics.Gal.OpenGL this.Image = Image; } - public void EnsureSetup(GalImage Image) + public void EnsureSetup(GalImage NewImage) { - if (Width != Image.Width || - Height != Image.Height || - Format != Image.Format || - !Initialized) + if (Width == NewImage.Width && + Height == NewImage.Height && + Format == NewImage.Format && + Initialized) { - (PixelInternalFormat InternalFormat, PixelFormat PixelFormat, PixelType PixelType) = - OGLEnumConverter.GetImageFormat(Image.Format); + return; + } - GL.BindTexture(TextureTarget.Texture2D, Handle); + PixelInternalFormat InternalFmt; + PixelFormat PixelFormat; + PixelType PixelType; - if (Initialized) + if (ImageUtils.IsCompressed(NewImage.Format)) + { + InternalFmt = (PixelInternalFormat)OGLEnumConverter.GetCompressedImageFormat(NewImage.Format); + + PixelFormat = default(PixelFormat); + PixelType = default(PixelType); + } + else + { + (InternalFmt, PixelFormat, PixelType) = OGLEnumConverter.GetImageFormat(NewImage.Format); + } + + GL.BindTexture(TextureTarget.Texture2D, Handle); + + if (Initialized) + { + if (CopyBuffer == 0) { - if (CopyBuffer == 0) - { - CopyBuffer = GL.GenBuffer(); - } - - int MaxWidth = Math.Max(Image.Width, Width); - int MaxHeight = Math.Max(Image.Height, Height); - - int CurrentSize = MaxWidth * MaxHeight * MaxBpp; - - GL.BindBuffer(BufferTarget.PixelPackBuffer, CopyBuffer); - GL.BindBuffer(BufferTarget.PixelUnpackBuffer, CopyBuffer); - - if (CopyBufferSize < CurrentSize) - { - CopyBufferSize = CurrentSize; - - GL.BufferData(BufferTarget.PixelPackBuffer, CurrentSize, IntPtr.Zero, BufferUsageHint.StreamCopy); - } - - GL.GetTexImage(TextureTarget.Texture2D, 0, this.PixelFormat, this.PixelType, IntPtr.Zero); - - GL.DeleteTexture(Handle); - - Handle = GL.GenTexture(); - - GL.BindTexture(TextureTarget.Texture2D, Handle); + CopyBuffer = GL.GenBuffer(); } - const int MinFilter = (int)TextureMinFilter.Linear; - const int MagFilter = (int)TextureMagFilter.Linear; + int CurrentSize = Math.Max(ImageUtils.GetSize(NewImage), + ImageUtils.GetSize(Image)); - GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMinFilter, MinFilter); - GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMagFilter, MagFilter); + GL.BindBuffer(BufferTarget.PixelPackBuffer, CopyBuffer); + GL.BindBuffer(BufferTarget.PixelUnpackBuffer, CopyBuffer); - const int Level = 0; - const int Border = 0; + if (CopyBufferSize < CurrentSize) + { + CopyBufferSize = CurrentSize; + GL.BufferData(BufferTarget.PixelPackBuffer, CurrentSize, IntPtr.Zero, BufferUsageHint.StreamCopy); + } + + if (ImageUtils.IsCompressed(Image.Format)) + { + GL.GetCompressedTexImage(TextureTarget.Texture2D, 0, IntPtr.Zero); + } + else + { + GL.GetTexImage(TextureTarget.Texture2D, 0, this.PixelFormat, this.PixelType, IntPtr.Zero); + } + + GL.DeleteTexture(Handle); + + Handle = GL.GenTexture(); + + GL.BindTexture(TextureTarget.Texture2D, Handle); + } + + const int MinFilter = (int)TextureMinFilter.Linear; + const int MagFilter = (int)TextureMagFilter.Linear; + + GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMinFilter, MinFilter); + GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMagFilter, MagFilter); + + const int Level = 0; + const int Border = 0; + + if (ImageUtils.IsCompressed(NewImage.Format)) + { + Console.WriteLine("Hit"); + + GL.CompressedTexImage2D( + TextureTarget.Texture2D, + Level, + (InternalFormat)InternalFmt, + NewImage.Width, + NewImage.Height, + Border, + ImageUtils.GetSize(NewImage), + IntPtr.Zero); + } + else + { GL.TexImage2D( TextureTarget.Texture2D, Level, - InternalFormat, - Image.Width, - Image.Height, + InternalFmt, + NewImage.Width, + NewImage.Height, Border, PixelFormat, PixelType, IntPtr.Zero); - - if (Initialized) - { - GL.BindBuffer(BufferTarget.PixelPackBuffer, 0); - GL.BindBuffer(BufferTarget.PixelUnpackBuffer, 0); - } - - this.Image = Image; - - this.InternalFormat = InternalFormat; - this.PixelFormat = PixelFormat; - this.PixelType = PixelType; - - Initialized = true; } + + if (Initialized) + { + GL.BindBuffer(BufferTarget.PixelPackBuffer, 0); + GL.BindBuffer(BufferTarget.PixelUnpackBuffer, 0); + } + + Image = NewImage; + + this.InternalFormat = InternalFmt; + this.PixelFormat = PixelFormat; + this.PixelType = PixelType; + + Initialized = true; } - public bool HasColor { get => ImageFormatConverter.HasColor(Format); } - public bool HasDepth { get => ImageFormatConverter.HasDepth(Format); } - public bool HasStencil { get => ImageFormatConverter.HasStencil(Format); } + public bool HasColor => ImageUtils.HasColor(Image.Format); + public bool HasDepth => ImageUtils.HasDepth(Image.Format); + public bool HasStencil => ImageUtils.HasStencil(Image.Format); } } diff --git a/Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs b/Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs index 959d0e329..1d4f4cf77 100644 --- a/Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs +++ b/Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs @@ -129,52 +129,51 @@ namespace Ryujinx.Graphics.Gal.OpenGL { switch (Format) { - case GalImageFormat.R32G32B32A32_SFLOAT: return (PixelInternalFormat.Rgba32f, PixelFormat.Rgba, PixelType.Float); - case GalImageFormat.R32G32B32A32_SINT: return (PixelInternalFormat.Rgba32i, PixelFormat.RgbaInteger, PixelType.Int); - case GalImageFormat.R32G32B32A32_UINT: return (PixelInternalFormat.Rgba32ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt); - case GalImageFormat.R16G16B16A16_SFLOAT: return (PixelInternalFormat.Rgba16f, PixelFormat.Rgba, PixelType.HalfFloat); - case GalImageFormat.R16G16B16A16_SINT: return (PixelInternalFormat.Rgba16i, PixelFormat.RgbaInteger, PixelType.Short); - case GalImageFormat.R16G16B16A16_UINT: return (PixelInternalFormat.Rgba16ui, PixelFormat.RgbaInteger, PixelType.UnsignedShort); - case GalImageFormat.R32G32_SFLOAT: return (PixelInternalFormat.Rg32f, PixelFormat.Rg, PixelType.Float); - case GalImageFormat.R32G32_SINT: return (PixelInternalFormat.Rg32i, PixelFormat.RgInteger, PixelType.Int); - case GalImageFormat.R32G32_UINT: return (PixelInternalFormat.Rg32ui, PixelFormat.RgInteger, PixelType.UnsignedInt); - case GalImageFormat.A8B8G8R8_SNORM_PACK32: return (PixelInternalFormat.Rgba8Snorm, PixelFormat.Rgba, PixelType.Byte); - case GalImageFormat.A8B8G8R8_UNORM_PACK32: return (PixelInternalFormat.Rgba8, PixelFormat.Rgba, PixelType.UnsignedByte); - case GalImageFormat.A8B8G8R8_SINT_PACK32: return (PixelInternalFormat.Rgba8i, PixelFormat.RgbaInteger, PixelType.Byte); - case GalImageFormat.A8B8G8R8_UINT_PACK32: return (PixelInternalFormat.Rgba8ui, PixelFormat.RgbaInteger, PixelType.UnsignedByte); - case GalImageFormat.A8B8G8R8_SRGB_PACK32: return (PixelInternalFormat.Srgb8Alpha8, PixelFormat.Rgba, PixelType.UnsignedByte); - case GalImageFormat.A2B10G10R10_UINT_PACK32: return (PixelInternalFormat.Rgb10A2ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt2101010Reversed); - case GalImageFormat.A2B10G10R10_UNORM_PACK32: return (PixelInternalFormat.Rgb10A2, PixelFormat.Rgba, PixelType.UnsignedInt2101010Reversed); - case GalImageFormat.R32_SFLOAT: return (PixelInternalFormat.R32f, PixelFormat.Red, PixelType.Float); - case GalImageFormat.R32_SINT: return (PixelInternalFormat.R32i, PixelFormat.Red, PixelType.Int); - case GalImageFormat.R32_UINT: return (PixelInternalFormat.R32ui, PixelFormat.Red, PixelType.UnsignedInt); - case GalImageFormat.A1R5G5B5_UNORM_PACK16: return (PixelInternalFormat.Rgb5A1, PixelFormat.Rgba, PixelType.UnsignedShort5551); - case GalImageFormat.B5G6R5_UNORM_PACK16: return (PixelInternalFormat.Rgba, PixelFormat.Rgb, PixelType.UnsignedShort565); - case GalImageFormat.R16G16_SFLOAT: return (PixelInternalFormat.Rg16f, PixelFormat.Rg, PixelType.HalfFloat); - case GalImageFormat.R16G16_SINT: return (PixelInternalFormat.Rg16i, PixelFormat.RgInteger, PixelType.Short); - case GalImageFormat.R16G16_SNORM: return (PixelInternalFormat.Rg16Snorm, PixelFormat.Rg, PixelType.Byte); - case GalImageFormat.R16G16_UNORM: return (PixelInternalFormat.Rg16, PixelFormat.Rg, PixelType.UnsignedShort); - case GalImageFormat.R8G8_SINT: return (PixelInternalFormat.Rg8i, PixelFormat.RgInteger, PixelType.Byte); - case GalImageFormat.R8G8_SNORM: return (PixelInternalFormat.Rg8Snorm, PixelFormat.Rg, PixelType.Byte); - case GalImageFormat.R8G8_UINT: return (PixelInternalFormat.Rg8ui, PixelFormat.RgInteger, PixelType.UnsignedByte); - case GalImageFormat.R8G8_UNORM: return (PixelInternalFormat.Rg8, PixelFormat.Rg, PixelType.UnsignedByte); - case GalImageFormat.R16_SFLOAT: return (PixelInternalFormat.R16f, PixelFormat.Red, PixelType.HalfFloat); - case GalImageFormat.R16_SINT: return (PixelInternalFormat.R16i, PixelFormat.RedInteger, PixelType.Short); - case GalImageFormat.R16_SNORM: return (PixelInternalFormat.R16Snorm, PixelFormat.Red, PixelType.Byte); - case GalImageFormat.R16_UINT: return (PixelInternalFormat.R16ui, PixelFormat.RedInteger, PixelType.UnsignedShort); - case GalImageFormat.R16_UNORM: return (PixelInternalFormat.R16, PixelFormat.Red, PixelType.UnsignedShort); - case GalImageFormat.R8_SINT: return (PixelInternalFormat.R8i, PixelFormat.RedInteger, PixelType.Byte); - case GalImageFormat.R8_SNORM: return (PixelInternalFormat.R8Snorm, PixelFormat.Red, PixelType.Byte); - case GalImageFormat.R8_UINT: return (PixelInternalFormat.R8ui, PixelFormat.RedInteger, PixelType.UnsignedByte); - case GalImageFormat.R8_UNORM: return (PixelInternalFormat.R8, PixelFormat.Red, PixelType.UnsignedByte); - case GalImageFormat.B10G11R11_UFLOAT_PACK32: return (PixelInternalFormat.R11fG11fB10f, PixelFormat.Rgb, PixelType.UnsignedInt10F11F11FRev); + case GalImageFormat.R32G32B32A32 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rgba32f, PixelFormat.Rgba, PixelType.Float); + case GalImageFormat.R32G32B32A32 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba32i, PixelFormat.RgbaInteger, PixelType.Int); + case GalImageFormat.R32G32B32A32 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba32ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt); + case GalImageFormat.R16G16B16A16 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rgba16f, PixelFormat.Rgba, PixelType.HalfFloat); + case GalImageFormat.R16G16B16A16 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba16i, PixelFormat.RgbaInteger, PixelType.Short); + case GalImageFormat.R16G16B16A16 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba16ui, PixelFormat.RgbaInteger, PixelType.UnsignedShort); + case GalImageFormat.R32G32 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rg32f, PixelFormat.Rg, PixelType.Float); + case GalImageFormat.R32G32 | GalImageFormat.Sint: return (PixelInternalFormat.Rg32i, PixelFormat.RgInteger, PixelType.Int); + case GalImageFormat.R32G32 | GalImageFormat.Uint: return (PixelInternalFormat.Rg32ui, PixelFormat.RgInteger, PixelType.UnsignedInt); + case GalImageFormat.A8B8G8R8 | GalImageFormat.Snorm: return (PixelInternalFormat.Rgba8Snorm, PixelFormat.Rgba, PixelType.Byte); + case GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba8, PixelFormat.Rgba, PixelType.UnsignedByte); + case GalImageFormat.A8B8G8R8 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba8i, PixelFormat.RgbaInteger, PixelType.Byte); + case GalImageFormat.A8B8G8R8 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba8ui, PixelFormat.RgbaInteger, PixelType.UnsignedByte); + case GalImageFormat.A8B8G8R8_SRGB: return (PixelInternalFormat.Srgb8Alpha8, PixelFormat.Rgba, PixelType.UnsignedByte); + case GalImageFormat.A4B4G4R4 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba4, PixelFormat.Rgba, PixelType.UnsignedShort4444Reversed); + case GalImageFormat.A2B10G10R10 | GalImageFormat.Uint: return (PixelInternalFormat.Rgb10A2ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt2101010Reversed); + case GalImageFormat.A2B10G10R10 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgb10A2, PixelFormat.Rgba, PixelType.UnsignedInt2101010Reversed); + case GalImageFormat.R32 | GalImageFormat.Sfloat: return (PixelInternalFormat.R32f, PixelFormat.Red, PixelType.Float); + case GalImageFormat.R32 | GalImageFormat.Sint: return (PixelInternalFormat.R32i, PixelFormat.Red, PixelType.Int); + case GalImageFormat.R32 | GalImageFormat.Uint: return (PixelInternalFormat.R32ui, PixelFormat.Red, PixelType.UnsignedInt); + case GalImageFormat.A1R5G5B5 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgb5A1, PixelFormat.Rgba, PixelType.UnsignedShort5551); + case GalImageFormat.B5G6R5 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba, PixelFormat.Rgb, PixelType.UnsignedShort565); + case GalImageFormat.R16G16 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rg16f, PixelFormat.Rg, PixelType.HalfFloat); + case GalImageFormat.R16G16 | GalImageFormat.Sint: return (PixelInternalFormat.Rg16i, PixelFormat.RgInteger, PixelType.Short); + case GalImageFormat.R16G16 | GalImageFormat.Snorm: return (PixelInternalFormat.Rg16Snorm, PixelFormat.Rg, PixelType.Byte); + case GalImageFormat.R16G16 | GalImageFormat.Unorm: return (PixelInternalFormat.Rg16, PixelFormat.Rg, PixelType.UnsignedShort); + case GalImageFormat.R8G8 | GalImageFormat.Sint: return (PixelInternalFormat.Rg8i, PixelFormat.RgInteger, PixelType.Byte); + case GalImageFormat.R8G8 | GalImageFormat.Snorm: return (PixelInternalFormat.Rg8Snorm, PixelFormat.Rg, PixelType.Byte); + case GalImageFormat.R8G8 | GalImageFormat.Uint: return (PixelInternalFormat.Rg8ui, PixelFormat.RgInteger, PixelType.UnsignedByte); + case GalImageFormat.R8G8 | GalImageFormat.Unorm: return (PixelInternalFormat.Rg8, PixelFormat.Rg, PixelType.UnsignedByte); + case GalImageFormat.R16 | GalImageFormat.Sfloat: return (PixelInternalFormat.R16f, PixelFormat.Red, PixelType.HalfFloat); + case GalImageFormat.R16 | GalImageFormat.Sint: return (PixelInternalFormat.R16i, PixelFormat.RedInteger, PixelType.Short); + case GalImageFormat.R16 | GalImageFormat.Snorm: return (PixelInternalFormat.R16Snorm, PixelFormat.Red, PixelType.Byte); + case GalImageFormat.R16 | GalImageFormat.Uint: return (PixelInternalFormat.R16ui, PixelFormat.RedInteger, PixelType.UnsignedShort); + case GalImageFormat.R16 | GalImageFormat.Unorm: return (PixelInternalFormat.R16, PixelFormat.Red, PixelType.UnsignedShort); + case GalImageFormat.R8 | GalImageFormat.Sint: return (PixelInternalFormat.R8i, PixelFormat.RedInteger, PixelType.Byte); + case GalImageFormat.R8 | GalImageFormat.Snorm: return (PixelInternalFormat.R8Snorm, PixelFormat.Red, PixelType.Byte); + case GalImageFormat.R8 | GalImageFormat.Uint: return (PixelInternalFormat.R8ui, PixelFormat.RedInteger, PixelType.UnsignedByte); + case GalImageFormat.R8 | GalImageFormat.Unorm: return (PixelInternalFormat.R8, PixelFormat.Red, PixelType.UnsignedByte); + case GalImageFormat.B10G11R11 | GalImageFormat.Sfloat: return (PixelInternalFormat.R11fG11fB10f, PixelFormat.Rgb, PixelType.UnsignedInt10F11F11FRev); - case GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED: return (PixelInternalFormat.Rgba4, PixelFormat.Rgba, PixelType.UnsignedShort4444Reversed); - - case GalImageFormat.D24_UNORM_S8_UINT: return (PixelInternalFormat.Depth24Stencil8, PixelFormat.DepthStencil, PixelType.UnsignedInt248); - case GalImageFormat.D32_SFLOAT: return (PixelInternalFormat.DepthComponent32f, PixelFormat.DepthComponent, PixelType.Float); - case GalImageFormat.D16_UNORM: return (PixelInternalFormat.DepthComponent16, PixelFormat.DepthComponent, PixelType.UnsignedShort); - case GalImageFormat.D32_SFLOAT_S8_UINT: return (PixelInternalFormat.Depth32fStencil8, PixelFormat.DepthStencil, PixelType.Float32UnsignedInt248Rev); + case GalImageFormat.D24_S8 | GalImageFormat.Unorm: return (PixelInternalFormat.Depth24Stencil8, PixelFormat.DepthStencil, PixelType.UnsignedInt248); + case GalImageFormat.D32 | GalImageFormat.Sfloat: return (PixelInternalFormat.DepthComponent32f, PixelFormat.DepthComponent, PixelType.Float); + case GalImageFormat.D16 | GalImageFormat.Unorm: return (PixelInternalFormat.DepthComponent16, PixelFormat.DepthComponent, PixelType.UnsignedShort); + case GalImageFormat.D32_S8 | GalImageFormat.Uint: return (PixelInternalFormat.Depth32fStencil8, PixelFormat.DepthStencil, PixelType.Float32UnsignedInt248Rev); } throw new NotImplementedException(Format.ToString()); @@ -184,16 +183,16 @@ namespace Ryujinx.Graphics.Gal.OpenGL { switch (Format) { - case GalImageFormat.BC6H_UFLOAT_BLOCK: return InternalFormat.CompressedRgbBptcUnsignedFloat; - case GalImageFormat.BC6H_SFLOAT_BLOCK: return InternalFormat.CompressedRgbBptcSignedFloat; - case GalImageFormat.BC7_UNORM_BLOCK: return InternalFormat.CompressedRgbaBptcUnorm; - case GalImageFormat.BC1_RGBA_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt1Ext; - case GalImageFormat.BC2_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt3Ext; - case GalImageFormat.BC3_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt5Ext; - case GalImageFormat.BC4_SNORM_BLOCK: return InternalFormat.CompressedSignedRedRgtc1; - case GalImageFormat.BC4_UNORM_BLOCK: return InternalFormat.CompressedRedRgtc1; - case GalImageFormat.BC5_SNORM_BLOCK: return InternalFormat.CompressedSignedRgRgtc2; - case GalImageFormat.BC5_UNORM_BLOCK: return InternalFormat.CompressedRgRgtc2; + case GalImageFormat.BC6H_UF16 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbBptcUnsignedFloat; + case GalImageFormat.BC6H_SF16 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbBptcSignedFloat; + case GalImageFormat.BC7 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaBptcUnorm; + case GalImageFormat.BC1_RGBA | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt1Ext; + case GalImageFormat.BC2 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt3Ext; + case GalImageFormat.BC3 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt5Ext; + case GalImageFormat.BC4 | GalImageFormat.Snorm: return InternalFormat.CompressedSignedRedRgtc1; + case GalImageFormat.BC4 | GalImageFormat.Unorm: return InternalFormat.CompressedRedRgtc1; + case GalImageFormat.BC5 | GalImageFormat.Snorm: return InternalFormat.CompressedSignedRgRgtc2; + case GalImageFormat.BC5 | GalImageFormat.Unorm: return InternalFormat.CompressedRgRgtc2; } throw new NotImplementedException(Format.ToString()); diff --git a/Ryujinx.Graphics/Gal/OpenGL/OGLFrameBuffer.cs b/Ryujinx.Graphics/Gal/OpenGL/OGLRenderTarget.cs similarity index 98% rename from Ryujinx.Graphics/Gal/OpenGL/OGLFrameBuffer.cs rename to Ryujinx.Graphics/Gal/OpenGL/OGLRenderTarget.cs index 12239c4f0..99bfa350d 100644 --- a/Ryujinx.Graphics/Gal/OpenGL/OGLFrameBuffer.cs +++ b/Ryujinx.Graphics/Gal/OpenGL/OGLRenderTarget.cs @@ -1,9 +1,10 @@ using OpenTK.Graphics.OpenGL; +using Ryujinx.Graphics.Texture; using System; namespace Ryujinx.Graphics.Gal.OpenGL { - class OGLFrameBuffer : IGalFrameBuffer + class OGLRenderTarget : IGalRenderTarget { private struct Rect { @@ -24,7 +25,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL private const int NativeWidth = 1280; private const int NativeHeight = 720; - private const GalImageFormat RawFormat = GalImageFormat.A8B8G8R8_UNORM_PACK32; + private const GalImageFormat RawFormat = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm; private OGLTexture Texture; @@ -56,7 +57,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL private int DepthAttachment; private int StencilAttachment; - public OGLFrameBuffer(OGLTexture Texture) + public OGLRenderTarget(OGLTexture Texture) { ColorAttachments = new int[8]; @@ -379,7 +380,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL { if (Texture.TryGetImage(Key, out ImageHandler Tex)) { - byte[] Data = new byte[Tex.Width * Tex.Height * ImageHandler.MaxBpp]; + byte[] Data = new byte[ImageUtils.GetSize(Tex.Image)]; GL.BindTexture(TextureTarget.Texture2D, Tex.Handle); diff --git a/Ryujinx.Graphics/Gal/OpenGL/OGLRenderer.cs b/Ryujinx.Graphics/Gal/OpenGL/OGLRenderer.cs index 985f1086f..a23541f3d 100644 --- a/Ryujinx.Graphics/Gal/OpenGL/OGLRenderer.cs +++ b/Ryujinx.Graphics/Gal/OpenGL/OGLRenderer.cs @@ -7,7 +7,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL { public IGalConstBuffer Buffer { get; private set; } - public IGalFrameBuffer FrameBuffer { get; private set; } + public IGalRenderTarget RenderTarget { get; private set; } public IGalRasterizer Rasterizer { get; private set; } @@ -25,7 +25,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL Texture = new OGLTexture(); - FrameBuffer = new OGLFrameBuffer(Texture as OGLTexture); + RenderTarget = new OGLRenderTarget(Texture as OGLTexture); Rasterizer = new OGLRasterizer(); diff --git a/Ryujinx.Graphics/Gal/OpenGL/OGLTexture.cs b/Ryujinx.Graphics/Gal/OpenGL/OGLTexture.cs index e4d4bd648..82f9c9139 100644 --- a/Ryujinx.Graphics/Gal/OpenGL/OGLTexture.cs +++ b/Ryujinx.Graphics/Gal/OpenGL/OGLTexture.cs @@ -1,5 +1,5 @@ using OpenTK.Graphics.OpenGL; -using Ryujinx.Graphics.Gal.Texture; +using Ryujinx.Graphics.Texture; using System; namespace Ryujinx.Graphics.Gal.OpenGL @@ -39,7 +39,11 @@ namespace Ryujinx.Graphics.Gal.OpenGL const int Level = 0; //TODO: Support mipmap textures. const int Border = 0; - if (IsCompressedTextureFormat(Image.Format)) + GalImageFormat TypeLess = Image.Format & GalImageFormat.FormatMask; + + bool IsASTC = TypeLess >= GalImageFormat.ASTC_BEGIN && TypeLess <= GalImageFormat.ASTC_END; + + if (ImageUtils.IsCompressed(Image.Format) && !IsASTC) { InternalFormat InternalFmt = OGLEnumConverter.GetCompressedImageFormat(Image.Format); @@ -55,7 +59,8 @@ namespace Ryujinx.Graphics.Gal.OpenGL } else { - if (Image.Format >= GalImageFormat.ASTC_BEGIN && Image.Format <= GalImageFormat.ASTC_END) + //TODO: Use KHR_texture_compression_astc_hdr when available + if (IsASTC) { int TextureBlockWidth = GetAstcBlockWidth(Image.Format); int TextureBlockHeight = GetAstcBlockHeight(Image.Format); @@ -67,7 +72,17 @@ namespace Ryujinx.Graphics.Gal.OpenGL Image.Width, Image.Height, 1); - Image.Format = GalImageFormat.A8B8G8R8_UNORM_PACK32; + Image.Format = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm; + } + else if (TypeLess == GalImageFormat.G8R8) + { + Data = ImageConverter.G8R8ToR8G8( + Data, + Image.Width, + Image.Height, + 1); + + Image.Format = GalImageFormat.R8G8 | (Image.Format & GalImageFormat.FormatMask); } (PixelInternalFormat InternalFormat, PixelFormat Format, PixelType Type) = OGLEnumConverter.GetImageFormat(Image.Format); @@ -123,20 +138,20 @@ namespace Ryujinx.Graphics.Gal.OpenGL { switch (Format) { - case GalImageFormat.ASTC_4x4_UNORM_BLOCK: return 4; - case GalImageFormat.ASTC_5x5_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_6x6_UNORM_BLOCK: return 6; - case GalImageFormat.ASTC_8x8_UNORM_BLOCK: return 8; - case GalImageFormat.ASTC_10x10_UNORM_BLOCK: return 10; - case GalImageFormat.ASTC_12x12_UNORM_BLOCK: return 12; - case GalImageFormat.ASTC_5x4_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_6x5_UNORM_BLOCK: return 6; - case GalImageFormat.ASTC_8x6_UNORM_BLOCK: return 8; - case GalImageFormat.ASTC_10x8_UNORM_BLOCK: return 10; - case GalImageFormat.ASTC_12x10_UNORM_BLOCK: return 12; - case GalImageFormat.ASTC_8x5_UNORM_BLOCK: return 8; - case GalImageFormat.ASTC_10x5_UNORM_BLOCK: return 10; - case GalImageFormat.ASTC_10x6_UNORM_BLOCK: return 10; + case GalImageFormat.ASTC_4x4 | GalImageFormat.Unorm: return 4; + case GalImageFormat.ASTC_5x5 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_6x6 | GalImageFormat.Unorm: return 6; + case GalImageFormat.ASTC_8x8 | GalImageFormat.Unorm: return 8; + case GalImageFormat.ASTC_10x10 | GalImageFormat.Unorm: return 10; + case GalImageFormat.ASTC_12x12 | GalImageFormat.Unorm: return 12; + case GalImageFormat.ASTC_5x4 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_6x5 | GalImageFormat.Unorm: return 6; + case GalImageFormat.ASTC_8x6 | GalImageFormat.Unorm: return 8; + case GalImageFormat.ASTC_10x8 | GalImageFormat.Unorm: return 10; + case GalImageFormat.ASTC_12x10 | GalImageFormat.Unorm: return 12; + case GalImageFormat.ASTC_8x5 | GalImageFormat.Unorm: return 8; + case GalImageFormat.ASTC_10x5 | GalImageFormat.Unorm: return 10; + case GalImageFormat.ASTC_10x6 | GalImageFormat.Unorm: return 10; } throw new ArgumentException(nameof(Format)); @@ -146,20 +161,20 @@ namespace Ryujinx.Graphics.Gal.OpenGL { switch (Format) { - case GalImageFormat.ASTC_4x4_UNORM_BLOCK: return 4; - case GalImageFormat.ASTC_5x5_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_6x6_UNORM_BLOCK: return 6; - case GalImageFormat.ASTC_8x8_UNORM_BLOCK: return 8; - case GalImageFormat.ASTC_10x10_UNORM_BLOCK: return 10; - case GalImageFormat.ASTC_12x12_UNORM_BLOCK: return 12; - case GalImageFormat.ASTC_5x4_UNORM_BLOCK: return 4; - case GalImageFormat.ASTC_6x5_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_8x6_UNORM_BLOCK: return 6; - case GalImageFormat.ASTC_10x8_UNORM_BLOCK: return 8; - case GalImageFormat.ASTC_12x10_UNORM_BLOCK: return 10; - case GalImageFormat.ASTC_8x5_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_10x5_UNORM_BLOCK: return 5; - case GalImageFormat.ASTC_10x6_UNORM_BLOCK: return 6; + case GalImageFormat.ASTC_4x4 | GalImageFormat.Unorm: return 4; + case GalImageFormat.ASTC_5x5 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_6x6 | GalImageFormat.Unorm: return 6; + case GalImageFormat.ASTC_8x8 | GalImageFormat.Unorm: return 8; + case GalImageFormat.ASTC_10x10 | GalImageFormat.Unorm: return 10; + case GalImageFormat.ASTC_12x12 | GalImageFormat.Unorm: return 12; + case GalImageFormat.ASTC_5x4 | GalImageFormat.Unorm: return 4; + case GalImageFormat.ASTC_6x5 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_8x6 | GalImageFormat.Unorm: return 6; + case GalImageFormat.ASTC_10x8 | GalImageFormat.Unorm: return 8; + case GalImageFormat.ASTC_12x10 | GalImageFormat.Unorm: return 10; + case GalImageFormat.ASTC_8x5 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_10x5 | GalImageFormat.Unorm: return 5; + case GalImageFormat.ASTC_10x6 | GalImageFormat.Unorm: return 6; } throw new ArgumentException(nameof(Format)); @@ -216,25 +231,5 @@ namespace Ryujinx.Graphics.Gal.OpenGL GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureBorderColor, Color); } - - private static bool IsCompressedTextureFormat(GalImageFormat Format) - { - switch (Format) - { - case GalImageFormat.BC6H_UFLOAT_BLOCK: - case GalImageFormat.BC6H_SFLOAT_BLOCK: - case GalImageFormat.BC7_UNORM_BLOCK: - case GalImageFormat.BC1_RGBA_UNORM_BLOCK: - case GalImageFormat.BC2_UNORM_BLOCK: - case GalImageFormat.BC3_UNORM_BLOCK: - case GalImageFormat.BC4_SNORM_BLOCK: - case GalImageFormat.BC4_UNORM_BLOCK: - case GalImageFormat.BC5_SNORM_BLOCK: - case GalImageFormat.BC5_UNORM_BLOCK: - return true; - } - - return false; - } } } diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs index afff7e9b3..c2ee474b1 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs @@ -33,20 +33,20 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Fadd_I32(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperA = GetOperGpr8 (OpCode); - ShaderIrNode OperB = GetOperImmf32_20(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); + ShaderIrNode OperB = OpCode.Immf32_20(); - bool NegB = ((OpCode >> 53) & 1) != 0; - bool AbsA = ((OpCode >> 54) & 1) != 0; - bool NegA = ((OpCode >> 56) & 1) != 0; - bool AbsB = ((OpCode >> 57) & 1) != 0; + bool NegB = OpCode.Read(53); + bool AbsA = OpCode.Read(54); + bool NegA = OpCode.Read(56); + bool AbsB = OpCode.Read(57); OperA = GetAluFabsFneg(OperA, AbsA, NegA); OperB = GetAluFabsFneg(OperB, AbsB, NegB); ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Fadd, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } public static void Fadd_R(ShaderIrBlock Block, long OpCode, long Position) @@ -91,12 +91,12 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Fmul_I32(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperA = GetOperGpr8 (OpCode); - ShaderIrNode OperB = GetOperImmf32_20(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); + ShaderIrNode OperB = OpCode.Immf32_20(); ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Fmul, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } public static void Fmul_C(ShaderIrBlock Block, long OpCode, long Position) @@ -156,16 +156,16 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Iadd_I32(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperA = GetOperGpr8 (OpCode); - ShaderIrNode OperB = GetOperImm32_20(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); + ShaderIrNode OperB = OpCode.Imm32_20(); - bool NegA = ((OpCode >> 56) & 1) != 0; + bool NegA = OpCode.Read(56); OperA = GetAluIneg(OperA, NegA); ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Add, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } public static void Iadd_R(ShaderIrBlock Block, long OpCode, long Position) @@ -205,16 +205,16 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Ipa(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperA = GetOperAbuf28(OpCode); - ShaderIrNode OperB = GetOperGpr20 (OpCode); + ShaderIrNode OperA = OpCode.Abuf28(); + ShaderIrNode OperB = OpCode.Gpr20(); - ShaderIpaMode Mode = (ShaderIpaMode)((OpCode >> 54) & 3); + ShaderIpaMode Mode = (ShaderIpaMode)(OpCode.Read(54, 3)); ShaderIrMetaIpa Meta = new ShaderIrMetaIpa(Mode); ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Ipa, OperA, OperB, null, Meta); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } public static void Iscadd_C(ShaderIrBlock Block, long OpCode, long Position) @@ -264,10 +264,10 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Lop_I32(ShaderIrBlock Block, long OpCode, long Position) { - int SubOp = (int)(OpCode >> 53) & 3; + int SubOp = OpCode.Read(53, 3); - bool InvA = ((OpCode >> 55) & 1) != 0; - bool InvB = ((OpCode >> 56) & 1) != 0; + bool InvA = OpCode.Read(55); + bool InvB = OpCode.Read(56); ShaderIrInst Inst = 0; @@ -278,21 +278,21 @@ namespace Ryujinx.Graphics.Gal.Shader case 2: Inst = ShaderIrInst.Xor; break; } - ShaderIrNode OperB = GetAluNot(GetOperImm32_20(OpCode), InvB); + ShaderIrNode OperB = GetAluNot(OpCode.Imm32_20(), InvB); //SubOp == 3 is pass, used by the not instruction //which just moves the inverted register value. if (SubOp < 3) { - ShaderIrNode OperA = GetAluNot(GetOperGpr8(OpCode), InvA); + ShaderIrNode OperA = GetAluNot(OpCode.Gpr8(), InvA); ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } else { - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperB), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperB))); } } @@ -313,10 +313,10 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Mufu(ShaderIrBlock Block, long OpCode, long Position) { - int SubOp = (int)(OpCode >> 20) & 0xf; + int SubOp = OpCode.Read(20, 0xf); - bool AbsA = ((OpCode >> 46) & 1) != 0; - bool NegA = ((OpCode >> 48) & 1) != 0; + bool AbsA = OpCode.Read(46); + bool NegA = OpCode.Read(48); ShaderIrInst Inst = 0; @@ -333,23 +333,23 @@ namespace Ryujinx.Graphics.Gal.Shader default: throw new NotImplementedException(SubOp.ToString()); } - ShaderIrNode OperA = GetOperGpr8(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); ShaderIrOp Op = new ShaderIrOp(Inst, GetAluFabsFneg(OperA, AbsA, NegA)); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } public static void Psetp(ShaderIrBlock Block, long OpCode, long Position) { - bool NegA = ((OpCode >> 15) & 1) != 0; - bool NegB = ((OpCode >> 32) & 1) != 0; - bool NegP = ((OpCode >> 42) & 1) != 0; + bool NegA = OpCode.Read(15); + bool NegB = OpCode.Read(32); + bool NegP = OpCode.Read(42); - ShaderIrInst LopInst = GetBLop24(OpCode); + ShaderIrInst LopInst = OpCode.BLop24(); - ShaderIrNode OperA = GetOperPred12(OpCode); - ShaderIrNode OperB = GetOperPred29(OpCode); + ShaderIrNode OperA = OpCode.Pred12(); + ShaderIrNode OperB = OpCode.Pred29(); if (NegA) { @@ -363,13 +363,13 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOp Op = new ShaderIrOp(LopInst, OperA, OperB); - ShaderIrOperPred P0Node = GetOperPred3 (OpCode); - ShaderIrOperPred P1Node = GetOperPred0 (OpCode); - ShaderIrOperPred P2Node = GetOperPred39(OpCode); + ShaderIrOperPred P0Node = OpCode.Pred3(); + ShaderIrOperPred P1Node = OpCode.Pred0(); + ShaderIrOperPred P2Node = OpCode.Pred39(); - Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op))); - LopInst = GetBLop45(OpCode); + LopInst = OpCode.BLop45(); if (LopInst == ShaderIrInst.Band && P1Node.IsConst && P2Node.IsConst) { @@ -387,11 +387,11 @@ namespace Ryujinx.Graphics.Gal.Shader Op = new ShaderIrOp(LopInst, Op, P2NNode); - Block.AddNode(GetPredNode(new ShaderIrAsg(P1Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P1Node, Op))); Op = new ShaderIrOp(LopInst, P0Node, P2NNode); - Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op))); } public static void Rro_C(ShaderIrBlock Block, long OpCode, long Position) @@ -441,33 +441,33 @@ namespace Ryujinx.Graphics.Gal.Shader private static ShaderIrInst GetShrInst(long OpCode) { - bool Signed = ((OpCode >> 48) & 1) != 0; + bool Signed = OpCode.Read(48); return Signed ? ShaderIrInst.Asr : ShaderIrInst.Lsr; } public static void Vmad(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperA = GetOperGpr8(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); ShaderIrNode OperB; - if (((OpCode >> 50) & 1) != 0) + if (OpCode.Read(50)) { - OperB = GetOperGpr20(OpCode); + OperB = OpCode.Gpr20(); } else { - OperB = GetOperImm19_20(OpCode); + OperB = OpCode.Imm19_20(); } - ShaderIrOperGpr OperC = GetOperGpr39(OpCode); + ShaderIrOperGpr OperC = OpCode.Gpr39(); ShaderIrNode Tmp = new ShaderIrOp(ShaderIrInst.Mul, OperA, OperB); ShaderIrNode Final = new ShaderIrOp(ShaderIrInst.Add, Tmp, OperC); - int Shr = (int)((OpCode >> 51) & 3); + int Shr = OpCode.Read(51, 3); if (Shr != 0) { @@ -478,7 +478,7 @@ namespace Ryujinx.Graphics.Gal.Shader Block.AddNode(new ShaderIrCmnt("Stubbed. Instruction is reduced to a * b + c")); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Final), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Final))); } public static void Xmad_CR(ShaderIrBlock Block, long OpCode, long Position) @@ -507,20 +507,20 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderOper Oper, ShaderIrInst Inst) { - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } ShaderIrNode Op = new ShaderIrOp(Inst, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitBfe(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -528,23 +528,23 @@ namespace Ryujinx.Graphics.Gal.Shader //TODO: Handle the case where position + length //is greater than the word size, in this case the sign bit //needs to be replicated to fill the remaining space. - bool NegB = ((OpCode >> 48) & 1) != 0; - bool NegA = ((OpCode >> 49) & 1) != 0; + bool NegB = OpCode.Read(48); + bool NegA = OpCode.Read(49); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } ShaderIrNode Op; - bool Signed = ((OpCode >> 48) & 1) != 0; //? + bool Signed = OpCode.Read(48); //? if (OperB is ShaderIrOperImm PosLen) { @@ -576,25 +576,25 @@ namespace Ryujinx.Graphics.Gal.Shader Op = ExtendTo32(Op, Signed, OpLen); } - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitFadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - bool NegB = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 46) & 1) != 0; - bool NegA = ((OpCode >> 48) & 1) != 0; - bool AbsB = ((OpCode >> 49) & 1) != 0; + bool NegB = OpCode.Read(45); + bool AbsA = OpCode.Read(46); + bool NegA = OpCode.Read(48); + bool AbsB = OpCode.Read(49); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; OperA = GetAluFabsFneg(OperA, AbsA, NegA); switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -603,20 +603,20 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fadd, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitFmul(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - bool NegB = ((OpCode >> 48) & 1) != 0; + bool NegB = OpCode.Read(48); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -625,22 +625,22 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fmul, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitFfma(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - bool NegB = ((OpCode >> 48) & 1) != 0; - bool NegC = ((OpCode >> 49) & 1) != 0; + bool NegB = OpCode.Read(48); + bool NegC = OpCode.Read(49); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB, OperC; + ShaderIrNode OperA = OpCode.Gpr8(), OperB, OperC; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RC: OperB = GetOperGpr39 (OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RC: OperB = OpCode.Gpr39(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -649,62 +649,62 @@ namespace Ryujinx.Graphics.Gal.Shader if (Oper == ShaderOper.RC) { - OperC = GetAluFneg(GetOperCbuf34(OpCode), NegC); + OperC = GetAluFneg(OpCode.Cbuf34(), NegC); } else { - OperC = GetAluFneg(GetOperGpr39(OpCode), NegC); + OperC = GetAluFneg(OpCode.Gpr39(), NegC); } ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Ffma, OperA, OperB, OperC); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitIadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - ShaderIrNode OperA = GetOperGpr8(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); ShaderIrNode OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } - bool NegA = ((OpCode >> 49) & 1) != 0; - bool NegB = ((OpCode >> 48) & 1) != 0; + bool NegA = OpCode.Read(49); + bool NegB = OpCode.Read(48); OperA = GetAluIneg(OperA, NegA); OperB = GetAluIneg(OperB, NegB); ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Add, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitIadd3(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - int Mode = (int)((OpCode >> 37) & 3); + int Mode = OpCode.Read(37, 3); - bool Neg1 = ((OpCode >> 51) & 1) != 0; - bool Neg2 = ((OpCode >> 50) & 1) != 0; - bool Neg3 = ((OpCode >> 49) & 1) != 0; + bool Neg1 = OpCode.Read(51); + bool Neg2 = OpCode.Read(50); + bool Neg3 = OpCode.Read(49); - int Height1 = (int)((OpCode >> 35) & 3); - int Height2 = (int)((OpCode >> 33) & 3); - int Height3 = (int)((OpCode >> 31) & 3); + int Height1 = OpCode.Read(35, 3); + int Height2 = OpCode.Read(33, 3); + int Height3 = OpCode.Read(31, 3); ShaderIrNode OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -726,9 +726,9 @@ namespace Ryujinx.Graphics.Gal.Shader } } - ShaderIrNode Src1 = GetAluIneg(ApplyHeight(GetOperGpr8(OpCode), Height1), Neg1); + ShaderIrNode Src1 = GetAluIneg(ApplyHeight(OpCode.Gpr8(), Height1), Neg1); ShaderIrNode Src2 = GetAluIneg(ApplyHeight(OperB, Height2), Neg2); - ShaderIrNode Src3 = GetAluIneg(ApplyHeight(GetOperGpr39(OpCode), Height3), Neg3); + ShaderIrNode Src3 = GetAluIneg(ApplyHeight(OpCode.Gpr39(), Height3), Neg3); ShaderIrOp Sum = new ShaderIrOp(ShaderIrInst.Add, Src1, Src2); @@ -744,23 +744,23 @@ namespace Ryujinx.Graphics.Gal.Shader //Note: Here there should be a "+ 1" when carry flag is set //but since carry is mostly ignored by other instructions, it's excluded for now - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), new ShaderIrOp(ShaderIrInst.Add, Sum, Src3)), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), new ShaderIrOp(ShaderIrInst.Add, Sum, Src3)))); } private static void EmitIscadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - bool NegB = ((OpCode >> 48) & 1) != 0; - bool NegA = ((OpCode >> 49) & 1) != 0; + bool NegB = OpCode.Read(48); + bool NegA = OpCode.Read(49); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; - ShaderIrOperImm Scale = GetOperImm5_39(OpCode); + ShaderIrOperImm Scale = OpCode.Imm5_39(); switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -771,7 +771,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOp ScaleOp = new ShaderIrOp(ShaderIrInst.Lsl, OperA, Scale); ShaderIrOp AddOp = new ShaderIrOp(ShaderIrInst.Add, OperB, ScaleOp); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), AddOp), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), AddOp))); } private static void EmitFmnmx(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -786,12 +786,12 @@ namespace Ryujinx.Graphics.Gal.Shader private static void EmitMnmx(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper) { - bool NegB = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 46) & 1) != 0; - bool NegA = ((OpCode >> 48) & 1) != 0; - bool AbsB = ((OpCode >> 49) & 1) != 0; + bool NegB = OpCode.Read(45); + bool AbsA = OpCode.Read(46); + bool NegA = OpCode.Read(48); + bool AbsB = OpCode.Read(49); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; if (IsFloat) { @@ -804,10 +804,10 @@ namespace Ryujinx.Graphics.Gal.Shader switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -821,7 +821,7 @@ namespace Ryujinx.Graphics.Gal.Shader OperB = GetAluIabsIneg(OperB, AbsB, NegB); } - ShaderIrOperPred Pred = GetOperPred39(OpCode); + ShaderIrOperPred Pred = OpCode.Pred39(); ShaderIrOp Op; @@ -830,26 +830,26 @@ namespace Ryujinx.Graphics.Gal.Shader if (Pred.IsConst) { - bool IsMax = ((OpCode >> 42) & 1) != 0; + bool IsMax = OpCode.Read(42); Op = new ShaderIrOp(IsMax ? MaxInst : MinInst, OperA, OperB); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } else { - ShaderIrNode PredN = GetOperPred39N(OpCode); + ShaderIrNode PredN = OpCode.Pred39N(); ShaderIrOp OpMax = new ShaderIrOp(MaxInst, OperA, OperB); ShaderIrOp OpMin = new ShaderIrOp(MinInst, OperA, OperB); - ShaderIrAsg AsgMax = new ShaderIrAsg(GetOperGpr0(OpCode), OpMax); - ShaderIrAsg AsgMin = new ShaderIrAsg(GetOperGpr0(OpCode), OpMin); + ShaderIrAsg AsgMax = new ShaderIrAsg(OpCode.Gpr0(), OpMax); + ShaderIrAsg AsgMin = new ShaderIrAsg(OpCode.Gpr0(), OpMin); - Block.AddNode(GetPredNode(new ShaderIrCond(PredN, AsgMax, Not: true), OpCode)); - Block.AddNode(GetPredNode(new ShaderIrCond(PredN, AsgMin, Not: false), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrCond(PredN, AsgMax, Not: true))); + Block.AddNode(OpCode.PredNode(new ShaderIrCond(PredN, AsgMin, Not: false))); } } @@ -857,16 +857,16 @@ namespace Ryujinx.Graphics.Gal.Shader { //Note: this is a range reduction instruction and is supposed to //be used with Mufu, here it just moves the value and ignores the operation. - bool NegA = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 49) & 1) != 0; + bool NegA = OpCode.Read(45); + bool AbsA = OpCode.Read(49); ShaderIrNode OperA; switch (Oper) { - case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperA = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperA = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -875,7 +875,7 @@ namespace Ryujinx.Graphics.Gal.Shader Block.AddNode(new ShaderIrCmnt("Stubbed.")); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA))); } private static void EmitFset(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -890,21 +890,21 @@ namespace Ryujinx.Graphics.Gal.Shader private static void EmitSet(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper) { - bool NegA = ((OpCode >> 43) & 1) != 0; - bool AbsB = ((OpCode >> 44) & 1) != 0; - bool NegB = ((OpCode >> 53) & 1) != 0; - bool AbsA = ((OpCode >> 54) & 1) != 0; + bool NegA = OpCode.Read(43); + bool AbsB = OpCode.Read(44); + bool NegB = OpCode.Read(53); + bool AbsA = OpCode.Read(54); - bool BoolFloat = ((OpCode >> (IsFloat ? 52 : 44)) & 1) != 0; + bool BoolFloat = OpCode.Read(IsFloat ? 52 : 44); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -916,18 +916,18 @@ namespace Ryujinx.Graphics.Gal.Shader OperA = GetAluFabsFneg(OperA, AbsA, NegA); OperB = GetAluFabsFneg(OperB, AbsB, NegB); - CmpInst = GetCmpF(OpCode); + CmpInst = OpCode.CmpF(); } else { - CmpInst = GetCmp(OpCode); + CmpInst = OpCode.Cmp(); } ShaderIrOp Op = new ShaderIrOp(CmpInst, OperA, OperB); - ShaderIrInst LopInst = GetBLop45(OpCode); + ShaderIrInst LopInst = OpCode.BLop45(); - ShaderIrOperPred PNode = GetOperPred39(OpCode); + ShaderIrOperPred PNode = OpCode.Pred39(); ShaderIrNode Imm0, Imm1; @@ -942,8 +942,8 @@ namespace Ryujinx.Graphics.Gal.Shader Imm1 = new ShaderIrOperImm(-1); } - ShaderIrNode Asg0 = new ShaderIrAsg(GetOperGpr0(OpCode), Imm0); - ShaderIrNode Asg1 = new ShaderIrAsg(GetOperGpr0(OpCode), Imm1); + ShaderIrNode Asg0 = new ShaderIrAsg(OpCode.Gpr0(), Imm0); + ShaderIrNode Asg1 = new ShaderIrAsg(OpCode.Gpr0(), Imm1); if (LopInst != ShaderIrInst.Band || !PNode.IsConst) { @@ -958,8 +958,8 @@ namespace Ryujinx.Graphics.Gal.Shader Asg1 = new ShaderIrCond(Op, Asg1, Not: false); } - Block.AddNode(GetPredNode(Asg0, OpCode)); - Block.AddNode(GetPredNode(Asg1, OpCode)); + Block.AddNode(OpCode.PredNode(Asg0)); + Block.AddNode(OpCode.PredNode(Asg1)); } private static void EmitFsetp(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -974,19 +974,19 @@ namespace Ryujinx.Graphics.Gal.Shader private static void EmitSetp(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper) { - bool AbsA = ((OpCode >> 7) & 1) != 0; - bool NegP = ((OpCode >> 42) & 1) != 0; - bool NegA = ((OpCode >> 43) & 1) != 0; - bool AbsB = ((OpCode >> 44) & 1) != 0; + bool AbsA = OpCode.Read(7); + bool NegP = OpCode.Read(42); + bool NegA = OpCode.Read(43); + bool AbsB = OpCode.Read(44); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB; + ShaderIrNode OperA = OpCode.Gpr8(), OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break; - case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -998,22 +998,22 @@ namespace Ryujinx.Graphics.Gal.Shader OperA = GetAluFabsFneg(OperA, AbsA, NegA); OperB = GetAluFabs (OperB, AbsB); - CmpInst = GetCmpF(OpCode); + CmpInst = OpCode.CmpF(); } else { - CmpInst = GetCmp(OpCode); + CmpInst = OpCode.Cmp(); } ShaderIrOp Op = new ShaderIrOp(CmpInst, OperA, OperB); - ShaderIrOperPred P0Node = GetOperPred3 (OpCode); - ShaderIrOperPred P1Node = GetOperPred0 (OpCode); - ShaderIrOperPred P2Node = GetOperPred39(OpCode); + ShaderIrOperPred P0Node = OpCode.Pred3(); + ShaderIrOperPred P1Node = OpCode.Pred0(); + ShaderIrOperPred P2Node = OpCode.Pred39(); - Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op))); - ShaderIrInst LopInst = GetBLop45(OpCode); + ShaderIrInst LopInst = OpCode.BLop45(); if (LopInst == ShaderIrInst.Band && P1Node.IsConst && P2Node.IsConst) { @@ -1031,19 +1031,19 @@ namespace Ryujinx.Graphics.Gal.Shader Op = new ShaderIrOp(LopInst, Op, P2NNode); - Block.AddNode(GetPredNode(new ShaderIrAsg(P1Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P1Node, Op))); Op = new ShaderIrOp(LopInst, P0Node, P2NNode); - Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op))); } private static void EmitLop(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - int SubOp = (int)(OpCode >> 41) & 3; + int SubOp = OpCode.Read(41, 3); - bool InvA = ((OpCode >> 39) & 1) != 0; - bool InvB = ((OpCode >> 40) & 1) != 0; + bool InvA = OpCode.Read(39); + bool InvB = OpCode.Read(40); ShaderIrInst Inst = 0; @@ -1054,14 +1054,14 @@ namespace Ryujinx.Graphics.Gal.Shader case 2: Inst = ShaderIrInst.Xor; break; } - ShaderIrNode OperA = GetAluNot(GetOperGpr8(OpCode), InvA); + ShaderIrNode OperA = GetAluNot(OpCode.Gpr8(), InvA); ShaderIrNode OperB; switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -1081,23 +1081,23 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrNode Compare = new ShaderIrOp(ShaderIrInst.Cne, Op, new ShaderIrOperImm(0)); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperPred48(OpCode), Compare), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Pred48(), Compare))); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitXmad(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { //TODO: Confirm SignAB/C, it is just a guess. //TODO: Implement Mode 3 (CSFU), what it does? - bool SignAB = ((OpCode >> 48) & 1) != 0; - bool SignC = ((OpCode >> 49) & 1) != 0; - bool HighB = ((OpCode >> 52) & 1) != 0; - bool HighA = ((OpCode >> 53) & 1) != 0; + bool SignAB = OpCode.Read(48); + bool SignC = OpCode.Read(49); + bool HighB = OpCode.Read(52); + bool HighA = OpCode.Read(53); - int Mode = (int)(OpCode >> 50) & 7; + int Mode = OpCode.Read(50, 7); - ShaderIrNode OperA = GetOperGpr8(OpCode), OperB, OperC; + ShaderIrNode OperA = OpCode.Gpr8(), OperB, OperC; ShaderIrOperImm Imm16 = new ShaderIrOperImm(16); ShaderIrOperImm ImmMsk = new ShaderIrOperImm(0xffff); @@ -1112,10 +1112,10 @@ namespace Ryujinx.Graphics.Gal.Shader switch (Oper) { - case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break; - case ShaderOper.RC: OperB = GetOperGpr39 (OpCode); break; - case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break; + case ShaderOper.RC: OperB = OpCode.Gpr39(); break; + case ShaderOper.RR: OperB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -1124,14 +1124,14 @@ namespace Ryujinx.Graphics.Gal.Shader if (Oper == ShaderOper.RC) { - OperC = GetOperCbuf34(OpCode); + OperC = OpCode.Cbuf34(); } else { - OperC = GetOperGpr39(OpCode); + OperC = OpCode.Gpr39(); - ProductShiftLeft = ((OpCode >> 36) & 1) != 0; - Merge = ((OpCode >> 37) & 1) != 0; + ProductShiftLeft = OpCode.Read(36); + Merge = OpCode.Read(37); } switch (Mode) @@ -1172,7 +1172,7 @@ namespace Ryujinx.Graphics.Gal.Shader AddOp = new ShaderIrOp(ShaderIrInst.Or, AddOp, OperB); } - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), AddOp), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), AddOp))); } } } \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeFlow.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeFlow.cs index 2c699a1b8..dfd10e002 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeFlow.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeFlow.cs @@ -15,11 +15,11 @@ namespace Ryujinx.Graphics.Gal.Shader throw new NotImplementedException(); } - int Target = ((int)(OpCode >> 20) << 8) >> 8; + int Target = OpCode.Branch(); ShaderIrOperImm Imm = new ShaderIrOperImm(Target); - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Bra, Imm), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Bra, Imm))); } public static void Exit(ShaderIrBlock Block, long OpCode, long Position) @@ -29,14 +29,14 @@ namespace Ryujinx.Graphics.Gal.Shader //TODO: Figure out what the other condition codes mean... if (CCode == 0xf) { - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Exit), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Exit))); } } public static void Kil(ShaderIrBlock Block, long OpCode, long Position) { - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Kil), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Kil))); } public static void Ssy(ShaderIrBlock Block, long OpCode, long Position) @@ -48,7 +48,7 @@ namespace Ryujinx.Graphics.Gal.Shader throw new NotImplementedException(); } - int Offset = ((int)(OpCode >> 20) << 8) >> 8; + int Offset = OpCode.Branch(); int Target = (int)(Position + Offset); @@ -61,7 +61,7 @@ namespace Ryujinx.Graphics.Gal.Shader { //TODO: Implement Sync condition codes - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Sync), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Sync))); } } } \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeHelper.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeHelper.cs index 2093f0706..010f06aa6 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeHelper.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeHelper.cs @@ -4,244 +4,6 @@ namespace Ryujinx.Graphics.Gal.Shader { static class ShaderDecodeHelper { - public static ShaderIrOperAbuf[] GetOperAbuf20(long OpCode) - { - int Abuf = (int)(OpCode >> 20) & 0x3ff; - int Size = (int)(OpCode >> 47) & 3; - - ShaderIrOperGpr Vertex = GetOperGpr39(OpCode); - - ShaderIrOperAbuf[] Opers = new ShaderIrOperAbuf[Size + 1]; - - for (int Index = 0; Index <= Size; Index++) - { - Opers[Index] = new ShaderIrOperAbuf(Abuf + Index * 4, Vertex); - } - - return Opers; - } - - public static ShaderIrOperAbuf GetOperAbuf28(long OpCode) - { - int Abuf = (int)(OpCode >> 28) & 0x3ff; - - return new ShaderIrOperAbuf(Abuf, GetOperGpr39(OpCode)); - } - - public static ShaderIrOperCbuf GetOperCbuf34(long OpCode) - { - return new ShaderIrOperCbuf( - (int)(OpCode >> 34) & 0x1f, - (int)(OpCode >> 20) & 0x3fff); - } - - public static ShaderIrOperGpr GetOperGpr8(long OpCode) - { - return new ShaderIrOperGpr((int)(OpCode >> 8) & 0xff); - } - - public static ShaderIrOperGpr GetOperGpr20(long OpCode) - { - return new ShaderIrOperGpr((int)(OpCode >> 20) & 0xff); - } - - public static ShaderIrOperGpr GetOperGpr39(long OpCode) - { - return new ShaderIrOperGpr((int)(OpCode >> 39) & 0xff); - } - - public static ShaderIrOperGpr GetOperGpr0(long OpCode) - { - return new ShaderIrOperGpr((int)(OpCode >> 0) & 0xff); - } - - public static ShaderIrOperGpr GetOperGpr28(long OpCode) - { - return new ShaderIrOperGpr((int)(OpCode >> 28) & 0xff); - } - - public static ShaderIrOperImm GetOperImm5_39(long OpCode) - { - return new ShaderIrOperImm((int)(OpCode >> 39) & 0x1f); - } - - public static ShaderIrOperImm GetOperImm13_36(long OpCode) - { - return new ShaderIrOperImm((int)(OpCode >> 36) & 0x1fff); - } - - public static ShaderIrOperImm GetOperImm32_20(long OpCode) - { - return new ShaderIrOperImm((int)(OpCode >> 20)); - } - - public static ShaderIrOperImmf GetOperImmf32_20(long OpCode) - { - return new ShaderIrOperImmf(BitConverter.Int32BitsToSingle((int)(OpCode >> 20))); - } - - public static ShaderIrOperImm GetOperImm19_20(long OpCode) - { - int Value = (int)(OpCode >> 20) & 0x7ffff; - - bool Neg = ((OpCode >> 56) & 1) != 0; - - if (Neg) - { - Value = -Value; - } - - return new ShaderIrOperImm((int)Value); - } - - public static ShaderIrOperImmf GetOperImmf19_20(long OpCode) - { - uint Imm = (uint)(OpCode >> 20) & 0x7ffff; - - bool Neg = ((OpCode >> 56) & 1) != 0; - - Imm <<= 12; - - if (Neg) - { - Imm |= 0x80000000; - } - - float Value = BitConverter.Int32BitsToSingle((int)Imm); - - return new ShaderIrOperImmf(Value); - } - - public static ShaderIrOperPred GetOperPred0(long OpCode) - { - return new ShaderIrOperPred((int)(OpCode >> 0) & 7); - } - - public static ShaderIrOperPred GetOperPred3(long OpCode) - { - return new ShaderIrOperPred((int)(OpCode >> 3) & 7); - } - - public static ShaderIrOperPred GetOperPred12(long OpCode) - { - return new ShaderIrOperPred((int)(OpCode >> 12) & 7); - } - - public static ShaderIrOperPred GetOperPred29(long OpCode) - { - return new ShaderIrOperPred((int)(OpCode >> 29) & 7); - } - - public static ShaderIrNode GetOperPred39N(long OpCode) - { - ShaderIrNode Node = GetOperPred39(OpCode); - - if (((OpCode >> 42) & 1) != 0) - { - Node = new ShaderIrOp(ShaderIrInst.Bnot, Node); - } - - return Node; - } - - public static ShaderIrOperPred GetOperPred39(long OpCode) - { - return new ShaderIrOperPred((int)(OpCode >> 39) & 7); - } - - public static ShaderIrOperPred GetOperPred48(long OpCode) - { - return new ShaderIrOperPred((int)((OpCode >> 48) & 7)); - } - - public static ShaderIrInst GetCmp(long OpCode) - { - switch ((int)(OpCode >> 49) & 7) - { - case 1: return ShaderIrInst.Clt; - case 2: return ShaderIrInst.Ceq; - case 3: return ShaderIrInst.Cle; - case 4: return ShaderIrInst.Cgt; - case 5: return ShaderIrInst.Cne; - case 6: return ShaderIrInst.Cge; - } - - throw new ArgumentException(nameof(OpCode)); - } - - public static ShaderIrInst GetCmpF(long OpCode) - { - switch ((int)(OpCode >> 48) & 0xf) - { - case 0x1: return ShaderIrInst.Fclt; - case 0x2: return ShaderIrInst.Fceq; - case 0x3: return ShaderIrInst.Fcle; - case 0x4: return ShaderIrInst.Fcgt; - case 0x5: return ShaderIrInst.Fcne; - case 0x6: return ShaderIrInst.Fcge; - case 0x7: return ShaderIrInst.Fcnum; - case 0x8: return ShaderIrInst.Fcnan; - case 0x9: return ShaderIrInst.Fcltu; - case 0xa: return ShaderIrInst.Fcequ; - case 0xb: return ShaderIrInst.Fcleu; - case 0xc: return ShaderIrInst.Fcgtu; - case 0xd: return ShaderIrInst.Fcneu; - case 0xe: return ShaderIrInst.Fcgeu; - } - - throw new ArgumentException(nameof(OpCode)); - } - - public static ShaderIrInst GetBLop45(long OpCode) - { - switch ((int)(OpCode >> 45) & 3) - { - case 0: return ShaderIrInst.Band; - case 1: return ShaderIrInst.Bor; - case 2: return ShaderIrInst.Bxor; - } - - throw new ArgumentException(nameof(OpCode)); - } - - public static ShaderIrInst GetBLop24(long OpCode) - { - switch ((int)(OpCode >> 24) & 3) - { - case 0: return ShaderIrInst.Band; - case 1: return ShaderIrInst.Bor; - case 2: return ShaderIrInst.Bxor; - } - - throw new ArgumentException(nameof(OpCode)); - } - - public static ShaderIrNode GetPredNode(ShaderIrNode Node, long OpCode) - { - ShaderIrOperPred Pred = GetPredNode(OpCode); - - if (Pred.Index != ShaderIrOperPred.UnusedIndex) - { - bool Inv = ((OpCode >> 19) & 1) != 0; - - Node = new ShaderIrCond(Pred, Node, Inv); - } - - return Node; - } - - private static ShaderIrOperPred GetPredNode(long OpCode) - { - int Pred = (int)(OpCode >> 16) & 0xf; - - if (Pred != 0xf) - { - Pred &= 7; - } - - return new ShaderIrOperPred(Pred); - } - public static ShaderIrNode GetAluFabsFneg(ShaderIrNode Node, bool Abs, bool Neg) { return GetAluFneg(GetAluFabs(Node, Abs), Neg); diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMem.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMem.cs index 2ae58bf89..508a0205d 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMem.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMem.cs @@ -33,28 +33,28 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Ld_A(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode[] Opers = GetOperAbuf20(OpCode); + ShaderIrNode[] Opers = OpCode.Abuf20(); //Used by GS - ShaderIrOperGpr Vertex = GetOperGpr39(OpCode); + ShaderIrOperGpr Vertex = OpCode.Gpr39(); int Index = 0; foreach (ShaderIrNode OperA in Opers) { - ShaderIrOperGpr OperD = GetOperGpr0(OpCode); + ShaderIrOperGpr OperD = OpCode.Gpr0(); OperD.Index += Index++; - Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, OperA), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, OperA))); } } public static void Ld_C(ShaderIrBlock Block, long OpCode, long Position) { - int CbufPos = (int)(OpCode >> 22) & 0x3fff; - int CbufIndex = (int)(OpCode >> 36) & 0x1f; - int Type = (int)(OpCode >> 48) & 7; + int CbufPos = OpCode.Read(22, 0x3fff); + int CbufIndex = OpCode.Read(36, 0x1f); + int Type = OpCode.Read(48, 7); if (Type > 5) { @@ -63,7 +63,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOperGpr Temp = ShaderIrOperGpr.MakeTemporary(); - Block.AddNode(new ShaderIrAsg(Temp, GetOperGpr8(OpCode))); + Block.AddNode(new ShaderIrAsg(Temp, OpCode.Gpr8())); int Count = Type == 5 ? 2 : 1; @@ -71,7 +71,7 @@ namespace Ryujinx.Graphics.Gal.Shader { ShaderIrOperCbuf OperA = new ShaderIrOperCbuf(CbufIndex, CbufPos, Temp); - ShaderIrOperGpr OperD = GetOperGpr0(OpCode); + ShaderIrOperGpr OperD = OpCode.Gpr0(); OperA.Pos += Index; OperD.Index += Index; @@ -93,43 +93,43 @@ namespace Ryujinx.Graphics.Gal.Shader Node = ExtendTo32(Node, Signed, Size); } - Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, Node), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Node))); } } public static void St_A(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode[] Opers = GetOperAbuf20(OpCode); + ShaderIrNode[] Opers = OpCode.Abuf20(); int Index = 0; foreach (ShaderIrNode OperA in Opers) { - ShaderIrOperGpr OperD = GetOperGpr0(OpCode); + ShaderIrOperGpr OperD = OpCode.Gpr0(); OperD.Index += Index++; - Block.AddNode(GetPredNode(new ShaderIrAsg(OperA, OperD), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, OperD))); } } public static void Texq(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrNode OperD = GetOperGpr0(OpCode); - ShaderIrNode OperA = GetOperGpr8(OpCode); + ShaderIrNode OperD = OpCode.Gpr0(); + ShaderIrNode OperA = OpCode.Gpr8(); - ShaderTexqInfo Info = (ShaderTexqInfo)((OpCode >> 22) & 0x1f); + ShaderTexqInfo Info = (ShaderTexqInfo)(OpCode.Read(22, 0x1f)); ShaderIrMetaTexq Meta0 = new ShaderIrMetaTexq(Info, 0); ShaderIrMetaTexq Meta1 = new ShaderIrMetaTexq(Info, 1); - ShaderIrNode OperC = GetOperImm13_36(OpCode); + ShaderIrNode OperC = OpCode.Imm13_36(); ShaderIrOp Op0 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta0); ShaderIrOp Op1 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta1); - Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, Op0), OpCode)); - Block.AddNode(GetPredNode(new ShaderIrAsg(OperA, Op1), OpCode)); //Is this right? + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Op0))); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, Op1))); //Is this right? } public static void Tex(ShaderIrBlock Block, long OpCode, long Position) @@ -149,7 +149,7 @@ namespace Ryujinx.Graphics.Gal.Shader for (int Index = 0; Index < Coords.Length; Index++) { - Coords[Index] = GetOperGpr8(OpCode); + Coords[Index] = OpCode.Gpr8(); Coords[Index].Index += Index; @@ -159,11 +159,11 @@ namespace Ryujinx.Graphics.Gal.Shader } } - int ChMask = (int)(OpCode >> 31) & 0xf; + int ChMask = OpCode.Read(31, 0xf); ShaderIrNode OperC = GprHandle - ? (ShaderIrNode)GetOperGpr20 (OpCode) - : (ShaderIrNode)GetOperImm13_36(OpCode); + ? (ShaderIrNode)OpCode.Gpr20() + : (ShaderIrNode)OpCode.Imm13_36(); ShaderIrInst Inst = GprHandle ? ShaderIrInst.Texb : ShaderIrInst.Texs; @@ -175,7 +175,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOp Op = new ShaderIrOp(Inst, Coords[0], Coords[1], OperC, Meta); - Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op))); } int RegInc = 0; @@ -189,7 +189,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch); - ShaderIrOperGpr Dst = GetOperGpr0(OpCode); + ShaderIrOperGpr Dst = OpCode.Gpr0(); Dst.Index += RegInc++; @@ -198,7 +198,7 @@ namespace Ryujinx.Graphics.Gal.Shader continue; } - Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src))); } } @@ -215,14 +215,14 @@ namespace Ryujinx.Graphics.Gal.Shader private static void EmitTexs(ShaderIrBlock Block, long OpCode, ShaderIrInst Inst) { //TODO: Support other formats. - ShaderIrNode OperA = GetOperGpr8 (OpCode); - ShaderIrNode OperB = GetOperGpr20 (OpCode); - ShaderIrNode OperC = GetOperImm13_36(OpCode); + ShaderIrNode OperA = OpCode.Gpr8(); + ShaderIrNode OperB = OpCode.Gpr20(); + ShaderIrNode OperC = OpCode.Imm13_36(); int LutIndex; - LutIndex = GetOperGpr0 (OpCode).Index != ShaderIrOperGpr.ZRIndex ? 1 : 0; - LutIndex |= GetOperGpr28(OpCode).Index != ShaderIrOperGpr.ZRIndex ? 2 : 0; + LutIndex = OpCode.Gpr0 ().Index != ShaderIrOperGpr.ZRIndex ? 1 : 0; + LutIndex |= OpCode.Gpr28().Index != ShaderIrOperGpr.ZRIndex ? 2 : 0; if (LutIndex == 0) { @@ -231,7 +231,7 @@ namespace Ryujinx.Graphics.Gal.Shader return; } - int ChMask = MaskLut[LutIndex, (OpCode >> 50) & 7]; + int ChMask = MaskLut[LutIndex, OpCode.Read(50, 7)]; for (int Ch = 0; Ch < 4; Ch++) { @@ -241,7 +241,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB, OperC, Meta); - Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op))); } int RegInc = 0; @@ -252,11 +252,11 @@ namespace Ryujinx.Graphics.Gal.Shader switch (LutIndex) { - case 1: Dst = GetOperGpr0 (OpCode); break; - case 2: Dst = GetOperGpr28(OpCode); break; + case 1: Dst = OpCode.Gpr0(); break; + case 2: Dst = OpCode.Gpr28(); break; case 3: Dst = (RegInc >> 1) != 0 - ? GetOperGpr28(OpCode) - : GetOperGpr0 (OpCode); break; + ? OpCode.Gpr28() + : OpCode.Gpr0 (); break; default: throw new InvalidOperationException(); } @@ -279,7 +279,7 @@ namespace Ryujinx.Graphics.Gal.Shader if (Dst.Index != ShaderIrOperGpr.ZRIndex) { - Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src))); } } } diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMove.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMove.cs index aef92c5a9..add394027 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMove.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeMove.cs @@ -92,35 +92,35 @@ namespace Ryujinx.Graphics.Gal.Shader Block.AddNode(new ShaderIrCmnt("Stubbed.")); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), GetOperGpr8(OpCode)), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OpCode.Gpr8()))); } public static void Mov_C(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrOperCbuf Cbuf = GetOperCbuf34(OpCode); + ShaderIrOperCbuf Cbuf = OpCode.Cbuf34(); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Cbuf), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Cbuf))); } public static void Mov_I(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrOperImm Imm = GetOperImm19_20(OpCode); + ShaderIrOperImm Imm = OpCode.Imm19_20(); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Imm), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Imm))); } public static void Mov_I32(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrOperImm Imm = GetOperImm32_20(OpCode); + ShaderIrOperImm Imm = OpCode.Imm32_20(); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Imm), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Imm))); } public static void Mov_R(ShaderIrBlock Block, long OpCode, long Position) { - ShaderIrOperGpr Gpr = GetOperGpr20(OpCode); + ShaderIrOperGpr Gpr = OpCode.Gpr20(); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Gpr), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Gpr))); } public static void Sel_C(ShaderIrBlock Block, long OpCode, long Position) @@ -145,21 +145,21 @@ namespace Ryujinx.Graphics.Gal.Shader //Zero is used as a special number to get a valid "0 * 0 + VertexIndex" in a GS ShaderIrNode Source = new ShaderIrOperImm(0); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Source), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Source))); } private static void EmitF2f(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - bool NegA = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 49) & 1) != 0; + bool NegA = OpCode.Read(45); + bool AbsA = OpCode.Read(49); ShaderIrNode OperA; switch (Oper) { - case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperA = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperA = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -173,7 +173,7 @@ namespace Ryujinx.Graphics.Gal.Shader OperA = new ShaderIrOp(RoundInst, OperA); } - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA))); } private static void EmitF2i(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -188,16 +188,16 @@ namespace Ryujinx.Graphics.Gal.Shader throw new NotImplementedException(); } - bool NegA = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 49) & 1) != 0; + bool NegA = OpCode.Read(45); + bool AbsA = OpCode.Read(49); ShaderIrNode OperA; switch (Oper) { - case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperA = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperA = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -242,7 +242,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrNode Op = new ShaderIrOp(Inst, OperA); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitI2f(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -257,18 +257,18 @@ namespace Ryujinx.Graphics.Gal.Shader throw new NotImplementedException(); } - int Sel = (int)(OpCode >> 41) & 3; + int Sel = OpCode.Read(41, 3); - bool NegA = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 49) & 1) != 0; + bool NegA = OpCode.Read(45); + bool AbsA = OpCode.Read(49); ShaderIrNode OperA; switch (Oper) { - case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: OperA = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperA = OpCode.Cbuf34(); break; + case ShaderOper.Imm: OperA = OpCode.Imm19_20(); break; + case ShaderOper.RR: OperA = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -297,7 +297,7 @@ namespace Ryujinx.Graphics.Gal.Shader ShaderIrNode Op = new ShaderIrOp(Inst, OperA); - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op))); } private static void EmitI2i(ShaderIrBlock Block, long OpCode, ShaderOper Oper) @@ -312,19 +312,19 @@ namespace Ryujinx.Graphics.Gal.Shader throw new NotImplementedException(); } - int Sel = (int)(OpCode >> 41) & 3; + int Sel = OpCode.Read(41, 3); - bool NegA = ((OpCode >> 45) & 1) != 0; - bool AbsA = ((OpCode >> 49) & 1) != 0; - bool SatA = ((OpCode >> 50) & 1) != 0; + bool NegA = OpCode.Read(45); + bool AbsA = OpCode.Read(49); + bool SatA = OpCode.Read(50); ShaderIrNode OperA; switch (Oper) { - case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break; - case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break; - case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: OperA = OpCode.Cbuf34(); break; + case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break; + case ShaderOper.RR: OperA = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } @@ -372,36 +372,36 @@ namespace Ryujinx.Graphics.Gal.Shader } } - Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA))); } private static void EmitSel(ShaderIrBlock Block, long OpCode, ShaderOper Oper) { - ShaderIrOperGpr Dst = GetOperGpr0 (OpCode); - ShaderIrNode Pred = GetOperPred39N(OpCode); + ShaderIrOperGpr Dst = OpCode.Gpr0(); + ShaderIrNode Pred = OpCode.Pred39N(); - ShaderIrNode ResultA = GetOperGpr8(OpCode); + ShaderIrNode ResultA = OpCode.Gpr8(); ShaderIrNode ResultB; switch (Oper) { - case ShaderOper.CR: ResultB = GetOperCbuf34 (OpCode); break; - case ShaderOper.Imm: ResultB = GetOperImm19_20(OpCode); break; - case ShaderOper.RR: ResultB = GetOperGpr20 (OpCode); break; + case ShaderOper.CR: ResultB = OpCode.Cbuf34(); break; + case ShaderOper.Imm: ResultB = OpCode.Imm19_20(); break; + case ShaderOper.RR: ResultB = OpCode.Gpr20(); break; default: throw new ArgumentException(nameof(Oper)); } - Block.AddNode(GetPredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultA), false), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultA), false))); - Block.AddNode(GetPredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultB), true), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultB), true))); } private static IntType GetIntType(long OpCode) { - bool Signed = ((OpCode >> 13) & 1) != 0; + bool Signed = OpCode.Read(13); - IntType Type = (IntType)((OpCode >> 10) & 3); + IntType Type = (IntType)(OpCode.Read(10, 3)); if (Signed) { @@ -413,12 +413,12 @@ namespace Ryujinx.Graphics.Gal.Shader private static FloatType GetFloatType(long OpCode) { - return (FloatType)((OpCode >> 8) & 3); + return (FloatType)(OpCode.Read(8, 3)); } private static ShaderIrInst GetRoundInst(long OpCode) { - switch ((OpCode >> 39) & 3) + switch (OpCode.Read(39, 3)) { case 1: return ShaderIrInst.Floor; case 2: return ShaderIrInst.Ceil; diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeOpCode.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeOpCode.cs new file mode 100644 index 000000000..3af17cae8 --- /dev/null +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeOpCode.cs @@ -0,0 +1,260 @@ +using System; + +namespace Ryujinx.Graphics.Gal.Shader +{ + static partial class ShaderDecode + { + private static int Read(this long OpCode, int Position, int Mask) + { + return (int)(OpCode >> Position) & Mask; + } + + private static bool Read(this long OpCode, int Position) + { + return ((OpCode >> Position) & 1) != 0; + } + + private static int Branch(this long OpCode) + { + return ((int)(OpCode >> 20) << 8) >> 8; + } + + private static ShaderIrOperAbuf[] Abuf20(this long OpCode) + { + int Abuf = OpCode.Read(20, 0x3ff); + int Size = OpCode.Read(47, 3); + + ShaderIrOperGpr Vertex = OpCode.Gpr39(); + + ShaderIrOperAbuf[] Opers = new ShaderIrOperAbuf[Size + 1]; + + for (int Index = 0; Index <= Size; Index++) + { + Opers[Index] = new ShaderIrOperAbuf(Abuf + Index * 4, Vertex); + } + + return Opers; + } + + private static ShaderIrOperAbuf Abuf28(this long OpCode) + { + int Abuf = OpCode.Read(28, 0x3ff); + + return new ShaderIrOperAbuf(Abuf, OpCode.Gpr39()); + } + + private static ShaderIrOperCbuf Cbuf34(this long OpCode) + { + return new ShaderIrOperCbuf( + OpCode.Read(34, 0x1f), + OpCode.Read(20, 0x3fff)); + } + + private static ShaderIrOperGpr Gpr8(this long OpCode) + { + return new ShaderIrOperGpr(OpCode.Read(8, 0xff)); + } + + private static ShaderIrOperGpr Gpr20(this long OpCode) + { + return new ShaderIrOperGpr(OpCode.Read(20, 0xff)); + } + + private static ShaderIrOperGpr Gpr39(this long OpCode) + { + return new ShaderIrOperGpr(OpCode.Read(39, 0xff)); + } + + private static ShaderIrOperGpr Gpr0(this long OpCode) + { + return new ShaderIrOperGpr(OpCode.Read(0, 0xff)); + } + + private static ShaderIrOperGpr Gpr28(this long OpCode) + { + return new ShaderIrOperGpr(OpCode.Read(28, 0xff)); + } + + private static ShaderIrOperImm Imm5_39(this long OpCode) + { + return new ShaderIrOperImm(OpCode.Read(39, 0x1f)); + } + + private static ShaderIrOperImm Imm13_36(this long OpCode) + { + return new ShaderIrOperImm(OpCode.Read(36, 0x1fff)); + } + + private static ShaderIrOperImm Imm32_20(this long OpCode) + { + return new ShaderIrOperImm((int)(OpCode >> 20)); + } + + private static ShaderIrOperImmf Immf32_20(this long OpCode) + { + return new ShaderIrOperImmf(BitConverter.Int32BitsToSingle((int)(OpCode >> 20))); + } + + private static ShaderIrOperImm Imm19_20(this long OpCode) + { + int Value = OpCode.Read(20, 0x7ffff); + + bool Neg = OpCode.Read(56); + + if (Neg) + { + Value = -Value; + } + + return new ShaderIrOperImm(Value); + } + + private static ShaderIrOperImmf Immf19_20(this long OpCode) + { + uint Imm = (uint)(OpCode >> 20) & 0x7ffff; + + bool Neg = OpCode.Read(56); + + Imm <<= 12; + + if (Neg) + { + Imm |= 0x80000000; + } + + float Value = BitConverter.Int32BitsToSingle((int)Imm); + + return new ShaderIrOperImmf(Value); + } + + private static ShaderIrOperPred Pred0(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(0, 7)); + } + + private static ShaderIrOperPred Pred3(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(3, 7)); + } + + private static ShaderIrOperPred Pred12(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(12, 7)); + } + + private static ShaderIrOperPred Pred29(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(29, 7)); + } + + private static ShaderIrNode Pred39N(this long OpCode) + { + ShaderIrNode Node = OpCode.Pred39(); + + if (OpCode.Read(42)) + { + Node = new ShaderIrOp(ShaderIrInst.Bnot, Node); + } + + return Node; + } + + private static ShaderIrOperPred Pred39(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(39, 7)); + } + + private static ShaderIrOperPred Pred48(this long OpCode) + { + return new ShaderIrOperPred(OpCode.Read(48, 7)); + } + + private static ShaderIrInst Cmp(this long OpCode) + { + switch (OpCode.Read(49, 7)) + { + case 1: return ShaderIrInst.Clt; + case 2: return ShaderIrInst.Ceq; + case 3: return ShaderIrInst.Cle; + case 4: return ShaderIrInst.Cgt; + case 5: return ShaderIrInst.Cne; + case 6: return ShaderIrInst.Cge; + } + + throw new ArgumentException(nameof(OpCode)); + } + + private static ShaderIrInst CmpF(this long OpCode) + { + switch (OpCode.Read(48, 0xf)) + { + case 0x1: return ShaderIrInst.Fclt; + case 0x2: return ShaderIrInst.Fceq; + case 0x3: return ShaderIrInst.Fcle; + case 0x4: return ShaderIrInst.Fcgt; + case 0x5: return ShaderIrInst.Fcne; + case 0x6: return ShaderIrInst.Fcge; + case 0x7: return ShaderIrInst.Fcnum; + case 0x8: return ShaderIrInst.Fcnan; + case 0x9: return ShaderIrInst.Fcltu; + case 0xa: return ShaderIrInst.Fcequ; + case 0xb: return ShaderIrInst.Fcleu; + case 0xc: return ShaderIrInst.Fcgtu; + case 0xd: return ShaderIrInst.Fcneu; + case 0xe: return ShaderIrInst.Fcgeu; + } + + throw new ArgumentException(nameof(OpCode)); + } + + private static ShaderIrInst BLop45(this long OpCode) + { + switch (OpCode.Read(45, 3)) + { + case 0: return ShaderIrInst.Band; + case 1: return ShaderIrInst.Bor; + case 2: return ShaderIrInst.Bxor; + } + + throw new ArgumentException(nameof(OpCode)); + } + + private static ShaderIrInst BLop24(this long OpCode) + { + switch (OpCode.Read(24, 3)) + { + case 0: return ShaderIrInst.Band; + case 1: return ShaderIrInst.Bor; + case 2: return ShaderIrInst.Bxor; + } + + throw new ArgumentException(nameof(OpCode)); + } + + private static ShaderIrNode PredNode(this long OpCode, ShaderIrNode Node) + { + ShaderIrOperPred Pred = OpCode.PredNode(); + + if (Pred.Index != ShaderIrOperPred.UnusedIndex) + { + bool Inv = OpCode.Read(19); + + Node = new ShaderIrCond(Pred, Node, Inv); + } + + return Node; + } + + private static ShaderIrOperPred PredNode(this long OpCode) + { + int Pred = OpCode.Read(16, 0xf); + + if (Pred != 0xf) + { + Pred &= 7; + } + + return new ShaderIrOperPred(Pred); + } + } +} \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeSpecial.cs b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeSpecial.cs index 4300c32e3..c3e42654a 100644 --- a/Ryujinx.Graphics/Gal/Shader/ShaderDecodeSpecial.cs +++ b/Ryujinx.Graphics/Gal/Shader/ShaderDecodeSpecial.cs @@ -7,20 +7,20 @@ namespace Ryujinx.Graphics.Gal.Shader public static void Out_R(ShaderIrBlock Block, long OpCode, long Position) { //TODO: Those registers have to be used for something - ShaderIrOperGpr Gpr0 = GetOperGpr0(OpCode); - ShaderIrOperGpr Gpr8 = GetOperGpr8(OpCode); - ShaderIrOperGpr Gpr20 = GetOperGpr20(OpCode); + ShaderIrOperGpr Gpr0 = OpCode.Gpr0(); + ShaderIrOperGpr Gpr8 = OpCode.Gpr8(); + ShaderIrOperGpr Gpr20 = OpCode.Gpr20(); - int Type = (int)((OpCode >> 39) & 3); + int Type = OpCode.Read(39, 3); if ((Type & 1) != 0) { - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Emit), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Emit))); } if ((Type & 2) != 0) { - Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Cut), OpCode)); + Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Cut))); } } } diff --git a/Ryujinx.HLE/Gpu/Engines/INvGpuEngine.cs b/Ryujinx.Graphics/INvGpuEngine.cs similarity index 68% rename from Ryujinx.HLE/Gpu/Engines/INvGpuEngine.cs rename to Ryujinx.Graphics/INvGpuEngine.cs index 068878a98..810303b9f 100644 --- a/Ryujinx.HLE/Gpu/Engines/INvGpuEngine.cs +++ b/Ryujinx.Graphics/INvGpuEngine.cs @@ -1,6 +1,6 @@ -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { interface INvGpuEngine { diff --git a/Ryujinx.HLE/Gpu/Engines/MacroInterpreter.cs b/Ryujinx.Graphics/MacroInterpreter.cs similarity index 99% rename from Ryujinx.HLE/Gpu/Engines/MacroInterpreter.cs rename to Ryujinx.Graphics/MacroInterpreter.cs index 423e20213..20e7895b4 100644 --- a/Ryujinx.HLE/Gpu/Engines/MacroInterpreter.cs +++ b/Ryujinx.Graphics/MacroInterpreter.cs @@ -1,8 +1,8 @@ -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using System; using System.Collections.Generic; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { class MacroInterpreter { diff --git a/Ryujinx.HLE/Gpu/Memory/NvGpuBufferType.cs b/Ryujinx.Graphics/Memory/NvGpuBufferType.cs similarity index 59% rename from Ryujinx.HLE/Gpu/Memory/NvGpuBufferType.cs rename to Ryujinx.Graphics/Memory/NvGpuBufferType.cs index a6c03f425..6f0d25718 100644 --- a/Ryujinx.HLE/Gpu/Memory/NvGpuBufferType.cs +++ b/Ryujinx.Graphics/Memory/NvGpuBufferType.cs @@ -1,6 +1,6 @@ -namespace Ryujinx.HLE.Gpu.Memory +namespace Ryujinx.Graphics.Memory { - enum NvGpuBufferType + public enum NvGpuBufferType { Index, Vertex, diff --git a/Ryujinx.HLE/Gpu/Memory/NvGpuPBEntry.cs b/Ryujinx.Graphics/Memory/NvGpuPBEntry.cs similarity index 88% rename from Ryujinx.HLE/Gpu/Memory/NvGpuPBEntry.cs rename to Ryujinx.Graphics/Memory/NvGpuPBEntry.cs index aba89e3c9..6b93c1699 100644 --- a/Ryujinx.HLE/Gpu/Memory/NvGpuPBEntry.cs +++ b/Ryujinx.Graphics/Memory/NvGpuPBEntry.cs @@ -1,9 +1,9 @@ using System; using System.Collections.ObjectModel; -namespace Ryujinx.HLE.Gpu.Memory +namespace Ryujinx.Graphics.Memory { - struct NvGpuPBEntry + public struct NvGpuPBEntry { public int Method { get; private set; } diff --git a/Ryujinx.HLE/Gpu/Memory/NvGpuPushBuffer.cs b/Ryujinx.Graphics/Memory/NvGpuPushBuffer.cs similarity index 97% rename from Ryujinx.HLE/Gpu/Memory/NvGpuPushBuffer.cs rename to Ryujinx.Graphics/Memory/NvGpuPushBuffer.cs index 6121b3e61..0902ebfc9 100644 --- a/Ryujinx.HLE/Gpu/Memory/NvGpuPushBuffer.cs +++ b/Ryujinx.Graphics/Memory/NvGpuPushBuffer.cs @@ -1,9 +1,9 @@ using System.Collections.Generic; using System.IO; -namespace Ryujinx.HLE.Gpu.Memory +namespace Ryujinx.Graphics.Memory { - static class NvGpuPushBuffer + public static class NvGpuPushBuffer { private enum SubmissionMode { diff --git a/Ryujinx.HLE/Gpu/Memory/NvGpuVmm.cs b/Ryujinx.Graphics/Memory/NvGpuVmm.cs similarity index 99% rename from Ryujinx.HLE/Gpu/Memory/NvGpuVmm.cs rename to Ryujinx.Graphics/Memory/NvGpuVmm.cs index e7e180646..0082fb275 100644 --- a/Ryujinx.HLE/Gpu/Memory/NvGpuVmm.cs +++ b/Ryujinx.Graphics/Memory/NvGpuVmm.cs @@ -2,9 +2,9 @@ using ChocolArm64.Memory; using Ryujinx.Graphics.Gal; using System; -namespace Ryujinx.HLE.Gpu.Memory +namespace Ryujinx.Graphics.Memory { - class NvGpuVmm : IAMemory, IGalMemory + public class NvGpuVmm : IAMemory, IGalMemory { public const long AddrSize = 1L << 40; diff --git a/Ryujinx.HLE/Gpu/Memory/NvGpuVmmCache.cs b/Ryujinx.Graphics/Memory/NvGpuVmmCache.cs similarity index 97% rename from Ryujinx.HLE/Gpu/Memory/NvGpuVmmCache.cs rename to Ryujinx.Graphics/Memory/NvGpuVmmCache.cs index b3f253b3e..56979e1f0 100644 --- a/Ryujinx.HLE/Gpu/Memory/NvGpuVmmCache.cs +++ b/Ryujinx.Graphics/Memory/NvGpuVmmCache.cs @@ -1,12 +1,13 @@ using ChocolArm64.Memory; -using Ryujinx.HLE.Memory; using System; using System.Collections.Generic; -namespace Ryujinx.HLE.Gpu.Memory +namespace Ryujinx.Graphics.Memory { class NvGpuVmmCache { + private const long RamSize = 4L * 1024 * 1024 * 1024; + private const int MaxCpCount = 10000; private const int MaxCpTimeDelta = 60000; @@ -226,7 +227,7 @@ namespace Ryujinx.HLE.Gpu.Memory { if (Residency == null) { - Residency = new HashSet[DeviceMemory.RamSize / PageSize]; + Residency = new HashSet[RamSize / PageSize]; for (int i = 0; i < Residency.Length; i++) { diff --git a/Ryujinx.HLE/Gpu/NvGpu.cs b/Ryujinx.Graphics/NvGpu.cs similarity index 89% rename from Ryujinx.HLE/Gpu/NvGpu.cs rename to Ryujinx.Graphics/NvGpu.cs index 625cb727f..7ba700b89 100644 --- a/Ryujinx.HLE/Gpu/NvGpu.cs +++ b/Ryujinx.Graphics/NvGpu.cs @@ -1,9 +1,9 @@ using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Engines; +using Ryujinx.Graphics; -namespace Ryujinx.HLE.Gpu +namespace Ryujinx.Graphics { - class NvGpu + public class NvGpu { public IGalRenderer Renderer { get; private set; } diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine.cs b/Ryujinx.Graphics/NvGpuEngine.cs similarity index 82% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngine.cs rename to Ryujinx.Graphics/NvGpuEngine.cs index f9d6342cf..3d5e118a5 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine.cs +++ b/Ryujinx.Graphics/NvGpuEngine.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { enum NvGpuEngine { diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine2d.cs b/Ryujinx.Graphics/NvGpuEngine2d.cs similarity index 93% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngine2d.cs rename to Ryujinx.Graphics/NvGpuEngine2d.cs index 7fb5ea8af..f26b00204 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine2d.cs +++ b/Ryujinx.Graphics/NvGpuEngine2d.cs @@ -1,12 +1,12 @@ using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Memory; -using Ryujinx.HLE.Gpu.Texture; +using Ryujinx.Graphics.Memory; +using Ryujinx.Graphics.Texture; using System; using System.Collections.Generic; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { - class NvGpuEngine2d : INvGpuEngine + public class NvGpuEngine2d : INvGpuEngine { private enum CopyOperation { @@ -103,7 +103,7 @@ namespace Ryujinx.HLE.Gpu.Engines SrcPitch, SrcBlockHeight, 1, SrcSwizzle, - GalTextureFormat.A8B8G8R8); + GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm); } TextureInfo DstTexture() @@ -115,7 +115,7 @@ namespace Ryujinx.HLE.Gpu.Engines DstPitch, DstBlockHeight, 1, DstSwizzle, - GalTextureFormat.A8B8G8R8); + GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm); } //TODO: fb -> fb copies, tex -> fb copies, formats other than RGBA8, @@ -123,7 +123,7 @@ namespace Ryujinx.HLE.Gpu.Engines if (IsSrcFb && IsDstFb) { //Frame Buffer -> Frame Buffer copy. - Gpu.Renderer.FrameBuffer.Copy( + Gpu.Renderer.RenderTarget.Copy( SrcKey, DstKey, 0, @@ -138,7 +138,7 @@ namespace Ryujinx.HLE.Gpu.Engines if (IsSrcFb) { //Frame Buffer -> Texture copy. - Gpu.Renderer.FrameBuffer.GetBufferData(SrcKey, (byte[] Buffer) => + Gpu.Renderer.RenderTarget.GetBufferData(SrcKey, (byte[] Buffer) => { TextureInfo Src = SrcTexture(); TextureInfo Dst = DstTexture(); @@ -156,7 +156,7 @@ namespace Ryujinx.HLE.Gpu.Engines { byte[] Buffer = TextureReader.Read(Vmm, SrcTexture()); - Gpu.Renderer.FrameBuffer.SetBufferData( + Gpu.Renderer.RenderTarget.SetBufferData( DstKey, DstWidth, DstHeight, diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine2dReg.cs b/Ryujinx.Graphics/NvGpuEngine2dReg.cs similarity index 95% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngine2dReg.cs rename to Ryujinx.Graphics/NvGpuEngine2dReg.cs index 29d66d463..00f6f578d 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine2dReg.cs +++ b/Ryujinx.Graphics/NvGpuEngine2dReg.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { enum NvGpuEngine2dReg { diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine3d.cs b/Ryujinx.Graphics/NvGpuEngine3d.cs similarity index 96% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngine3d.cs rename to Ryujinx.Graphics/NvGpuEngine3d.cs index 0d2f3befd..624eddae0 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine3d.cs +++ b/Ryujinx.Graphics/NvGpuEngine3d.cs @@ -1,12 +1,12 @@ using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Memory; -using Ryujinx.HLE.Gpu.Texture; +using Ryujinx.Graphics.Memory; +using Ryujinx.Graphics.Texture; using System; using System.Collections.Generic; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { - class NvGpuEngine3d : INvGpuEngine + public class NvGpuEngine3d : INvGpuEngine { public int[] Registers { get; private set; } @@ -158,6 +158,7 @@ namespace Ryujinx.HLE.Gpu.Engines int Stencil = ReadRegister(NvGpuEngine3dReg.ClearStencil); SetFrameBuffer(Vmm, FbIndex); + SetZeta(Vmm); Gpu.Renderer.Rasterizer.ClearBuffers( @@ -176,7 +177,7 @@ namespace Ryujinx.HLE.Gpu.Engines if (VA == 0 || Format == 0) { - Gpu.Renderer.FrameBuffer.UnbindColor(FbIndex); + Gpu.Renderer.RenderTarget.UnbindColor(FbIndex); return; } @@ -200,16 +201,17 @@ namespace Ryujinx.HLE.Gpu.Engines int VpW = (int)(TX + MathF.Abs(SX)) - VpX; int VpH = (int)(TY + MathF.Abs(SY)) - VpY; - GalImageFormat ImageFormat = ImageFormatConverter.ConvertFrameBuffer((GalFrameBufferFormat)Format); + GalImageFormat ImageFormat = ImageUtils.ConvertSurface((GalSurfaceFormat)Format); GalImage Image = new GalImage(Width, Height, ImageFormat); - long Size = TextureHelper.GetTextureSize(Image); + long Size = ImageUtils.GetSize(Image); Gpu.Renderer.Texture.CreateFb(Key, Size, Image); - Gpu.Renderer.FrameBuffer.BindColor(Key, FbIndex); - Gpu.Renderer.FrameBuffer.SetViewport(VpX, VpY, VpW, VpH); + Gpu.Renderer.RenderTarget.BindColor(Key, FbIndex); + + Gpu.Renderer.RenderTarget.SetViewport(VpX, VpY, VpW, VpH); } private void SetZeta(NvGpuVmm Vmm) @@ -222,7 +224,7 @@ namespace Ryujinx.HLE.Gpu.Engines if (ZA == 0 || Format == 0 || !ZetaEnable) { - Gpu.Renderer.FrameBuffer.UnbindZeta(); + Gpu.Renderer.RenderTarget.UnbindZeta(); return; } @@ -232,14 +234,15 @@ namespace Ryujinx.HLE.Gpu.Engines int Width = ReadRegister(NvGpuEngine3dReg.ZetaHoriz); int Height = ReadRegister(NvGpuEngine3dReg.ZetaVert); - GalImageFormat ImageFormat = ImageFormatConverter.ConvertZeta((GalZetaFormat)Format); + GalImageFormat ImageFormat = ImageUtils.ConvertZeta((GalZetaFormat)Format); GalImage Image = new GalImage(Width, Height, ImageFormat); - long Size = TextureHelper.GetTextureSize(Image); + long Size = ImageUtils.GetSize(Image); Gpu.Renderer.Texture.CreateFb(Key, Size, Image); - Gpu.Renderer.FrameBuffer.BindZeta(Key); + + Gpu.Renderer.RenderTarget.BindZeta(Key); } private long[] UploadShaders(NvGpuVmm Vmm) @@ -441,11 +444,11 @@ namespace Ryujinx.HLE.Gpu.Engines Map[i] = (int)((Control >> Shift) & 7); } - Gpu.Renderer.FrameBuffer.SetMap(Map); + Gpu.Renderer.RenderTarget.SetMap(Map); } else { - Gpu.Renderer.FrameBuffer.SetMap(null); + Gpu.Renderer.RenderTarget.SetMap(null); } } @@ -519,13 +522,13 @@ namespace Ryujinx.HLE.Gpu.Engines //we shouldn't read anything from memory and bind //the frame buffer texture instead, since we're not //really writing anything to memory. - Gpu.Renderer.FrameBuffer.BindTexture(Key, TexIndex); + Gpu.Renderer.RenderTarget.BindTexture(Key, TexIndex); } else { GalImage NewImage = TextureFactory.MakeTexture(Vmm, TicPosition); - long Size = (uint)TextureHelper.GetTextureSize(NewImage); + long Size = (uint)ImageUtils.GetSize(NewImage); bool HasCachedTexture = false; diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine3dReg.cs b/Ryujinx.Graphics/NvGpuEngine3dReg.cs similarity index 99% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngine3dReg.cs rename to Ryujinx.Graphics/NvGpuEngine3dReg.cs index ace324e91..f96e71150 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngine3dReg.cs +++ b/Ryujinx.Graphics/NvGpuEngine3dReg.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { enum NvGpuEngine3dReg { diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngineDma.cs b/Ryujinx.Graphics/NvGpuEngineDma.cs similarity index 96% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngineDma.cs rename to Ryujinx.Graphics/NvGpuEngineDma.cs index 7e355e8de..04be742f8 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngineDma.cs +++ b/Ryujinx.Graphics/NvGpuEngineDma.cs @@ -1,10 +1,10 @@ -using Ryujinx.HLE.Gpu.Memory; -using Ryujinx.HLE.Gpu.Texture; +using Ryujinx.Graphics.Memory; +using Ryujinx.Graphics.Texture; using System.Collections.Generic; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { - class NvGpuEngineDma : INvGpuEngine + public class NvGpuEngineDma : INvGpuEngine { public int[] Registers { get; private set; } diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuEngineDmaReg.cs b/Ryujinx.Graphics/NvGpuEngineDmaReg.cs similarity index 93% rename from Ryujinx.HLE/Gpu/Engines/NvGpuEngineDmaReg.cs rename to Ryujinx.Graphics/NvGpuEngineDmaReg.cs index 835a822d1..b0fa1fbf3 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuEngineDmaReg.cs +++ b/Ryujinx.Graphics/NvGpuEngineDmaReg.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { enum NvGpuEngineDmaReg { diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuFifo.cs b/Ryujinx.Graphics/NvGpuFifo.cs similarity index 98% rename from Ryujinx.HLE/Gpu/Engines/NvGpuFifo.cs rename to Ryujinx.Graphics/NvGpuFifo.cs index 0e6266548..3b79a055e 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuFifo.cs +++ b/Ryujinx.Graphics/NvGpuFifo.cs @@ -1,10 +1,10 @@ -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using System.Collections.Concurrent; using System.Threading; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { - class NvGpuFifo + public class NvGpuFifo { private const int MacrosCount = 0x80; private const int MacroIndexMask = MacrosCount - 1; diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuFifoMeth.cs b/Ryujinx.Graphics/NvGpuFifoMeth.cs similarity index 86% rename from Ryujinx.HLE/Gpu/Engines/NvGpuFifoMeth.cs rename to Ryujinx.Graphics/NvGpuFifoMeth.cs index ffd179f26..c5cb6e942 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuFifoMeth.cs +++ b/Ryujinx.Graphics/NvGpuFifoMeth.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { enum NvGpuFifoMeth { diff --git a/Ryujinx.HLE/Gpu/Engines/NvGpuMethod.cs b/Ryujinx.Graphics/NvGpuMethod.cs similarity index 52% rename from Ryujinx.HLE/Gpu/Engines/NvGpuMethod.cs rename to Ryujinx.Graphics/NvGpuMethod.cs index 04c92f2a9..5babf2c32 100644 --- a/Ryujinx.HLE/Gpu/Engines/NvGpuMethod.cs +++ b/Ryujinx.Graphics/NvGpuMethod.cs @@ -1,6 +1,6 @@ -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; -namespace Ryujinx.HLE.Gpu.Engines +namespace Ryujinx.Graphics { delegate void NvGpuMethod(NvGpuVmm Vmm, NvGpuPBEntry PBEntry); } \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/Texture/ASTCDecoder.cs b/Ryujinx.Graphics/Texture/ASTCDecoder.cs similarity index 97% rename from Ryujinx.Graphics/Gal/Texture/ASTCDecoder.cs rename to Ryujinx.Graphics/Texture/ASTCDecoder.cs index da1b9ef41..1efa02552 100644 --- a/Ryujinx.Graphics/Gal/Texture/ASTCDecoder.cs +++ b/Ryujinx.Graphics/Texture/ASTCDecoder.cs @@ -1,1384 +1,1384 @@ -using System; -using System.Collections; -using System.Collections.Generic; -using System.Diagnostics; -using System.IO; - -namespace Ryujinx.Graphics.Gal.Texture -{ - public class ASTCDecoderException : Exception - { - public ASTCDecoderException(string ExMsg) : base(ExMsg) { } - } - - //https://github.com/GammaUNC/FasTC/blob/master/ASTCEncoder/src/Decompressor.cpp - public static class ASTCDecoder - { - struct TexelWeightParams - { - public int Width; - public int Height; - public bool DualPlane; - public int MaxWeight; - public bool Error; - public bool VoidExtentLDR; - public bool VoidExtentHDR; - - public int GetPackedBitSize() - { - // How many indices do we have? - int Indices = Height * Width; - - if (DualPlane) - { - Indices *= 2; - } - - IntegerEncoded IntEncoded = IntegerEncoded.CreateEncoding(MaxWeight); - - return IntEncoded.GetBitLength(Indices); - } - - public int GetNumWeightValues() - { - int Ret = Width * Height; - - if (DualPlane) - { - Ret *= 2; - } - - return Ret; - } - } - - public static byte[] DecodeToRGBA8888( - byte[] InputBuffer, - int BlockX, - int BlockY, - int BlockZ, - int X, - int Y, - int Z) - { - using (MemoryStream InputStream = new MemoryStream(InputBuffer)) - { - BinaryReader BinReader = new BinaryReader(InputStream); - - if (BlockX > 12 || BlockY > 12) - { - throw new ASTCDecoderException("Block size unsupported!"); - } - - if (BlockZ != 1 || Z != 1) - { - throw new ASTCDecoderException("3D compressed textures unsupported!"); - } - - using (MemoryStream OutputStream = new MemoryStream()) - { - int BlockIndex = 0; - - for (int j = 0; j < Y; j += BlockY) - { - for (int i = 0; i < X; i += BlockX) - { - int[] DecompressedData = new int[144]; - - DecompressBlock(BinReader.ReadBytes(0x10), DecompressedData, BlockX, BlockY); - - int DecompressedWidth = Math.Min(BlockX, X - i); - int DecompressedHeight = Math.Min(BlockY, Y - j); - int BaseOffsets = (j * X + i) * 4; - - for (int jj = 0; jj < DecompressedHeight; jj++) - { - OutputStream.Seek(BaseOffsets + jj * X * 4, SeekOrigin.Begin); - - byte[] OutputBuffer = new byte[DecompressedData.Length * sizeof(int)]; - Buffer.BlockCopy(DecompressedData, 0, OutputBuffer, 0, OutputBuffer.Length); - - OutputStream.Write(OutputBuffer, jj * BlockX * 4, DecompressedWidth * 4); - } - - BlockIndex++; - } - } - - return OutputStream.ToArray(); - } - } - } - - public static bool DecompressBlock( - byte[] InputBuffer, - int[] OutputBuffer, - int BlockWidth, - int BlockHeight) - { - BitArrayStream BitStream = new BitArrayStream(new BitArray(InputBuffer)); - TexelWeightParams TexelParams = DecodeBlockInfo(BitStream); - - if (TexelParams.Error) - { - throw new ASTCDecoderException("Invalid block mode"); - } - - if (TexelParams.VoidExtentLDR) - { - FillVoidExtentLDR(BitStream, OutputBuffer, BlockWidth, BlockHeight); - - return true; - } - - if (TexelParams.VoidExtentHDR) - { - throw new ASTCDecoderException("HDR void extent blocks are unsupported!"); - } - - if (TexelParams.Width > BlockWidth) - { - throw new ASTCDecoderException("Texel weight grid width should be smaller than block width"); - } - - if (TexelParams.Height > BlockHeight) - { - throw new ASTCDecoderException("Texel weight grid height should be smaller than block height"); - } - - // Read num partitions - int NumberPartitions = BitStream.ReadBits(2) + 1; - Debug.Assert(NumberPartitions <= 4); - - if (NumberPartitions == 4 && TexelParams.DualPlane) - { - throw new ASTCDecoderException("Dual plane mode is incompatible with four partition blocks"); - } - - // Based on the number of partitions, read the color endpoint mode for - // each partition. - - // Determine partitions, partition index, and color endpoint modes - int PlaneIndices = -1; - int PartitionIndex; - uint[] ColorEndpointMode = { 0, 0, 0, 0 }; - - BitArrayStream ColorEndpointStream = new BitArrayStream(new BitArray(16 * 8)); - - // Read extra config data... - uint BaseColorEndpointMode = 0; - - if (NumberPartitions == 1) - { - ColorEndpointMode[0] = (uint)BitStream.ReadBits(4); - PartitionIndex = 0; - } - else - { - PartitionIndex = BitStream.ReadBits(10); - BaseColorEndpointMode = (uint)BitStream.ReadBits(6); - } - - uint BaseMode = (BaseColorEndpointMode & 3); - - // Remaining bits are color endpoint data... - int NumberWeightBits = TexelParams.GetPackedBitSize(); - int RemainingBits = 128 - NumberWeightBits - BitStream.Position; - - // Consider extra bits prior to texel data... - uint ExtraColorEndpointModeBits = 0; - - if (BaseMode != 0) - { - switch (NumberPartitions) - { - case 2: ExtraColorEndpointModeBits += 2; break; - case 3: ExtraColorEndpointModeBits += 5; break; - case 4: ExtraColorEndpointModeBits += 8; break; - default: Debug.Assert(false); break; - } - } - - RemainingBits -= (int)ExtraColorEndpointModeBits; - - // Do we have a dual plane situation? - int PlaneSelectorBits = 0; - - if (TexelParams.DualPlane) - { - PlaneSelectorBits = 2; - } - - RemainingBits -= PlaneSelectorBits; - - // Read color data... - int ColorDataBits = RemainingBits; - - while (RemainingBits > 0) - { - int NumberBits = Math.Min(RemainingBits, 8); - int Bits = BitStream.ReadBits(NumberBits); - ColorEndpointStream.WriteBits(Bits, NumberBits); - RemainingBits -= 8; - } - - // Read the plane selection bits - PlaneIndices = BitStream.ReadBits(PlaneSelectorBits); - - // Read the rest of the CEM - if (BaseMode != 0) - { - uint ExtraColorEndpointMode = (uint)BitStream.ReadBits((int)ExtraColorEndpointModeBits); - uint TempColorEndpointMode = (ExtraColorEndpointMode << 6) | BaseColorEndpointMode; - TempColorEndpointMode >>= 2; - - bool[] C = new bool[4]; - - for (int i = 0; i < NumberPartitions; i++) - { - C[i] = (TempColorEndpointMode & 1) != 0; - TempColorEndpointMode >>= 1; - } - - byte[] M = new byte[4]; - - for (int i = 0; i < NumberPartitions; i++) - { - M[i] = (byte)(TempColorEndpointMode & 3); - TempColorEndpointMode >>= 2; - Debug.Assert(M[i] <= 3); - } - - for (int i = 0; i < NumberPartitions; i++) - { - ColorEndpointMode[i] = BaseMode; - if (!(C[i])) ColorEndpointMode[i] -= 1; - ColorEndpointMode[i] <<= 2; - ColorEndpointMode[i] |= M[i]; - } - } - else if (NumberPartitions > 1) - { - uint TempColorEndpointMode = BaseColorEndpointMode >> 2; - - for (uint i = 0; i < NumberPartitions; i++) - { - ColorEndpointMode[i] = TempColorEndpointMode; - } - } - - // Make sure everything up till here is sane. - for (int i = 0; i < NumberPartitions; i++) - { - Debug.Assert(ColorEndpointMode[i] < 16); - } - Debug.Assert(BitStream.Position + TexelParams.GetPackedBitSize() == 128); - - // Decode both color data and texel weight data - int[] ColorValues = new int[32]; // Four values * two endpoints * four maximum partitions - DecodeColorValues(ColorValues, ColorEndpointStream.ToByteArray(), ColorEndpointMode, NumberPartitions, ColorDataBits); - - ASTCPixel[][] EndPoints = new ASTCPixel[4][]; - EndPoints[0] = new ASTCPixel[2]; - EndPoints[1] = new ASTCPixel[2]; - EndPoints[2] = new ASTCPixel[2]; - EndPoints[3] = new ASTCPixel[2]; - - int ColorValuesPosition = 0; - - for (int i = 0; i < NumberPartitions; i++) - { - ComputeEndpoints(EndPoints[i], ColorValues, ColorEndpointMode[i], ref ColorValuesPosition); - } - - // Read the texel weight data. - byte[] TexelWeightData = (byte[])InputBuffer.Clone(); - - // Reverse everything - for (int i = 0; i < 8; i++) - { - byte a = ReverseByte(TexelWeightData[i]); - byte b = ReverseByte(TexelWeightData[15 - i]); - - TexelWeightData[i] = b; - TexelWeightData[15 - i] = a; - } - - // Make sure that higher non-texel bits are set to zero - int ClearByteStart = (TexelParams.GetPackedBitSize() >> 3) + 1; - TexelWeightData[ClearByteStart - 1] &= (byte)((1 << (TexelParams.GetPackedBitSize() % 8)) - 1); - - int cLen = 16 - ClearByteStart; - for (int i = ClearByteStart; i < ClearByteStart + cLen; i++) TexelWeightData[i] = 0; - - List TexelWeightValues = new List(); - BitArrayStream WeightBitStream = new BitArrayStream(new BitArray(TexelWeightData)); - - IntegerEncoded.DecodeIntegerSequence(TexelWeightValues, WeightBitStream, TexelParams.MaxWeight, TexelParams.GetNumWeightValues()); - - // Blocks can be at most 12x12, so we can have as many as 144 weights - int[][] Weights = new int[2][]; - Weights[0] = new int[144]; - Weights[1] = new int[144]; - - UnquantizeTexelWeights(Weights, TexelWeightValues, TexelParams, BlockWidth, BlockHeight); - - // Now that we have endpoints and weights, we can interpolate and generate - // the proper decoding... - for (int j = 0; j < BlockHeight; j++) - { - for (int i = 0; i < BlockWidth; i++) - { - int Partition = Select2DPartition(PartitionIndex, i, j, NumberPartitions, ((BlockHeight * BlockWidth) < 32)); - Debug.Assert(Partition < NumberPartitions); - - ASTCPixel Pixel = new ASTCPixel(0, 0, 0, 0); - for (int Component = 0; Component < 4; Component++) - { - int Component0 = EndPoints[Partition][0].GetComponent(Component); - Component0 = BitArrayStream.Replicate(Component0, 8, 16); - int Component1 = EndPoints[Partition][1].GetComponent(Component); - Component1 = BitArrayStream.Replicate(Component1, 8, 16); - - int Plane = 0; - - if (TexelParams.DualPlane && (((PlaneIndices + 1) & 3) == Component)) - { - Plane = 1; - } - - int Weight = Weights[Plane][j * BlockWidth + i]; - int FinalComponent = (Component0 * (64 - Weight) + Component1 * Weight + 32) / 64; - - if (FinalComponent == 65535) - { - Pixel.SetComponent(Component, 255); - } - else - { - double FinalComponentFloat = FinalComponent; - Pixel.SetComponent(Component, (int)(255.0 * (FinalComponentFloat / 65536.0) + 0.5)); - } - } - - OutputBuffer[j * BlockWidth + i] = Pixel.Pack(); - } - } - - return true; - } - - private static int Select2DPartition(int Seed, int X, int Y, int PartitionCount, bool IsSmallBlock) - { - return SelectPartition(Seed, X, Y, 0, PartitionCount, IsSmallBlock); - } - - private static int SelectPartition(int Seed, int X, int Y, int Z, int PartitionCount, bool IsSmallBlock) - { - if (PartitionCount == 1) - { - return 0; - } - - if (IsSmallBlock) - { - X <<= 1; - Y <<= 1; - Z <<= 1; - } - - Seed += (PartitionCount - 1) * 1024; - - int RightNum = Hash52((uint)Seed); - byte Seed01 = (byte)(RightNum & 0xF); - byte Seed02 = (byte)((RightNum >> 4) & 0xF); - byte Seed03 = (byte)((RightNum >> 8) & 0xF); - byte Seed04 = (byte)((RightNum >> 12) & 0xF); - byte Seed05 = (byte)((RightNum >> 16) & 0xF); - byte Seed06 = (byte)((RightNum >> 20) & 0xF); - byte Seed07 = (byte)((RightNum >> 24) & 0xF); - byte Seed08 = (byte)((RightNum >> 28) & 0xF); - byte Seed09 = (byte)((RightNum >> 18) & 0xF); - byte Seed10 = (byte)((RightNum >> 22) & 0xF); - byte Seed11 = (byte)((RightNum >> 26) & 0xF); - byte Seed12 = (byte)(((RightNum >> 30) | (RightNum << 2)) & 0xF); - - Seed01 *= Seed01; Seed02 *= Seed02; - Seed03 *= Seed03; Seed04 *= Seed04; - Seed05 *= Seed05; Seed06 *= Seed06; - Seed07 *= Seed07; Seed08 *= Seed08; - Seed09 *= Seed09; Seed10 *= Seed10; - Seed11 *= Seed11; Seed12 *= Seed12; - - int SeedHash1, SeedHash2, SeedHash3; - - if ((Seed & 1) != 0) - { - SeedHash1 = (Seed & 2) != 0 ? 4 : 5; - SeedHash2 = (PartitionCount == 3) ? 6 : 5; - } - else - { - SeedHash1 = (PartitionCount == 3) ? 6 : 5; - SeedHash2 = (Seed & 2) != 0 ? 4 : 5; - } - - SeedHash3 = (Seed & 0x10) != 0 ? SeedHash1 : SeedHash2; - - Seed01 >>= SeedHash1; Seed02 >>= SeedHash2; Seed03 >>= SeedHash1; Seed04 >>= SeedHash2; - Seed05 >>= SeedHash1; Seed06 >>= SeedHash2; Seed07 >>= SeedHash1; Seed08 >>= SeedHash2; - Seed09 >>= SeedHash3; Seed10 >>= SeedHash3; Seed11 >>= SeedHash3; Seed12 >>= SeedHash3; - - int a = Seed01 * X + Seed02 * Y + Seed11 * Z + (RightNum >> 14); - int b = Seed03 * X + Seed04 * Y + Seed12 * Z + (RightNum >> 10); - int c = Seed05 * X + Seed06 * Y + Seed09 * Z + (RightNum >> 6); - int d = Seed07 * X + Seed08 * Y + Seed10 * Z + (RightNum >> 2); - - a &= 0x3F; b &= 0x3F; c &= 0x3F; d &= 0x3F; - - if (PartitionCount < 4) d = 0; - if (PartitionCount < 3) c = 0; - - if (a >= b && a >= c && a >= d) return 0; - else if (b >= c && b >= d) return 1; - else if (c >= d) return 2; - return 3; - } - - static int Hash52(uint Val) - { - Val ^= Val >> 15; Val -= Val << 17; Val += Val << 7; Val += Val << 4; - Val ^= Val >> 5; Val += Val << 16; Val ^= Val >> 7; Val ^= Val >> 3; - Val ^= Val << 6; Val ^= Val >> 17; - - return (int)Val; - } - - static void UnquantizeTexelWeights( - int[][] OutputBuffer, - List Weights, - TexelWeightParams TexelParams, - int BlockWidth, - int BlockHeight) - { - int WeightIndices = 0; - int[][] Unquantized = new int[2][]; - Unquantized[0] = new int[144]; - Unquantized[1] = new int[144]; - - for (int i = 0; i < Weights.Count; i++) - { - Unquantized[0][WeightIndices] = UnquantizeTexelWeight(Weights[i]); - - if (TexelParams.DualPlane) - { - i++; - Unquantized[1][WeightIndices] = UnquantizeTexelWeight(Weights[i]); - - if (i == Weights.Count) - { - break; - } - } - - if (++WeightIndices >= (TexelParams.Width * TexelParams.Height)) break; - } - - // Do infill if necessary (Section C.2.18) ... - int Ds = (1024 + (BlockWidth / 2)) / (BlockWidth - 1); - int Dt = (1024 + (BlockHeight / 2)) / (BlockHeight - 1); - - int PlaneScale = TexelParams.DualPlane ? 2 : 1; - - for (int Plane = 0; Plane < PlaneScale; Plane++) - { - for (int t = 0; t < BlockHeight; t++) - { - for (int s = 0; s < BlockWidth; s++) - { - int cs = Ds * s; - int ct = Dt * t; - - int gs = (cs * (TexelParams.Width - 1) + 32) >> 6; - int gt = (ct * (TexelParams.Height - 1) + 32) >> 6; - - int js = gs >> 4; - int fs = gs & 0xF; - - int jt = gt >> 4; - int ft = gt & 0x0F; - - int w11 = (fs * ft + 8) >> 4; - int w10 = ft - w11; - int w01 = fs - w11; - int w00 = 16 - fs - ft + w11; - - int v0 = js + jt * TexelParams.Width; - - int p00 = 0; - int p01 = 0; - int p10 = 0; - int p11 = 0; - - if (v0 < (TexelParams.Width * TexelParams.Height)) - { - p00 = Unquantized[Plane][v0]; - } - - if (v0 + 1 < (TexelParams.Width * TexelParams.Height)) - { - p01 = Unquantized[Plane][v0 + 1]; - } - - if (v0 + TexelParams.Width < (TexelParams.Width * TexelParams.Height)) - { - p10 = Unquantized[Plane][v0 + TexelParams.Width]; - } - - if (v0 + TexelParams.Width + 1 < (TexelParams.Width * TexelParams.Height)) - { - p11 = Unquantized[Plane][v0 + TexelParams.Width + 1]; - } - - OutputBuffer[Plane][t * BlockWidth + s] = (p00 * w00 + p01 * w01 + p10 * w10 + p11 * w11 + 8) >> 4; - } - } - } - } - - static int UnquantizeTexelWeight(IntegerEncoded IntEncoded) - { - int BitValue = IntEncoded.BitValue; - int BitLength = IntEncoded.NumberBits; - - int A = BitArrayStream.Replicate(BitValue & 1, 1, 7); - int B = 0, C = 0, D = 0; - - int Result = 0; - - switch (IntEncoded.GetEncoding()) - { - case IntegerEncoded.EIntegerEncoding.JustBits: - Result = BitArrayStream.Replicate(BitValue, BitLength, 6); - break; - - case IntegerEncoded.EIntegerEncoding.Trit: - { - D = IntEncoded.TritValue; - Debug.Assert(D < 3); - - switch (BitLength) - { - case 0: - { - int[] Results = { 0, 32, 63 }; - Result = Results[D]; - - break; - } - - case 1: - { - C = 50; - break; - } - - case 2: - { - C = 23; - int b = (BitValue >> 1) & 1; - B = (b << 6) | (b << 2) | b; - - break; - } - - case 3: - { - C = 11; - int cb = (BitValue >> 1) & 3; - B = (cb << 5) | cb; - - break; - } - - default: - throw new ASTCDecoderException("Invalid trit encoding for texel weight"); - } - - break; - } - - case IntegerEncoded.EIntegerEncoding.Quint: - { - D = IntEncoded.QuintValue; - Debug.Assert(D < 5); - - switch (BitLength) - { - case 0: - { - int[] Results = { 0, 16, 32, 47, 63 }; - Result = Results[D]; - - break; - } - - case 1: - { - C = 28; - - break; - } - - case 2: - { - C = 13; - int b = (BitValue >> 1) & 1; - B = (b << 6) | (b << 1); - - break; - } - - default: - throw new ASTCDecoderException("Invalid quint encoding for texel weight"); - } - - break; - } - } - - if (IntEncoded.GetEncoding() != IntegerEncoded.EIntegerEncoding.JustBits && BitLength > 0) - { - // Decode the value... - Result = D * C + B; - Result ^= A; - Result = (A & 0x20) | (Result >> 2); - } - - Debug.Assert(Result < 64); - - // Change from [0,63] to [0,64] - if (Result > 32) - { - Result += 1; - } - - return Result; - } - - static byte ReverseByte(byte b) - { - // Taken from http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith64Bits - return (byte)((((b) * 0x80200802L) & 0x0884422110L) * 0x0101010101L >> 32); - } - - static uint[] ReadUintColorValues(int Number, int[] ColorValues, ref int ColorValuesPosition) - { - uint[] Ret = new uint[Number]; - - for (int i = 0; i < Number; i++) - { - Ret[i] = (uint)ColorValues[ColorValuesPosition++]; - } - - return Ret; - } - - static int[] ReadIntColorValues(int Number, int[] ColorValues, ref int ColorValuesPosition) - { - int[] Ret = new int[Number]; - - for (int i = 0; i < Number; i++) - { - Ret[i] = ColorValues[ColorValuesPosition++]; - } - - return Ret; - } - - static void ComputeEndpoints( - ASTCPixel[] EndPoints, - int[] ColorValues, - uint ColorEndpointMode, - ref int ColorValuesPosition) - { - switch (ColorEndpointMode) - { - case 0: - { - uint[] Val = ReadUintColorValues(2, ColorValues, ref ColorValuesPosition); - - EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[0], (short)Val[0]); - EndPoints[1] = new ASTCPixel(0xFF, (short)Val[1], (short)Val[1], (short)Val[1]); - - break; - } - - - case 1: - { - uint[] Val = ReadUintColorValues(2, ColorValues, ref ColorValuesPosition); - int L0 = (int)((Val[0] >> 2) | (Val[1] & 0xC0)); - int L1 = (int)Math.Max(L0 + (Val[1] & 0x3F), 0xFFU); - - EndPoints[0] = new ASTCPixel(0xFF, (short)L0, (short)L0, (short)L0); - EndPoints[1] = new ASTCPixel(0xFF, (short)L1, (short)L1, (short)L1); - - break; - } - - case 4: - { - uint[] Val = ReadUintColorValues(4, ColorValues, ref ColorValuesPosition); - - EndPoints[0] = new ASTCPixel((short)Val[2], (short)Val[0], (short)Val[0], (short)Val[0]); - EndPoints[1] = new ASTCPixel((short)Val[3], (short)Val[1], (short)Val[1], (short)Val[1]); - - break; - } - - case 5: - { - int[] Val = ReadIntColorValues(4, ColorValues, ref ColorValuesPosition); - - BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); - BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); - - EndPoints[0] = new ASTCPixel((short)Val[2], (short)Val[0], (short)Val[0], (short)Val[0]); - EndPoints[1] = new ASTCPixel((short)(Val[2] + Val[3]), (short)(Val[0] + Val[1]), (short)(Val[0] + Val[1]), (short)(Val[0] + Val[1])); - - EndPoints[0].ClampByte(); - EndPoints[1].ClampByte(); - - break; - } - - case 6: - { - uint[] Val = ReadUintColorValues(4, ColorValues, ref ColorValuesPosition); - - EndPoints[0] = new ASTCPixel(0xFF, (short)(Val[0] * Val[3] >> 8), (short)(Val[1] * Val[3] >> 8), (short)(Val[2] * Val[3] >> 8)); - EndPoints[1] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[1], (short)Val[2]); - - break; - } - - case 8: - { - uint[] Val = ReadUintColorValues(6, ColorValues, ref ColorValuesPosition); - - if (Val[1] + Val[3] + Val[5] >= Val[0] + Val[2] + Val[4]) - { - EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); - EndPoints[1] = new ASTCPixel(0xFF, (short)Val[1], (short)Val[3], (short)Val[5]); - } - else - { - EndPoints[0] = ASTCPixel.BlueContract(0xFF, (short)Val[1], (short)Val[3], (short)Val[5]); - EndPoints[1] = ASTCPixel.BlueContract(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); - } - - break; - } - - case 9: - { - int[] Val = ReadIntColorValues(6, ColorValues, ref ColorValuesPosition); - - BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); - BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); - BitArrayStream.BitTransferSigned(ref Val[5], ref Val[4]); - - if (Val[1] + Val[3] + Val[5] >= 0) - { - EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); - EndPoints[1] = new ASTCPixel(0xFF, (short)(Val[0] + Val[1]), (short)(Val[2] + Val[3]), (short)(Val[4] + Val[5])); - } - else - { - EndPoints[0] = ASTCPixel.BlueContract(0xFF, Val[0] + Val[1], Val[2] + Val[3], Val[4] + Val[5]); - EndPoints[1] = ASTCPixel.BlueContract(0xFF, Val[0], Val[2], Val[4]); - } - - EndPoints[0].ClampByte(); - EndPoints[1].ClampByte(); - - break; - } - - case 10: - { - uint[] Val = ReadUintColorValues(6, ColorValues, ref ColorValuesPosition); - - EndPoints[0] = new ASTCPixel((short)Val[4], (short)(Val[0] * Val[3] >> 8), (short)(Val[1] * Val[3] >> 8), (short)(Val[2] * Val[3] >> 8)); - EndPoints[1] = new ASTCPixel((short)Val[5], (short)Val[0], (short)Val[1], (short)Val[2]); - - break; - } - - case 12: - { - uint[] Val = ReadUintColorValues(8, ColorValues, ref ColorValuesPosition); - - if (Val[1] + Val[3] + Val[5] >= Val[0] + Val[2] + Val[4]) - { - EndPoints[0] = new ASTCPixel((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); - EndPoints[1] = new ASTCPixel((short)Val[7], (short)Val[1], (short)Val[3], (short)Val[5]); - } - else - { - EndPoints[0] = ASTCPixel.BlueContract((short)Val[7], (short)Val[1], (short)Val[3], (short)Val[5]); - EndPoints[1] = ASTCPixel.BlueContract((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); - } - - break; - } - - case 13: - { - int[] Val = ReadIntColorValues(8, ColorValues, ref ColorValuesPosition); - - BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); - BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); - BitArrayStream.BitTransferSigned(ref Val[5], ref Val[4]); - BitArrayStream.BitTransferSigned(ref Val[7], ref Val[6]); - - if (Val[1] + Val[3] + Val[5] >= 0) - { - EndPoints[0] = new ASTCPixel((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); - EndPoints[1] = new ASTCPixel((short)(Val[7] + Val[6]), (short)(Val[0] + Val[1]), (short)(Val[2] + Val[3]), (short)(Val[4] + Val[5])); - } - else - { - EndPoints[0] = ASTCPixel.BlueContract(Val[6] + Val[7], Val[0] + Val[1], Val[2] + Val[3], Val[4] + Val[5]); - EndPoints[1] = ASTCPixel.BlueContract(Val[6], Val[0], Val[2], Val[4]); - } - - EndPoints[0].ClampByte(); - EndPoints[1].ClampByte(); - - break; - } - - default: - throw new ASTCDecoderException("Unsupported color endpoint mode (is it HDR?)"); - } - } - - static void DecodeColorValues( - int[] OutputValues, - byte[] InputData, - uint[] Modes, - int NumberPartitions, - int NumberBitsForColorData) - { - // First figure out how many color values we have - int NumberValues = 0; - - for (int i = 0; i < NumberPartitions; i++) - { - NumberValues += (int)((Modes[i] >> 2) + 1) << 1; - } - - // Then based on the number of values and the remaining number of bits, - // figure out the max value for each of them... - int Range = 256; - - while (--Range > 0) - { - IntegerEncoded IntEncoded = IntegerEncoded.CreateEncoding(Range); - int BitLength = IntEncoded.GetBitLength(NumberValues); - - if (BitLength <= NumberBitsForColorData) - { - // Find the smallest possible range that matches the given encoding - while (--Range > 0) - { - IntegerEncoded NewIntEncoded = IntegerEncoded.CreateEncoding(Range); - if (!NewIntEncoded.MatchesEncoding(IntEncoded)) - { - break; - } - } - - // Return to last matching range. - Range++; - break; - } - } - - // We now have enough to decode our integer sequence. - List IntegerEncodedSequence = new List(); - BitArrayStream ColorBitStream = new BitArrayStream(new BitArray(InputData)); - - IntegerEncoded.DecodeIntegerSequence(IntegerEncodedSequence, ColorBitStream, Range, NumberValues); - - // Once we have the decoded values, we need to dequantize them to the 0-255 range - // This procedure is outlined in ASTC spec C.2.13 - int OutputIndices = 0; - - foreach (IntegerEncoded IntEncoded in IntegerEncodedSequence) - { - int BitLength = IntEncoded.NumberBits; - int BitValue = IntEncoded.BitValue; - - Debug.Assert(BitLength >= 1); - - int A = 0, B = 0, C = 0, D = 0; - // A is just the lsb replicated 9 times. - A = BitArrayStream.Replicate(BitValue & 1, 1, 9); - - switch (IntEncoded.GetEncoding()) - { - case IntegerEncoded.EIntegerEncoding.JustBits: - { - OutputValues[OutputIndices++] = BitArrayStream.Replicate(BitValue, BitLength, 8); - - break; - } - - case IntegerEncoded.EIntegerEncoding.Trit: - { - D = IntEncoded.TritValue; - - switch (BitLength) - { - case 1: - { - C = 204; - - break; - } - - case 2: - { - C = 93; - // B = b000b0bb0 - int b = (BitValue >> 1) & 1; - B = (b << 8) | (b << 4) | (b << 2) | (b << 1); - - break; - } - - case 3: - { - C = 44; - // B = cb000cbcb - int cb = (BitValue >> 1) & 3; - B = (cb << 7) | (cb << 2) | cb; - - break; - } - - - case 4: - { - C = 22; - // B = dcb000dcb - int dcb = (BitValue >> 1) & 7; - B = (dcb << 6) | dcb; - - break; - } - - case 5: - { - C = 11; - // B = edcb000ed - int edcb = (BitValue >> 1) & 0xF; - B = (edcb << 5) | (edcb >> 2); - - break; - } - - case 6: - { - C = 5; - // B = fedcb000f - int fedcb = (BitValue >> 1) & 0x1F; - B = (fedcb << 4) | (fedcb >> 4); - - break; - } - - default: - throw new ASTCDecoderException("Unsupported trit encoding for color values!"); - } - - break; - } - - case IntegerEncoded.EIntegerEncoding.Quint: - { - D = IntEncoded.QuintValue; - - switch (BitLength) - { - case 1: - { - C = 113; - - break; - } - - case 2: - { - C = 54; - // B = b0000bb00 - int b = (BitValue >> 1) & 1; - B = (b << 8) | (b << 3) | (b << 2); - - break; - } - - case 3: - { - C = 26; - // B = cb0000cbc - int cb = (BitValue >> 1) & 3; - B = (cb << 7) | (cb << 1) | (cb >> 1); - - break; - } - - case 4: - { - C = 13; - // B = dcb0000dc - int dcb = (BitValue >> 1) & 7; - B = (dcb << 6) | (dcb >> 1); - - break; - } - - case 5: - { - C = 6; - // B = edcb0000e - int edcb = (BitValue >> 1) & 0xF; - B = (edcb << 5) | (edcb >> 3); - - break; - } - - default: - throw new ASTCDecoderException("Unsupported quint encoding for color values!"); - } - break; - } - } - - if (IntEncoded.GetEncoding() != IntegerEncoded.EIntegerEncoding.JustBits) - { - int T = D * C + B; - T ^= A; - T = (A & 0x80) | (T >> 2); - - OutputValues[OutputIndices++] = T; - } - } - - // Make sure that each of our values is in the proper range... - for (int i = 0; i < NumberValues; i++) - { - Debug.Assert(OutputValues[i] <= 255); - } - } - - static void FillVoidExtentLDR(BitArrayStream BitStream, int[] OutputBuffer, int BlockWidth, int BlockHeight) - { - // Don't actually care about the void extent, just read the bits... - for (int i = 0; i < 4; ++i) - { - BitStream.ReadBits(13); - } - - // Decode the RGBA components and renormalize them to the range [0, 255] - ushort R = (ushort)BitStream.ReadBits(16); - ushort G = (ushort)BitStream.ReadBits(16); - ushort B = (ushort)BitStream.ReadBits(16); - ushort A = (ushort)BitStream.ReadBits(16); - - int RGBA = (R >> 8) | (G & 0xFF00) | ((B) & 0xFF00) << 8 | ((A) & 0xFF00) << 16; - - for (int j = 0; j < BlockHeight; j++) - { - for (int i = 0; i < BlockWidth; i++) - { - OutputBuffer[j * BlockWidth + i] = RGBA; - } - } - } - - static TexelWeightParams DecodeBlockInfo(BitArrayStream BitStream) - { - TexelWeightParams TexelParams = new TexelWeightParams(); - - // Read the entire block mode all at once - ushort ModeBits = (ushort)BitStream.ReadBits(11); - - // Does this match the void extent block mode? - if ((ModeBits & 0x01FF) == 0x1FC) - { - if ((ModeBits & 0x200) != 0) - { - TexelParams.VoidExtentHDR = true; - } - else - { - TexelParams.VoidExtentLDR = true; - } - - // Next two bits must be one. - if ((ModeBits & 0x400) == 0 || BitStream.ReadBits(1) == 0) - { - TexelParams.Error = true; - } - - return TexelParams; - } - - // First check if the last four bits are zero - if ((ModeBits & 0xF) == 0) - { - TexelParams.Error = true; - return TexelParams; - } - - // If the last two bits are zero, then if bits - // [6-8] are all ones, this is also reserved. - if ((ModeBits & 0x3) == 0 && (ModeBits & 0x1C0) == 0x1C0) - { - TexelParams.Error = true; - - return TexelParams; - } - - // Otherwise, there is no error... Figure out the layout - // of the block mode. Layout is determined by a number - // between 0 and 9 corresponding to table C.2.8 of the - // ASTC spec. - int Layout = 0; - - if ((ModeBits & 0x1) != 0 || (ModeBits & 0x2) != 0) - { - // layout is in [0-4] - if ((ModeBits & 0x8) != 0) - { - // layout is in [2-4] - if ((ModeBits & 0x4) != 0) - { - // layout is in [3-4] - if ((ModeBits & 0x100) != 0) - { - Layout = 4; - } - else - { - Layout = 3; - } - } - else - { - Layout = 2; - } - } - else - { - // layout is in [0-1] - if ((ModeBits & 0x4) != 0) - { - Layout = 1; - } - else - { - Layout = 0; - } - } - } - else - { - // layout is in [5-9] - if ((ModeBits & 0x100) != 0) - { - // layout is in [7-9] - if ((ModeBits & 0x80) != 0) - { - // layout is in [7-8] - Debug.Assert((ModeBits & 0x40) == 0); - - if ((ModeBits & 0x20) != 0) - { - Layout = 8; - } - else - { - Layout = 7; - } - } - else - { - Layout = 9; - } - } - else - { - // layout is in [5-6] - if ((ModeBits & 0x80) != 0) - { - Layout = 6; - } - else - { - Layout = 5; - } - } - } - - Debug.Assert(Layout < 10); - - // Determine R - int R = (ModeBits >> 4) & 1; - if (Layout < 5) - { - R |= (ModeBits & 0x3) << 1; - } - else - { - R |= (ModeBits & 0xC) >> 1; - } - - Debug.Assert(2 <= R && R <= 7); - - // Determine width & height - switch (Layout) - { - case 0: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 7) & 0x3; - - TexelParams.Width = B + 4; - TexelParams.Height = A + 2; - - break; - } - - case 1: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 7) & 0x3; - - TexelParams.Width = B + 8; - TexelParams.Height = A + 2; - - break; - } - - case 2: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 7) & 0x3; - - TexelParams.Width = A + 2; - TexelParams.Height = B + 8; - - break; - } - - case 3: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 7) & 0x1; - - TexelParams.Width = A + 2; - TexelParams.Height = B + 6; - - break; - } - - case 4: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 7) & 0x1; - - TexelParams.Width = B + 2; - TexelParams.Height = A + 2; - - break; - } - - case 5: - { - int A = (ModeBits >> 5) & 0x3; - - TexelParams.Width = 12; - TexelParams.Height = A + 2; - - break; - } - - case 6: - { - int A = (ModeBits >> 5) & 0x3; - - TexelParams.Width = A + 2; - TexelParams.Height = 12; - - break; - } - - case 7: - { - TexelParams.Width = 6; - TexelParams.Height = 10; - - break; - } - - case 8: - { - TexelParams.Width = 10; - TexelParams.Height = 6; - break; - } - - case 9: - { - int A = (ModeBits >> 5) & 0x3; - int B = (ModeBits >> 9) & 0x3; - - TexelParams.Width = A + 6; - TexelParams.Height = B + 6; - - break; - } - - default: - //Don't know this layout... - TexelParams.Error = true; - break; - } - - // Determine whether or not we're using dual planes - // and/or high precision layouts. - bool D = ((Layout != 9) && ((ModeBits & 0x400) != 0)); - bool H = (Layout != 9) && ((ModeBits & 0x200) != 0); - - if (H) - { - int[] MaxWeights = { 9, 11, 15, 19, 23, 31 }; - TexelParams.MaxWeight = MaxWeights[R - 2]; - } - else - { - int[] MaxWeights = { 1, 2, 3, 4, 5, 7 }; - TexelParams.MaxWeight = MaxWeights[R - 2]; - } - - TexelParams.DualPlane = D; - - return TexelParams; - } - } -} +using System; +using System.Collections; +using System.Collections.Generic; +using System.Diagnostics; +using System.IO; + +namespace Ryujinx.Graphics.Texture +{ + public class ASTCDecoderException : Exception + { + public ASTCDecoderException(string ExMsg) : base(ExMsg) { } + } + + //https://github.com/GammaUNC/FasTC/blob/master/ASTCEncoder/src/Decompressor.cpp + public static class ASTCDecoder + { + struct TexelWeightParams + { + public int Width; + public int Height; + public bool DualPlane; + public int MaxWeight; + public bool Error; + public bool VoidExtentLDR; + public bool VoidExtentHDR; + + public int GetPackedBitSize() + { + // How many indices do we have? + int Indices = Height * Width; + + if (DualPlane) + { + Indices *= 2; + } + + IntegerEncoded IntEncoded = IntegerEncoded.CreateEncoding(MaxWeight); + + return IntEncoded.GetBitLength(Indices); + } + + public int GetNumWeightValues() + { + int Ret = Width * Height; + + if (DualPlane) + { + Ret *= 2; + } + + return Ret; + } + } + + public static byte[] DecodeToRGBA8888( + byte[] InputBuffer, + int BlockX, + int BlockY, + int BlockZ, + int X, + int Y, + int Z) + { + using (MemoryStream InputStream = new MemoryStream(InputBuffer)) + { + BinaryReader BinReader = new BinaryReader(InputStream); + + if (BlockX > 12 || BlockY > 12) + { + throw new ASTCDecoderException("Block size unsupported!"); + } + + if (BlockZ != 1 || Z != 1) + { + throw new ASTCDecoderException("3D compressed textures unsupported!"); + } + + using (MemoryStream OutputStream = new MemoryStream()) + { + int BlockIndex = 0; + + for (int j = 0; j < Y; j += BlockY) + { + for (int i = 0; i < X; i += BlockX) + { + int[] DecompressedData = new int[144]; + + DecompressBlock(BinReader.ReadBytes(0x10), DecompressedData, BlockX, BlockY); + + int DecompressedWidth = Math.Min(BlockX, X - i); + int DecompressedHeight = Math.Min(BlockY, Y - j); + int BaseOffsets = (j * X + i) * 4; + + for (int jj = 0; jj < DecompressedHeight; jj++) + { + OutputStream.Seek(BaseOffsets + jj * X * 4, SeekOrigin.Begin); + + byte[] OutputBuffer = new byte[DecompressedData.Length * sizeof(int)]; + Buffer.BlockCopy(DecompressedData, 0, OutputBuffer, 0, OutputBuffer.Length); + + OutputStream.Write(OutputBuffer, jj * BlockX * 4, DecompressedWidth * 4); + } + + BlockIndex++; + } + } + + return OutputStream.ToArray(); + } + } + } + + public static bool DecompressBlock( + byte[] InputBuffer, + int[] OutputBuffer, + int BlockWidth, + int BlockHeight) + { + BitArrayStream BitStream = new BitArrayStream(new BitArray(InputBuffer)); + TexelWeightParams TexelParams = DecodeBlockInfo(BitStream); + + if (TexelParams.Error) + { + throw new ASTCDecoderException("Invalid block mode"); + } + + if (TexelParams.VoidExtentLDR) + { + FillVoidExtentLDR(BitStream, OutputBuffer, BlockWidth, BlockHeight); + + return true; + } + + if (TexelParams.VoidExtentHDR) + { + throw new ASTCDecoderException("HDR void extent blocks are unsupported!"); + } + + if (TexelParams.Width > BlockWidth) + { + throw new ASTCDecoderException("Texel weight grid width should be smaller than block width"); + } + + if (TexelParams.Height > BlockHeight) + { + throw new ASTCDecoderException("Texel weight grid height should be smaller than block height"); + } + + // Read num partitions + int NumberPartitions = BitStream.ReadBits(2) + 1; + Debug.Assert(NumberPartitions <= 4); + + if (NumberPartitions == 4 && TexelParams.DualPlane) + { + throw new ASTCDecoderException("Dual plane mode is incompatible with four partition blocks"); + } + + // Based on the number of partitions, read the color endpoint mode for + // each partition. + + // Determine partitions, partition index, and color endpoint modes + int PlaneIndices = -1; + int PartitionIndex; + uint[] ColorEndpointMode = { 0, 0, 0, 0 }; + + BitArrayStream ColorEndpointStream = new BitArrayStream(new BitArray(16 * 8)); + + // Read extra config data... + uint BaseColorEndpointMode = 0; + + if (NumberPartitions == 1) + { + ColorEndpointMode[0] = (uint)BitStream.ReadBits(4); + PartitionIndex = 0; + } + else + { + PartitionIndex = BitStream.ReadBits(10); + BaseColorEndpointMode = (uint)BitStream.ReadBits(6); + } + + uint BaseMode = (BaseColorEndpointMode & 3); + + // Remaining bits are color endpoint data... + int NumberWeightBits = TexelParams.GetPackedBitSize(); + int RemainingBits = 128 - NumberWeightBits - BitStream.Position; + + // Consider extra bits prior to texel data... + uint ExtraColorEndpointModeBits = 0; + + if (BaseMode != 0) + { + switch (NumberPartitions) + { + case 2: ExtraColorEndpointModeBits += 2; break; + case 3: ExtraColorEndpointModeBits += 5; break; + case 4: ExtraColorEndpointModeBits += 8; break; + default: Debug.Assert(false); break; + } + } + + RemainingBits -= (int)ExtraColorEndpointModeBits; + + // Do we have a dual plane situation? + int PlaneSelectorBits = 0; + + if (TexelParams.DualPlane) + { + PlaneSelectorBits = 2; + } + + RemainingBits -= PlaneSelectorBits; + + // Read color data... + int ColorDataBits = RemainingBits; + + while (RemainingBits > 0) + { + int NumberBits = Math.Min(RemainingBits, 8); + int Bits = BitStream.ReadBits(NumberBits); + ColorEndpointStream.WriteBits(Bits, NumberBits); + RemainingBits -= 8; + } + + // Read the plane selection bits + PlaneIndices = BitStream.ReadBits(PlaneSelectorBits); + + // Read the rest of the CEM + if (BaseMode != 0) + { + uint ExtraColorEndpointMode = (uint)BitStream.ReadBits((int)ExtraColorEndpointModeBits); + uint TempColorEndpointMode = (ExtraColorEndpointMode << 6) | BaseColorEndpointMode; + TempColorEndpointMode >>= 2; + + bool[] C = new bool[4]; + + for (int i = 0; i < NumberPartitions; i++) + { + C[i] = (TempColorEndpointMode & 1) != 0; + TempColorEndpointMode >>= 1; + } + + byte[] M = new byte[4]; + + for (int i = 0; i < NumberPartitions; i++) + { + M[i] = (byte)(TempColorEndpointMode & 3); + TempColorEndpointMode >>= 2; + Debug.Assert(M[i] <= 3); + } + + for (int i = 0; i < NumberPartitions; i++) + { + ColorEndpointMode[i] = BaseMode; + if (!(C[i])) ColorEndpointMode[i] -= 1; + ColorEndpointMode[i] <<= 2; + ColorEndpointMode[i] |= M[i]; + } + } + else if (NumberPartitions > 1) + { + uint TempColorEndpointMode = BaseColorEndpointMode >> 2; + + for (uint i = 0; i < NumberPartitions; i++) + { + ColorEndpointMode[i] = TempColorEndpointMode; + } + } + + // Make sure everything up till here is sane. + for (int i = 0; i < NumberPartitions; i++) + { + Debug.Assert(ColorEndpointMode[i] < 16); + } + Debug.Assert(BitStream.Position + TexelParams.GetPackedBitSize() == 128); + + // Decode both color data and texel weight data + int[] ColorValues = new int[32]; // Four values * two endpoints * four maximum partitions + DecodeColorValues(ColorValues, ColorEndpointStream.ToByteArray(), ColorEndpointMode, NumberPartitions, ColorDataBits); + + ASTCPixel[][] EndPoints = new ASTCPixel[4][]; + EndPoints[0] = new ASTCPixel[2]; + EndPoints[1] = new ASTCPixel[2]; + EndPoints[2] = new ASTCPixel[2]; + EndPoints[3] = new ASTCPixel[2]; + + int ColorValuesPosition = 0; + + for (int i = 0; i < NumberPartitions; i++) + { + ComputeEndpoints(EndPoints[i], ColorValues, ColorEndpointMode[i], ref ColorValuesPosition); + } + + // Read the texel weight data. + byte[] TexelWeightData = (byte[])InputBuffer.Clone(); + + // Reverse everything + for (int i = 0; i < 8; i++) + { + byte a = ReverseByte(TexelWeightData[i]); + byte b = ReverseByte(TexelWeightData[15 - i]); + + TexelWeightData[i] = b; + TexelWeightData[15 - i] = a; + } + + // Make sure that higher non-texel bits are set to zero + int ClearByteStart = (TexelParams.GetPackedBitSize() >> 3) + 1; + TexelWeightData[ClearByteStart - 1] &= (byte)((1 << (TexelParams.GetPackedBitSize() % 8)) - 1); + + int cLen = 16 - ClearByteStart; + for (int i = ClearByteStart; i < ClearByteStart + cLen; i++) TexelWeightData[i] = 0; + + List TexelWeightValues = new List(); + BitArrayStream WeightBitStream = new BitArrayStream(new BitArray(TexelWeightData)); + + IntegerEncoded.DecodeIntegerSequence(TexelWeightValues, WeightBitStream, TexelParams.MaxWeight, TexelParams.GetNumWeightValues()); + + // Blocks can be at most 12x12, so we can have as many as 144 weights + int[][] Weights = new int[2][]; + Weights[0] = new int[144]; + Weights[1] = new int[144]; + + UnquantizeTexelWeights(Weights, TexelWeightValues, TexelParams, BlockWidth, BlockHeight); + + // Now that we have endpoints and weights, we can interpolate and generate + // the proper decoding... + for (int j = 0; j < BlockHeight; j++) + { + for (int i = 0; i < BlockWidth; i++) + { + int Partition = Select2DPartition(PartitionIndex, i, j, NumberPartitions, ((BlockHeight * BlockWidth) < 32)); + Debug.Assert(Partition < NumberPartitions); + + ASTCPixel Pixel = new ASTCPixel(0, 0, 0, 0); + for (int Component = 0; Component < 4; Component++) + { + int Component0 = EndPoints[Partition][0].GetComponent(Component); + Component0 = BitArrayStream.Replicate(Component0, 8, 16); + int Component1 = EndPoints[Partition][1].GetComponent(Component); + Component1 = BitArrayStream.Replicate(Component1, 8, 16); + + int Plane = 0; + + if (TexelParams.DualPlane && (((PlaneIndices + 1) & 3) == Component)) + { + Plane = 1; + } + + int Weight = Weights[Plane][j * BlockWidth + i]; + int FinalComponent = (Component0 * (64 - Weight) + Component1 * Weight + 32) / 64; + + if (FinalComponent == 65535) + { + Pixel.SetComponent(Component, 255); + } + else + { + double FinalComponentFloat = FinalComponent; + Pixel.SetComponent(Component, (int)(255.0 * (FinalComponentFloat / 65536.0) + 0.5)); + } + } + + OutputBuffer[j * BlockWidth + i] = Pixel.Pack(); + } + } + + return true; + } + + private static int Select2DPartition(int Seed, int X, int Y, int PartitionCount, bool IsSmallBlock) + { + return SelectPartition(Seed, X, Y, 0, PartitionCount, IsSmallBlock); + } + + private static int SelectPartition(int Seed, int X, int Y, int Z, int PartitionCount, bool IsSmallBlock) + { + if (PartitionCount == 1) + { + return 0; + } + + if (IsSmallBlock) + { + X <<= 1; + Y <<= 1; + Z <<= 1; + } + + Seed += (PartitionCount - 1) * 1024; + + int RightNum = Hash52((uint)Seed); + byte Seed01 = (byte)(RightNum & 0xF); + byte Seed02 = (byte)((RightNum >> 4) & 0xF); + byte Seed03 = (byte)((RightNum >> 8) & 0xF); + byte Seed04 = (byte)((RightNum >> 12) & 0xF); + byte Seed05 = (byte)((RightNum >> 16) & 0xF); + byte Seed06 = (byte)((RightNum >> 20) & 0xF); + byte Seed07 = (byte)((RightNum >> 24) & 0xF); + byte Seed08 = (byte)((RightNum >> 28) & 0xF); + byte Seed09 = (byte)((RightNum >> 18) & 0xF); + byte Seed10 = (byte)((RightNum >> 22) & 0xF); + byte Seed11 = (byte)((RightNum >> 26) & 0xF); + byte Seed12 = (byte)(((RightNum >> 30) | (RightNum << 2)) & 0xF); + + Seed01 *= Seed01; Seed02 *= Seed02; + Seed03 *= Seed03; Seed04 *= Seed04; + Seed05 *= Seed05; Seed06 *= Seed06; + Seed07 *= Seed07; Seed08 *= Seed08; + Seed09 *= Seed09; Seed10 *= Seed10; + Seed11 *= Seed11; Seed12 *= Seed12; + + int SeedHash1, SeedHash2, SeedHash3; + + if ((Seed & 1) != 0) + { + SeedHash1 = (Seed & 2) != 0 ? 4 : 5; + SeedHash2 = (PartitionCount == 3) ? 6 : 5; + } + else + { + SeedHash1 = (PartitionCount == 3) ? 6 : 5; + SeedHash2 = (Seed & 2) != 0 ? 4 : 5; + } + + SeedHash3 = (Seed & 0x10) != 0 ? SeedHash1 : SeedHash2; + + Seed01 >>= SeedHash1; Seed02 >>= SeedHash2; Seed03 >>= SeedHash1; Seed04 >>= SeedHash2; + Seed05 >>= SeedHash1; Seed06 >>= SeedHash2; Seed07 >>= SeedHash1; Seed08 >>= SeedHash2; + Seed09 >>= SeedHash3; Seed10 >>= SeedHash3; Seed11 >>= SeedHash3; Seed12 >>= SeedHash3; + + int a = Seed01 * X + Seed02 * Y + Seed11 * Z + (RightNum >> 14); + int b = Seed03 * X + Seed04 * Y + Seed12 * Z + (RightNum >> 10); + int c = Seed05 * X + Seed06 * Y + Seed09 * Z + (RightNum >> 6); + int d = Seed07 * X + Seed08 * Y + Seed10 * Z + (RightNum >> 2); + + a &= 0x3F; b &= 0x3F; c &= 0x3F; d &= 0x3F; + + if (PartitionCount < 4) d = 0; + if (PartitionCount < 3) c = 0; + + if (a >= b && a >= c && a >= d) return 0; + else if (b >= c && b >= d) return 1; + else if (c >= d) return 2; + return 3; + } + + static int Hash52(uint Val) + { + Val ^= Val >> 15; Val -= Val << 17; Val += Val << 7; Val += Val << 4; + Val ^= Val >> 5; Val += Val << 16; Val ^= Val >> 7; Val ^= Val >> 3; + Val ^= Val << 6; Val ^= Val >> 17; + + return (int)Val; + } + + static void UnquantizeTexelWeights( + int[][] OutputBuffer, + List Weights, + TexelWeightParams TexelParams, + int BlockWidth, + int BlockHeight) + { + int WeightIndices = 0; + int[][] Unquantized = new int[2][]; + Unquantized[0] = new int[144]; + Unquantized[1] = new int[144]; + + for (int i = 0; i < Weights.Count; i++) + { + Unquantized[0][WeightIndices] = UnquantizeTexelWeight(Weights[i]); + + if (TexelParams.DualPlane) + { + i++; + Unquantized[1][WeightIndices] = UnquantizeTexelWeight(Weights[i]); + + if (i == Weights.Count) + { + break; + } + } + + if (++WeightIndices >= (TexelParams.Width * TexelParams.Height)) break; + } + + // Do infill if necessary (Section C.2.18) ... + int Ds = (1024 + (BlockWidth / 2)) / (BlockWidth - 1); + int Dt = (1024 + (BlockHeight / 2)) / (BlockHeight - 1); + + int PlaneScale = TexelParams.DualPlane ? 2 : 1; + + for (int Plane = 0; Plane < PlaneScale; Plane++) + { + for (int t = 0; t < BlockHeight; t++) + { + for (int s = 0; s < BlockWidth; s++) + { + int cs = Ds * s; + int ct = Dt * t; + + int gs = (cs * (TexelParams.Width - 1) + 32) >> 6; + int gt = (ct * (TexelParams.Height - 1) + 32) >> 6; + + int js = gs >> 4; + int fs = gs & 0xF; + + int jt = gt >> 4; + int ft = gt & 0x0F; + + int w11 = (fs * ft + 8) >> 4; + int w10 = ft - w11; + int w01 = fs - w11; + int w00 = 16 - fs - ft + w11; + + int v0 = js + jt * TexelParams.Width; + + int p00 = 0; + int p01 = 0; + int p10 = 0; + int p11 = 0; + + if (v0 < (TexelParams.Width * TexelParams.Height)) + { + p00 = Unquantized[Plane][v0]; + } + + if (v0 + 1 < (TexelParams.Width * TexelParams.Height)) + { + p01 = Unquantized[Plane][v0 + 1]; + } + + if (v0 + TexelParams.Width < (TexelParams.Width * TexelParams.Height)) + { + p10 = Unquantized[Plane][v0 + TexelParams.Width]; + } + + if (v0 + TexelParams.Width + 1 < (TexelParams.Width * TexelParams.Height)) + { + p11 = Unquantized[Plane][v0 + TexelParams.Width + 1]; + } + + OutputBuffer[Plane][t * BlockWidth + s] = (p00 * w00 + p01 * w01 + p10 * w10 + p11 * w11 + 8) >> 4; + } + } + } + } + + static int UnquantizeTexelWeight(IntegerEncoded IntEncoded) + { + int BitValue = IntEncoded.BitValue; + int BitLength = IntEncoded.NumberBits; + + int A = BitArrayStream.Replicate(BitValue & 1, 1, 7); + int B = 0, C = 0, D = 0; + + int Result = 0; + + switch (IntEncoded.GetEncoding()) + { + case IntegerEncoded.EIntegerEncoding.JustBits: + Result = BitArrayStream.Replicate(BitValue, BitLength, 6); + break; + + case IntegerEncoded.EIntegerEncoding.Trit: + { + D = IntEncoded.TritValue; + Debug.Assert(D < 3); + + switch (BitLength) + { + case 0: + { + int[] Results = { 0, 32, 63 }; + Result = Results[D]; + + break; + } + + case 1: + { + C = 50; + break; + } + + case 2: + { + C = 23; + int b = (BitValue >> 1) & 1; + B = (b << 6) | (b << 2) | b; + + break; + } + + case 3: + { + C = 11; + int cb = (BitValue >> 1) & 3; + B = (cb << 5) | cb; + + break; + } + + default: + throw new ASTCDecoderException("Invalid trit encoding for texel weight"); + } + + break; + } + + case IntegerEncoded.EIntegerEncoding.Quint: + { + D = IntEncoded.QuintValue; + Debug.Assert(D < 5); + + switch (BitLength) + { + case 0: + { + int[] Results = { 0, 16, 32, 47, 63 }; + Result = Results[D]; + + break; + } + + case 1: + { + C = 28; + + break; + } + + case 2: + { + C = 13; + int b = (BitValue >> 1) & 1; + B = (b << 6) | (b << 1); + + break; + } + + default: + throw new ASTCDecoderException("Invalid quint encoding for texel weight"); + } + + break; + } + } + + if (IntEncoded.GetEncoding() != IntegerEncoded.EIntegerEncoding.JustBits && BitLength > 0) + { + // Decode the value... + Result = D * C + B; + Result ^= A; + Result = (A & 0x20) | (Result >> 2); + } + + Debug.Assert(Result < 64); + + // Change from [0,63] to [0,64] + if (Result > 32) + { + Result += 1; + } + + return Result; + } + + static byte ReverseByte(byte b) + { + // Taken from http://graphics.stanford.edu/~seander/bithacks.html#ReverseByteWith64Bits + return (byte)((((b) * 0x80200802L) & 0x0884422110L) * 0x0101010101L >> 32); + } + + static uint[] ReadUintColorValues(int Number, int[] ColorValues, ref int ColorValuesPosition) + { + uint[] Ret = new uint[Number]; + + for (int i = 0; i < Number; i++) + { + Ret[i] = (uint)ColorValues[ColorValuesPosition++]; + } + + return Ret; + } + + static int[] ReadIntColorValues(int Number, int[] ColorValues, ref int ColorValuesPosition) + { + int[] Ret = new int[Number]; + + for (int i = 0; i < Number; i++) + { + Ret[i] = ColorValues[ColorValuesPosition++]; + } + + return Ret; + } + + static void ComputeEndpoints( + ASTCPixel[] EndPoints, + int[] ColorValues, + uint ColorEndpointMode, + ref int ColorValuesPosition) + { + switch (ColorEndpointMode) + { + case 0: + { + uint[] Val = ReadUintColorValues(2, ColorValues, ref ColorValuesPosition); + + EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[0], (short)Val[0]); + EndPoints[1] = new ASTCPixel(0xFF, (short)Val[1], (short)Val[1], (short)Val[1]); + + break; + } + + + case 1: + { + uint[] Val = ReadUintColorValues(2, ColorValues, ref ColorValuesPosition); + int L0 = (int)((Val[0] >> 2) | (Val[1] & 0xC0)); + int L1 = (int)Math.Max(L0 + (Val[1] & 0x3F), 0xFFU); + + EndPoints[0] = new ASTCPixel(0xFF, (short)L0, (short)L0, (short)L0); + EndPoints[1] = new ASTCPixel(0xFF, (short)L1, (short)L1, (short)L1); + + break; + } + + case 4: + { + uint[] Val = ReadUintColorValues(4, ColorValues, ref ColorValuesPosition); + + EndPoints[0] = new ASTCPixel((short)Val[2], (short)Val[0], (short)Val[0], (short)Val[0]); + EndPoints[1] = new ASTCPixel((short)Val[3], (short)Val[1], (short)Val[1], (short)Val[1]); + + break; + } + + case 5: + { + int[] Val = ReadIntColorValues(4, ColorValues, ref ColorValuesPosition); + + BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); + BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); + + EndPoints[0] = new ASTCPixel((short)Val[2], (short)Val[0], (short)Val[0], (short)Val[0]); + EndPoints[1] = new ASTCPixel((short)(Val[2] + Val[3]), (short)(Val[0] + Val[1]), (short)(Val[0] + Val[1]), (short)(Val[0] + Val[1])); + + EndPoints[0].ClampByte(); + EndPoints[1].ClampByte(); + + break; + } + + case 6: + { + uint[] Val = ReadUintColorValues(4, ColorValues, ref ColorValuesPosition); + + EndPoints[0] = new ASTCPixel(0xFF, (short)(Val[0] * Val[3] >> 8), (short)(Val[1] * Val[3] >> 8), (short)(Val[2] * Val[3] >> 8)); + EndPoints[1] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[1], (short)Val[2]); + + break; + } + + case 8: + { + uint[] Val = ReadUintColorValues(6, ColorValues, ref ColorValuesPosition); + + if (Val[1] + Val[3] + Val[5] >= Val[0] + Val[2] + Val[4]) + { + EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); + EndPoints[1] = new ASTCPixel(0xFF, (short)Val[1], (short)Val[3], (short)Val[5]); + } + else + { + EndPoints[0] = ASTCPixel.BlueContract(0xFF, (short)Val[1], (short)Val[3], (short)Val[5]); + EndPoints[1] = ASTCPixel.BlueContract(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); + } + + break; + } + + case 9: + { + int[] Val = ReadIntColorValues(6, ColorValues, ref ColorValuesPosition); + + BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); + BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); + BitArrayStream.BitTransferSigned(ref Val[5], ref Val[4]); + + if (Val[1] + Val[3] + Val[5] >= 0) + { + EndPoints[0] = new ASTCPixel(0xFF, (short)Val[0], (short)Val[2], (short)Val[4]); + EndPoints[1] = new ASTCPixel(0xFF, (short)(Val[0] + Val[1]), (short)(Val[2] + Val[3]), (short)(Val[4] + Val[5])); + } + else + { + EndPoints[0] = ASTCPixel.BlueContract(0xFF, Val[0] + Val[1], Val[2] + Val[3], Val[4] + Val[5]); + EndPoints[1] = ASTCPixel.BlueContract(0xFF, Val[0], Val[2], Val[4]); + } + + EndPoints[0].ClampByte(); + EndPoints[1].ClampByte(); + + break; + } + + case 10: + { + uint[] Val = ReadUintColorValues(6, ColorValues, ref ColorValuesPosition); + + EndPoints[0] = new ASTCPixel((short)Val[4], (short)(Val[0] * Val[3] >> 8), (short)(Val[1] * Val[3] >> 8), (short)(Val[2] * Val[3] >> 8)); + EndPoints[1] = new ASTCPixel((short)Val[5], (short)Val[0], (short)Val[1], (short)Val[2]); + + break; + } + + case 12: + { + uint[] Val = ReadUintColorValues(8, ColorValues, ref ColorValuesPosition); + + if (Val[1] + Val[3] + Val[5] >= Val[0] + Val[2] + Val[4]) + { + EndPoints[0] = new ASTCPixel((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); + EndPoints[1] = new ASTCPixel((short)Val[7], (short)Val[1], (short)Val[3], (short)Val[5]); + } + else + { + EndPoints[0] = ASTCPixel.BlueContract((short)Val[7], (short)Val[1], (short)Val[3], (short)Val[5]); + EndPoints[1] = ASTCPixel.BlueContract((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); + } + + break; + } + + case 13: + { + int[] Val = ReadIntColorValues(8, ColorValues, ref ColorValuesPosition); + + BitArrayStream.BitTransferSigned(ref Val[1], ref Val[0]); + BitArrayStream.BitTransferSigned(ref Val[3], ref Val[2]); + BitArrayStream.BitTransferSigned(ref Val[5], ref Val[4]); + BitArrayStream.BitTransferSigned(ref Val[7], ref Val[6]); + + if (Val[1] + Val[3] + Val[5] >= 0) + { + EndPoints[0] = new ASTCPixel((short)Val[6], (short)Val[0], (short)Val[2], (short)Val[4]); + EndPoints[1] = new ASTCPixel((short)(Val[7] + Val[6]), (short)(Val[0] + Val[1]), (short)(Val[2] + Val[3]), (short)(Val[4] + Val[5])); + } + else + { + EndPoints[0] = ASTCPixel.BlueContract(Val[6] + Val[7], Val[0] + Val[1], Val[2] + Val[3], Val[4] + Val[5]); + EndPoints[1] = ASTCPixel.BlueContract(Val[6], Val[0], Val[2], Val[4]); + } + + EndPoints[0].ClampByte(); + EndPoints[1].ClampByte(); + + break; + } + + default: + throw new ASTCDecoderException("Unsupported color endpoint mode (is it HDR?)"); + } + } + + static void DecodeColorValues( + int[] OutputValues, + byte[] InputData, + uint[] Modes, + int NumberPartitions, + int NumberBitsForColorData) + { + // First figure out how many color values we have + int NumberValues = 0; + + for (int i = 0; i < NumberPartitions; i++) + { + NumberValues += (int)((Modes[i] >> 2) + 1) << 1; + } + + // Then based on the number of values and the remaining number of bits, + // figure out the max value for each of them... + int Range = 256; + + while (--Range > 0) + { + IntegerEncoded IntEncoded = IntegerEncoded.CreateEncoding(Range); + int BitLength = IntEncoded.GetBitLength(NumberValues); + + if (BitLength <= NumberBitsForColorData) + { + // Find the smallest possible range that matches the given encoding + while (--Range > 0) + { + IntegerEncoded NewIntEncoded = IntegerEncoded.CreateEncoding(Range); + if (!NewIntEncoded.MatchesEncoding(IntEncoded)) + { + break; + } + } + + // Return to last matching range. + Range++; + break; + } + } + + // We now have enough to decode our integer sequence. + List IntegerEncodedSequence = new List(); + BitArrayStream ColorBitStream = new BitArrayStream(new BitArray(InputData)); + + IntegerEncoded.DecodeIntegerSequence(IntegerEncodedSequence, ColorBitStream, Range, NumberValues); + + // Once we have the decoded values, we need to dequantize them to the 0-255 range + // This procedure is outlined in ASTC spec C.2.13 + int OutputIndices = 0; + + foreach (IntegerEncoded IntEncoded in IntegerEncodedSequence) + { + int BitLength = IntEncoded.NumberBits; + int BitValue = IntEncoded.BitValue; + + Debug.Assert(BitLength >= 1); + + int A = 0, B = 0, C = 0, D = 0; + // A is just the lsb replicated 9 times. + A = BitArrayStream.Replicate(BitValue & 1, 1, 9); + + switch (IntEncoded.GetEncoding()) + { + case IntegerEncoded.EIntegerEncoding.JustBits: + { + OutputValues[OutputIndices++] = BitArrayStream.Replicate(BitValue, BitLength, 8); + + break; + } + + case IntegerEncoded.EIntegerEncoding.Trit: + { + D = IntEncoded.TritValue; + + switch (BitLength) + { + case 1: + { + C = 204; + + break; + } + + case 2: + { + C = 93; + // B = b000b0bb0 + int b = (BitValue >> 1) & 1; + B = (b << 8) | (b << 4) | (b << 2) | (b << 1); + + break; + } + + case 3: + { + C = 44; + // B = cb000cbcb + int cb = (BitValue >> 1) & 3; + B = (cb << 7) | (cb << 2) | cb; + + break; + } + + + case 4: + { + C = 22; + // B = dcb000dcb + int dcb = (BitValue >> 1) & 7; + B = (dcb << 6) | dcb; + + break; + } + + case 5: + { + C = 11; + // B = edcb000ed + int edcb = (BitValue >> 1) & 0xF; + B = (edcb << 5) | (edcb >> 2); + + break; + } + + case 6: + { + C = 5; + // B = fedcb000f + int fedcb = (BitValue >> 1) & 0x1F; + B = (fedcb << 4) | (fedcb >> 4); + + break; + } + + default: + throw new ASTCDecoderException("Unsupported trit encoding for color values!"); + } + + break; + } + + case IntegerEncoded.EIntegerEncoding.Quint: + { + D = IntEncoded.QuintValue; + + switch (BitLength) + { + case 1: + { + C = 113; + + break; + } + + case 2: + { + C = 54; + // B = b0000bb00 + int b = (BitValue >> 1) & 1; + B = (b << 8) | (b << 3) | (b << 2); + + break; + } + + case 3: + { + C = 26; + // B = cb0000cbc + int cb = (BitValue >> 1) & 3; + B = (cb << 7) | (cb << 1) | (cb >> 1); + + break; + } + + case 4: + { + C = 13; + // B = dcb0000dc + int dcb = (BitValue >> 1) & 7; + B = (dcb << 6) | (dcb >> 1); + + break; + } + + case 5: + { + C = 6; + // B = edcb0000e + int edcb = (BitValue >> 1) & 0xF; + B = (edcb << 5) | (edcb >> 3); + + break; + } + + default: + throw new ASTCDecoderException("Unsupported quint encoding for color values!"); + } + break; + } + } + + if (IntEncoded.GetEncoding() != IntegerEncoded.EIntegerEncoding.JustBits) + { + int T = D * C + B; + T ^= A; + T = (A & 0x80) | (T >> 2); + + OutputValues[OutputIndices++] = T; + } + } + + // Make sure that each of our values is in the proper range... + for (int i = 0; i < NumberValues; i++) + { + Debug.Assert(OutputValues[i] <= 255); + } + } + + static void FillVoidExtentLDR(BitArrayStream BitStream, int[] OutputBuffer, int BlockWidth, int BlockHeight) + { + // Don't actually care about the void extent, just read the bits... + for (int i = 0; i < 4; ++i) + { + BitStream.ReadBits(13); + } + + // Decode the RGBA components and renormalize them to the range [0, 255] + ushort R = (ushort)BitStream.ReadBits(16); + ushort G = (ushort)BitStream.ReadBits(16); + ushort B = (ushort)BitStream.ReadBits(16); + ushort A = (ushort)BitStream.ReadBits(16); + + int RGBA = (R >> 8) | (G & 0xFF00) | ((B) & 0xFF00) << 8 | ((A) & 0xFF00) << 16; + + for (int j = 0; j < BlockHeight; j++) + { + for (int i = 0; i < BlockWidth; i++) + { + OutputBuffer[j * BlockWidth + i] = RGBA; + } + } + } + + static TexelWeightParams DecodeBlockInfo(BitArrayStream BitStream) + { + TexelWeightParams TexelParams = new TexelWeightParams(); + + // Read the entire block mode all at once + ushort ModeBits = (ushort)BitStream.ReadBits(11); + + // Does this match the void extent block mode? + if ((ModeBits & 0x01FF) == 0x1FC) + { + if ((ModeBits & 0x200) != 0) + { + TexelParams.VoidExtentHDR = true; + } + else + { + TexelParams.VoidExtentLDR = true; + } + + // Next two bits must be one. + if ((ModeBits & 0x400) == 0 || BitStream.ReadBits(1) == 0) + { + TexelParams.Error = true; + } + + return TexelParams; + } + + // First check if the last four bits are zero + if ((ModeBits & 0xF) == 0) + { + TexelParams.Error = true; + return TexelParams; + } + + // If the last two bits are zero, then if bits + // [6-8] are all ones, this is also reserved. + if ((ModeBits & 0x3) == 0 && (ModeBits & 0x1C0) == 0x1C0) + { + TexelParams.Error = true; + + return TexelParams; + } + + // Otherwise, there is no error... Figure out the layout + // of the block mode. Layout is determined by a number + // between 0 and 9 corresponding to table C.2.8 of the + // ASTC spec. + int Layout = 0; + + if ((ModeBits & 0x1) != 0 || (ModeBits & 0x2) != 0) + { + // layout is in [0-4] + if ((ModeBits & 0x8) != 0) + { + // layout is in [2-4] + if ((ModeBits & 0x4) != 0) + { + // layout is in [3-4] + if ((ModeBits & 0x100) != 0) + { + Layout = 4; + } + else + { + Layout = 3; + } + } + else + { + Layout = 2; + } + } + else + { + // layout is in [0-1] + if ((ModeBits & 0x4) != 0) + { + Layout = 1; + } + else + { + Layout = 0; + } + } + } + else + { + // layout is in [5-9] + if ((ModeBits & 0x100) != 0) + { + // layout is in [7-9] + if ((ModeBits & 0x80) != 0) + { + // layout is in [7-8] + Debug.Assert((ModeBits & 0x40) == 0); + + if ((ModeBits & 0x20) != 0) + { + Layout = 8; + } + else + { + Layout = 7; + } + } + else + { + Layout = 9; + } + } + else + { + // layout is in [5-6] + if ((ModeBits & 0x80) != 0) + { + Layout = 6; + } + else + { + Layout = 5; + } + } + } + + Debug.Assert(Layout < 10); + + // Determine R + int R = (ModeBits >> 4) & 1; + if (Layout < 5) + { + R |= (ModeBits & 0x3) << 1; + } + else + { + R |= (ModeBits & 0xC) >> 1; + } + + Debug.Assert(2 <= R && R <= 7); + + // Determine width & height + switch (Layout) + { + case 0: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 7) & 0x3; + + TexelParams.Width = B + 4; + TexelParams.Height = A + 2; + + break; + } + + case 1: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 7) & 0x3; + + TexelParams.Width = B + 8; + TexelParams.Height = A + 2; + + break; + } + + case 2: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 7) & 0x3; + + TexelParams.Width = A + 2; + TexelParams.Height = B + 8; + + break; + } + + case 3: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 7) & 0x1; + + TexelParams.Width = A + 2; + TexelParams.Height = B + 6; + + break; + } + + case 4: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 7) & 0x1; + + TexelParams.Width = B + 2; + TexelParams.Height = A + 2; + + break; + } + + case 5: + { + int A = (ModeBits >> 5) & 0x3; + + TexelParams.Width = 12; + TexelParams.Height = A + 2; + + break; + } + + case 6: + { + int A = (ModeBits >> 5) & 0x3; + + TexelParams.Width = A + 2; + TexelParams.Height = 12; + + break; + } + + case 7: + { + TexelParams.Width = 6; + TexelParams.Height = 10; + + break; + } + + case 8: + { + TexelParams.Width = 10; + TexelParams.Height = 6; + break; + } + + case 9: + { + int A = (ModeBits >> 5) & 0x3; + int B = (ModeBits >> 9) & 0x3; + + TexelParams.Width = A + 6; + TexelParams.Height = B + 6; + + break; + } + + default: + //Don't know this layout... + TexelParams.Error = true; + break; + } + + // Determine whether or not we're using dual planes + // and/or high precision layouts. + bool D = ((Layout != 9) && ((ModeBits & 0x400) != 0)); + bool H = (Layout != 9) && ((ModeBits & 0x200) != 0); + + if (H) + { + int[] MaxWeights = { 9, 11, 15, 19, 23, 31 }; + TexelParams.MaxWeight = MaxWeights[R - 2]; + } + else + { + int[] MaxWeights = { 1, 2, 3, 4, 5, 7 }; + TexelParams.MaxWeight = MaxWeights[R - 2]; + } + + TexelParams.DualPlane = D; + + return TexelParams; + } + } +} diff --git a/Ryujinx.Graphics/Gal/Texture/ASTCPixel.cs b/Ryujinx.Graphics/Texture/ASTCPixel.cs similarity index 95% rename from Ryujinx.Graphics/Gal/Texture/ASTCPixel.cs rename to Ryujinx.Graphics/Texture/ASTCPixel.cs index 4a2998186..c43eaf938 100644 --- a/Ryujinx.Graphics/Gal/Texture/ASTCPixel.cs +++ b/Ryujinx.Graphics/Texture/ASTCPixel.cs @@ -1,138 +1,138 @@ -using System; -using System.Diagnostics; - -namespace Ryujinx.Graphics.Gal.Texture -{ - class ASTCPixel - { - public short R { get; set; } - public short G { get; set; } - public short B { get; set; } - public short A { get; set; } - - byte[] BitDepth = new byte[4]; - - public ASTCPixel(short _A, short _R, short _G, short _B) - { - A = _A; - R = _R; - G = _G; - B = _B; - - for (int i = 0; i < 4; i++) - BitDepth[i] = 8; - } - - public void ClampByte() - { - R = Math.Min(Math.Max(R, (short)0), (short)255); - G = Math.Min(Math.Max(G, (short)0), (short)255); - B = Math.Min(Math.Max(B, (short)0), (short)255); - A = Math.Min(Math.Max(A, (short)0), (short)255); - } - - public short GetComponent(int Index) - { - switch(Index) - { - case 0: return A; - case 1: return R; - case 2: return G; - case 3: return B; - } - - return 0; - } - - public void SetComponent(int Index, int Value) - { - switch (Index) - { - case 0: - A = (short)Value; - break; - case 1: - R = (short)Value; - break; - case 2: - G = (short)Value; - break; - case 3: - B = (short)Value; - break; - } - } - - public void ChangeBitDepth(byte[] Depth) - { - for(int i = 0; i< 4; i++) - { - int Value = ChangeBitDepth(GetComponent(i), BitDepth[i], Depth[i]); - - SetComponent(i, Value); - BitDepth[i] = Depth[i]; - } - } - - short ChangeBitDepth(short Value, byte OldDepth, byte NewDepth) - { - Debug.Assert(NewDepth <= 8); - Debug.Assert(OldDepth <= 8); - - if (OldDepth == NewDepth) - { - // Do nothing - return Value; - } - else if (OldDepth == 0 && NewDepth != 0) - { - return (short)((1 << NewDepth) - 1); - } - else if (NewDepth > OldDepth) - { - return (short)BitArrayStream.Replicate(Value, OldDepth, NewDepth); - } - else - { - // oldDepth > newDepth - if (NewDepth == 0) - { - return 0xFF; - } - else - { - byte BitsWasted = (byte)(OldDepth - NewDepth); - short TempValue = Value; - - TempValue = (short)((TempValue + (1 << (BitsWasted - 1))) >> BitsWasted); - TempValue = Math.Min(Math.Max((short)0, TempValue), (short)((1 << NewDepth) - 1)); - - return (byte)(TempValue); - } - } - } - - public int Pack() - { - ASTCPixel NewPixel = new ASTCPixel(A, R, G, B); - byte[] eightBitDepth = { 8, 8, 8, 8 }; - - NewPixel.ChangeBitDepth(eightBitDepth); - - return (byte)NewPixel.A << 24 | - (byte)NewPixel.B << 16 | - (byte)NewPixel.G << 8 | - (byte)NewPixel.R << 0; - } - - // Adds more precision to the blue channel as described - // in C.2.14 - public static ASTCPixel BlueContract(int a, int r, int g, int b) - { - return new ASTCPixel((short)(a), - (short)((r + b) >> 1), - (short)((g + b) >> 1), - (short)(b)); - } - } -} +using System; +using System.Diagnostics; + +namespace Ryujinx.Graphics.Texture +{ + class ASTCPixel + { + public short R { get; set; } + public short G { get; set; } + public short B { get; set; } + public short A { get; set; } + + byte[] BitDepth = new byte[4]; + + public ASTCPixel(short _A, short _R, short _G, short _B) + { + A = _A; + R = _R; + G = _G; + B = _B; + + for (int i = 0; i < 4; i++) + BitDepth[i] = 8; + } + + public void ClampByte() + { + R = Math.Min(Math.Max(R, (short)0), (short)255); + G = Math.Min(Math.Max(G, (short)0), (short)255); + B = Math.Min(Math.Max(B, (short)0), (short)255); + A = Math.Min(Math.Max(A, (short)0), (short)255); + } + + public short GetComponent(int Index) + { + switch(Index) + { + case 0: return A; + case 1: return R; + case 2: return G; + case 3: return B; + } + + return 0; + } + + public void SetComponent(int Index, int Value) + { + switch (Index) + { + case 0: + A = (short)Value; + break; + case 1: + R = (short)Value; + break; + case 2: + G = (short)Value; + break; + case 3: + B = (short)Value; + break; + } + } + + public void ChangeBitDepth(byte[] Depth) + { + for(int i = 0; i< 4; i++) + { + int Value = ChangeBitDepth(GetComponent(i), BitDepth[i], Depth[i]); + + SetComponent(i, Value); + BitDepth[i] = Depth[i]; + } + } + + short ChangeBitDepth(short Value, byte OldDepth, byte NewDepth) + { + Debug.Assert(NewDepth <= 8); + Debug.Assert(OldDepth <= 8); + + if (OldDepth == NewDepth) + { + // Do nothing + return Value; + } + else if (OldDepth == 0 && NewDepth != 0) + { + return (short)((1 << NewDepth) - 1); + } + else if (NewDepth > OldDepth) + { + return (short)BitArrayStream.Replicate(Value, OldDepth, NewDepth); + } + else + { + // oldDepth > newDepth + if (NewDepth == 0) + { + return 0xFF; + } + else + { + byte BitsWasted = (byte)(OldDepth - NewDepth); + short TempValue = Value; + + TempValue = (short)((TempValue + (1 << (BitsWasted - 1))) >> BitsWasted); + TempValue = Math.Min(Math.Max((short)0, TempValue), (short)((1 << NewDepth) - 1)); + + return (byte)(TempValue); + } + } + } + + public int Pack() + { + ASTCPixel NewPixel = new ASTCPixel(A, R, G, B); + byte[] eightBitDepth = { 8, 8, 8, 8 }; + + NewPixel.ChangeBitDepth(eightBitDepth); + + return (byte)NewPixel.A << 24 | + (byte)NewPixel.B << 16 | + (byte)NewPixel.G << 8 | + (byte)NewPixel.R << 0; + } + + // Adds more precision to the blue channel as described + // in C.2.14 + public static ASTCPixel BlueContract(int a, int r, int g, int b) + { + return new ASTCPixel((short)(a), + (short)((r + b) >> 1), + (short)((g + b) >> 1), + (short)(b)); + } + } +} diff --git a/Ryujinx.Graphics/Gal/Texture/BitArrayStream.cs b/Ryujinx.Graphics/Texture/BitArrayStream.cs similarity index 95% rename from Ryujinx.Graphics/Gal/Texture/BitArrayStream.cs rename to Ryujinx.Graphics/Texture/BitArrayStream.cs index eb2204c4b..2a8ed0910 100644 --- a/Ryujinx.Graphics/Gal/Texture/BitArrayStream.cs +++ b/Ryujinx.Graphics/Texture/BitArrayStream.cs @@ -1,120 +1,121 @@ -using System; -using System.Collections; - -namespace Ryujinx.Graphics.Gal.Texture -{ - public class BitArrayStream - { - public BitArray BitsArray; - public int Position { get; private set; } - - public BitArrayStream(BitArray BitArray) - { - BitsArray = BitArray; - Position = 0; - } - - public short ReadBits(int Length) - { - int RetValue = 0; - for (int i = Position; i < Position + Length; i++) - { - if (BitsArray[i]) - { - RetValue |= 1 << (i - Position); - } - } - - Position += Length; - return (short)RetValue; - } - - public int ReadBits(int Start, int End) - { - int RetValue = 0; - for (int i = Start; i <= End; i++) - { - if (BitsArray[i]) - { - RetValue |= 1 << (i - Start); - } - } - - return RetValue; - } - - public int ReadBit(int Index) - { - return Convert.ToInt32(BitsArray[Index]); - } - - public void WriteBits(int Value, int Length) - { - for (int i = Position; i < Position + Length; i++) - { - BitsArray[i] = ((Value >> (i - Position)) & 1) != 0; - } - - Position += Length; - } - - public byte[] ToByteArray() - { - byte[] RetArray = new byte[(BitsArray.Length + 7) / 8]; - BitsArray.CopyTo(RetArray, 0); - return RetArray; - } - - public static int Replicate(int Value, int NumberBits, int ToBit) - { - if (NumberBits == 0) return 0; - if (ToBit == 0) return 0; - - int TempValue = Value & ((1 << NumberBits) - 1); - int RetValue = TempValue; - int ResLength = NumberBits; - - while (ResLength < ToBit) - { - int Comp = 0; - if (NumberBits > ToBit - ResLength) - { - int NewShift = ToBit - ResLength; - Comp = NumberBits - NewShift; - NumberBits = NewShift; - } - RetValue <<= NumberBits; - RetValue |= TempValue >> Comp; - ResLength += NumberBits; - } - return RetValue; - } - - public static int PopCnt(int Number) - { - int Counter; - for (Counter = 0; Number != 0; Counter++) - { - Number &= Number - 1; - } - return Counter; - } - - public static void Swap(ref T lhs, ref T rhs) - { - T Temp = lhs; - lhs = rhs; - rhs = Temp; - } - - // Transfers a bit as described in C.2.14 - public static void BitTransferSigned(ref int a, ref int b) - { - b >>= 1; - b |= a & 0x80; - a >>= 1; - a &= 0x3F; - if ((a & 0x20) != 0) a -= 0x40; - } - } -} +using System; +using System.Collections; + +namespace Ryujinx.Graphics.Texture +{ + public class BitArrayStream + { + public BitArray BitsArray; + + public int Position { get; private set; } + + public BitArrayStream(BitArray BitArray) + { + BitsArray = BitArray; + Position = 0; + } + + public short ReadBits(int Length) + { + int RetValue = 0; + for (int i = Position; i < Position + Length; i++) + { + if (BitsArray[i]) + { + RetValue |= 1 << (i - Position); + } + } + + Position += Length; + return (short)RetValue; + } + + public int ReadBits(int Start, int End) + { + int RetValue = 0; + for (int i = Start; i <= End; i++) + { + if (BitsArray[i]) + { + RetValue |= 1 << (i - Start); + } + } + + return RetValue; + } + + public int ReadBit(int Index) + { + return Convert.ToInt32(BitsArray[Index]); + } + + public void WriteBits(int Value, int Length) + { + for (int i = Position; i < Position + Length; i++) + { + BitsArray[i] = ((Value >> (i - Position)) & 1) != 0; + } + + Position += Length; + } + + public byte[] ToByteArray() + { + byte[] RetArray = new byte[(BitsArray.Length + 7) / 8]; + BitsArray.CopyTo(RetArray, 0); + return RetArray; + } + + public static int Replicate(int Value, int NumberBits, int ToBit) + { + if (NumberBits == 0) return 0; + if (ToBit == 0) return 0; + + int TempValue = Value & ((1 << NumberBits) - 1); + int RetValue = TempValue; + int ResLength = NumberBits; + + while (ResLength < ToBit) + { + int Comp = 0; + if (NumberBits > ToBit - ResLength) + { + int NewShift = ToBit - ResLength; + Comp = NumberBits - NewShift; + NumberBits = NewShift; + } + RetValue <<= NumberBits; + RetValue |= TempValue >> Comp; + ResLength += NumberBits; + } + return RetValue; + } + + public static int PopCnt(int Number) + { + int Counter; + for (Counter = 0; Number != 0; Counter++) + { + Number &= Number - 1; + } + return Counter; + } + + public static void Swap(ref T lhs, ref T rhs) + { + T Temp = lhs; + lhs = rhs; + rhs = Temp; + } + + // Transfers a bit as described in C.2.14 + public static void BitTransferSigned(ref int a, ref int b) + { + b >>= 1; + b |= a & 0x80; + a >>= 1; + a &= 0x3F; + if ((a & 0x20) != 0) a -= 0x40; + } + } +} diff --git a/Ryujinx.HLE/Gpu/Texture/BlockLinearSwizzle.cs b/Ryujinx.Graphics/Texture/BlockLinearSwizzle.cs similarity index 97% rename from Ryujinx.HLE/Gpu/Texture/BlockLinearSwizzle.cs rename to Ryujinx.Graphics/Texture/BlockLinearSwizzle.cs index e66d76136..9451291e9 100644 --- a/Ryujinx.HLE/Gpu/Texture/BlockLinearSwizzle.cs +++ b/Ryujinx.Graphics/Texture/BlockLinearSwizzle.cs @@ -1,6 +1,6 @@ using System; -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { class BlockLinearSwizzle : ISwizzle { diff --git a/Ryujinx.HLE/Gpu/Texture/ISwizzle.cs b/Ryujinx.Graphics/Texture/ISwizzle.cs similarity index 70% rename from Ryujinx.HLE/Gpu/Texture/ISwizzle.cs rename to Ryujinx.Graphics/Texture/ISwizzle.cs index 222aab163..583fc20c5 100644 --- a/Ryujinx.HLE/Gpu/Texture/ISwizzle.cs +++ b/Ryujinx.Graphics/Texture/ISwizzle.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { interface ISwizzle { diff --git a/Ryujinx.Graphics/Texture/ImageConverter.cs b/Ryujinx.Graphics/Texture/ImageConverter.cs new file mode 100644 index 000000000..89529061f --- /dev/null +++ b/Ryujinx.Graphics/Texture/ImageConverter.cs @@ -0,0 +1,24 @@ +namespace Ryujinx.Graphics.Texture +{ + static class ImageConverter + { + public static byte[] G8R8ToR8G8( + byte[] Data, + int Width, + int Height, + int Depth) + { + int Texels = Width * Height * Depth; + + byte[] Output = new byte[Texels * 2]; + + for (int Texel = 0; Texel < Texels; Texel++) + { + Output[Texel * 2 + 0] = Data[Texel * 2 + 1]; + Output[Texel * 2 + 1] = Data[Texel * 2 + 0]; + } + + return Output; + } + } +} \ No newline at end of file diff --git a/Ryujinx.Graphics/Texture/ImageUtils.cs b/Ryujinx.Graphics/Texture/ImageUtils.cs new file mode 100644 index 000000000..ccea43ec1 --- /dev/null +++ b/Ryujinx.Graphics/Texture/ImageUtils.cs @@ -0,0 +1,357 @@ +using Ryujinx.Graphics.Gal; +using System; +using System.Collections.Generic; + +namespace Ryujinx.Graphics.Texture +{ + static class ImageUtils + { + struct ImageDescriptor + { + public TextureReaderDelegate Reader; + + public bool HasColor; + public bool HasDepth; + public bool HasStencil; + + public bool Compressed; + + public ImageDescriptor( + TextureReaderDelegate Reader, + bool HasColor, + bool HasDepth, + bool HasStencil, + bool Compressed) + { + this.Reader = Reader; + this.HasColor = HasColor; + this.HasDepth = HasDepth; + this.HasStencil = HasStencil; + this.Compressed = Compressed; + } + } + + private const GalImageFormat Snorm = GalImageFormat.Snorm; + private const GalImageFormat Unorm = GalImageFormat.Unorm; + private const GalImageFormat Sint = GalImageFormat.Sint; + private const GalImageFormat Uint = GalImageFormat.Uint; + private const GalImageFormat Sfloat = GalImageFormat.Sfloat; + + private static readonly Dictionary s_TextureTable = + new Dictionary() + { + { GalTextureFormat.R32G32B32A32, GalImageFormat.R32G32B32A32 | Sint | Uint | Sfloat }, + { GalTextureFormat.R16G16B16A16, GalImageFormat.R16G16B16A16 | Snorm | Unorm | Sint | Uint | Sfloat }, + { GalTextureFormat.R32G32, GalImageFormat.R32G32 | Sint | Uint | Sfloat }, + { GalTextureFormat.A8B8G8R8, GalImageFormat.A8B8G8R8 | Snorm | Unorm | Sint | Uint }, + { GalTextureFormat.A2B10G10R10, GalImageFormat.A2B10G10R10 | Snorm | Unorm | Sint | Uint }, + { GalTextureFormat.G8R8, GalImageFormat.G8R8 | Snorm | Unorm | Sint | Uint }, + { GalTextureFormat.R16, GalImageFormat.R16 | Snorm | Unorm | Sint | Uint | Sfloat }, + { GalTextureFormat.R8, GalImageFormat.R8 | Snorm | Unorm | Sint | Uint }, + { GalTextureFormat.R32, GalImageFormat.R32 | Sint | Uint | Sfloat }, + { GalTextureFormat.A4B4G4R4, GalImageFormat.A4B4G4R4 | Unorm }, + { GalTextureFormat.A1B5G5R5, GalImageFormat.A1R5G5B5 | Unorm }, + { GalTextureFormat.B5G6R5, GalImageFormat.B5G6R5 | Unorm }, + { GalTextureFormat.BF10GF11RF11, GalImageFormat.B10G11R11 | Sfloat }, + { GalTextureFormat.Z24S8, GalImageFormat.D24_S8 | Unorm }, + { GalTextureFormat.ZF32, GalImageFormat.D32 | Sfloat }, + { GalTextureFormat.ZF32_X24S8, GalImageFormat.D32_S8 | Unorm }, + + //Compressed formats + { GalTextureFormat.BC6H_SF16, GalImageFormat.BC6H_SF16 | Unorm }, + { GalTextureFormat.BC6H_UF16, GalImageFormat.BC6H_UF16 | Unorm }, + { GalTextureFormat.BC7U, GalImageFormat.BC7 | Unorm }, + { GalTextureFormat.BC1, GalImageFormat.BC1_RGBA | Unorm }, + { GalTextureFormat.BC2, GalImageFormat.BC2 | Unorm }, + { GalTextureFormat.BC3, GalImageFormat.BC3 | Unorm }, + { GalTextureFormat.BC4, GalImageFormat.BC4 | Unorm | Snorm }, + { GalTextureFormat.BC5, GalImageFormat.BC5 | Unorm | Snorm }, + { GalTextureFormat.Astc2D4x4, GalImageFormat.ASTC_4x4 | Unorm }, + { GalTextureFormat.Astc2D5x5, GalImageFormat.ASTC_5x5 | Unorm }, + { GalTextureFormat.Astc2D6x6, GalImageFormat.ASTC_6x6 | Unorm }, + { GalTextureFormat.Astc2D8x8, GalImageFormat.ASTC_8x8 | Unorm }, + { GalTextureFormat.Astc2D10x10, GalImageFormat.ASTC_10x10 | Unorm }, + { GalTextureFormat.Astc2D12x12, GalImageFormat.ASTC_12x12 | Unorm }, + { GalTextureFormat.Astc2D5x4, GalImageFormat.ASTC_5x4 | Unorm }, + { GalTextureFormat.Astc2D6x5, GalImageFormat.ASTC_6x5 | Unorm }, + { GalTextureFormat.Astc2D8x6, GalImageFormat.ASTC_8x6 | Unorm }, + { GalTextureFormat.Astc2D10x8, GalImageFormat.ASTC_10x8 | Unorm }, + { GalTextureFormat.Astc2D12x10, GalImageFormat.ASTC_12x10 | Unorm }, + { GalTextureFormat.Astc2D8x5, GalImageFormat.ASTC_8x5 | Unorm }, + { GalTextureFormat.Astc2D10x5, GalImageFormat.ASTC_10x5 | Unorm }, + { GalTextureFormat.Astc2D10x6, GalImageFormat.ASTC_10x6 | Unorm } + }; + + private static readonly Dictionary s_ImageTable = + new Dictionary() + { + { GalImageFormat.R32G32B32A32, new ImageDescriptor(TextureReader.Read16Bpp, true, false, false, false) }, + { GalImageFormat.R16G16B16A16, new ImageDescriptor(TextureReader.Read8Bpp, true, false, false, false) }, + { GalImageFormat.R32G32, new ImageDescriptor(TextureReader.Read8Bpp, true, false, false, false) }, + { GalImageFormat.A8B8G8R8, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.A2B10G10R10, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.R32, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.A4B4G4R4, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) }, + { GalImageFormat.BC6H_SF16, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.BC6H_UF16, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.A1R5G5B5, new ImageDescriptor(TextureReader.Read5551, true, false, false, false) }, + { GalImageFormat.B5G6R5, new ImageDescriptor(TextureReader.Read565, true, false, false, false) }, + { GalImageFormat.BC7, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.R16G16, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.R8G8, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) }, + { GalImageFormat.G8R8, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) }, + { GalImageFormat.R16, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) }, + { GalImageFormat.R8, new ImageDescriptor(TextureReader.Read1Bpp, true, false, false, false) }, + { GalImageFormat.B10G11R11, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.A8B8G8R8_SRGB, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) }, + { GalImageFormat.BC1_RGBA, new ImageDescriptor(TextureReader.Read8Bpt4x4, true, false, false, true) }, + { GalImageFormat.BC2, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.BC3, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.BC4, new ImageDescriptor(TextureReader.Read8Bpt4x4, true, false, false, true) }, + { GalImageFormat.BC5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.ASTC_4x4, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) }, + { GalImageFormat.ASTC_5x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture5x5, true, false, false, true) }, + { GalImageFormat.ASTC_6x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture6x6, true, false, false, true) }, + { GalImageFormat.ASTC_8x8, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x8, true, false, false, true) }, + { GalImageFormat.ASTC_10x10, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x10, true, false, false, true) }, + { GalImageFormat.ASTC_12x12, new ImageDescriptor(TextureReader.Read16BptCompressedTexture12x12, true, false, false, true) }, + { GalImageFormat.ASTC_5x4, new ImageDescriptor(TextureReader.Read16BptCompressedTexture5x4, true, false, false, true) }, + { GalImageFormat.ASTC_6x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture6x5, true, false, false, true) }, + { GalImageFormat.ASTC_8x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x6, true, false, false, true) }, + { GalImageFormat.ASTC_10x8, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x8, true, false, false, true) }, + { GalImageFormat.ASTC_12x10, new ImageDescriptor(TextureReader.Read16BptCompressedTexture12x10, true, false, false, true) }, + { GalImageFormat.ASTC_8x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x5, true, false, false, true) }, + { GalImageFormat.ASTC_10x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x5, true, false, false, true) }, + { GalImageFormat.ASTC_10x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x6, true, false, false, true) }, + + { GalImageFormat.D24_S8, new ImageDescriptor(TextureReader.Read4Bpp, false, true, true, false) }, + { GalImageFormat.D32, new ImageDescriptor(TextureReader.Read4Bpp, false, true, false, false) }, + { GalImageFormat.D16, new ImageDescriptor(TextureReader.Read2Bpp, false, true, false, false) }, + { GalImageFormat.D32_S8, new ImageDescriptor(TextureReader.Read8Bpp, false, true, true, false) }, + }; + + public static GalImageFormat ConvertTexture( + GalTextureFormat Format, + GalTextureType RType, + GalTextureType GType, + GalTextureType BType, + GalTextureType AType) + { + if (RType != GType || RType != BType || RType != AType) + { + throw new NotImplementedException("Per component types are not implemented"); + } + + if (!s_TextureTable.TryGetValue(Format, out GalImageFormat ImageFormat)) + { + throw new NotImplementedException("Texture with format " + ((int)Format).ToString("x2") + " not implemented"); + } + + GalTextureType Type = RType; + + GalImageFormat FormatType = GetFormatType(RType); + + if (ImageFormat.HasFlag(FormatType)) + { + return (ImageFormat & GalImageFormat.FormatMask) | FormatType; + } + else + { + throw new NotImplementedException("Texture with format " + Format + + " and component type " + Type + " is not implemented"); + } + } + + public static GalImageFormat ConvertSurface(GalSurfaceFormat Format) + { + switch (Format) + { + case GalSurfaceFormat.RGBA32Float: return GalImageFormat.R32G32B32A32 | Sfloat; + case GalSurfaceFormat.RGBA16Float: return GalImageFormat.R16G16B16A16 | Sfloat; + case GalSurfaceFormat.RG32Float: return GalImageFormat.R32G32 | Sfloat; + case GalSurfaceFormat.RG32Sint: return GalImageFormat.R32G32 | Sint; + case GalSurfaceFormat.RG32Uint: return GalImageFormat.R32G32 | Uint; + case GalSurfaceFormat.BGRA8Unorm: return GalImageFormat.R8G8B8A8 | Unorm; //Is this right? + case GalSurfaceFormat.BGRA8Srgb: return GalImageFormat.A8B8G8R8_SRGB; //This one might be wrong + case GalSurfaceFormat.RGB10A2Unorm: return GalImageFormat.A2B10G10R10 | Unorm; + case GalSurfaceFormat.RGBA8Unorm: return GalImageFormat.A8B8G8R8 | Unorm; + case GalSurfaceFormat.RGBA8Srgb: return GalImageFormat.A8B8G8R8_SRGB; + case GalSurfaceFormat.RGBA8Snorm: return GalImageFormat.A8B8G8R8 | Snorm; + case GalSurfaceFormat.RG16Snorm: return GalImageFormat.R16G16 | Snorm; + case GalSurfaceFormat.RG16Float: return GalImageFormat.R16G16 | Sfloat; + case GalSurfaceFormat.R11G11B10Float: return GalImageFormat.B10G11R11 | Sfloat; + case GalSurfaceFormat.R32Float: return GalImageFormat.R32 | Sfloat; + case GalSurfaceFormat.RG8Unorm: return GalImageFormat.R8G8 | Unorm; + case GalSurfaceFormat.RG8Snorm: return GalImageFormat.R8 | Snorm; + case GalSurfaceFormat.R16Float: return GalImageFormat.R16 | Sfloat; + case GalSurfaceFormat.R8Unorm: return GalImageFormat.R8 | Unorm; + } + + throw new NotImplementedException(Format.ToString()); + } + + public static GalImageFormat ConvertZeta(GalZetaFormat Format) + { + switch (Format) + { + case GalZetaFormat.Z32Float: return GalImageFormat.D32 | Sfloat; + case GalZetaFormat.S8Z24Unorm: return GalImageFormat.D24_S8 | Unorm; + case GalZetaFormat.Z16Unorm: return GalImageFormat.D16 | Unorm; + //This one might not be Uint, change when a texture uses this format + case GalZetaFormat.Z32S8X24Float: return GalImageFormat.D32_S8 | Uint; + } + + throw new NotImplementedException(Format.ToString()); + } + + public static TextureReaderDelegate GetReader(GalImageFormat Format) + { + return GetImageDescriptor(Format).Reader; + } + + public static int GetSize(GalImage Image) + { + switch (Image.Format & GalImageFormat.FormatMask) + { + case GalImageFormat.R32G32B32A32: + return Image.Width * Image.Height * 16; + + case GalImageFormat.R16G16B16A16: + case GalImageFormat.D32_S8: + case GalImageFormat.R32G32: + return Image.Width * Image.Height * 8; + + case GalImageFormat.A8B8G8R8: + case GalImageFormat.A8B8G8R8_SRGB: + case GalImageFormat.A2B10G10R10: + case GalImageFormat.R16G16: + case GalImageFormat.R32: + case GalImageFormat.D32: + case GalImageFormat.B10G11R11: + case GalImageFormat.D24_S8: + return Image.Width * Image.Height * 4; + + case GalImageFormat.B4G4R4A4: + case GalImageFormat.A1R5G5B5: + case GalImageFormat.B5G6R5: + case GalImageFormat.R8G8: + case GalImageFormat.R16: + case GalImageFormat.D16: + return Image.Width * Image.Height * 2; + + case GalImageFormat.R8: + return Image.Width * Image.Height; + + case GalImageFormat.BC1_RGBA: + case GalImageFormat.BC4: + { + return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 8); + } + + case GalImageFormat.BC6H_SF16: + case GalImageFormat.BC6H_UF16: + case GalImageFormat.BC7: + case GalImageFormat.BC2: + case GalImageFormat.BC3: + case GalImageFormat.BC5: + case GalImageFormat.ASTC_4x4: + return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 16); + + case GalImageFormat.ASTC_5x5: + return CompressedTextureSize(Image.Width, Image.Height, 5, 5, 16); + + case GalImageFormat.ASTC_6x6: + return CompressedTextureSize(Image.Width, Image.Height, 6, 6, 16); + + case GalImageFormat.ASTC_8x8: + return CompressedTextureSize(Image.Width, Image.Height, 8, 8, 16); + + case GalImageFormat.ASTC_10x10: + return CompressedTextureSize(Image.Width, Image.Height, 10, 10, 16); + + case GalImageFormat.ASTC_12x12: + return CompressedTextureSize(Image.Width, Image.Height, 12, 12, 16); + + case GalImageFormat.ASTC_5x4: + return CompressedTextureSize(Image.Width, Image.Height, 5, 4, 16); + + case GalImageFormat.ASTC_6x5: + return CompressedTextureSize(Image.Width, Image.Height, 6, 5, 16); + + case GalImageFormat.ASTC_8x6: + return CompressedTextureSize(Image.Width, Image.Height, 8, 6, 16); + + case GalImageFormat.ASTC_10x8: + return CompressedTextureSize(Image.Width, Image.Height, 10, 8, 16); + + case GalImageFormat.ASTC_12x10: + return CompressedTextureSize(Image.Width, Image.Height, 12, 10, 16); + + case GalImageFormat.ASTC_8x5: + return CompressedTextureSize(Image.Width, Image.Height, 8, 5, 16); + + case GalImageFormat.ASTC_10x5: + return CompressedTextureSize(Image.Width, Image.Height, 10, 5, 16); + + case GalImageFormat.ASTC_10x6: + return CompressedTextureSize(Image.Width, Image.Height, 10, 6, 16); + } + + throw new NotImplementedException((Image.Format & GalImageFormat.FormatMask).ToString()); + } + + public static bool HasColor(GalImageFormat Format) + { + return GetImageDescriptor(Format).HasColor; + } + + public static bool HasDepth(GalImageFormat Format) + { + return GetImageDescriptor(Format).HasDepth; + } + + public static bool HasStencil(GalImageFormat Format) + { + return GetImageDescriptor(Format).HasStencil; + } + + public static bool IsCompressed(GalImageFormat Format) + { + return GetImageDescriptor(Format).Compressed; + } + + private static ImageDescriptor GetImageDescriptor(GalImageFormat Format) + { + GalImageFormat TypeLess = (Format & GalImageFormat.FormatMask); + + if (s_ImageTable.TryGetValue(TypeLess, out ImageDescriptor Descriptor)) + { + return Descriptor; + } + + throw new NotImplementedException("Image with format " + TypeLess.ToString() + " not implemented"); + } + + private static GalImageFormat GetFormatType(GalTextureType Type) + { + switch (Type) + { + case GalTextureType.Snorm: return Snorm; + case GalTextureType.Unorm: return Unorm; + case GalTextureType.Sint: return Sint; + case GalTextureType.Uint: return Uint; + case GalTextureType.Float: return Sfloat; + + default: throw new NotImplementedException(((int)Type).ToString()); + } + } + + private static int CompressedTextureSize(int TextureWidth, int TextureHeight, int BlockWidth, int BlockHeight, int Bpb) + { + int W = (TextureWidth + (BlockWidth - 1)) / BlockWidth; + int H = (TextureHeight + (BlockHeight - 1)) / BlockHeight; + + return W * H * Bpb; + } + } +} \ No newline at end of file diff --git a/Ryujinx.Graphics/Gal/Texture/IntegerEncoded.cs b/Ryujinx.Graphics/Texture/IntegerEncoded.cs similarity index 96% rename from Ryujinx.Graphics/Gal/Texture/IntegerEncoded.cs rename to Ryujinx.Graphics/Texture/IntegerEncoded.cs index 0adabe17e..683cb7704 100644 --- a/Ryujinx.Graphics/Gal/Texture/IntegerEncoded.cs +++ b/Ryujinx.Graphics/Texture/IntegerEncoded.cs @@ -1,269 +1,269 @@ -using System.Collections; -using System.Collections.Generic; - -namespace Ryujinx.Graphics.Gal.Texture -{ - public struct IntegerEncoded - { - public enum EIntegerEncoding - { - JustBits, - Quint, - Trit - } - - EIntegerEncoding Encoding; - public int NumberBits { get; private set; } - public int BitValue { get; private set; } - public int TritValue { get; private set; } - public int QuintValue { get; private set; } - - public IntegerEncoded(EIntegerEncoding _Encoding, int NumBits) - { - Encoding = _Encoding; - NumberBits = NumBits; - BitValue = 0; - TritValue = 0; - QuintValue = 0; - } - - public bool MatchesEncoding(IntegerEncoded Other) - { - return Encoding == Other.Encoding && NumberBits == Other.NumberBits; - } - - public EIntegerEncoding GetEncoding() - { - return Encoding; - } - - public int GetBitLength(int NumberVals) - { - int TotalBits = NumberBits * NumberVals; - if (Encoding == EIntegerEncoding.Trit) - { - TotalBits += (NumberVals * 8 + 4) / 5; - } - else if (Encoding == EIntegerEncoding.Quint) - { - TotalBits += (NumberVals * 7 + 2) / 3; - } - return TotalBits; - } - - public static IntegerEncoded CreateEncoding(int MaxVal) - { - while (MaxVal > 0) - { - int Check = MaxVal + 1; - - // Is maxVal a power of two? - if ((Check & (Check - 1)) == 0) - { - return new IntegerEncoded(EIntegerEncoding.JustBits, BitArrayStream.PopCnt(MaxVal)); - } - - // Is maxVal of the type 3*2^n - 1? - if ((Check % 3 == 0) && ((Check / 3) & ((Check / 3) - 1)) == 0) - { - return new IntegerEncoded(EIntegerEncoding.Trit, BitArrayStream.PopCnt(Check / 3 - 1)); - } - - // Is maxVal of the type 5*2^n - 1? - if ((Check % 5 == 0) && ((Check / 5) & ((Check / 5) - 1)) == 0) - { - return new IntegerEncoded(EIntegerEncoding.Quint, BitArrayStream.PopCnt(Check / 5 - 1)); - } - - // Apparently it can't be represented with a bounded integer sequence... - // just iterate. - MaxVal--; - } - - return new IntegerEncoded(EIntegerEncoding.JustBits, 0); - } - - public static void DecodeTritBlock( - BitArrayStream BitStream, - List ListIntegerEncoded, - int NumberBitsPerValue) - { - // Implement the algorithm in section C.2.12 - int[] m = new int[5]; - int[] t = new int[5]; - int T; - - // Read the trit encoded block according to - // table C.2.14 - m[0] = BitStream.ReadBits(NumberBitsPerValue); - T = BitStream.ReadBits(2); - m[1] = BitStream.ReadBits(NumberBitsPerValue); - T |= BitStream.ReadBits(2) << 2; - m[2] = BitStream.ReadBits(NumberBitsPerValue); - T |= BitStream.ReadBits(1) << 4; - m[3] = BitStream.ReadBits(NumberBitsPerValue); - T |= BitStream.ReadBits(2) << 5; - m[4] = BitStream.ReadBits(NumberBitsPerValue); - T |= BitStream.ReadBits(1) << 7; - - int C = 0; - - BitArrayStream Tb = new BitArrayStream(new BitArray(new int[] { T })); - if (Tb.ReadBits(2, 4) == 7) - { - C = (Tb.ReadBits(5, 7) << 2) | Tb.ReadBits(0, 1); - t[4] = t[3] = 2; - } - else - { - C = Tb.ReadBits(0, 4); - if (Tb.ReadBits(5, 6) == 3) - { - t[4] = 2; - t[3] = Tb.ReadBit(7); - } - else - { - t[4] = Tb.ReadBit(7); - t[3] = Tb.ReadBits(5, 6); - } - } - - BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C })); - if (Cb.ReadBits(0, 1) == 3) - { - t[2] = 2; - t[1] = Cb.ReadBit(4); - t[0] = (Cb.ReadBit(3) << 1) | (Cb.ReadBit(2) & ~Cb.ReadBit(3)); - } - else if (Cb.ReadBits(2, 3) == 3) - { - t[2] = 2; - t[1] = 2; - t[0] = Cb.ReadBits(0, 1); - } - else - { - t[2] = Cb.ReadBit(4); - t[1] = Cb.ReadBits(2, 3); - t[0] = (Cb.ReadBit(1) << 1) | (Cb.ReadBit(0) & ~Cb.ReadBit(1)); - } - - for (int i = 0; i < 5; i++) - { - IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Trit, NumberBitsPerValue) - { - BitValue = m[i], - TritValue = t[i] - }; - ListIntegerEncoded.Add(IntEncoded); - } - } - - public static void DecodeQuintBlock( - BitArrayStream BitStream, - List ListIntegerEncoded, - int NumberBitsPerValue) - { - // Implement the algorithm in section C.2.12 - int[] m = new int[3]; - int[] q = new int[3]; - int Q; - - // Read the trit encoded block according to - // table C.2.15 - m[0] = BitStream.ReadBits(NumberBitsPerValue); - Q = BitStream.ReadBits(3); - m[1] = BitStream.ReadBits(NumberBitsPerValue); - Q |= BitStream.ReadBits(2) << 3; - m[2] = BitStream.ReadBits(NumberBitsPerValue); - Q |= BitStream.ReadBits(2) << 5; - - BitArrayStream Qb = new BitArrayStream(new BitArray(new int[] { Q })); - if (Qb.ReadBits(1, 2) == 3 && Qb.ReadBits(5, 6) == 0) - { - q[0] = q[1] = 4; - q[2] = (Qb.ReadBit(0) << 2) | ((Qb.ReadBit(4) & ~Qb.ReadBit(0)) << 1) | (Qb.ReadBit(3) & ~Qb.ReadBit(0)); - } - else - { - int C = 0; - if (Qb.ReadBits(1, 2) == 3) - { - q[2] = 4; - C = (Qb.ReadBits(3, 4) << 3) | ((~Qb.ReadBits(5, 6) & 3) << 1) | Qb.ReadBit(0); - } - else - { - q[2] = Qb.ReadBits(5, 6); - C = Qb.ReadBits(0, 4); - } - - BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C })); - if (Cb.ReadBits(0, 2) == 5) - { - q[1] = 4; - q[0] = Cb.ReadBits(3, 4); - } - else - { - q[1] = Cb.ReadBits(3, 4); - q[0] = Cb.ReadBits(0, 2); - } - } - - for (int i = 0; i < 3; i++) - { - IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Quint, NumberBitsPerValue) - { - BitValue = m[i], - QuintValue = q[i] - }; - ListIntegerEncoded.Add(IntEncoded); - } - } - - public static void DecodeIntegerSequence( - List DecodeIntegerSequence, - BitArrayStream BitStream, - int MaxRange, - int NumberValues) - { - // Determine encoding parameters - IntegerEncoded IntEncoded = CreateEncoding(MaxRange); - - // Start decoding - int NumberValuesDecoded = 0; - while (NumberValuesDecoded < NumberValues) - { - switch (IntEncoded.GetEncoding()) - { - case EIntegerEncoding.Quint: - { - DecodeQuintBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits); - NumberValuesDecoded += 3; - - break; - } - - case EIntegerEncoding.Trit: - { - DecodeTritBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits); - NumberValuesDecoded += 5; - - break; - } - - case EIntegerEncoding.JustBits: - { - IntEncoded.BitValue = BitStream.ReadBits(IntEncoded.NumberBits); - DecodeIntegerSequence.Add(IntEncoded); - NumberValuesDecoded++; - - break; - } - } - } - } - } -} +using System.Collections; +using System.Collections.Generic; + +namespace Ryujinx.Graphics.Texture +{ + public struct IntegerEncoded + { + public enum EIntegerEncoding + { + JustBits, + Quint, + Trit + } + + EIntegerEncoding Encoding; + public int NumberBits { get; private set; } + public int BitValue { get; private set; } + public int TritValue { get; private set; } + public int QuintValue { get; private set; } + + public IntegerEncoded(EIntegerEncoding _Encoding, int NumBits) + { + Encoding = _Encoding; + NumberBits = NumBits; + BitValue = 0; + TritValue = 0; + QuintValue = 0; + } + + public bool MatchesEncoding(IntegerEncoded Other) + { + return Encoding == Other.Encoding && NumberBits == Other.NumberBits; + } + + public EIntegerEncoding GetEncoding() + { + return Encoding; + } + + public int GetBitLength(int NumberVals) + { + int TotalBits = NumberBits * NumberVals; + if (Encoding == EIntegerEncoding.Trit) + { + TotalBits += (NumberVals * 8 + 4) / 5; + } + else if (Encoding == EIntegerEncoding.Quint) + { + TotalBits += (NumberVals * 7 + 2) / 3; + } + return TotalBits; + } + + public static IntegerEncoded CreateEncoding(int MaxVal) + { + while (MaxVal > 0) + { + int Check = MaxVal + 1; + + // Is maxVal a power of two? + if ((Check & (Check - 1)) == 0) + { + return new IntegerEncoded(EIntegerEncoding.JustBits, BitArrayStream.PopCnt(MaxVal)); + } + + // Is maxVal of the type 3*2^n - 1? + if ((Check % 3 == 0) && ((Check / 3) & ((Check / 3) - 1)) == 0) + { + return new IntegerEncoded(EIntegerEncoding.Trit, BitArrayStream.PopCnt(Check / 3 - 1)); + } + + // Is maxVal of the type 5*2^n - 1? + if ((Check % 5 == 0) && ((Check / 5) & ((Check / 5) - 1)) == 0) + { + return new IntegerEncoded(EIntegerEncoding.Quint, BitArrayStream.PopCnt(Check / 5 - 1)); + } + + // Apparently it can't be represented with a bounded integer sequence... + // just iterate. + MaxVal--; + } + + return new IntegerEncoded(EIntegerEncoding.JustBits, 0); + } + + public static void DecodeTritBlock( + BitArrayStream BitStream, + List ListIntegerEncoded, + int NumberBitsPerValue) + { + // Implement the algorithm in section C.2.12 + int[] m = new int[5]; + int[] t = new int[5]; + int T; + + // Read the trit encoded block according to + // table C.2.14 + m[0] = BitStream.ReadBits(NumberBitsPerValue); + T = BitStream.ReadBits(2); + m[1] = BitStream.ReadBits(NumberBitsPerValue); + T |= BitStream.ReadBits(2) << 2; + m[2] = BitStream.ReadBits(NumberBitsPerValue); + T |= BitStream.ReadBits(1) << 4; + m[3] = BitStream.ReadBits(NumberBitsPerValue); + T |= BitStream.ReadBits(2) << 5; + m[4] = BitStream.ReadBits(NumberBitsPerValue); + T |= BitStream.ReadBits(1) << 7; + + int C = 0; + + BitArrayStream Tb = new BitArrayStream(new BitArray(new int[] { T })); + if (Tb.ReadBits(2, 4) == 7) + { + C = (Tb.ReadBits(5, 7) << 2) | Tb.ReadBits(0, 1); + t[4] = t[3] = 2; + } + else + { + C = Tb.ReadBits(0, 4); + if (Tb.ReadBits(5, 6) == 3) + { + t[4] = 2; + t[3] = Tb.ReadBit(7); + } + else + { + t[4] = Tb.ReadBit(7); + t[3] = Tb.ReadBits(5, 6); + } + } + + BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C })); + if (Cb.ReadBits(0, 1) == 3) + { + t[2] = 2; + t[1] = Cb.ReadBit(4); + t[0] = (Cb.ReadBit(3) << 1) | (Cb.ReadBit(2) & ~Cb.ReadBit(3)); + } + else if (Cb.ReadBits(2, 3) == 3) + { + t[2] = 2; + t[1] = 2; + t[0] = Cb.ReadBits(0, 1); + } + else + { + t[2] = Cb.ReadBit(4); + t[1] = Cb.ReadBits(2, 3); + t[0] = (Cb.ReadBit(1) << 1) | (Cb.ReadBit(0) & ~Cb.ReadBit(1)); + } + + for (int i = 0; i < 5; i++) + { + IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Trit, NumberBitsPerValue) + { + BitValue = m[i], + TritValue = t[i] + }; + ListIntegerEncoded.Add(IntEncoded); + } + } + + public static void DecodeQuintBlock( + BitArrayStream BitStream, + List ListIntegerEncoded, + int NumberBitsPerValue) + { + // Implement the algorithm in section C.2.12 + int[] m = new int[3]; + int[] q = new int[3]; + int Q; + + // Read the trit encoded block according to + // table C.2.15 + m[0] = BitStream.ReadBits(NumberBitsPerValue); + Q = BitStream.ReadBits(3); + m[1] = BitStream.ReadBits(NumberBitsPerValue); + Q |= BitStream.ReadBits(2) << 3; + m[2] = BitStream.ReadBits(NumberBitsPerValue); + Q |= BitStream.ReadBits(2) << 5; + + BitArrayStream Qb = new BitArrayStream(new BitArray(new int[] { Q })); + if (Qb.ReadBits(1, 2) == 3 && Qb.ReadBits(5, 6) == 0) + { + q[0] = q[1] = 4; + q[2] = (Qb.ReadBit(0) << 2) | ((Qb.ReadBit(4) & ~Qb.ReadBit(0)) << 1) | (Qb.ReadBit(3) & ~Qb.ReadBit(0)); + } + else + { + int C = 0; + if (Qb.ReadBits(1, 2) == 3) + { + q[2] = 4; + C = (Qb.ReadBits(3, 4) << 3) | ((~Qb.ReadBits(5, 6) & 3) << 1) | Qb.ReadBit(0); + } + else + { + q[2] = Qb.ReadBits(5, 6); + C = Qb.ReadBits(0, 4); + } + + BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C })); + if (Cb.ReadBits(0, 2) == 5) + { + q[1] = 4; + q[0] = Cb.ReadBits(3, 4); + } + else + { + q[1] = Cb.ReadBits(3, 4); + q[0] = Cb.ReadBits(0, 2); + } + } + + for (int i = 0; i < 3; i++) + { + IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Quint, NumberBitsPerValue) + { + BitValue = m[i], + QuintValue = q[i] + }; + ListIntegerEncoded.Add(IntEncoded); + } + } + + public static void DecodeIntegerSequence( + List DecodeIntegerSequence, + BitArrayStream BitStream, + int MaxRange, + int NumberValues) + { + // Determine encoding parameters + IntegerEncoded IntEncoded = CreateEncoding(MaxRange); + + // Start decoding + int NumberValuesDecoded = 0; + while (NumberValuesDecoded < NumberValues) + { + switch (IntEncoded.GetEncoding()) + { + case EIntegerEncoding.Quint: + { + DecodeQuintBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits); + NumberValuesDecoded += 3; + + break; + } + + case EIntegerEncoding.Trit: + { + DecodeTritBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits); + NumberValuesDecoded += 5; + + break; + } + + case EIntegerEncoding.JustBits: + { + IntEncoded.BitValue = BitStream.ReadBits(IntEncoded.NumberBits); + DecodeIntegerSequence.Add(IntEncoded); + NumberValuesDecoded++; + + break; + } + } + } + } + } +} diff --git a/Ryujinx.HLE/Gpu/Texture/LinearSwizzle.cs b/Ryujinx.Graphics/Texture/LinearSwizzle.cs similarity index 90% rename from Ryujinx.HLE/Gpu/Texture/LinearSwizzle.cs rename to Ryujinx.Graphics/Texture/LinearSwizzle.cs index 720f78322..ef468e27b 100644 --- a/Ryujinx.HLE/Gpu/Texture/LinearSwizzle.cs +++ b/Ryujinx.Graphics/Texture/LinearSwizzle.cs @@ -1,4 +1,4 @@ -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { class LinearSwizzle : ISwizzle { diff --git a/Ryujinx.HLE/Gpu/Texture/TextureFactory.cs b/Ryujinx.Graphics/Texture/TextureFactory.cs similarity index 92% rename from Ryujinx.HLE/Gpu/Texture/TextureFactory.cs rename to Ryujinx.Graphics/Texture/TextureFactory.cs index 0ef33d3b7..fa7a0f80e 100644 --- a/Ryujinx.HLE/Gpu/Texture/TextureFactory.cs +++ b/Ryujinx.Graphics/Texture/TextureFactory.cs @@ -1,8 +1,8 @@ using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using System; -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { static class TextureFactory { @@ -10,12 +10,7 @@ namespace Ryujinx.HLE.Gpu.Texture { int[] Tic = ReadWords(Vmm, TicPosition, 8); - GalTextureType RType = (GalTextureType)((Tic[0] >> 7) & 7); - GalTextureType GType = (GalTextureType)((Tic[0] >> 10) & 7); - GalTextureType BType = (GalTextureType)((Tic[0] >> 13) & 7); - GalTextureType AType = (GalTextureType)((Tic[0] >> 16) & 7); - - GalImageFormat Format = ImageFormatConverter.ConvertTexture((GalTextureFormat)(Tic[0] & 0x7f), RType, GType, BType, AType); + GalImageFormat Format = GetImageFormat(Tic); GalTextureSource XSource = (GalTextureSource)((Tic[0] >> 19) & 7); GalTextureSource YSource = (GalTextureSource)((Tic[0] >> 22) & 7); @@ -39,7 +34,7 @@ namespace Ryujinx.HLE.Gpu.Texture { int[] Tic = ReadWords(Vmm, TicPosition, 8); - GalTextureFormat Format = (GalTextureFormat)(Tic[0] & 0x7f); + GalImageFormat Format = GetImageFormat(Tic); long TextureAddress = (uint)Tic[1]; @@ -110,6 +105,18 @@ namespace Ryujinx.HLE.Gpu.Texture BorderColor); } + private static GalImageFormat GetImageFormat(int[] Tic) + { + GalTextureType RType = (GalTextureType)((Tic[0] >> 7) & 7); + GalTextureType GType = (GalTextureType)((Tic[0] >> 10) & 7); + GalTextureType BType = (GalTextureType)((Tic[0] >> 13) & 7); + GalTextureType AType = (GalTextureType)((Tic[0] >> 16) & 7); + + GalTextureFormat Format = (GalTextureFormat)(Tic[0] & 0x7f); + + return ImageUtils.ConvertTexture(Format, RType, GType, BType, AType); + } + private static int[] ReadWords(NvGpuVmm Vmm, long Position, int Count) { int[] Words = new int[Count]; diff --git a/Ryujinx.Graphics/Texture/TextureHelper.cs b/Ryujinx.Graphics/Texture/TextureHelper.cs new file mode 100644 index 000000000..8130ab41a --- /dev/null +++ b/Ryujinx.Graphics/Texture/TextureHelper.cs @@ -0,0 +1,45 @@ +using ChocolArm64.Memory; +using Ryujinx.Graphics.Gal; +using Ryujinx.Graphics.Memory; +using System; + +namespace Ryujinx.Graphics.Texture +{ + static class TextureHelper + { + public static ISwizzle GetSwizzle(TextureInfo Texture, int BlockWidth, int Bpp) + { + int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth; + + int AlignMask = Texture.TileWidth * (64 / Bpp) - 1; + + Width = (Width + AlignMask) & ~AlignMask; + + switch (Texture.Swizzle) + { + case TextureSwizzle._1dBuffer: + case TextureSwizzle.Pitch: + case TextureSwizzle.PitchColorKey: + return new LinearSwizzle(Texture.Pitch, Bpp); + + case TextureSwizzle.BlockLinear: + case TextureSwizzle.BlockLinearColorKey: + return new BlockLinearSwizzle(Width, Bpp, Texture.BlockHeight); + } + + throw new NotImplementedException(Texture.Swizzle.ToString()); + } + + public static (AMemory Memory, long Position) GetMemoryAndPosition( + IAMemory Memory, + long Position) + { + if (Memory is NvGpuVmm Vmm) + { + return (Vmm.Memory, Vmm.GetPhysicalAddress(Position)); + } + + return ((AMemory)Memory, Position); + } + } +} diff --git a/Ryujinx.HLE/Gpu/Texture/TextureInfo.cs b/Ryujinx.Graphics/Texture/TextureInfo.cs similarity index 86% rename from Ryujinx.HLE/Gpu/Texture/TextureInfo.cs rename to Ryujinx.Graphics/Texture/TextureInfo.cs index 2a98ce00f..66445dcce 100644 --- a/Ryujinx.HLE/Gpu/Texture/TextureInfo.cs +++ b/Ryujinx.Graphics/Texture/TextureInfo.cs @@ -1,8 +1,8 @@ using Ryujinx.Graphics.Gal; -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { - struct TextureInfo + public struct TextureInfo { public long Position { get; private set; } @@ -15,7 +15,7 @@ namespace Ryujinx.HLE.Gpu.Texture public TextureSwizzle Swizzle { get; private set; } - public GalTextureFormat Format { get; private set; } + public GalImageFormat Format { get; private set; } public TextureInfo( long Position, @@ -34,7 +34,7 @@ namespace Ryujinx.HLE.Gpu.Texture Swizzle = TextureSwizzle.BlockLinear; - Format = GalTextureFormat.A8B8G8R8; + Format = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm; } public TextureInfo( @@ -45,7 +45,7 @@ namespace Ryujinx.HLE.Gpu.Texture int BlockHeight, int TileWidth, TextureSwizzle Swizzle, - GalTextureFormat Format) + GalImageFormat Format) { this.Position = Position; this.Width = Width; diff --git a/Ryujinx.HLE/Gpu/Texture/TextureReader.cs b/Ryujinx.Graphics/Texture/TextureReader.cs similarity index 63% rename from Ryujinx.HLE/Gpu/Texture/TextureReader.cs rename to Ryujinx.Graphics/Texture/TextureReader.cs index d293bf9f1..dbaed1a8e 100644 --- a/Ryujinx.HLE/Gpu/Texture/TextureReader.cs +++ b/Ryujinx.Graphics/Texture/TextureReader.cs @@ -2,58 +2,20 @@ using ChocolArm64.Memory; using Ryujinx.Graphics.Gal; using System; -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { - static class TextureReader + delegate byte[] TextureReaderDelegate(IAMemory Memory, TextureInfo Texture); + + public static class TextureReader { public static byte[] Read(IAMemory Memory, TextureInfo Texture) { - switch (Texture.Format) - { - case GalTextureFormat.R32G32B32A32: return Read16Bpp (Memory, Texture); - case GalTextureFormat.R16G16B16A16: return Read8Bpp (Memory, Texture); - case GalTextureFormat.R32G32: return Read8Bpp (Memory, Texture); - case GalTextureFormat.A8B8G8R8: return Read4Bpp (Memory, Texture); - case GalTextureFormat.A2B10G10R10: return Read4Bpp (Memory, Texture); - case GalTextureFormat.R32: return Read4Bpp (Memory, Texture); - case GalTextureFormat.BF10GF11RF11: return Read4Bpp (Memory, Texture); - case GalTextureFormat.Z24S8: return Read4Bpp (Memory, Texture); - case GalTextureFormat.A1B5G5R5: return Read5551 (Memory, Texture); - case GalTextureFormat.B5G6R5: return Read565 (Memory, Texture); - case GalTextureFormat.A4B4G4R4: return Read2Bpp (Memory, Texture); - case GalTextureFormat.G8R8: return Read2Bpp (Memory, Texture); - case GalTextureFormat.R16: return Read2Bpp (Memory, Texture); - case GalTextureFormat.R8: return Read1Bpp (Memory, Texture); - case GalTextureFormat.BC6H_SF16: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.BC6H_UF16: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.BC7U: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.BC1: return Read8Bpt4x4 (Memory, Texture); - case GalTextureFormat.BC2: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.BC3: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.BC4: return Read8Bpt4x4 (Memory, Texture); - case GalTextureFormat.BC5: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.ZF32: return Read4Bpp (Memory, Texture); - case GalTextureFormat.ZF32_X24S8: return Read8Bpp (Memory, Texture); - case GalTextureFormat.Astc2D4x4: return Read16BptCompressedTexture(Memory, Texture, 4, 4); - case GalTextureFormat.Astc2D5x5: return Read16BptCompressedTexture(Memory, Texture, 5, 5); - case GalTextureFormat.Astc2D6x6: return Read16BptCompressedTexture(Memory, Texture, 6, 6); - case GalTextureFormat.Astc2D8x8: return Read16BptCompressedTexture(Memory, Texture, 8, 8); - case GalTextureFormat.Astc2D10x10: return Read16BptCompressedTexture(Memory, Texture, 10, 10); - case GalTextureFormat.Astc2D12x12: return Read16BptCompressedTexture(Memory, Texture, 12, 12); - case GalTextureFormat.Astc2D5x4: return Read16BptCompressedTexture(Memory, Texture, 5, 4); - case GalTextureFormat.Astc2D6x5: return Read16BptCompressedTexture(Memory, Texture, 6, 5); - case GalTextureFormat.Astc2D8x6: return Read16BptCompressedTexture(Memory, Texture, 8, 6); - case GalTextureFormat.Astc2D10x8: return Read16BptCompressedTexture(Memory, Texture, 10, 8); - case GalTextureFormat.Astc2D12x10: return Read16BptCompressedTexture(Memory, Texture, 12, 10); - case GalTextureFormat.Astc2D8x5: return Read16BptCompressedTexture(Memory, Texture, 8, 5); - case GalTextureFormat.Astc2D10x5: return Read16BptCompressedTexture(Memory, Texture, 10, 5); - case GalTextureFormat.Astc2D10x6: return Read16BptCompressedTexture(Memory, Texture, 10, 6); - } + TextureReaderDelegate Reader = ImageUtils.GetReader(Texture.Format); - throw new NotImplementedException("0x" + ((int)Texture.Format).ToString("x2")); + return Reader(Memory, Texture); } - private unsafe static byte[] Read1Bpp(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read1Bpp(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -86,7 +48,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read5551(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read5551(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -124,7 +86,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read565(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read565(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -161,7 +123,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read2Bpp(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read2Bpp(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -194,7 +156,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read4Bpp(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read4Bpp(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -227,7 +189,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read8Bpp(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read8Bpp(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -260,7 +222,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read16Bpp(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read16Bpp(IAMemory Memory, TextureInfo Texture) { int Width = Texture.Width; int Height = Texture.Height; @@ -295,7 +257,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read8Bpt4x4(IAMemory Memory, TextureInfo Texture) + internal unsafe static byte[] Read8Bpt4x4(IAMemory Memory, TextureInfo Texture) { int Width = (Texture.Width + 3) / 4; int Height = (Texture.Height + 3) / 4; @@ -328,7 +290,7 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } - private unsafe static byte[] Read16BptCompressedTexture(IAMemory Memory, TextureInfo Texture, int BlockWidth, int BlockHeight) + internal unsafe static byte[] Read16BptCompressedTexture(IAMemory Memory, TextureInfo Texture, int BlockWidth, int BlockHeight) { int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth; int Height = (Texture.Height + (BlockHeight - 1)) / BlockHeight; @@ -362,5 +324,75 @@ namespace Ryujinx.HLE.Gpu.Texture return Output; } + + internal static byte[] Read16BptCompressedTexture4x4(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 4, 4); + } + + internal static byte[] Read16BptCompressedTexture5x5(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 5, 5); + } + + internal static byte[] Read16BptCompressedTexture6x6(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 6, 6); + } + + internal static byte[] Read16BptCompressedTexture8x8(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 8, 8); + } + + internal static byte[] Read16BptCompressedTexture10x10(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 10, 10); + } + + internal static byte[] Read16BptCompressedTexture12x12(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 12, 12); + } + + internal static byte[] Read16BptCompressedTexture5x4(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 5, 4); + } + + internal static byte[] Read16BptCompressedTexture6x5(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 6, 5); + } + + internal static byte[] Read16BptCompressedTexture8x6(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 8, 6); + } + + internal static byte[] Read16BptCompressedTexture10x8(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 10, 8); + } + + internal static byte[] Read16BptCompressedTexture12x10(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 12, 10); + } + + internal static byte[] Read16BptCompressedTexture8x5(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 5, 5); + } + + internal static byte[] Read16BptCompressedTexture10x5(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 10, 5); + } + + internal static byte[] Read16BptCompressedTexture10x6(IAMemory Memory, TextureInfo Texture) + { + return Read16BptCompressedTexture(Memory, Texture, 10, 6); + } } } diff --git a/Ryujinx.HLE/Gpu/Texture/TextureSwizzle.cs b/Ryujinx.Graphics/Texture/TextureSwizzle.cs similarity index 73% rename from Ryujinx.HLE/Gpu/Texture/TextureSwizzle.cs rename to Ryujinx.Graphics/Texture/TextureSwizzle.cs index 076df97ab..c67a5367e 100644 --- a/Ryujinx.HLE/Gpu/Texture/TextureSwizzle.cs +++ b/Ryujinx.Graphics/Texture/TextureSwizzle.cs @@ -1,6 +1,6 @@ -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { - enum TextureSwizzle + public enum TextureSwizzle { _1dBuffer = 0, PitchColorKey = 1, diff --git a/Ryujinx.HLE/Gpu/Texture/TextureWriter.cs b/Ryujinx.Graphics/Texture/TextureWriter.cs similarity index 90% rename from Ryujinx.HLE/Gpu/Texture/TextureWriter.cs rename to Ryujinx.Graphics/Texture/TextureWriter.cs index 6c3dda6be..16e78c56f 100644 --- a/Ryujinx.HLE/Gpu/Texture/TextureWriter.cs +++ b/Ryujinx.Graphics/Texture/TextureWriter.cs @@ -1,6 +1,8 @@ using ChocolArm64.Memory; +using Ryujinx.Graphics.Gal; +using Ryujinx.Graphics.Memory; -namespace Ryujinx.HLE.Gpu.Texture +namespace Ryujinx.Graphics.Texture { static class TextureWriter { diff --git a/Ryujinx.HLE/FileSystem/SaveDataType.cs b/Ryujinx.HLE/FileSystem/SaveDataType.cs new file mode 100644 index 000000000..edfe8ab1d --- /dev/null +++ b/Ryujinx.HLE/FileSystem/SaveDataType.cs @@ -0,0 +1,12 @@ +namespace Ryujinx.HLE.FileSystem +{ + enum SaveDataType : byte + { + SystemSaveData, + SaveData, + BcatDeliveryCacheStorage, + DeviceSaveData, + TemporaryStorage, + CacheStorage + } +} diff --git a/Ryujinx.HLE/FileSystem/SaveHelper.cs b/Ryujinx.HLE/FileSystem/SaveHelper.cs new file mode 100644 index 000000000..67f010169 --- /dev/null +++ b/Ryujinx.HLE/FileSystem/SaveHelper.cs @@ -0,0 +1,46 @@ +using Ryujinx.HLE.HOS; +using System.IO; + +using static Ryujinx.HLE.FileSystem.VirtualFileSystem; + +namespace Ryujinx.HLE.FileSystem +{ + static class SaveHelper + { + public static string GetSavePath(SaveInfo SaveMetaData, ServiceCtx Context) + { + string BaseSavePath = NandPath; + long CurrentTitleId = SaveMetaData.TitleId; + + switch (SaveMetaData.SaveSpaceId) + { + case SaveSpaceId.NandUser: + BaseSavePath = UserNandPath; + break; + case SaveSpaceId.NandSystem: + BaseSavePath = SystemNandPath; + break; + case SaveSpaceId.SdCard: + BaseSavePath = Path.Combine(SdCardPath, "Nintendo"); + break; + } + + BaseSavePath = Path.Combine(BaseSavePath, "save"); + + if (SaveMetaData.TitleId == 0 && SaveMetaData.SaveDataType == SaveDataType.SaveData) + { + if (Context.Process.MetaData != null) + { + CurrentTitleId = Context.Process.MetaData.ACI0.TitleId; + } + } + + string SavePath = Path.Combine(BaseSavePath, + SaveMetaData.SaveId.ToString("x16"), + SaveMetaData.UserId.ToString(), + SaveMetaData.SaveDataType == SaveDataType.SaveData ? CurrentTitleId.ToString("x16") : string.Empty); + + return SavePath; + } + } +} diff --git a/Ryujinx.HLE/FileSystem/SaveInfo.cs b/Ryujinx.HLE/FileSystem/SaveInfo.cs new file mode 100644 index 000000000..f3790ec78 --- /dev/null +++ b/Ryujinx.HLE/FileSystem/SaveInfo.cs @@ -0,0 +1,28 @@ +using Ryujinx.HLE.HOS.SystemState; + +namespace Ryujinx.HLE.FileSystem +{ + struct SaveInfo + { + public long TitleId { get; private set; } + public long SaveId { get; private set; } + public UserId UserId { get; private set; } + + public SaveDataType SaveDataType { get; private set; } + public SaveSpaceId SaveSpaceId { get; private set; } + + public SaveInfo( + long TitleId, + long SaveId, + SaveDataType SaveDataType, + UserId UserId, + SaveSpaceId SaveSpaceId) + { + this.TitleId = TitleId; + this.UserId = UserId; + this.SaveId = SaveId; + this.SaveDataType = SaveDataType; + this.SaveSpaceId = SaveSpaceId; + } + } +} diff --git a/Ryujinx.HLE/FileSystem/SaveSpaceId.cs b/Ryujinx.HLE/FileSystem/SaveSpaceId.cs new file mode 100644 index 000000000..5a2b32d63 --- /dev/null +++ b/Ryujinx.HLE/FileSystem/SaveSpaceId.cs @@ -0,0 +1,10 @@ +namespace Ryujinx.HLE.FileSystem +{ + enum SaveSpaceId : byte + { + NandSystem, + NandUser, + SdCard, + TemporaryStorage + } +} diff --git a/Ryujinx.HLE/VirtualFileSystem.cs b/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs similarity index 79% rename from Ryujinx.HLE/VirtualFileSystem.cs rename to Ryujinx.HLE/FileSystem/VirtualFileSystem.cs index 31b8e184c..e621ec2b1 100644 --- a/Ryujinx.HLE/VirtualFileSystem.cs +++ b/Ryujinx.HLE/FileSystem/VirtualFileSystem.cs @@ -1,14 +1,18 @@ +using Ryujinx.HLE.HOS; using System; using System.IO; -namespace Ryujinx.HLE +namespace Ryujinx.HLE.FileSystem { class VirtualFileSystem : IDisposable { - private const string BasePath = "RyuFs"; - private const string NandPath = "nand"; - private const string SdCardPath = "sdmc"; - private const string SystemPath = "system"; + public const string BasePath = "RyuFs"; + public const string NandPath = "nand"; + public const string SdCardPath = "sdmc"; + public const string SystemPath = "system"; + + public static string SystemNandPath = Path.Combine(NandPath, "system"); + public static string UserNandPath = Path.Combine(NandPath, "user"); public Stream RomFs { get; private set; } @@ -17,6 +21,12 @@ namespace Ryujinx.HLE RomFs = new FileStream(FileName, FileMode.Open, FileAccess.Read); } + public void SetRomFs(Stream RomfsStream) + { + RomFs?.Close(); + RomFs = RomfsStream; + } + public string GetFullPath(string BasePath, string FileName) { if (FileName.StartsWith("//")) @@ -44,10 +54,15 @@ namespace Ryujinx.HLE public string GetSdCardPath() => MakeDirAndGetFullPath(SdCardPath); - public string GetGameSavesPath() => MakeDirAndGetFullPath(NandPath); + public string GetNandPath() => MakeDirAndGetFullPath(NandPath); public string GetSystemPath() => MakeDirAndGetFullPath(SystemPath); + public string GetGameSavePath(SaveInfo Save, ServiceCtx Context) + { + return MakeDirAndGetFullPath(SaveHelper.GetSavePath(Save, Context)); + } + public string SwitchPathToSystemPath(string SwitchPath) { string[] Parts = SwitchPath.Split(":"); diff --git a/Ryujinx.HLE/Gpu/Texture/TextureHelper.cs b/Ryujinx.HLE/Gpu/Texture/TextureHelper.cs deleted file mode 100644 index 2683174d8..000000000 --- a/Ryujinx.HLE/Gpu/Texture/TextureHelper.cs +++ /dev/null @@ -1,204 +0,0 @@ -using ChocolArm64.Memory; -using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Memory; -using System; - -namespace Ryujinx.HLE.Gpu.Texture -{ - static class TextureHelper - { - public static ISwizzle GetSwizzle(TextureInfo Texture, int BlockWidth, int Bpp) - { - int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth; - - int AlignMask = Texture.TileWidth * (64 / Bpp) - 1; - - Width = (Width + AlignMask) & ~AlignMask; - - switch (Texture.Swizzle) - { - case TextureSwizzle._1dBuffer: - case TextureSwizzle.Pitch: - case TextureSwizzle.PitchColorKey: - return new LinearSwizzle(Texture.Pitch, Bpp); - - case TextureSwizzle.BlockLinear: - case TextureSwizzle.BlockLinearColorKey: - return new BlockLinearSwizzle(Width, Bpp, Texture.BlockHeight); - } - - throw new NotImplementedException(Texture.Swizzle.ToString()); - } - - public static int GetTextureSize(GalImage Image) - { - switch (Image.Format) - { - case GalImageFormat.R32G32B32A32_SFLOAT: - case GalImageFormat.R32G32B32A32_SINT: - case GalImageFormat.R32G32B32A32_UINT: - return Image.Width * Image.Height * 16; - - case GalImageFormat.R16G16B16A16_SFLOAT: - case GalImageFormat.R16G16B16A16_SINT: - case GalImageFormat.R16G16B16A16_SNORM: - case GalImageFormat.R16G16B16A16_UINT: - case GalImageFormat.R16G16B16A16_UNORM: - case GalImageFormat.D32_SFLOAT_S8_UINT: - case GalImageFormat.R32G32_SFLOAT: - case GalImageFormat.R32G32_SINT: - case GalImageFormat.R32G32_UINT: - return Image.Width * Image.Height * 8; - - case GalImageFormat.A8B8G8R8_SINT_PACK32: - case GalImageFormat.A8B8G8R8_SNORM_PACK32: - case GalImageFormat.A8B8G8R8_UINT_PACK32: - case GalImageFormat.A8B8G8R8_UNORM_PACK32: - case GalImageFormat.A8B8G8R8_SRGB_PACK32: - case GalImageFormat.A2B10G10R10_SINT_PACK32: - case GalImageFormat.A2B10G10R10_SNORM_PACK32: - case GalImageFormat.A2B10G10R10_UINT_PACK32: - case GalImageFormat.A2B10G10R10_UNORM_PACK32: - case GalImageFormat.R16G16_SFLOAT: - case GalImageFormat.R16G16_SINT: - case GalImageFormat.R16G16_SNORM: - case GalImageFormat.R16G16_UINT: - case GalImageFormat.R16G16_UNORM: - case GalImageFormat.R32_SFLOAT: - case GalImageFormat.R32_SINT: - case GalImageFormat.R32_UINT: - case GalImageFormat.D32_SFLOAT: - case GalImageFormat.B10G11R11_UFLOAT_PACK32: - case GalImageFormat.D24_UNORM_S8_UINT: - return Image.Width * Image.Height * 4; - - case GalImageFormat.B4G4R4A4_UNORM_PACK16: - case GalImageFormat.A1R5G5B5_UNORM_PACK16: - case GalImageFormat.B5G6R5_UNORM_PACK16: - case GalImageFormat.R8G8_SINT: - case GalImageFormat.R8G8_SNORM: - case GalImageFormat.R8G8_UINT: - case GalImageFormat.R8G8_UNORM: - case GalImageFormat.R16_SFLOAT: - case GalImageFormat.R16_SINT: - case GalImageFormat.R16_SNORM: - case GalImageFormat.R16_UINT: - case GalImageFormat.R16_UNORM: - case GalImageFormat.D16_UNORM: - return Image.Width * Image.Height * 2; - - case GalImageFormat.R8_SINT: - case GalImageFormat.R8_SNORM: - case GalImageFormat.R8_UINT: - case GalImageFormat.R8_UNORM: - return Image.Width * Image.Height; - - case GalImageFormat.BC1_RGBA_UNORM_BLOCK: - case GalImageFormat.BC4_SNORM_BLOCK: - case GalImageFormat.BC4_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 8); - } - - case GalImageFormat.BC6H_SFLOAT_BLOCK: - case GalImageFormat.BC6H_UFLOAT_BLOCK: - case GalImageFormat.BC7_UNORM_BLOCK: - case GalImageFormat.BC2_UNORM_BLOCK: - case GalImageFormat.BC3_UNORM_BLOCK: - case GalImageFormat.BC5_SNORM_BLOCK: - case GalImageFormat.BC5_UNORM_BLOCK: - case GalImageFormat.ASTC_4x4_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 16); - } - - case GalImageFormat.ASTC_5x5_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 5, 5, 16); - } - - case GalImageFormat.ASTC_6x6_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 6, 6, 16); - } - - case GalImageFormat.ASTC_8x8_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 8, 8, 16); - } - - case GalImageFormat.ASTC_10x10_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 10, 10, 16); - } - - case GalImageFormat.ASTC_12x12_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 12, 12, 16); - } - - case GalImageFormat.ASTC_5x4_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 5, 4, 16); - } - - case GalImageFormat.ASTC_6x5_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 6, 5, 16); - } - - case GalImageFormat.ASTC_8x6_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 8, 6, 16); - } - - case GalImageFormat.ASTC_10x8_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 10, 8, 16); - } - - case GalImageFormat.ASTC_12x10_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 12, 10, 16); - } - - case GalImageFormat.ASTC_8x5_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 8, 5, 16); - } - - case GalImageFormat.ASTC_10x5_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 10, 5, 16); - } - - case GalImageFormat.ASTC_10x6_UNORM_BLOCK: - { - return CompressedTextureSize(Image.Width, Image.Height, 10, 6, 16); - } - } - - throw new NotImplementedException(Image.Format.ToString()); - } - - public static int CompressedTextureSize(int TextureWidth, int TextureHeight, int BlockWidth, int BlockHeight, int Bpb) - { - int W = (TextureWidth + (BlockWidth - 1)) / BlockWidth; - int H = (TextureHeight + (BlockHeight - 1)) / BlockHeight; - - return W * H * Bpb; - } - - public static (AMemory Memory, long Position) GetMemoryAndPosition( - IAMemory Memory, - long Position) - { - if (Memory is NvGpuVmm Vmm) - { - return (Vmm.Memory, Vmm.GetPhysicalAddress(Position)); - } - - return ((AMemory)Memory, Position); - } - } -} diff --git a/Ryujinx.HLE/HOS/Horizon.cs b/Ryujinx.HLE/HOS/Horizon.cs index a55796752..2e216cdf1 100644 --- a/Ryujinx.HLE/HOS/Horizon.cs +++ b/Ryujinx.HLE/HOS/Horizon.cs @@ -1,3 +1,4 @@ +using LibHac; using Ryujinx.HLE.HOS.Font; using Ryujinx.HLE.HOS.Kernel; using Ryujinx.HLE.HOS.SystemState; @@ -7,6 +8,7 @@ using Ryujinx.HLE.Logging; using System; using System.Collections.Concurrent; using System.IO; +using System.Linq; namespace Ryujinx.HLE.HOS { @@ -30,6 +32,8 @@ namespace Ryujinx.HLE.HOS internal KEvent VsyncEvent { get; private set; } + internal Keyset KeySet { get; private set; } + public Horizon(Switch Device) { this.Device = Device; @@ -52,6 +56,8 @@ namespace Ryujinx.HLE.HOS Font = new SharedFontManager(Device, FontSharedMem.PA); VsyncEvent = new KEvent(); + + LoadKeySet(); } public void LoadCart(string ExeFsDir, string RomFsFile = null) @@ -103,7 +109,7 @@ namespace Ryujinx.HLE.HOS } } - if (!MainProcess.MetaData.Is64Bits) + if (!(MainProcess.MetaData?.Is64Bits ?? true)) { throw new NotImplementedException("32-bit titles are unsupported!"); } @@ -119,6 +125,179 @@ namespace Ryujinx.HLE.HOS MainProcess.Run(); } + public void LoadXci(string XciFile) + { + FileStream File = new FileStream(XciFile, FileMode.Open, FileAccess.Read); + + Xci Xci = new Xci(KeySet, File); + + Nca Nca = GetXciMainNca(Xci); + + if (Nca == null) + { + Device.Log.PrintError(LogClass.Loader, "Unable to load XCI"); + + return; + } + + LoadNca(Nca); + } + + private Nca GetXciMainNca(Xci Xci) + { + if (Xci.SecurePartition == null) + { + throw new InvalidDataException("Could not find XCI secure partition"); + } + + Nca MainNca = null; + Nca PatchNca = null; + + foreach (PfsFileEntry FileEntry in Xci.SecurePartition.Files.Where(x => x.Name.EndsWith(".nca"))) + { + Stream NcaStream = Xci.SecurePartition.OpenFile(FileEntry); + + Nca Nca = new Nca(KeySet, NcaStream, true); + + if (Nca.Header.ContentType == ContentType.Program) + { + if (Nca.Sections.Any(x => x?.Type == SectionType.Romfs)) + { + MainNca = Nca; + } + else if (Nca.Sections.Any(x => x?.Type == SectionType.Bktr)) + { + PatchNca = Nca; + } + } + } + + if (MainNca == null) + { + Device.Log.PrintError(LogClass.Loader, "Could not find an Application NCA in the provided XCI file"); + } + + MainNca.SetBaseNca(PatchNca); + + return MainNca; + } + + public void LoadNca(string NcaFile) + { + FileStream File = new FileStream(NcaFile, FileMode.Open, FileAccess.Read); + + Nca Nca = new Nca(KeySet, File, true); + + LoadNca(Nca); + } + + public void LoadNsp(string NspFile) + { + FileStream File = new FileStream(NspFile, FileMode.Open, FileAccess.Read); + + Pfs Nsp = new Pfs(File); + + PfsFileEntry TicketFile = Nsp.Files.FirstOrDefault(x => x.Name.EndsWith(".tik")); + + // Load title key from the NSP's ticket in case the user doesn't have a title key file + if (TicketFile != null) + { + // todo Change when Ticket(Stream) overload is added + Ticket Ticket = new Ticket(new BinaryReader(Nsp.OpenFile(TicketFile))); + + KeySet.TitleKeys[Ticket.RightsId] = Ticket.GetTitleKey(KeySet); + } + + foreach (PfsFileEntry NcaFile in Nsp.Files.Where(x => x.Name.EndsWith(".nca"))) + { + Nca Nca = new Nca(KeySet, Nsp.OpenFile(NcaFile), true); + + if (Nca.Header.ContentType == ContentType.Program) + { + LoadNca(Nca); + + return; + } + } + + Device.Log.PrintError(LogClass.Loader, "Could not find an Application NCA in the provided NSP file"); + } + + public void LoadNca(Nca Nca) + { + NcaSection RomfsSection = Nca.Sections.FirstOrDefault(x => x?.Type == SectionType.Romfs); + NcaSection ExefsSection = Nca.Sections.FirstOrDefault(x => x?.IsExefs == true); + + if (ExefsSection == null) + { + Device.Log.PrintError(LogClass.Loader, "No ExeFS found in NCA"); + + return; + } + + if (RomfsSection == null) + { + Device.Log.PrintError(LogClass.Loader, "No RomFS found in NCA"); + + return; + } + + Stream RomfsStream = Nca.OpenSection(RomfsSection.SectionNum, false); + Device.FileSystem.SetRomFs(RomfsStream); + + Stream ExefsStream = Nca.OpenSection(ExefsSection.SectionNum, false); + Pfs Exefs = new Pfs(ExefsStream); + + Npdm MetaData = null; + + if (Exefs.FileExists("main.npdm")) + { + Device.Log.PrintInfo(LogClass.Loader, "Loading main.npdm..."); + + MetaData = new Npdm(Exefs.OpenFile("main.npdm")); + } + else + { + Device.Log.PrintWarning(LogClass.Loader, $"NPDM file not found, using default values!"); + } + + Process MainProcess = MakeProcess(MetaData); + + void LoadNso(string Filename) + { + foreach (PfsFileEntry File in Exefs.Files.Where(x => x.Name.StartsWith(Filename))) + { + if (Path.GetExtension(File.Name) != string.Empty) + { + continue; + } + + Device.Log.PrintInfo(LogClass.Loader, $"Loading {Filename}..."); + + string Name = Path.GetFileNameWithoutExtension(File.Name); + + Nso Program = new Nso(Exefs.OpenFile(File), Name); + + MainProcess.LoadProgram(Program); + } + } + + if (!MainProcess.MetaData.Is64Bits) + { + throw new NotImplementedException("32-bit titles are unsupported!"); + } + + LoadNso("rtld"); + + MainProcess.SetEmptyArgs(); + + LoadNso("main"); + LoadNso("subsdk"); + LoadNso("sdk"); + + MainProcess.Run(); + } + public void LoadProgram(string FilePath) { bool IsNro = Path.GetExtension(FilePath).ToLower() == ".nro"; @@ -156,6 +335,42 @@ namespace Ryujinx.HLE.HOS MainProcess.Run(IsNro); } + public void LoadKeySet() + { + string KeyFile = null; + string TitleKeyFile = null; + string ConsoleKeyFile = null; + + string Home = Environment.GetFolderPath(Environment.SpecialFolder.UserProfile); + + LoadSetAtPath(Path.Combine(Home, ".switch")); + LoadSetAtPath(Device.FileSystem.GetSystemPath()); + + KeySet = ExternalKeys.ReadKeyFile(KeyFile, TitleKeyFile, ConsoleKeyFile); + + void LoadSetAtPath(string BasePath) + { + string LocalKeyFile = Path.Combine(BasePath, "prod.keys"); + string LocalTitleKeyFile = Path.Combine(BasePath, "title.keys"); + string LocalConsoleKeyFile = Path.Combine(BasePath, "console.keys"); + + if (File.Exists(LocalKeyFile)) + { + KeyFile = LocalKeyFile; + } + + if (File.Exists(LocalTitleKeyFile)) + { + TitleKeyFile = LocalTitleKeyFile; + } + + if (File.Exists(LocalConsoleKeyFile)) + { + ConsoleKeyFile = LocalConsoleKeyFile; + } + } + } + public void SignalVsync() => VsyncEvent.WaitEvent.Set(); private Process MakeProcess(Npdm MetaData = null) diff --git a/Ryujinx.HLE/HOS/Services/FspSrv/IFileSystemProxy.cs b/Ryujinx.HLE/HOS/Services/FspSrv/IFileSystemProxy.cs index 14edcc759..937ea6d6b 100644 --- a/Ryujinx.HLE/HOS/Services/FspSrv/IFileSystemProxy.cs +++ b/Ryujinx.HLE/HOS/Services/FspSrv/IFileSystemProxy.cs @@ -1,5 +1,6 @@ +using Ryujinx.HLE.FileSystem; using Ryujinx.HLE.HOS.Ipc; -using Ryujinx.HLE.Logging; +using Ryujinx.HLE.HOS.SystemState; using System.Collections.Generic; namespace Ryujinx.HLE.HOS.Services.FspSrv @@ -14,13 +15,13 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv { m_Commands = new Dictionary() { - { 1, SetCurrentProcess }, - { 18, OpenSdCardFileSystem }, - { 22, CreateSaveDataFileSystem }, - { 51, OpenSaveDataFileSystem }, - { 200, OpenDataStorageByCurrentProcess }, - { 203, OpenPatchDataStorageByCurrentProcess }, - { 1005, GetGlobalAccessLogMode } + { 1, SetCurrentProcess }, + { 18, OpenSdCardFileSystem }, + { 51, OpenSaveDataFileSystem }, + { 52, OpenSaveDataFileSystemBySystemSaveDataId }, + { 200, OpenDataStorageByCurrentProcess }, + { 203, OpenPatchDataStorageByCurrentProcess }, + { 1005, GetGlobalAccessLogMode } }; } @@ -36,16 +37,16 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv return 0; } - public long CreateSaveDataFileSystem(ServiceCtx Context) + public long OpenSaveDataFileSystem(ServiceCtx Context) { - Context.Device.Log.PrintStub(LogClass.ServiceFs, "Stubbed."); + LoadSaveDataFileSystem(Context); return 0; } - public long OpenSaveDataFileSystem(ServiceCtx Context) + public long OpenSaveDataFileSystemBySystemSaveDataId(ServiceCtx Context) { - MakeObject(Context, new IFileSystem(Context.Device.FileSystem.GetGameSavesPath())); + LoadSaveDataFileSystem(Context); return 0; } @@ -70,5 +71,24 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv return 0; } + + public void LoadSaveDataFileSystem(ServiceCtx Context) + { + SaveSpaceId SaveSpaceId = (SaveSpaceId)Context.RequestData.ReadInt64(); + + long TitleId = Context.RequestData.ReadInt64(); + + UserId UserId = new UserId( + Context.RequestData.ReadInt64(), + Context.RequestData.ReadInt64()); + + long SaveId = Context.RequestData.ReadInt64(); + + SaveDataType SaveDataType = (SaveDataType)Context.RequestData.ReadByte(); + + SaveInfo SaveInfo = new SaveInfo(TitleId, SaveId, SaveDataType, UserId, SaveSpaceId); + + MakeObject(Context, new IFileSystem(Context.Device.FileSystem.GetGameSavePath(SaveInfo, Context))); + } } } \ No newline at end of file diff --git a/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASCtx.cs b/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASCtx.cs index 7b6a8676b..70275b2a9 100644 --- a/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASCtx.cs +++ b/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASCtx.cs @@ -1,4 +1,4 @@ -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using System.Collections.Generic; namespace Ryujinx.HLE.HOS.Services.Nv.NvGpuAS diff --git a/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASIoctl.cs b/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASIoctl.cs index c9be18ead..95eb5b986 100644 --- a/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASIoctl.cs +++ b/Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASIoctl.cs @@ -1,5 +1,5 @@ using ChocolArm64.Memory; -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using Ryujinx.HLE.HOS.Services.Nv.NvMap; using Ryujinx.HLE.Logging; using System; diff --git a/Ryujinx.HLE/HOS/Services/Nv/NvHostChannel/NvHostChannelIoctl.cs b/Ryujinx.HLE/HOS/Services/Nv/NvHostChannel/NvHostChannelIoctl.cs index 842447f3f..f4ed48217 100644 --- a/Ryujinx.HLE/HOS/Services/Nv/NvHostChannel/NvHostChannelIoctl.cs +++ b/Ryujinx.HLE/HOS/Services/Nv/NvHostChannel/NvHostChannelIoctl.cs @@ -1,5 +1,5 @@ using ChocolArm64.Memory; -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using Ryujinx.HLE.HOS.Services.Nv.NvGpuAS; using Ryujinx.HLE.Logging; using System; diff --git a/Ryujinx.HLE/HOS/Services/Nv/NvMap/NvMapIoctl.cs b/Ryujinx.HLE/HOS/Services/Nv/NvMap/NvMapIoctl.cs index 782f7b800..38da2889e 100644 --- a/Ryujinx.HLE/HOS/Services/Nv/NvMap/NvMapIoctl.cs +++ b/Ryujinx.HLE/HOS/Services/Nv/NvMap/NvMapIoctl.cs @@ -1,5 +1,5 @@ using ChocolArm64.Memory; -using Ryujinx.HLE.Gpu.Memory; +using Ryujinx.Graphics.Memory; using Ryujinx.HLE.Logging; using Ryujinx.HLE.Utilities; using System.Collections.Concurrent; diff --git a/Ryujinx.HLE/HOS/Services/Vi/NvFlinger.cs b/Ryujinx.HLE/HOS/Services/Vi/NvFlinger.cs index 12c173113..2a6918c44 100644 --- a/Ryujinx.HLE/HOS/Services/Vi/NvFlinger.cs +++ b/Ryujinx.HLE/HOS/Services/Vi/NvFlinger.cs @@ -1,5 +1,5 @@ using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu.Texture; +using Ryujinx.Graphics.Texture; using Ryujinx.HLE.HOS.Kernel; using Ryujinx.HLE.HOS.Services.Nv.NvMap; using Ryujinx.HLE.Logging; @@ -199,6 +199,11 @@ namespace Ryujinx.HLE.HOS.Services.Android SendFrameBuffer(Context, Slot); + if (Context.Device.EnableDeviceVsync) + { + Context.Device.VsyncEvent.WaitOne(); + } + return MakeReplyParcel(Context, 1280, 720, 0, 0, 0); } @@ -303,7 +308,7 @@ namespace Ryujinx.HLE.HOS.Services.Android int Right = Crop.Right; int Bottom = Crop.Bottom; - Renderer.QueueAction(() => Renderer.FrameBuffer.SetTransform(FlipX, FlipY, Top, Left, Right, Bottom)); + Renderer.QueueAction(() => Renderer.RenderTarget.SetTransform(FlipX, FlipY, Top, Left, Right, Bottom)); //TODO: Support double buffering here aswell, it is broken for GPU //frame buffers because it seems to be completely out of sync. @@ -311,7 +316,7 @@ namespace Ryujinx.HLE.HOS.Services.Android { //Frame buffer is rendered to by the GPU, we can just //bind the frame buffer texture, it's not necessary to read anything. - Renderer.QueueAction(() => Renderer.FrameBuffer.Set(FbAddr)); + Renderer.QueueAction(() => Renderer.RenderTarget.Set(FbAddr)); } else { @@ -321,7 +326,7 @@ namespace Ryujinx.HLE.HOS.Services.Android byte[] Data = TextureReader.Read(Context.Memory, Texture); - Renderer.QueueAction(() => Renderer.FrameBuffer.Set(Data, FbWidth, FbHeight)); + Renderer.QueueAction(() => Renderer.RenderTarget.Set(Data, FbWidth, FbHeight)); } Context.Device.Gpu.Renderer.QueueAction(() => ReleaseBuffer(Slot)); diff --git a/Ryujinx.HLE/Ryujinx.HLE.csproj b/Ryujinx.HLE/Ryujinx.HLE.csproj index fa4c254e2..cd1bb0345 100644 --- a/Ryujinx.HLE/Ryujinx.HLE.csproj +++ b/Ryujinx.HLE/Ryujinx.HLE.csproj @@ -25,6 +25,7 @@ + diff --git a/Ryujinx.HLE/Switch.cs b/Ryujinx.HLE/Switch.cs index 03dc44e85..a3f874ee5 100644 --- a/Ryujinx.HLE/Switch.cs +++ b/Ryujinx.HLE/Switch.cs @@ -1,11 +1,13 @@ using Ryujinx.Audio; +using Ryujinx.Graphics; using Ryujinx.Graphics.Gal; -using Ryujinx.HLE.Gpu; +using Ryujinx.HLE.FileSystem; using Ryujinx.HLE.HOS; using Ryujinx.HLE.Input; using Ryujinx.HLE.Logging; using Ryujinx.HLE.Memory; using System; +using System.Threading; namespace Ryujinx.HLE { @@ -27,6 +29,12 @@ namespace Ryujinx.HLE public Hid Hid { get; private set; } + public bool EnableDeviceVsync { get; set; } = true; + + public AutoResetEvent VsyncEvent { get; private set; } + + public event EventHandler Finish; + public Switch(IGalRenderer Renderer, IAalOutput AudioOut) { if (Renderer == null) @@ -54,6 +62,8 @@ namespace Ryujinx.HLE Statistics = new PerformanceStatistics(); Hid = new Hid(this, System.HidSharedMem.PA); + + VsyncEvent = new AutoResetEvent(true); } public void LoadCart(string ExeFsDir, string RomFsFile = null) @@ -61,6 +71,21 @@ namespace Ryujinx.HLE System.LoadCart(ExeFsDir, RomFsFile); } + public void LoadXci(string XciFile) + { + System.LoadXci(XciFile); + } + + public void LoadNca(string NcaFile) + { + System.LoadNca(NcaFile); + } + + public void LoadNsp(string NspFile) + { + System.LoadNsp(NspFile); + } + public void LoadProgram(string FileName) { System.LoadProgram(FileName); @@ -93,6 +118,8 @@ namespace Ryujinx.HLE if (Disposing) { System.Dispose(); + + VsyncEvent.Dispose(); } } } diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index 6e013aa05..1f7151ffe 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -33,9 +33,10 @@ namespace Ryujinx.Tests.Cpu static CpuTest() { UnicornAvailable = UnicornAArch64.IsAvailable(); + if (!UnicornAvailable) { - Console.WriteLine("WARNING: Could not find unicorn"); + Console.WriteLine("WARNING: Could not find Unicorn."); } } @@ -43,7 +44,7 @@ namespace Ryujinx.Tests.Cpu public void Setup() { Position = 0x1000; - Size = 0x1000; + Size = 0x1000; EntryPoint = Position; @@ -79,10 +80,12 @@ namespace Ryujinx.Tests.Cpu protected void Opcode(uint Opcode) { Thread.Memory.WriteUInt32(Position, Opcode); + if (UnicornAvailable) { UnicornEmu.MemoryWrite32((ulong)Position, Opcode); } + Position += 4; } @@ -97,14 +100,18 @@ namespace Ryujinx.Tests.Cpu Thread.ThreadState.X1 = X1; Thread.ThreadState.X2 = X2; Thread.ThreadState.X3 = X3; + Thread.ThreadState.X31 = X31; + Thread.ThreadState.V0 = V0; Thread.ThreadState.V1 = V1; Thread.ThreadState.V2 = V2; + Thread.ThreadState.Overflow = Overflow; - Thread.ThreadState.Carry = Carry; - Thread.ThreadState.Zero = Zero; + Thread.ThreadState.Carry = Carry; + Thread.ThreadState.Zero = Zero; Thread.ThreadState.Negative = Negative; + Thread.ThreadState.Fpcr = Fpcr; Thread.ThreadState.Fpsr = Fpsr; @@ -114,14 +121,18 @@ namespace Ryujinx.Tests.Cpu UnicornEmu.X[1] = X1; UnicornEmu.X[2] = X2; UnicornEmu.X[3] = X3; + UnicornEmu.SP = X31; + UnicornEmu.Q[0] = V0; UnicornEmu.Q[1] = V1; UnicornEmu.Q[2] = V2; + UnicornEmu.OverflowFlag = Overflow; - UnicornEmu.CarryFlag = Carry; - UnicornEmu.ZeroFlag = Zero; + UnicornEmu.CarryFlag = Carry; + UnicornEmu.ZeroFlag = Zero; UnicornEmu.NegativeFlag = Negative; + UnicornEmu.Fpcr = Fpcr; UnicornEmu.Fpsr = Fpsr; } @@ -144,10 +155,7 @@ namespace Ryujinx.Tests.Cpu } } - protected AThreadState GetThreadState() - { - return Thread.ThreadState; - } + protected AThreadState GetThreadState() => Thread.ThreadState; protected AThreadState SingleOpcode(uint Opcode, ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0, @@ -166,23 +174,44 @@ namespace Ryujinx.Tests.Cpu return GetThreadState(); } - protected void CompareAgainstUnicorn() + [Flags] + protected enum FPSR + { + None = 0, + + /// Invalid Operation cumulative floating-point exception bit. + IOC = 1 << 0, + /// Divide by Zero cumulative floating-point exception bit. + DZC = 1 << 1, + /// Overflow cumulative floating-point exception bit. + OFC = 1 << 2, + /// Underflow cumulative floating-point exception bit. + UFC = 1 << 3, + /// Inexact cumulative floating-point exception bit. + IXC = 1 << 4, + /// Input Denormal cumulative floating-point exception bit. + IDC = 1 << 7, + /// Cumulative saturation bit. + QC = 1 << 27 + } + + protected void CompareAgainstUnicorn(FPSR FpsrMask = FPSR.None) { if (!UnicornAvailable) { return; } - Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0])); - Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1])); - Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2])); - Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3])); - Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4])); - Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5])); - Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6])); - Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7])); - Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8])); - Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9])); + Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0])); + Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1])); + Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2])); + Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3])); + Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4])); + Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5])); + Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6])); + Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7])); + Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8])); + Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9])); Assert.That(Thread.ThreadState.X10, Is.EqualTo(UnicornEmu.X[10])); Assert.That(Thread.ThreadState.X11, Is.EqualTo(UnicornEmu.X[11])); Assert.That(Thread.ThreadState.X12, Is.EqualTo(UnicornEmu.X[12])); @@ -204,17 +233,19 @@ namespace Ryujinx.Tests.Cpu Assert.That(Thread.ThreadState.X28, Is.EqualTo(UnicornEmu.X[28])); Assert.That(Thread.ThreadState.X29, Is.EqualTo(UnicornEmu.X[29])); Assert.That(Thread.ThreadState.X30, Is.EqualTo(UnicornEmu.X[30])); + Assert.That(Thread.ThreadState.X31, Is.EqualTo(UnicornEmu.SP)); - Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0])); - Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1])); - Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2])); - Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3])); - Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4])); - Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5])); - Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6])); - Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7])); - Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8])); - Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9])); + + Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0])); + Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1])); + Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2])); + Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3])); + Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4])); + Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5])); + Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6])); + Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7])); + Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8])); + Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9])); Assert.That(Thread.ThreadState.V10, Is.EqualTo(UnicornEmu.Q[10])); Assert.That(Thread.ThreadState.V11, Is.EqualTo(UnicornEmu.Q[11])); Assert.That(Thread.ThreadState.V12, Is.EqualTo(UnicornEmu.Q[12])); @@ -238,11 +269,13 @@ namespace Ryujinx.Tests.Cpu Assert.That(Thread.ThreadState.V30, Is.EqualTo(UnicornEmu.Q[30])); Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31])); Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31])); - Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr)); - Assert.That(Thread.ThreadState.Fpsr & 0x08000000, Is.EqualTo(UnicornEmu.Fpsr & 0x08000000)); + + Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr)); + Assert.That(Thread.ThreadState.Fpsr & (int)FpsrMask, Is.EqualTo(UnicornEmu.Fpsr & (int)FpsrMask)); + Assert.That(Thread.ThreadState.Overflow, Is.EqualTo(UnicornEmu.OverflowFlag)); - Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag)); - Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag)); + Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag)); + Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag)); Assert.That(Thread.ThreadState.Negative, Is.EqualTo(UnicornEmu.NegativeFlag)); } diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 3a47dbee6..43952d195 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -1,4 +1,4 @@ -//#define Alu +#define Alu using ChocolArm64.State; @@ -6,334 +6,185 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Alu"), Ignore("Tested: second half of 2018.")] + [Category("Alu")] // Tested: second half of 2018. public sealed class CpuTestAlu : CpuTest { #if Alu - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("CLS , ")] + [Test, Pairwise, Description("CLS , ")] public void Cls_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC01400; // CLS X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Cls(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("CLS , ")] + [Test, Pairwise, Description("CLS , ")] public void Cls_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC01400; // CLS W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Cls(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } + CompareAgainstUnicorn(); } - [Test, Description("CLZ , ")] + [Test, Pairwise, Description("CLZ , ")] public void Clz_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC01000; // CLZ X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Clz(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("CLZ , ")] + [Test, Pairwise, Description("CLZ , ")] public void Clz_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC01000; // CLZ W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Clz(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("RBIT , ")] + [Test, Pairwise, Description("RBIT , ")] public void Rbit_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00000; // RBIT X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("RBIT , ")] + [Test, Pairwise, Description("RBIT , ")] public void Rbit_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00000; // RBIT W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV16 , ")] + [Test, Pairwise, Description("REV16 , ")] public void Rev16_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00400; // REV16 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV16 , ")] + [Test, Pairwise, Description("REV16 , ")] public void Rev16_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00400; // REV16 W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV32 , ")] + [Test, Pairwise, Description("REV32 , ")] public void Rev32_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00800; // REV32 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV , ")] + [Test, Pairwise, Description("REV , ")] public void Rev32_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn) { uint Opcode = 0x5AC00800; // REV W0, W0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("REV64 , ")] + [Test, Pairwise, Description("REV64 , ")] public void Rev64_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn) { uint Opcode = 0xDAC00C00; // REV64 X0, X0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Rev64(Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs index b648a337e..61eadefd3 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs @@ -1,4 +1,4 @@ -//#define AluImm +#define AluImm using ChocolArm64.State; @@ -6,824 +6,448 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluImm"), Ignore("Tested: second half of 2018.")] + [Category("AluImm")] // Tested: second half of 2018. public sealed class CpuTestAluImm : CpuTest { #if AluImm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImm = 2; + private const int RndCntImms = 2; + private const int RndCntImmr = 2; - [Test, Description("ADD , , #{, }")] + [Test, Pairwise, Description("ADD , , #{, }")] public void Add_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , #{, }")] + [Test, Pairwise, Description("ADD , , #{, }")] public void Add_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADDS , , #{, }")] + [Test, Pairwise, Description("ADDS , , #{, }")] public void Adds_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , #{, }")] + [Test, Pairwise, Description("ADDS , , #{, }")] public void Adds_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0x92400000; // AND X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x92000000; // AND X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , #")] + [Test, Pairwise, Description("AND , , #")] public void And_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x12000000; // AND W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , #")] + [Test, Pairwise, Description("ANDS , , #")] public void Ands_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x72000000; // ANDS W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xD2400000; // EOR X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , #")] + [Test, Pairwise, Description("EOR , , #")] public void Eor_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x52000000; // EOR W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_N1_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // { uint Opcode = 0xB2400000; // ORR X0, X0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_N0_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , #")] + [Test, Pairwise, Description("ORR , , #")] public void Orr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // { uint Opcode = 0x32000000; // ORR W0, W0, #0x1 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , #{, }")] + [Test, Pairwise, Description("SUB , , #{, }")] public void Sub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , #{, }")] + [Test, Pairwise, Description("SUB , , #{, }")] public void Sub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , #{, }")] + [Test, Pairwise, Description("SUBS , , #{, }")] public void Subs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Xn_SP); - - AArch64.X((int)Rn, new Bits(Xn_SP)); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP); - - AArch64.SP(new Bits(Xn_SP)); } - Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , #{, }")] + [Test, Pairwise, Description("SUBS , , #{, }")] public void Subs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, - [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm, [Values(0b00u, 0b01u)] uint shift) // { uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); - - AArch64.X((int)Rn, new Bits(Wn_WSP)); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); - - AArch64.SP(new Bits(Wn_WSP)); } - Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs index 49c82b742..58a99dfb1 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -1,4 +1,4 @@ -//#define AluRs +#define AluRs using ChocolArm64.State; @@ -6,1958 +6,1117 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluRs"), Ignore("Tested: second half of 2018.")] + [Category("AluRs")] // Tested: second half of 2018. public sealed class CpuTestAluRs : CpuTest { #if AluRs - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntAmount = 2; + private const int RndCntLsb = 2; - [Test, Description("ADC , , ")] + [Test, Pairwise, Description("ADC , , ")] public void Adc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0x9A000000; // ADC X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADC , , ")] + [Test, Pairwise, Description("ADC , , ")] public void Adc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x1A000000; // ADC W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADCS , , ")] + [Test, Pairwise, Description("ADCS , , ")] public void Adcs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xBA000000; // ADCS X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADCS , , ")] + [Test, Pairwise, Description("ADCS , , ")] public void Adcs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x3A000000; // ADCS W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, #}")] + [Test, Pairwise, Description("ADD , , {, #}")] public void Add_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, #}")] + [Test, Pairwise, Description("ADD , , {, #}")] public void Add_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - CompareAgainstUnicorn(); - } + CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, #}")] + [Test, Pairwise, Description("ADDS , , {, #}")] public void Adds_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, #}")] + [Test, Pairwise, Description("ADDS , , {, #}")] public void Adds_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("AND , , {, #}")] + [Test, Pairwise, Description("AND , , {, #}")] public void And_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8A000000; // AND X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("AND , , {, #}")] + [Test, Pairwise, Description("AND , , {, #}")] public void And_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0A000000; // AND W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ANDS , , {, #}")] + [Test, Pairwise, Description("ANDS , , {, #}")] public void Ands_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ANDS , , {, #}")] + [Test, Pairwise, Description("ANDS , , {, #}")] public void Ands_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ASRV , , ")] + [Test, Pairwise, Description("ASRV , , ")] public void Asrv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02800; // ASRV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ASRV , , ")] + [Test, Pairwise, Description("ASRV , , ")] public void Asrv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02800; // ASRV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("BIC , , {, #}")] + [Test, Pairwise, Description("BIC , , {, #}")] public void Bic_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("BIC , , {, #}")] + [Test, Pairwise, Description("BIC , , {, #}")] public void Bic_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("BICS , , {, #}")] + [Test, Pairwise, Description("BICS , , {, #}")] public void Bics_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("BICS , , {, #}")] + [Test, Pairwise, Description("BICS , , {, #}")] public void Bics_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CRC32X , , ")] + [Test, Pairwise, Description("CRC32X , , "), Ignore("Unicorn fails.")] public void Crc32x([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ulong)0x00_00_00_00_00_00_00_00, (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, (ulong)0x80_00_00_00_00_00_00_00, - (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC04C00; // CRC32X W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32W , , ")] + [Test, Pairwise, Description("CRC32W , , "), Ignore("Unicorn fails.")] public void Crc32w([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, - (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC04800; // CRC32W W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32H , , ")] + [Test, Pairwise, Description("CRC32H , , "), Ignore("Unicorn fails.")] public void Crc32h([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ushort)0x00_00, (ushort)0x7F_FF, - (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort Wm) { uint Opcode = 0x1AC04400; // CRC32H W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32B , , ")] + [Test, Pairwise, Description("CRC32B , , "), Ignore("Unicorn fails.")] public void Crc32b([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm) { uint Opcode = 0x1AC04000; // CRC32B W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CX , , ")] + [Test, Pairwise, Description("CRC32CX , , ")] public void Crc32cx([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ulong)0x00_00_00_00_00_00_00_00, (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, (ulong)0x80_00_00_00_00_00_00_00, - (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC05C00; // CRC32CX W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CW , , ")] + [Test, Pairwise, Description("CRC32CW , , ")] public void Crc32cw([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, - (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC05800; // CRC32CW W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CH , , ")] + [Test, Pairwise, Description("CRC32CH , , ")] public void Crc32ch([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((ushort)0x00_00, (ushort)0x7F_FF, - (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(RndCnt)] ushort Wm) { uint Opcode = 0x1AC05400; // CRC32CH W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("CRC32CB , , ")] + [Test, Pairwise, Description("CRC32CB , , ")] public void Crc32cb([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, - [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm) { uint Opcode = 0x1AC05000; // CRC32CB W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EON , , {, #}")] + [Test, Pairwise, Description("EON , , {, #}")] public void Eon_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCA200000; // EON X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EON , , {, #}")] + [Test, Pairwise, Description("EON , , {, #}")] public void Eon_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4A200000; // EON W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , {, #}")] + [Test, Pairwise, Description("EOR , , {, #}")] public void Eor_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EOR , , {, #}")] + [Test, Pairwise, Description("EOR , , {, #}")] public void Eor_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("EXTR , , , #")] + [Test, Pairwise, Description("EXTR , , , #")] public void Extr_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint lsb) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntLsb)] uint lsb) { uint Opcode = 0x93C00000; // EXTR X0, X0, X0, #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((lsb & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("EXTR , , , #")] + [Test, Pairwise, Description("EXTR , , , #")] public void Extr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint lsb) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntLsb)] uint lsb) { uint Opcode = 0x13800000; // EXTR W0, W0, W0, #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((lsb & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSLV , , ")] + [Test, Pairwise, Description("LSLV , , ")] public void Lslv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02000; // LSLV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSLV , , ")] + [Test, Pairwise, Description("LSLV , , ")] public void Lslv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02000; // LSLV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSRV , , ")] + [Test, Pairwise, Description("LSRV , , ")] public void Lsrv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02400; // LSRV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("LSRV , , ")] + [Test, Pairwise, Description("LSRV , , ")] public void Lsrv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02400; // LSRV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORN , , {, #}")] + [Test, Pairwise, Description("ORN , , {, #}")] public void Orn_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORN , , {, #}")] + [Test, Pairwise, Description("ORN , , {, #}")] public void Orn_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , {, #}")] + [Test, Pairwise, Description("ORR , , {, #}")] public void Orr_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("ORR , , {, #}")] + [Test, Pairwise, Description("ORR , , {, #}")] public void Orr_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("RORV , , ")] + [Test, Pairwise, Description("RORV , , ")] public void Rorv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC02C00; // RORV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("RORV , , ")] + [Test, Pairwise, Description("RORV , , ")] public void Rorv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC02C00; // RORV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBC , , ")] + [Test, Pairwise, Description("SBC , , ")] public void Sbc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xDA000000; // SBC X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBC , , ")] + [Test, Pairwise, Description("SBC , , ")] public void Sbc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x5A000000; // SBC W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBCS , , ")] + [Test, Pairwise, Description("SBCS , , ")] public void Sbcs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values] bool CarryIn) { uint Opcode = 0xFA000000; // SBCS X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Shared.PSTATE.C = CarryIn; - Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SBCS , , ")] + [Test, Pairwise, Description("SBCS , , ")] public void Sbcs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values] bool CarryIn) { uint Opcode = 0x7A000000; // SBCS W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Shared.PSTATE.C = CarryIn; - Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SDIV , , ")] + [Test, Pairwise, Description("SDIV , , ")] public void Sdiv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC00C00; // SDIV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SDIV , , ")] + [Test, Pairwise, Description("SDIV , , ")] public void Sdiv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC00C00; // SDIV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, #}")] + [Test, Pairwise, Description("SUB , , {, #}")] public void Sub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, #}")] + [Test, Pairwise, Description("SUB , , {, #}")] public void Sub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, #}")] + [Test, Pairwise, Description("SUBS , , {, #}")] public void Subs_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntAmount)] uint amount) { uint Opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - if (Rd != 31) - { - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, #}")] + [Test, Pairwise, Description("SUBS , , {, #}")] public void Subs_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b00u, 0b01u, 0b10u)] uint shift, // - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntAmount)] uint amount) { uint Opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); - Bits Op = new Bits(Opcode); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - if (Rd != 31) - { - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("UDIV , , ")] + [Test, Pairwise, Description("UDIV , , ")] public void Udiv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9AC00800; // UDIV X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UDIV , , ")] + [Test, Pairwise, Description("UDIV , , ")] public void Udiv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm) { uint Opcode = 0x1AC00800; // UDIV W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs index 41fd580a6..9c66532b9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs @@ -1,4 +1,4 @@ -//#define AluRx +#define AluRx using ChocolArm64.State; @@ -6,77 +6,51 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("AluRx"), Ignore("Tested: second half of 2018.")] + [Category("AluRx")] // Tested: second half of 2018. public sealed class CpuTestAluRx : CpuTest { #if AluRx - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0x8B206000; // ADD X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Xm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -84,50 +58,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -135,50 +90,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -186,50 +122,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -237,50 +154,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -288,50 +186,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADD , , {, {#}}")] + [Test, Pairwise, Description("ADD , , {, {#}}")] public void Add_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -339,95 +218,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xAB206000; // ADDS X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -435,45 +270,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -481,45 +291,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -527,45 +312,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -573,45 +333,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -619,45 +354,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("ADDS , , {, {#}}")] + [Test, Pairwise, Description("ADDS , , {, {#}}")] public void Adds_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -665,95 +375,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xCB206000; // SUB X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Xm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -761,50 +427,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -812,50 +459,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -863,50 +491,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { ulong _X31 = TestContext.CurrentContext.Random.NextULong(); - ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); - AArch64.X((int)Rn, new Bits(Xn_SP)); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); } else { ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); - - AArch64.SP(new Bits(Xn_SP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong SP = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -914,50 +523,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -965,50 +555,31 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUB , , {, {#}}")] + [Test, Pairwise, Description("SUB , , {, {#}}")] public void Sub_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1016,95 +587,51 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState; if (Rn != 31) { uint _W31 = TestContext.CurrentContext.Random.NextUInt(); - ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); - AArch64.X((int)Rn, new Bits(Wn_WSP)); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); } else { ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); - - AArch64.SP(new Bits(Wn_WSP)); } - AArch64.X((int)Rm, new Bits(Wm)); - Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint WSP = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); - } CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_X_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, - (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(RndCnt)] ulong Xm, [Values(0b011u, 0b111u)] uint extend, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) { uint Opcode = 0xEB206000; // SUBS X0, X0, X0, UXTX #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_W_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1112,45 +639,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_H_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1158,45 +660,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_B_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1204,45 +681,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); - AArch64.X((int)Rn, new Bits(Xn_SP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Xn_SP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - ulong _X31 = AArch64.SP(64).ToUInt64(); - - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_W_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((uint)0x00000000, (uint)0x7FFFFFFF, - (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(RndCnt)] uint Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1250,45 +702,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_H_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((ushort)0x0000, (ushort)0x7FFF, - (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + (ushort)0x8000, (ushort)0xFFFF)] [Random(RndCnt)] ushort Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1296,45 +723,20 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("SUBS , , {, {#}}")] + [Test, Pairwise, Description("SUBS , , {, {#}}")] public void Subs_B_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP, [Values((byte)0x00, (byte)0x7F, - (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + (byte)0x80, (byte)0xFF)] [Random(RndCnt)] byte Wm, [Values(0b000u, 0b001u, 0b010u, 0b011u, // [Values(0u, 1u, 2u, 3u, 4u)] uint amount) @@ -1342,34 +744,9 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); - Bits Op = new Bits(Opcode); AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); - AArch64.X((int)Rn, new Bits(Wn_WSP)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.SP(new Bits(Wn_WSP)); - Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); - - if (Rd != 31) - { - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - uint _W31 = AArch64.SP(32).ToUInt32(); - - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } - Assert.Multiple(() => - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs index c5be57885..427396f8b 100644 --- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -1,4 +1,4 @@ -//#define Bfm +#define Bfm using ChocolArm64.State; @@ -6,212 +6,127 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Bfm"), Ignore("Tested: second half of 2018.")] + [Category("Bfm")] // Tested: second half of 2018. public sealed class CpuTestBfm : CpuTest { #if Bfm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImmr = 2; + private const int RndCntImms = 2; - [Test, Description("BFM , , #, #")] + [Test, Pairwise, Description("BFM , , #, #")] public void Bfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, - [Random(2)] ulong _Xd, + [Random(RndCnt)] ulong _Xd, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Xd)); - AArch64.X((int)Rn, new Bits(Xn)); - Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("BFM , , #, #")] + [Test, Pairwise, Description("BFM , , #, #")] public void Bfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, - [Random(2)] uint _Wd, + [Random(RndCnt)] uint _Wd, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x33000000; // BFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Wd)); - AArch64.X((int)Rn, new Bits(Wn)); - Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBFM , , #, #")] + [Test, Pairwise, Description("SBFM , , #, #")] public void Sbfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SBFM , , #, #")] + [Test, Pairwise, Description("SBFM , , #, #")] public void Sbfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("UBFM , , #, #")] + [Test, Pairwise, Description("UBFM , , #, #")] public void Ubfm_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, - [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms) { uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UBFM , , #, #")] + [Test, Pairwise, Description("UBFM , , #, #")] public void Ubfm_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, - [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms) { uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs index 245b04c0a..7ca92d4fe 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs @@ -1,4 +1,4 @@ -//#define CcmpImm +#define CcmpImm using ChocolArm64.State; @@ -6,25 +6,20 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("CcmpImm"), Ignore("Tested: second half of 2018.")] + [Category("CcmpImm")] // Tested: second half of 2018. public sealed class CpuTestCcmpImm : CpuTest { #if CcmpImm - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntImm = 2; + private const int RndCntNzcv = 2; - [Test, Description("CCMN , #, #, ")] + [Test, Pairwise, Description("CCMN , #, #, ")] public void Ccmn_64bit([Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMN , #, #, ")] + [Test, Pairwise, Description("CCMN , #, #, ")] public void Ccmn_32bit([Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , #, #, ")] + [Test, Pairwise, Description("CCMP , #, #, ")] public void Ccmp_64bit([Values(1u, 31u)] uint Rn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , #, #, ")] + [Test, Pairwise, Description("CCMP , #, #, ")] public void Ccmp_32bit([Values(1u, 31u)] uint Rn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, - [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs index 8c4e503ee..36120f740 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs @@ -1,4 +1,4 @@ -//#define CcmpReg +#define CcmpReg using ChocolArm64.State; @@ -6,27 +6,21 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("CcmpReg"), Ignore("Tested: second half of 2018.")] + [Category("CcmpReg")] // Tested: second half of 2018. public sealed class CpuTestCcmpReg : CpuTest { #if CcmpReg - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; + private const int RndCntNzcv = 2; - [Test, Description("CCMN , , #, ")] + [Test, Pairwise, Description("CCMN , , #, ")] public void Ccmn_64bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMN , , #, ")] + [Test, Pairwise, Description("CCMN , , #, ")] public void Ccmn_32bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , , #, ")] + [Test, Pairwise, Description("CCMP , , #, ")] public void Ccmp_64bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, - [Random(0u, 15u, 1)] uint nzcv, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } - [Test, Description("CCMP , , #, ")] + [Test, Pairwise, Description("CCMP , , #, ")] public void Ccmp_32bit([Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, - [Random(0u, 15u, 1)] uint nzcv, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, + [Random(0u, 15u, RndCntNzcv)] uint nzcv, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // - { - Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); - Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); - Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); - Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/Ryujinx.Tests/Cpu/CpuTestCsel.cs index d532a12c6..2d88b9f03 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCsel.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCsel.cs @@ -1,4 +1,4 @@ -//#define Csel +#define Csel using ChocolArm64.State; @@ -6,27 +6,20 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Csel"), Ignore("Tested: second half of 2018.")] + [Category("Csel")] // Tested: second half of 2018. public sealed class CpuTestCsel : CpuTest { #if Csel - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("CSEL , , , ")] + [Test, Pairwise, Description("CSEL , , , ")] public void Csel_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSEL , , , ")] public void Csel_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINC , , , ")] public void Csinc_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINC , , , ")] public void Csinc_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINV , , , ")] public void Csinv_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSINV , , , ")] public void Csinv_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSNEG , , , ")] public void Csneg_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , , , ")] + [Test, Pairwise, Description("CSNEG , , , ")] public void Csneg_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // , #{, LSL #}")] + [Test, Pairwise, Description("MOVK , #{, LSL #}")] public void Movk_64bit([Values(0u, 31u)] uint Rd, - [Random(12)] ulong _Xd, - [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Random(RndCntImm)] ulong _Xd, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0 @@ -30,29 +23,16 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Xd)); - Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVK , #{, LSL #}")] + [Test, Pairwise, Description("MOVK , #{, LSL #}")] public void Movk_32bit([Values(0u, 31u)] uint Rd, - [Random(12)] uint _Wd, - [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Random(RndCntImm)] uint _Wd, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0 @@ -60,28 +40,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rd, new Bits(_Wd)); - Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVN , #{, LSL #}")] + [Test, Pairwise, Description("MOVN , #{, LSL #}")] public void Movn_64bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0 @@ -89,27 +56,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVN , #{, LSL #}")] + [Test, Pairwise, Description("MOVN , #{, LSL #}")] public void Movn_32bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0 @@ -117,27 +72,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVZ , #{, LSL #}")] + [Test, Pairwise, Description("MOVZ , #{, LSL #}")] public void Movz_64bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u, 32u, 48u)] uint shift) { uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0 @@ -145,27 +88,15 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MOVZ , #{, LSL #}")] + [Test, Pairwise, Description("MOVZ , #{, LSL #}")] public void Movz_32bit([Values(0u, 31u)] uint Rd, - [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm, [Values(0u, 16u)] uint shift) { uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0 @@ -173,21 +104,9 @@ namespace Ryujinx.Tests.Cpu Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs index 2e8aa76fa..056c45437 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMul.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs @@ -1,4 +1,4 @@ -//#define Mul +#define Mul using ChocolArm64.State; @@ -6,378 +6,223 @@ using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Mul"), Ignore("Tested: second half of 2018.")] + [Category("Mul")] // Tested: second half of 2018. public sealed class CpuTestMul : CpuTest { #if Mul - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } + private const int RndCnt = 2; - [Test, Description("MADD , , , ")] + [Test, Pairwise, Description("MADD , , , ")] public void Madd_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MADD , , , ")] + [Test, Pairwise, Description("MADD , , , ")] public void Madd_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa) { uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Wa)); - Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("MSUB , , , ")] + [Test, Pairwise, Description("MSUB , , , ")] public void Msub_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("MSUB , , , ")] + [Test, Pairwise, Description("MSUB , , , ")] public void Msub_32bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa) { uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Wa)); - Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - - Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); - } - else - { - Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMADDL , , , ")] + [Test, Pairwise, Description("SMADDL , , , ")] public void Smaddl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Smaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMADDL , , , ")] + [Test, Pairwise, Description("UMADDL , , , ")] public void Umaddl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMSUBL , , , ")] + [Test, Pairwise, Description("SMSUBL , , , ")] public void Smsubl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Smsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMSUBL , , , ")] + [Test, Pairwise, Description("UMSUBL , , , ")] public void Umsubl_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(3u, 31u)] uint Ra, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn, [Values(0x00000000u, 0x7FFFFFFFu, - 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + 0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa) { uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0 Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Wn)); - AArch64.X((int)Rm, new Bits(Wm)); - AArch64.X((int)Ra, new Bits(Xa)); - Base.Umsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("SMULH , , ")] + [Test, Pairwise, Description("SMULH , , ")] public void Smulh_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9B407C00; // SMULH X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Smulh(Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } - [Test, Description("UMULH , , ")] + [Test, Pairwise, Description("UMULH , , ")] public void Umulh_64bit([Values(0u, 31u)] uint Rd, [Values(1u, 31u)] uint Rn, [Values(2u, 31u)] uint Rm, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn, [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, - 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm) { uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); - if (Rd != 31) - { - Bits Op = new Bits(Opcode); - - AArch64.X((int)Rn, new Bits(Xn)); - AArch64.X((int)Rm, new Bits(Xm)); - Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]); - ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); - - Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); - } - else - { - Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); - } CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 37fb3e976..ec0cd104f 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -8,18 +8,10 @@ using System.Runtime.Intrinsics; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("Simd")/*, Ignore("Tested: second half of 2018.")*/] + [Category("Simd")] // Tested: second half of 2018. public sealed class CpuTestSimd : CpuTest { #if Simd - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } #region "ValueSource" private static ulong[] _1B1H1S1D_() @@ -156,7 +148,7 @@ namespace Ryujinx.Tests.Cpu } #endregion - private const int RndCnt = 4; + private const int RndCnt = 2; [Test, Pairwise, Description("ABS , ")] public void Abs_S_D([Values(0u)] uint Rd, @@ -166,21 +158,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE0B800; // ABS D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Abs_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -194,21 +177,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20B800; // ABS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -222,21 +196,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20B800; // ABS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -248,21 +213,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EF1B800; // ADDP D0, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Addp_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -276,21 +232,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E31B800; // ADDV B0, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -304,21 +251,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E31B800; // ADDV B0, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Addv_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -332,21 +270,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E204800; // CLS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -360,21 +289,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E204800; // CLS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cls_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -388,21 +308,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E204800; // CLZ V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -416,21 +327,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E204800; // CLZ V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Clz_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -442,21 +344,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE09800; // CMEQ D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmeq_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -470,21 +363,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E209800; // CMEQ V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -498,21 +382,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E209800; // CMEQ V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmeq_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -524,21 +399,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08800; // CMGE D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmge_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -552,21 +418,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208800; // CMGE V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -580,21 +437,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208800; // CMGE V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmge_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -606,21 +454,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08800; // CMGT D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmgt_Zero_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -634,21 +473,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208800; // CMGT V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -662,21 +492,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208800; // CMGT V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmgt_Zero_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -688,21 +509,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE09800; // CMLE D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmle_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -716,21 +528,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E209800; // CMLE V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -744,21 +547,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E209800; // CMLE V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmle_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -770,21 +564,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE0A800; // CMLT D0, D0, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmlt_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -798,21 +583,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20A800; // CMLT V0.8B, V0.8B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -826,21 +602,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20A800; // CMLT V0.16B, V0.16B, #0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cmlt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -852,21 +619,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E205800; // CNT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -878,21 +636,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E205800; // CNT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Cnt_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -904,37 +653,17 @@ namespace Ryujinx.Tests.Cpu { //const int FZFlagBit = 24; // Flush-to-zero mode control bit. - //const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit. - //const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit. - //const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit. - uint Opcode = 0x5E21A800; // FCVTNS S0, S0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - //Shared.FPCR = new Bits((uint)Fpcr); - SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - /*Assert.Multiple(() => - { - Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit])); - });*/ + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNS , ")] @@ -943,23 +672,19 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_F_")] [Random(RndCnt)] ulong A) { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x5E61A800; // FCVTNS D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Fcvtns_S(Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNS ., .")] @@ -969,24 +694,20 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_2S_F_")] [Random(RndCnt)] ulong A, [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((Q & 1) << 30); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A * Q); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q)); - SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNS ., .")] @@ -995,23 +716,19 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_F_")] [Random(RndCnt)] ulong A) { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Fcvtns_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNU , ")] @@ -1022,37 +739,17 @@ namespace Ryujinx.Tests.Cpu { //const int FZFlagBit = 24; // Flush-to-zero mode control bit. - //const int IDCFlagBit = 7; // Input Denormal cumulative floating-point exception bit. - //const int IXCFlagBit = 4; // Inexact cumulative floating-point exception bit. - //const int IOCFlagBit = 0; // Invalid Operation cumulative floating-point exception bit. - uint Opcode = 0x7E21A800; // FCVTNU S0, S0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - //Shared.FPCR = new Bits((uint)Fpcr); - SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - /*Assert.Multiple(() => - { - Assert.That(((ThreadState.Fpsr >> IDCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IDCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IXCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IXCFlagBit])); - Assert.That(((ThreadState.Fpsr >> IOCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[IOCFlagBit])); - });*/ + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNU , ")] @@ -1061,23 +758,19 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_F_")] [Random(RndCnt)] ulong A) { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x7E61A800; // FCVTNU D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Fcvtnu_S(Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNU ., .")] @@ -1087,24 +780,20 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_2S_F_")] [Random(RndCnt)] ulong A, [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((Q & 1) << 30); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A * Q); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A * Q)); - SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("FCVTNU ., .")] @@ -1113,23 +802,19 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1D_F_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_F_")] [Random(RndCnt)] ulong A) { + //const int FZFlagBit = 24; // Flush-to-zero mode control bit. + uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); + + //int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled. Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Fcvtnu_V(Op[30], Op[22], Op[9, 5], Op[4, 0]); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/); } [Test, Pairwise, Description("NEG , ")] @@ -1140,21 +825,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE0B800; // NEG D0, D0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Neg_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1168,21 +844,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E20B800; // NEG V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1196,21 +863,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E20B800; // NEG V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1222,21 +880,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E205800; // NOT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1248,21 +897,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E205800; // NOT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Not_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1274,21 +914,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E605800; // RBIT V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1300,21 +931,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E605800; // RBIT V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rbit_V(Op[30], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1326,21 +948,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E201800; // REV16 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1352,21 +965,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E201800; // REV16 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev16_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1380,21 +984,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200800; // REV32 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1408,21 +1003,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200800; // REV32 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev32_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1436,21 +1022,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200800; // REV64 V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1464,21 +1041,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200800; // REV64 V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Rev64_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1492,21 +1060,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E206800; // SADALP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1520,21 +1079,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E206800; // SADALP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1548,21 +1098,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202800; // SADDLP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1576,21 +1117,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202800; // SADDLP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Saddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1602,26 +1134,12 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - SimdFp.Sha256su0_V(Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1632,28 +1150,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E207800; // SQABS B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqabs_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQABS ., .")] @@ -1663,28 +1169,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E207800; // SQABS V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQABS ., .")] @@ -1694,28 +1188,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E207800; // SQABS V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQNEG , ")] @@ -1725,28 +1207,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E207800; // SQNEG B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqneg_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQNEG ., .")] @@ -1756,28 +1226,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E207800; // SQNEG V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQNEG ., .")] @@ -1787,28 +1245,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E207800; // SQNEG V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTN , ")] @@ -1818,28 +1264,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E214800; // SQXTN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTN{2} ., .")] @@ -1849,28 +1283,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E214800; // SQXTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTN{2} ., .")] @@ -1880,28 +1302,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E214800; // SQXTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTUN , ")] @@ -1911,28 +1321,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E212800; // SQXTUN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTUN{2} ., .")] @@ -1942,28 +1340,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E212800; // SQXTUN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQXTUN{2} ., .")] @@ -1973,28 +1359,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E212800; // SQXTUN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SUQADD , ")] @@ -2004,28 +1378,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E203800; // SUQADD B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Suqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SUQADD ., .")] @@ -2035,28 +1397,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E203800; // SUQADD V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SUQADD ., .")] @@ -2066,28 +1416,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E203800; // SUQADD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UADALP ., .")] @@ -2100,21 +1438,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E206800; // UADALP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2128,21 +1457,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E206800; // UADALP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uadalp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2156,21 +1476,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202800; // UADDLP V0.4H, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2184,21 +1495,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202800; // UADDLP V0.8H, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uaddlp_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2209,28 +1511,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E214800; // UQXTN B0, H0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Uqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQXTN{2} ., .")] @@ -2240,28 +1530,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H8B, 4S4H, 2D2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E214800; // UQXTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQXTN{2} ., .")] @@ -2271,28 +1549,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8H16B, 4S8H, 2D4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E214800; // UQXTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("USQADD , ")] @@ -2302,28 +1568,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E203800; // USQADD B0, B0 Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Usqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("USQADD ., .")] @@ -2333,28 +1587,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E203800; // USQADD V0.8B, V0.8B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("USQADD ., .")] @@ -2364,28 +1606,16 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E203800; // USQADD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("XTN{2} ., .")] @@ -2398,21 +1628,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E212800; // XTN V0.8B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2426,21 +1647,12 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E212800; // XTN2 V0.16B, V0.8H Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - SimdFp.Xtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index e9fd462eb..7a67d53b9 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu { public class CpuTestSimdArithmetic : CpuTest { - [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] // FMAX S0, S1, S2 [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] [TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)] @@ -22,17 +22,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)] [TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)] [TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)] - [TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] + [TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] // FMAX D0, D1, D2 [TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)] [TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)] public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result) { - // FMAX S0, S1, S2 - AThreadState ThreadState = SingleOpcode(Opcode, - V1: Sse.StaticCast(Sse2.SetVector128(0, A)), - V2: Sse.StaticCast(Sse2.SetVector128(0, B))); - Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast(ThreadState.V0), 0)); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } @@ -51,19 +53,23 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)] public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) { - uint Opcode = 0x4E22F420; + uint Opcode = 0x4E22F420; // FMAX V0.4S, V1.4S, V2.4S + Vector128 V1 = MakeVectorE0E1(A, B); Vector128 V2 = MakeVectorE0E1(C, D); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } - [TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] + [TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] // FMIN S0, S1, S2 [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)] [TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] [TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)] @@ -76,17 +82,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)] [TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)] [TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)] - [TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] + [TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] // FMIN D0, D1, D2 [TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] [TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)] public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result) { - // FMIN S0, S1, S2 - AThreadState ThreadState = SingleOpcode(Opcode, - V1: Sse.StaticCast(Sse2.SetVector128(0, A)), - V2: Sse.StaticCast(Sse2.SetVector128(0, B))); - Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast(ThreadState.V0), 0)); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } @@ -105,15 +113,19 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)] public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1) { - uint Opcode = 0x4EA2F420; + uint Opcode = 0x4EA2F420; // FMIN V0.4S, V1.4S, V2.4S + Vector128 V1 = MakeVectorE0E1(A, B); Vector128 V2 = MakeVectorE0E1(C, D); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -125,6 +137,7 @@ namespace Ryujinx.Tests.Cpu V0: Sse.SetVector128(0, B, 0, 0)); Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B)); + CompareAgainstUnicorn(); } @@ -137,21 +150,27 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x007FF000u, 0x7E800000u)] public void Frecpe_S(uint A, uint Result) { + uint Opcode = 0x5EA1D820; // FRECPE S0, S1 + Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x5EA1D820, V1: V1); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [Test, Description("FRECPS D0, D1, D2")] + [Test, Description("FRECPS D0, D1, D2"), Ignore("Not accurate enough.")] public void Frecps_S([Random(10)] double A, [Random(10)] double B) { AThreadState ThreadState = SingleOpcode(0x5E62FC20, V1: MakeVectorE0(A), V2: MakeVectorE0(B)); - Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B))); - //CompareAgainstUnicorn(); // Not accurate enough + Assert.That(VectorExtractDouble(ThreadState.V0, (byte)0), Is.EqualTo(2 - (A * B))); + + CompareAgainstUnicorn(); } [Test, Description("FRECPS V4.4S, V2.4S, V0.4S")] @@ -170,6 +189,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(Result)); Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(Result)); }); + CompareAgainstUnicorn(); } @@ -177,7 +197,7 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x3F99999Au, false, 0x3F800000u)] [TestCase(0x404CCCCDu, false, 0x40400000u)] [TestCase(0x40733333u, false, 0x40800000u)] - [TestCase(0x3fc00000u, false, 0x40000000u)] + [TestCase(0x3FC00000u, false, 0x40000000u)] [TestCase(0x40200000u, false, 0x40400000u)] [TestCase(0x00000000u, false, 0x00000000u)] [TestCase(0x00000000u, false, 0x00000000u)] @@ -213,42 +233,53 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frinta_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E264020; // FRINTA S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [Ignore("Wrong opcodes.")] + [TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTA V0.2D, V1.2D [TestCase(0x6E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] - [TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTX V0.4S, V1.4S + [TestCase(0x6E219820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] + [TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S + [TestCase(0x2E219820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] // FRINTA V0.2S, V1.2S [TestCase(0x2E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] [TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] [TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frinta_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -294,36 +325,31 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")] public void Frinti_S(uint A, char RoundType, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E27C020; // FRINTI S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E27C020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTI V0.2D, V1.2D [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] @@ -331,14 +357,14 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] - [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] - [TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] + [TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTI V0.4S, V1.4S + [TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] + [TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] + [TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] + [TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTI V0.2S, V1.2S + [TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x0000000000000000ul)] + [TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x0000000000000000ul)] [TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)] [TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'P', false, 0x0000000080000000ul, 0x0000000000000000ul)] [TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'M', false, 0x0000000080000000ul, 0x0000000000000000ul)] @@ -357,36 +383,29 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x2EA19820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frinti_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -394,7 +413,7 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x3F99999Au, false, 0x3F800000u)] [TestCase(0x404CCCCDu, false, 0x40400000u)] [TestCase(0x40733333u, false, 0x40400000u)] - [TestCase(0x3fc00000u, false, 0x3F800000u)] + [TestCase(0x3FC00000u, false, 0x3F800000u)] [TestCase(0x40200000u, false, 0x40000000u)] [TestCase(0x00000000u, false, 0x00000000u)] [TestCase(0x00000000u, false, 0x00000000u)] @@ -430,47 +449,58 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintm_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E254020; // FRINTM S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E254020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTM V0.2D, V1.2D [TestCase(0x4E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x4E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] // FRINTM V0.4S, V1.4S + [TestCase(0x0E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F8000003F800000ul, 0x0000000000000000ul)] // FRINTM V0.2S, V1.2S + [TestCase(0x0E219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0E219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintm_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } + [Ignore("Wrong opcode.")] [TestCase(0x3FE66666u, false, 0x40000000u)] [TestCase(0x3F99999Au, false, 0x3F800000u)] [TestCase(0x404CCCCDu, false, 0x40400000u)] [TestCase(0x40733333u, false, 0x40800000u)] - [TestCase(0x3fc00000u, false, 0x40000000u)] + [TestCase(0x3FC00000u, false, 0x40000000u)] [TestCase(0x40200000u, false, 0x40400000u)] [TestCase(0x00000000u, false, 0x00000000u)] [TestCase(0x00000000u, false, 0x00000000u)] @@ -506,42 +536,52 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintn_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E264020; // FRINTA S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTN V0.2D, V1.2D [TestCase(0x4E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x4E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)] - [TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x4E218820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTN V0.4S, V1.4S + [TestCase(0x4E218820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] + [TestCase(0x0E218820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTN V0.2S, V1.2S + [TestCase(0x0E218820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintn_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -549,7 +589,7 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x3F99999Au, false, 0x40000000u)] [TestCase(0x404CCCCDu, false, 0x40800000u)] [TestCase(0x40733333u, false, 0x40800000u)] - [TestCase(0x3fc00000u, false, 0x40000000u)] + [TestCase(0x3FC00000u, false, 0x40000000u)] [TestCase(0x40200000u, false, 0x40400000u)] [TestCase(0x00000000u, false, 0x00000000u)] [TestCase(0x00000000u, false, 0x00000000u)] @@ -585,39 +625,49 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintp_S(uint A, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E24C020; // FRINTP S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E24C020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] + [TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] // FRINTP V0.2D, v1.2D [TestCase(0x4EE18820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)] - [TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] - [TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] - [TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x4EA18820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] // FRINTP V0.4S, v1.4S + [TestCase(0x0EA18820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] // FRINTP V0.2S, v1.2S + [TestCase(0x0EA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] + [TestCase(0x0EA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)] + [TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")] + [TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintp_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; if(DefaultNaN) { FpcrTemp = 0x2000000; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } @@ -663,36 +713,31 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")] public void Frintx_S(uint A, char RoundType, bool DefaultNaN, uint Result) { + uint Opcode = 0x1E274020; // FRINTX S0, S1 + + Vector128 V1 = MakeVectorE0(A); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } - [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] + [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTX V0.2D, V1.2D [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)] @@ -700,14 +745,14 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] [TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] - [TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)] + [TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTX V0.4S, V1.4S + [TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)] + [TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] + [TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] + [TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S + [TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)] + [TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x0000000000000000ul)] + [TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x0000000000000000ul)] [TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)] [TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'P', false, 0x0000000080000000ul, 0x0000000000000000ul)] [TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'M', false, 0x0000000080000000ul, 0x0000000000000000ul)] @@ -726,45 +771,43 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x2E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")] public void Frintx_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1) { + Vector128 V1 = MakeVectorE0E1(A, B); + int FpcrTemp = 0x0; switch(RoundType) { - case 'N': - FpcrTemp = 0x0; - break; - - case 'P': - FpcrTemp = 0x400000; - break; - - case 'M': - FpcrTemp = 0x800000; - break; - - case 'Z': - FpcrTemp = 0xC00000; - break; + case 'N': FpcrTemp = 0x0; break; + case 'P': FpcrTemp = 0x400000; break; + case 'M': FpcrTemp = 0x800000; break; + case 'Z': FpcrTemp = 0xC00000; break; } if(DefaultNaN) { FpcrTemp |= 1 << 25; } - Vector128 V1 = MakeVectorE0E1(A, B); + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp); + Assert.Multiple(() => { - Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0)); - Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0)); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1)); }); + CompareAgainstUnicorn(); } [TestCase(0x41200000u, 0x3EA18000u)] public void Frsqrte_S(uint A, uint Result) { + uint Opcode = 0x7EA1D820; // FRSQRTE S0, S1 + Vector128 V1 = MakeVectorE0(A); - AThreadState ThreadState = SingleOpcode(0x7EA1D820, V1: V1); - Assert.AreEqual(Result, GetVectorE0(ThreadState.V0)); + + AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); + + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result)); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs index acf7000b9..a1558b05a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs @@ -24,12 +24,15 @@ namespace Ryujinx.Tests.Cpu } #endregion + private const int RndCnt = 2; + [Test, Description("FCMEQ D0, D1, D2 | FCMGE D0, D1, D2 | FCMGT D0, D1, D2")] - public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(8)] double A, - [ValueSource("_doubles_")] [Random(8)] double B, + public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A, + [ValueSource("_doubles_")] [Random(RndCnt)] double B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x5E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); Vector128 V2 = Sse.StaticCast(Sse2.SetScalarVector128(B)); @@ -52,15 +55,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ S0, S1, S2 | FCMGE S0, S1, S2 | FCMGT S0, S1, S2")] - public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x5E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetScalarVector128(A); Vector128 V2 = Sse.SetScalarVector128(B); @@ -85,15 +90,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.2D, V1.2D, V2.2D | FCMGE V0.2D, V1.2D, V2.2D | FCMGT V0.2D, V1.2D, V2.2D")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(8)] double A, - [ValueSource("_doubles_")] [Random(8)] double B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A, + [ValueSource("_doubles_")] [Random(RndCnt)] double B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x4E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); Vector128 V2 = Sse.StaticCast(Sse2.SetAllVector128(B)); @@ -115,15 +122,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.2S, V1.2S, V2.2S | FCMGE V0.2S, V1.2S, V2.2S | FCMGT V0.2S, V1.2S, V2.2S")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x0E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetVector128(0, 0, A, A); Vector128 V2 = Sse.SetVector128(0, 0, B, B); @@ -148,15 +157,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMEQ V0.4S, V1.4S, V2.4S | FCMGE V0.4S, V1.4S, V2.4S | FCMGT V0.4S, V1.4S, V2.4S")] - public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(8)] float A, - [ValueSource("_floats_")] [Random(8)] float B, + public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A, + [ValueSource("_floats_")] [Random(RndCnt)] float B, [Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT { uint Opcode = 0x4E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23); + Vector128 V1 = Sse.SetAllVector128(A); Vector128 V2 = Sse.SetAllVector128(B); @@ -180,15 +191,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT D0, D1, #0.0 | FCMGE D0, D1, #0.0 | FCMEQ D0, D1, #0.0 | FCMLE D0, D1, #0.0 | FCMLT D0, D1, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(8)] double A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x5EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble())); Vector128 V1 = Sse.StaticCast(Sse2.SetScalarVector128(A)); @@ -219,15 +232,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT S0, S1, #0.0 | FCMGE S0, S1, #0.0 | FCMEQ S0, S1, #0.0 | FCMLE S0, S1, #0.0 | FCMLT S0, S1, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x5EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetScalarVector128(A); @@ -260,15 +275,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.2D, V1.2D, #0.0 | FCMGE V0.2D, V1.2D, #0.0 | FCMEQ V0.2D, V1.2D, #0.0 | FCMLE V0.2D, V1.2D, #0.0 | FCMLT V0.2D, V1.2D, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(8)] double A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x4EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.StaticCast(Sse2.SetAllVector128(A)); AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); @@ -298,15 +315,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.2S, V1.2S, #0.0 | FCMGE V0.2S, V1.2S, #0.0 | FCMEQ V0.2S, V1.2S, #0.0 | FCMLE V0.2S, V1.2S, #0.0 | FCMLT V0.2S, V1.2S, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x0EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat()); Vector128 V1 = Sse.SetVector128(0, 0, A, A); @@ -339,15 +358,17 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero); Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero); }); + CompareAgainstUnicorn(); } [Test, Description("FCMGT V0.4S, V1.4S, #0.0 | FCMGE V0.4S, V1.4S, #0.0 | FCMEQ V0.4S, V1.4S, #0.0 | FCMLE V0.4S, V1.4S, #0.0 | FCMLT V0.4S, V1.4S, #0.0")] - public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(8)] float A, + public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A, [Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE [Values(0u, 1u)] uint bit13) // "LT" { uint Opcode = 0x4EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12); + Vector128 V1 = Sse.SetAllVector128(A); AThreadState ThreadState = SingleOpcode(Opcode, V1: V1); @@ -379,6 +400,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp)); Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp)); }); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs index 1e58a68a6..4efd8f31a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs @@ -22,6 +22,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E285800; // AESD V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); Vector128 V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); @@ -37,6 +38,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); }); + CompareAgainstUnicorn(); } @@ -52,6 +54,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E284800; // AESE V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH); Vector128 V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH); @@ -67,6 +70,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL)); Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH)); }); + CompareAgainstUnicorn(); } @@ -80,6 +84,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E287800; // AESIMC V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V = MakeVectorE0E1(ValueL, ValueH); AThreadState ThreadState = SingleOpcode( @@ -100,6 +105,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); }); } + CompareAgainstUnicorn(); } @@ -113,6 +119,7 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E286800; // AESMC V0.16B, V0.16B Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Vector128 V = MakeVectorE0E1(ValueL, ValueH); AThreadState ThreadState = SingleOpcode( @@ -133,6 +140,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH)); }); } + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs b/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs index 7f5f05ee4..3c8ad0711 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs @@ -23,7 +23,8 @@ namespace Ryujinx.Tests.Cpu [TestCase((ushort)0x0001, 0x33800000u)] // 5.96046448e-8 (Smallest Subnormal) public void Fcvtl_V_f16(ushort Value, uint Result) { - uint Opcode = 0x0E217801; + uint Opcode = 0x0E217801; // FCVTL V1.4S, V0.4H + Vector128 V0 = Sse.StaticCast(Sse2.SetAllVector128(Value)); AThreadState ThreadState = SingleOpcode(Opcode, V0: V0); @@ -35,6 +36,7 @@ namespace Ryujinx.Tests.Cpu Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V1), (byte)2), Is.EqualTo(Result)); Assert.That(Sse41.Extract(Sse.StaticCast(ThreadState.V1), (byte)3), Is.EqualTo(Result)); }); + CompareAgainstUnicorn(); } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index b7633e8be..b7150db30 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -8,18 +8,10 @@ using System.Runtime.Intrinsics; namespace Ryujinx.Tests.Cpu { - using Tester; - using Tester.Types; - - [Category("SimdReg")/*, Ignore("Tested: second half of 2018.")*/] + [Category("SimdReg")] // Tested: second half of 2018. public sealed class CpuTestSimdReg : CpuTest { #if SimdReg - [SetUp] - public void SetupTester() - { - AArch64.TakeReset(false); - } #region "ValueSource" private static ulong[] _1B1H1S1D_() @@ -98,23 +90,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08400; // ADD D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Add_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -130,23 +112,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208400; // ADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -162,23 +134,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208400; // ADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Add_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -194,23 +156,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E204000; // ADDHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -226,23 +178,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E204000; // ADDHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -258,23 +200,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20BC00; // ADDP V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -290,23 +222,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20BC00; // ADDP V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Addp_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -320,23 +242,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E201C00; // AND V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -350,23 +262,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E201C00; // AND V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.And_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -380,23 +282,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0E601C00; // BIC V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -410,23 +302,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4E601C00; // BIC V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bic_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -440,23 +322,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2EE01C00; // BIF V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -470,23 +342,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6EE01C00; // BIF V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bif_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -500,23 +362,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2EA01C00; // BIT V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -530,23 +382,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6EA01C00; // BIT V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bit_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -560,23 +402,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E601C00; // BSL V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -590,23 +422,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E601C00; // BSL V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Bsl_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -620,23 +442,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08C00; // CMEQ D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmeq_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -652,23 +464,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208C00; // CMEQ V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmeq_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -684,23 +486,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208C00; // CMEQ V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmeq_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -714,23 +506,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE03C00; // CMGE D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmge_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -746,23 +528,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203C00; // CMGE V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmge_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -778,23 +550,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203C00; // CMGE V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmge_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -808,23 +570,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE03400; // CMGT D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmgt_Reg_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -840,23 +592,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203400; // CMGT V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmgt_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -872,23 +614,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203400; // CMGT V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmgt_Reg_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -902,23 +634,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE03400; // CMHI D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhi_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -934,23 +656,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203400; // CMHI V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhi_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -966,23 +678,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203400; // CMHI V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmhi_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -996,23 +698,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE03C00; // CMHS D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhs_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1028,23 +720,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203C00; // CMHS V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmhs_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1060,23 +742,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203C00; // CMHS V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmhs_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1090,23 +762,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5EE08C00; // CMTST D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmtst_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1122,23 +784,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208C00; // CMTST V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Cmtst_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1154,23 +806,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208C00; // CMTST V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Cmtst_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1184,23 +826,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x2E201C00; // EOR V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Eor_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1214,23 +846,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x6E201C00; // EOR V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Eor_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1244,23 +866,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0EE01C00; // ORN V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1274,23 +886,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4EE01C00; // ORN V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Orn_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1304,23 +906,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x0EA01C00; // ORR V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1334,23 +926,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x4EA01C00; // ORR V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Orr_V(Op[30], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1366,23 +948,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E204000; // RADDHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1398,23 +970,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E204000; // RADDHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Raddhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1430,23 +992,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E206000; // RSUBHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1462,23 +1014,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E206000; // RSUBHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Rsubhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1494,23 +1036,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207C00; // SABA V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1526,23 +1058,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207C00; // SABA V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1558,23 +1080,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E205000; // SABAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1590,23 +1102,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E205000; // SABAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1622,23 +1124,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207400; // SABD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1654,23 +1146,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207400; // SABD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1686,23 +1168,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E207000; // SABDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1718,23 +1190,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E207000; // SABDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1750,23 +1212,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200000; // SADDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Saddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SADDL{2} ., ., .")] @@ -1781,23 +1234,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200000; // SADDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SADDW{2} ., ., .")] @@ -1812,23 +1256,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1844,23 +1278,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Saddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1874,31 +1298,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256h_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1912,31 +1318,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256h2_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1950,31 +1338,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z0, Z1); Vector128 V1 = MakeVectorE0E1(A0, A1); Vector128 V2 = MakeVectorE0E1(B0, B1); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z0)); AArch64.Vpart(0, 1, new Bits(Z1)); - AArch64.Vpart(1, 0, new Bits(A0)); AArch64.Vpart(1, 1, new Bits(A1)); - AArch64.Vpart(2, 0, new Bits(B0)); AArch64.Vpart(2, 1, new Bits(B1)); - SimdFp.Sha256su1_V(Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(AArch64.Vpart(64, 1, 1).ToUInt64())); - - Assert.That(GetVectorE0(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V2), Is.EqualTo(AArch64.Vpart(64, 2, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -1990,23 +1360,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E200400; // SHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHADD ., ., .")] @@ -2021,23 +1382,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E200400; // SHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHSUB ., ., .")] @@ -2052,23 +1404,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202400; // SHSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SHSUB ., ., .")] @@ -2083,23 +1426,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202400; // SHSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLAL{2} ., ., .")] @@ -2114,23 +1448,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E208000; // SMLAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Smlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLAL{2} ., ., .")] @@ -2145,23 +1470,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E208000; // SMLAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Smlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLSL{2} ., ., .")] @@ -2176,23 +1492,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E20A000; // SMLSL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Smlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SMLSL{2} ., ., .")] @@ -2207,23 +1514,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E20A000; // SMLSL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Smlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SQADD , , ")] @@ -2235,30 +1533,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E200C00; // SQADD B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQADD ., ., .")] @@ -2270,30 +1555,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E200C00; // SQADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQADD ., ., .")] @@ -2305,30 +1577,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E200C00; // SQADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQDMULH , , ")] @@ -2340,30 +1599,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E20B400; // SQDMULH B0, B0, B0 (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQDMULH ., ., .")] @@ -2375,30 +1621,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E20B400; // SQDMULH V0.8B, V0.8B, V0.8B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQDMULH ., ., .")] @@ -2410,30 +1643,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <8H, 4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E20B400; // SQDMULH V0.16B, V0.16B, V0.16B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQRDMULH , , ")] @@ -2445,30 +1665,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E20B400; // SQRDMULH B0, B0, B0 (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqrdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQRDMULH ., ., .")] @@ -2480,30 +1687,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E20B400; // SQRDMULH V0.8B, V0.8B, V0.8B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQRDMULH ., ., .")] @@ -2515,30 +1709,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, [Values(0b01u, 0b10u)] uint size) // <8H, 4S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E20B400; // SQRDMULH V0.16B, V0.16B, V0.16B (RESERVED) Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQSUB , , ")] @@ -2550,30 +1731,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x5E202C00; // SQSUB B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQSUB ., ., .")] @@ -2585,30 +1753,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x0E202C00; // SQSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SQSUB ., ., .")] @@ -2620,30 +1775,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x4E202C00; // SQSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("SRHADD ., ., .")] @@ -2658,23 +1800,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E201400; // SRHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SRHADD ., ., .")] @@ -2689,23 +1822,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E201400; // SRHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBL{2} ., ., .")] @@ -2720,23 +1844,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E202000; // SSUBL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Ssubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBL{2} ., ., .")] @@ -2751,23 +1866,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E202000; // SSUBL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Ssubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("SSUBW{2} ., ., .")] @@ -2782,23 +1888,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2814,23 +1910,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Ssubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2844,23 +1930,13 @@ namespace Ryujinx.Tests.Cpu { uint Opcode = 0x7EE08400; // SUB D0, D0, D0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2876,23 +1952,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208400; // SUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2908,23 +1974,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208400; // SUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Sub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2940,23 +1996,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E206000; // SUBHN V0.8B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -2972,23 +2018,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E206000; // SUBHN2 V0.16B, V0.8H, V0.8H Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Subhn_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3004,23 +2040,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E002800; // TRN1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Trn1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3036,23 +2062,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E002800; // TRN1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Trn1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3068,23 +2084,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E006800; // TRN2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Trn2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3100,23 +2106,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E006800; // TRN2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Trn2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3132,23 +2128,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207C00; // UABA V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3164,23 +2150,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207C00; // UABA V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaba_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3196,23 +2172,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E205000; // UABAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3228,23 +2194,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E205000; // UABAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3260,23 +2216,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207400; // UABD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3292,23 +2238,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207400; // UABD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3324,23 +2260,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E207000; // UABDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3356,23 +2282,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E207000; // UABDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uabdl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3388,23 +2304,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200000; // UADDL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uaddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UADDL{2} ., ., .")] @@ -3419,23 +2326,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200000; // UADDL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaddl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UADDW{2} ., ., .")] @@ -3450,23 +2348,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3482,23 +2370,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uaddw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -3514,23 +2392,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E200400; // UHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHADD ., ., .")] @@ -3545,23 +2414,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E200400; // UHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHSUB ., ., .")] @@ -3576,23 +2436,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202400; // UHSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UHSUB ., ., .")] @@ -3607,23 +2458,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202400; // UHSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLAL{2} ., ., .")] @@ -3638,23 +2480,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E208000; // UMLAL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Umlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLAL{2} ., ., .")] @@ -3669,23 +2502,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E208000; // UMLAL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Umlal_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLSL{2} ., ., .")] @@ -3700,23 +2524,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E20A000; // UMLSL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Umlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UMLSL{2} ., ., .")] @@ -3731,23 +2546,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E20A000; // UMLSL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Umlsl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("UQADD , , ")] @@ -3759,30 +2565,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E200C00; // UQADD B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQADD ., ., .")] @@ -3794,30 +2587,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E200C00; // UQADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQADD ., ., .")] @@ -3829,30 +2609,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E200C00; // UQADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQSUB , , ")] @@ -3864,30 +2631,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x7E202C00; // UQSUB B0, B0, B0 Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQSUB ., ., .")] @@ -3899,30 +2653,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x2E202C00; // UQSUB V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("UQSUB ., ., .")] @@ -3934,30 +2675,17 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B, [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> { - const int QCFlagBit = 27; // Cumulative saturation bit. - uint Opcode = 0x6E202C00; // UQSUB V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); - - Assert.That(((ThreadState.Fpsr >> QCFlagBit) & 1) != 0, Is.EqualTo(Shared.FPSR[QCFlagBit])); + CompareAgainstUnicorn(FpsrMask: FPSR.QC); } [Test, Pairwise, Description("URHADD ., ., .")] @@ -3972,23 +2700,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E201400; // URHADD V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("URHADD ., ., .")] @@ -4003,23 +2722,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E201400; // URHADD V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBL{2} ., ., .")] @@ -4034,23 +2744,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E202000; // USUBL V0.8H, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Usubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBL{2} ., ., .")] @@ -4065,23 +2766,14 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E202000; // USUBL2 V0.8H, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE1(A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Usubl_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); + CompareAgainstUnicorn(); } [Test, Pairwise, Description("USUBW{2} ., ., .")] @@ -4096,23 +2788,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); - SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4128,23 +2810,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE1(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Usubw_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4160,23 +2832,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E001800; // UZP1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uzp1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4192,23 +2854,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E001800; // UZP1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uzp1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4224,23 +2876,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E005800; // UZP2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Uzp2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4256,23 +2898,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E005800; // UZP2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Uzp2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4288,23 +2920,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E003800; // ZIP1 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Zip1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4320,23 +2942,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E003800; // ZIP1 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Zip1_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4352,23 +2964,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x0E007800; // ZIP2 V0.8B, V0.8B, V0.8B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0(A); Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.V(1, new Bits(A)); - AArch64.V(2, new Bits(B)); - SimdFp.Zip2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } @@ -4384,23 +2986,13 @@ namespace Ryujinx.Tests.Cpu uint Opcode = 0x4E007800; // ZIP2 V0.16B, V0.16B, V0.16B Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); Opcode |= ((size & 3) << 22); - Bits Op = new Bits(Opcode); Vector128 V0 = MakeVectorE0E1(Z, Z); Vector128 V1 = MakeVectorE0E1(A, A); Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); - AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); - AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); - AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); - SimdFp.Zip2_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); - - Assert.Multiple(() => - { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); - Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); - }); CompareAgainstUnicorn(); } #endif diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs new file mode 100644 index 000000000..4d14ab485 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs @@ -0,0 +1,143 @@ +#define SimdRegElem + +using ChocolArm64.State; + +using NUnit.Framework; + +using System.Runtime.Intrinsics; + +namespace Ryujinx.Tests.Cpu +{ + [Category("SimdRegElem")] // Tested: second half of 2018. + public sealed class CpuTestSimdRegElem : CpuTest + { +#if SimdRegElem + +#region "ValueSource" + private static ulong[] _2S_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + } + + private static ulong[] _4H_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul }; + } +#endregion + + private const int RndCnt = 2; + + [Test, Pairwise, Description("MLA ., ., .[]")] + public void Mla_Ve_4H_8H([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H_")] [Random(RndCnt)] ulong B, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index, + [Values(0b0u, 0b1u)] uint Q) // <4H, 8H> + { + uint H = (Index & 4) >> 2; + uint L = (Index & 2) >> 1; + uint M = (Index & 1) >> 0; + + uint Opcode = 0x2F400000; // MLA V0.4H, V0.4H, V0.H[0] + Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (L << 21) | (M << 20) | (H << 11); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + Vector128 V2 = MakeVectorE0E1(B, B * H); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("MLA ., ., .[]")] + public void Mla_Ve_2S_4S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_2S_")] [Random(RndCnt)] ulong B, + [Values(0u, 1u, 2u, 3u)] uint Index, + [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> + { + uint H = (Index & 2) >> 1; + uint L = (Index & 1) >> 0; + + uint Opcode = 0x2F800000; // MLA V0.2S, V0.2S, V0.S[0] + Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (L << 21) | (H << 11); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + Vector128 V2 = MakeVectorE0E1(B, B * H); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("MLS ., ., .[]")] + public void Mls_Ve_4H_8H([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H_")] [Random(RndCnt)] ulong B, + [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index, + [Values(0b0u, 0b1u)] uint Q) // <4H, 8H> + { + uint H = (Index & 4) >> 2; + uint L = (Index & 2) >> 1; + uint M = (Index & 1) >> 0; + + uint Opcode = 0x2F404000; // MLS V0.4H, V0.4H, V0.H[0] + Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (L << 21) | (M << 20) | (H << 11); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + Vector128 V2 = MakeVectorE0E1(B, B * H); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("MLS ., ., .[]")] + public void Mls_Ve_2S_4S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_2S_")] [Random(RndCnt)] ulong B, + [Values(0u, 1u, 2u, 3u)] uint Index, + [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> + { + uint H = (Index & 2) >> 1; + uint L = (Index & 1) >> 0; + + uint Opcode = 0x2F804000; // MLS V0.2S, V0.2S, V0.S[0] + Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (L << 21) | (H << 11); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + Vector128 V2 = MakeVectorE0E1(B, B * H); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2); + + CompareAgainstUnicorn(); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs new file mode 100644 index 000000000..772852226 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs @@ -0,0 +1,344 @@ +#define SimdShImm + +using ChocolArm64.State; + +using NUnit.Framework; + +using System.Runtime.Intrinsics; + +namespace Ryujinx.Tests.Cpu +{ + [Category("SimdShImm")] // Tested: second half of 2018. + public sealed class CpuTestSimdShImm : CpuTest + { +#if SimdShImm + +#region "ValueSource (Types)" + private static ulong[] _1D_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; + } + + private static ulong[] _2S_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + } + + private static ulong[] _4H_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul }; + } + + private static ulong[] _8B_() + { + return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful, + 0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul }; + } +#endregion + +#region "ValueSource (Opcodes)" + private static uint[] _ShrImm_S_D_() + { + return new uint[] + { + 0x5F402400u, // SRSHR D0, D0, #64 + 0x5F403400u, // SRSRA D0, D0, #64 + 0x5F400400u, // SSHR D0, D0, #64 + 0x5F401400u, // SSRA D0, D0, #64 + 0x7F402400u, // URSHR D0, D0, #64 + 0x7F403400u, // URSRA D0, D0, #64 + 0x7F400400u, // USHR D0, D0, #64 + 0x7F401400u // USRA D0, D0, #64 + }; + } + + private static uint[] _ShrImm_V_8B_16B_() + { + return new uint[] + { + 0x0F082400u, // SRSHR V0.8B, V0.8B, #8 + 0x0F083400u, // SRSRA V0.8B, V0.8B, #8 + 0x0F080400u, // SSHR V0.8B, V0.8B, #8 + 0x0F081400u, // SSRA V0.8B, V0.8B, #8 + 0x2F082400u, // URSHR V0.8B, V0.8B, #8 + 0x2F083400u, // URSRA V0.8B, V0.8B, #8 + 0x2F080400u, // USHR V0.8B, V0.8B, #8 + 0x2F081400u // USRA V0.8B, V0.8B, #8 + }; + } + + private static uint[] _ShrImm_V_4H_8H_() + { + return new uint[] + { + 0x0F102400u, // SRSHR V0.4H, V0.4H, #16 + 0x0F103400u, // SRSRA V0.4H, V0.4H, #16 + 0x0F100400u, // SSHR V0.4H, V0.4H, #16 + 0x0F101400u, // SSRA V0.4H, V0.4H, #16 + 0x2F102400u, // URSHR V0.4H, V0.4H, #16 + 0x2F103400u, // URSRA V0.4H, V0.4H, #16 + 0x2F100400u, // USHR V0.4H, V0.4H, #16 + 0x2F101400u // USRA V0.4H, V0.4H, #16 + }; + } + + private static uint[] _ShrImm_V_2S_4S_() + { + return new uint[] + { + 0x0F202400u, // SRSHR V0.2S, V0.2S, #32 + 0x0F203400u, // SRSRA V0.2S, V0.2S, #32 + 0x0F200400u, // SSHR V0.2S, V0.2S, #32 + 0x0F201400u, // SSRA V0.2S, V0.2S, #32 + 0x2F202400u, // URSHR V0.2S, V0.2S, #32 + 0x2F203400u, // URSRA V0.2S, V0.2S, #32 + 0x2F200400u, // USHR V0.2S, V0.2S, #32 + 0x2F201400u // USRA V0.2S, V0.2S, #32 + }; + } + + private static uint[] _ShrImm_V_2D_() + { + return new uint[] + { + 0x4F402400u, // SRSHR V0.2D, V0.2D, #64 + 0x4F403400u, // SRSRA V0.2D, V0.2D, #64 + 0x4F400400u, // SSHR V0.2D, V0.2D, #64 + 0x4F401400u, // SSRA V0.2D, V0.2D, #64 + 0x6F402400u, // URSHR V0.2D, V0.2D, #64 + 0x6F403400u, // URSRA V0.2D, V0.2D, #64 + 0x6F400400u, // USHR V0.2D, V0.2D, #64 + 0x6F401400u // USRA V0.2D, V0.2D, #64 + }; + } +#endregion + + private const int RndCnt = 2; + + [Test, Pairwise, Description("SHL , , #")] + public void Shl_S_D([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1D_")] [Random(RndCnt)] ulong A, + [Range(0u, 63u)] uint Shift) + { + uint ImmHB = (64 + Shift) & 0x7F; + + uint Opcode = 0x5F405400; // SHL D0, D0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (ImmHB << 16); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("SHL ., ., #")] + public void Shl_V_8B_16B([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, + [ValueSource("_8B_")] [Random(RndCnt)] ulong A, + [Range(0u, 7u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <8B, 16B> + { + uint ImmHB = (8 + Shift) & 0x7F; + + uint Opcode = 0x0F085400; // SHL V0.8B, V0.8B, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (ImmHB << 16); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("SHL ., ., #")] + public void Shl_V_4H_8H([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_4H_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H_")] [Random(RndCnt)] ulong A, + [Range(0u, 15u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <4H, 8H> + { + uint ImmHB = (16 + Shift) & 0x7F; + + uint Opcode = 0x0F105400; // SHL V0.4H, V0.4H, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (ImmHB << 16); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("SHL ., ., #")] + public void Shl_V_2S_4S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_2S_")] [Random(RndCnt)] ulong A, + [Range(0u, 31u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> + { + uint ImmHB = (32 + Shift) & 0x7F; + + uint Opcode = 0x0F205400; // SHL V0.2S, V0.2S, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (ImmHB << 16); + Opcode |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise, Description("SHL ., ., #")] + public void Shl_V_2D([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1D_")] [Random(RndCnt)] ulong A, + [Range(0u, 63u)] uint Shift) + { + uint ImmHB = (64 + Shift) & 0x7F; + + uint Opcode = 0x4F405400; // SHL V0.2D, V0.2D, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= (ImmHB << 16); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A); + + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void ShrImm_S_D([ValueSource("_ShrImm_S_D_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1D_")] [Random(RndCnt)] ulong A, + [Range(1u, 64u)] uint Shift) + { + uint ImmHB = (128 - Shift) & 0x7F; + + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= (ImmHB << 16); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void ShrImm_V_8B_16B([ValueSource("_ShrImm_V_8B_16B_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, + [ValueSource("_8B_")] [Random(RndCnt)] ulong A, + [Range(1u, 8u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <8B, 16B> + { + uint ImmHB = (16 - Shift) & 0x7F; + + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= (ImmHB << 16); + Opcodes |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void ShrImm_V_4H_8H([ValueSource("_ShrImm_V_4H_8H_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_4H_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H_")] [Random(RndCnt)] ulong A, + [Range(1u, 16u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <4H, 8H> + { + uint ImmHB = (32 - Shift) & 0x7F; + + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= (ImmHB << 16); + Opcodes |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void ShrImm_V_2S_4S([ValueSource("_ShrImm_V_2S_4S_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_2S_")] [Random(RndCnt)] ulong A, + [Range(1u, 32u)] uint Shift, + [Values(0b0u, 0b1u)] uint Q) // <2S, 4S> + { + uint ImmHB = (64 - Shift) & 0x7F; + + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= (ImmHB << 16); + Opcodes |= ((Q & 1) << 30); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A * Q); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void ShrImm_V_2D([ValueSource("_ShrImm_V_2D_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1D_")] [Random(RndCnt)] ulong A, + [Range(1u, 64u)] uint Shift) + { + uint ImmHB = (128 - Shift) & 0x7F; + + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= (ImmHB << 16); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs deleted file mode 100644 index e3aa4e40b..000000000 --- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs +++ /dev/null @@ -1,7346 +0,0 @@ -// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Instructions.cs - -// https://developer.arm.com/products/architecture/a-profile/exploration-tools -// ..\A64_v83A_ISA_xml_00bet6.1\ISA_v83A_A64_xml_00bet6.1_OPT\xhtml\ - -using System.Numerics; - -namespace Ryujinx.Tests.Cpu.Tester -{ - using Types; - - using static AArch64; - using static Shared; - - // index.html - internal static class Base - { -#region "Alu" - // cls_int.html - public static void Cls(bool sf, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits operand1 = X(datasize, n); - - BigInteger result = (BigInteger)CountLeadingSignBits(operand1); - - X(d, result.SubBigInteger(datasize - 1, 0)); - } - - // clz_int.html - public static void Clz(bool sf, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits operand1 = X(datasize, n); - - BigInteger result = (BigInteger)CountLeadingZeroBits(operand1); - - X(d, result.SubBigInteger(datasize - 1, 0)); - } - - // rbit_int.html - public static void Rbit(bool sf, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result = new Bits(datasize); - Bits operand = X(datasize, n); - - for (int i = 0; i <= datasize - 1; i++) - { - result[datasize - 1 - i] = operand[i]; - } - - X(d, result); - } - - // rev16_int.html - public static void Rev16(bool sf, Bits Rn, Bits Rd) - { - /* Bits opc = "01"; */ - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - int container_size = 16; - - /* Operation */ - Bits result = new Bits(datasize); - Bits operand = X(datasize, n); - - int containers = datasize / container_size; - int elements_per_container = container_size / 8; - int index = 0; - int rev_index; - - for (int c = 0; c <= containers - 1; c++) - { - rev_index = index + ((elements_per_container - 1) * 8); - - for (int e = 0; e <= elements_per_container - 1; e++) - { - result[rev_index + 7, rev_index] = operand[index + 7, index]; - - index = index + 8; - rev_index = rev_index - 8; - } - } - - X(d, result); - } - - // rev32_int.html - // (rev.html) - public static void Rev32(bool sf, Bits Rn, Bits Rd) - { - /* Bits opc = "10"; */ - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - int container_size = 32; - - /* Operation */ - Bits result = new Bits(datasize); - Bits operand = X(datasize, n); - - int containers = datasize / container_size; - int elements_per_container = container_size / 8; - int index = 0; - int rev_index; - - for (int c = 0; c <= containers - 1; c++) - { - rev_index = index + ((elements_per_container - 1) * 8); - - for (int e = 0; e <= elements_per_container - 1; e++) - { - result[rev_index + 7, rev_index] = operand[index + 7, index]; - - index = index + 8; - rev_index = rev_index - 8; - } - } - - X(d, result); - } - - // rev64_rev.html - // (rev.html) - public static void Rev64(Bits Rn, Bits Rd) - { - /* Bits opc = "11"; */ - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int container_size = 64; - - /* Operation */ - Bits result = new Bits(64); - Bits operand = X(64, n); - - int containers = 64 / container_size; - int elements_per_container = container_size / 8; - int index = 0; - int rev_index; - - for (int c = 0; c <= containers - 1; c++) - { - rev_index = index + ((elements_per_container - 1) * 8); - - for (int e = 0; e <= elements_per_container - 1; e++) - { - result[rev_index + 7, rev_index] = operand[index + 7, index]; - - index = index + 8; - rev_index = rev_index - 8; - } - } - - X(d, result); - } -#endregion - -#region "AluImm" - // add_addsub_imm.html - public static void Add_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - switch (shift) - { - default: - case Bits bits when bits == "00": - imm = ZeroExtend(imm12, datasize); - break; - case Bits bits when bits == "01": - imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); - break; - /* when '1x' ReservedValue(); */ - } - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - - (result, _) = AddWithCarry(datasize, operand1, imm, false); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // adds_addsub_imm.html - public static void Adds_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - switch (shift) - { - default: - case Bits bits when bits == "00": - imm = ZeroExtend(imm12, datasize); - break; - case Bits bits when bits == "01": - imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); - break; - /* when '1x' ReservedValue(); */ - } - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits nzcv; - - (result, nzcv) = AddWithCarry(datasize, operand1, imm, false); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // and_log_imm.html - public static void And_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - /* if sf == '0' && N != '0' then ReservedValue(); */ - - (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); - - /* Operation */ - Bits operand1 = X(datasize, n); - - Bits result = AND(operand1, imm); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // ands_log_imm.html - public static void Ands_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - /* if sf == '0' && N != '0' then ReservedValue(); */ - - (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); - - /* Operation */ - Bits operand1 = X(datasize, n); - - Bits result = AND(operand1, imm); - - PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); - - X(d, result); - } - - // eor_log_imm.html - public static void Eor_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - /* if sf == '0' && N != '0' then ReservedValue(); */ - - (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); - - /* Operation */ - Bits operand1 = X(datasize, n); - - Bits result = EOR(operand1, imm); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // orr_log_imm.html - public static void Orr_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - /* if sf == '0' && N != '0' then ReservedValue(); */ - - (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); - - /* Operation */ - Bits operand1 = X(datasize, n); - - Bits result = OR(operand1, imm); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // sub_addsub_imm.html - public static void Sub_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - switch (shift) - { - default: - case Bits bits when bits == "00": - imm = ZeroExtend(imm12, datasize); - break; - case Bits bits when bits == "01": - imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); - break; - /* when '1x' ReservedValue(); */ - } - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = NOT(imm); - - (result, _) = AddWithCarry(datasize, operand1, operand2, true); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // subs_addsub_imm.html - public static void Subs_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits imm; - - switch (shift) - { - default: - case Bits bits when bits == "00": - imm = ZeroExtend(imm12, datasize); - break; - case Bits bits when bits == "01": - imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); - break; - /* when '1x' ReservedValue(); */ - } - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = NOT(imm); - Bits nzcv; - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); - - PSTATE.NZCV(nzcv); - - X(d, result); - } -#endregion - -#region "AluRs" - // adc.html - public static void Adc(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - (result, _) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); - - X(d, result); - } - - // adcs.html - public static void Adcs(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - Bits nzcv; - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // add_addsub_shift.html - public static void Add_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if shift == '11' then ReservedValue(); */ - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - (result, _) = AddWithCarry(datasize, operand1, operand2, false); - - X(d, result); - } - - // adds_addsub_shift.html - public static void Adds_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if shift == '11' then ReservedValue(); */ - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - Bits nzcv; - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, false); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // and_log_shift.html - public static void And_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - Bits result = AND(operand1, operand2); - - X(d, result); - } - - // ands_log_shift.html - public static void Ands_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - Bits result = AND(operand1, operand2); - - PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); - - X(d, result); - } - - // asrv.html - public static void Asrv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /*readonly */Bits op2 = "10"; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ShiftType shift_type = DecodeShift(op2); - - /* Operation */ - Bits operand2 = X(datasize, m); - - Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) - - X(d, result); - } - - // bic_log_shift.html - public static void Bic(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - operand2 = NOT(operand2); - - Bits result = AND(operand1, operand2); - - X(d, result); - } - - // bics.html - public static void Bics(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - operand2 = NOT(operand2); - - Bits result = AND(operand1, operand2); - - PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); - - X(d, result); - } - - // crc32.html - public static void Crc32(bool sf, Bits Rm, Bits sz, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if sf == '1' && sz != '11' then UnallocatedEncoding(); */ - /* if sf == '0' && sz == '11' then UnallocatedEncoding(); */ - - int size = 8 << (int)UInt(sz); - - /* Operation */ - /* if !HaveCRCExt() then UnallocatedEncoding(); */ - - Bits acc = X(32, n); // accumulator - Bits val = X(size, m); // input value - Bits poly = new Bits(0x04C11DB7u); - - Bits tempacc = Bits.Concat(BitReverse(acc), Zeros(size)); - Bits tempval = Bits.Concat(BitReverse(val), Zeros(32)); - - // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation - X(d, BitReverse(Poly32Mod2(EOR(tempacc, tempval), poly))); - } - - // crc32c.html - public static void Crc32c(bool sf, Bits Rm, Bits sz, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if sf == '1' && sz != '11' then UnallocatedEncoding(); */ - /* if sf == '0' && sz == '11' then UnallocatedEncoding(); */ - - int size = 8 << (int)UInt(sz); - - /* Operation */ - /* if !HaveCRCExt() then UnallocatedEncoding(); */ - - Bits acc = X(32, n); // accumulator - Bits val = X(size, m); // input value - Bits poly = new Bits(0x1EDC6F41u); - - Bits tempacc = Bits.Concat(BitReverse(acc), Zeros(size)); - Bits tempval = Bits.Concat(BitReverse(val), Zeros(32)); - - // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation - X(d, BitReverse(Poly32Mod2(EOR(tempacc, tempval), poly))); - } - - // eon.html - public static void Eon(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - operand2 = NOT(operand2); - - Bits result = EOR(operand1, operand2); - - X(d, result); - } - - // eor_log_shift.html - public static void Eor_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - Bits result = EOR(operand1, operand2); - - X(d, result); - } - - // extr.html - public static void Extr(bool sf, bool N, Bits Rm, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if N != sf then UnallocatedEncoding(); */ - /* if sf == '0' && imms<5> == '1' then ReservedValue(); */ - - int lsb = (int)UInt(imms); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - Bits concat = Bits.Concat(operand1, operand2); - - Bits result = concat[lsb + datasize - 1, lsb]; - - X(d, result); - } - - // lslv.html - public static void Lslv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /*readonly */Bits op2 = "00"; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ShiftType shift_type = DecodeShift(op2); - - /* Operation */ - Bits operand2 = X(datasize, m); - - Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) - - X(d, result); - } - - // lsrv.html - public static void Lsrv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /*readonly */Bits op2 = "01"; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ShiftType shift_type = DecodeShift(op2); - - /* Operation */ - Bits operand2 = X(datasize, m); - - Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) - - X(d, result); - } - - // orn_log_shift.html - public static void Orn(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - operand2 = NOT(operand2); - - Bits result = OR(operand1, operand2); - - X(d, result); - } - - // orr_log_shift.html - public static void Orr_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - Bits result = OR(operand1, operand2); - - X(d, result); - } - - // rorv.html - public static void Rorv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /*readonly */Bits op2 = "11"; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ShiftType shift_type = DecodeShift(op2); - - /* Operation */ - Bits operand2 = X(datasize, m); - - Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) - - X(d, result); - } - - // sbc.html - public static void Sbc(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - operand2 = NOT(operand2); - - (result, _) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); - - X(d, result); - } - - // sbcs.html - public static void Sbcs(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - Bits nzcv; - - operand2 = NOT(operand2); - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // sdiv.html - public static void Sdiv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - BigInteger result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (IsZero(operand2)) - { - result = (BigInteger)0m; - } - else - { - result = RoundTowardsZero(Real(Int(operand1, false)) / Real(Int(operand2, false))); - } - - X(d, result.SubBigInteger(datasize - 1, 0)); - } - - // sub_addsub_shift.html - public static void Sub_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if shift == '11' then ReservedValue(); */ - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - - operand2 = NOT(operand2); - - (result, _) = AddWithCarry(datasize, operand1, operand2, true); - - X(d, result); - } - - // subs_addsub_shift.html - public static void Subs_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* if shift == '11' then ReservedValue(); */ - /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ - - ShiftType shift_type = DecodeShift(shift); - int shift_amount = (int)UInt(imm6); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); - Bits nzcv; - - operand2 = NOT(operand2); - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // udiv.html - public static void Udiv(bool sf, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - BigInteger result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (IsZero(operand2)) - { - result = (BigInteger)0m; - } - else - { - result = RoundTowardsZero(Real(Int(operand1, true)) / Real(Int(operand2, true))); - } - - X(d, result.SubBigInteger(datasize - 1, 0)); - } -#endregion - -#region "AluRx" - // add_addsub_ext.html - public static void Add_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ExtendType extend_type = DecodeRegExtend(option); - int shift = (int)UInt(imm3); - - /* if shift > 4 then ReservedValue(); */ - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = ExtendReg(datasize, m, extend_type, shift); - - (result, _) = AddWithCarry(datasize, operand1, operand2, false); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // adds_addsub_ext.html - public static void Adds_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ExtendType extend_type = DecodeRegExtend(option); - int shift = (int)UInt(imm3); - - /* if shift > 4 then ReservedValue(); */ - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = ExtendReg(datasize, m, extend_type, shift); - Bits nzcv; - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, false); - - PSTATE.NZCV(nzcv); - - X(d, result); - } - - // sub_addsub_ext.html - public static void Sub_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ExtendType extend_type = DecodeRegExtend(option); - int shift = (int)UInt(imm3); - - /* if shift > 4 then ReservedValue(); */ - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = ExtendReg(datasize, m, extend_type, shift); - - operand2 = NOT(operand2); - - (result, _) = AddWithCarry(datasize, operand1, operand2, true); - - if (d == 31) - { - SP(result); - } - else - { - X(d, result); - } - } - - // subs_addsub_ext.html - public static void Subs_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - ExtendType extend_type = DecodeRegExtend(option); - int shift = (int)UInt(imm3); - - /* if shift > 4 then ReservedValue(); */ - - /* Operation */ - Bits result; - Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); - Bits operand2 = ExtendReg(datasize, m, extend_type, shift); - Bits nzcv; - - operand2 = NOT(operand2); - - (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); - - PSTATE.NZCV(nzcv); - - X(d, result); - } -#endregion - -#region "Bfm" - // bfm.html - public static void Bfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - int R; - Bits wmask; - Bits tmask; - - /* if sf == '1' && N != '1' then ReservedValue(); */ - /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ - - R = (int)UInt(immr); - (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); - - /* Operation */ - Bits dst = X(datasize, d); - Bits src = X(datasize, n); - - // perform bitfield move on low bits - Bits bot = OR(AND(dst, NOT(wmask)), AND(ROR(src, R), wmask)); - - // combine extension bits and result bits - X(d, OR(AND(dst, NOT(tmask)), AND(bot, tmask))); - } - - // sbfm.html - public static void Sbfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - int R; - int S; - Bits wmask; - Bits tmask; - - /* if sf == '1' && N != '1' then ReservedValue(); */ - /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ - - R = (int)UInt(immr); - S = (int)UInt(imms); - (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); - - /* Operation */ - Bits src = X(datasize, n); - - // perform bitfield move on low bits - Bits bot = AND(ROR(src, R), wmask); - - // determine extension bits (sign, zero or dest register) - Bits top = Replicate(datasize, src[S]); - - // combine extension bits and result bits - X(d, OR(AND(top, NOT(tmask)), AND(bot, tmask))); - } - - // ubfm.html - public static void Ubfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - int R; - Bits wmask; - Bits tmask; - - /* if sf == '1' && N != '1' then ReservedValue(); */ - /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ - - R = (int)UInt(immr); - (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); - - /* Operation */ - Bits src = X(datasize, n); - - // perform bitfield move on low bits - Bits bot = AND(ROR(src, R), wmask); - - // combine extension bits and result bits - X(d, AND(bot, tmask)); - } -#endregion - -#region "CcmpImm" - // ccmn_imm.html - public static void Ccmn_Imm(bool sf, Bits imm5, Bits cond, Bits Rn, Bits nzcv) - { - /* Decode */ - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits flags = nzcv; - Bits imm = ZeroExtend(imm5, datasize); - - /* Operation */ - Bits operand1 = X(datasize, n); - - if (ConditionHolds(cond)) - { - (_, flags) = AddWithCarry(datasize, operand1, imm, false); - } - - PSTATE.NZCV(flags); - } - - // ccmp_imm.html - public static void Ccmp_Imm(bool sf, Bits imm5, Bits cond, Bits Rn, Bits nzcv) - { - /* Decode */ - int n = (int)UInt(Rn); - - int datasize = (sf ? 64 : 32); - - Bits flags = nzcv; - Bits imm = ZeroExtend(imm5, datasize); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2; - - if (ConditionHolds(cond)) - { - operand2 = NOT(imm); - (_, flags) = AddWithCarry(datasize, operand1, operand2, true); - } - - PSTATE.NZCV(flags); - } -#endregion - -#region "CcmpReg" - // ccmn_reg.html - public static void Ccmn_Reg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits nzcv) - { - /* Decode */ - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - Bits flags = nzcv; - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - (_, flags) = AddWithCarry(datasize, operand1, operand2, false); - } - - PSTATE.NZCV(flags); - } - - // ccmp_reg.html - public static void Ccmp_Reg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits nzcv) - { - /* Decode */ - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - Bits flags = nzcv; - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - operand2 = NOT(operand2); - (_, flags) = AddWithCarry(datasize, operand1, operand2, true); - } - - PSTATE.NZCV(flags); - } -#endregion - -#region "Csel" - // csel.html - public static void Csel(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - result = operand1; - } - else - { - result = operand2; - } - - X(d, result); - } - - // csinc.html - public static void Csinc(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - result = operand1; - } - else - { - result = operand2 + 1; - } - - X(d, result); - } - - // csinv.html - public static void Csinv(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - result = operand1; - } - else - { - result = NOT(operand2); - } - - X(d, result); - } - - // csneg.html - public static void Csneg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits result; - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - - if (ConditionHolds(cond)) - { - result = operand1; - } - else - { - result = NOT(operand2); - result = result + 1; - } - - X(d, result); - } -#endregion - -#region "Mov" - // movk.html - public static void Movk(bool sf, Bits hw, Bits imm16, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ - - int pos = (int)UInt(Bits.Concat(hw, "0000")); - - /* Operation */ - Bits result = X(datasize, d); - - result[pos + 15, pos] = imm16; - - X(d, result); - } - - // movn.html - public static void Movn(bool sf, Bits hw, Bits imm16, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ - - int pos = (int)UInt(Bits.Concat(hw, "0000")); - - /* Operation */ - Bits result = Zeros(datasize); - - result[pos + 15, pos] = imm16; - result = NOT(result); - - X(d, result); - } - - // movz.html - public static void Movz(bool sf, Bits hw, Bits imm16, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - - int datasize = (sf ? 64 : 32); - - /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ - - int pos = (int)UInt(Bits.Concat(hw, "0000")); - - /* Operation */ - Bits result = Zeros(datasize); - - result[pos + 15, pos] = imm16; - - X(d, result); - } -#endregion - -#region "Mul" - // madd.html - public static void Madd(bool sf, Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - Bits operand3 = X(datasize, a); - - BigInteger result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); - - X(d, result.SubBigInteger(datasize - 1, 0)); - } - - // msub.html - public static void Msub(bool sf, Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - int datasize = (sf ? 64 : 32); - - /* Operation */ - Bits operand1 = X(datasize, n); - Bits operand2 = X(datasize, m); - Bits operand3 = X(datasize, a); - - BigInteger result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); - - X(d, result.SubBigInteger(datasize - 1, 0)); - } - - // smaddl.html - public static void Smaddl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - /* Operation */ - Bits operand1 = X(32, n); - Bits operand2 = X(32, m); - Bits operand3 = X(64, a); - - BigInteger result = Int(operand3, false) + (Int(operand1, false) * Int(operand2, false)); - - X(d, result.SubBigInteger(63, 0)); - } - - // umaddl.html - public static void Umaddl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - /* Operation */ - Bits operand1 = X(32, n); - Bits operand2 = X(32, m); - Bits operand3 = X(64, a); - - BigInteger result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); - - X(d, result.SubBigInteger(63, 0)); - } - - // smsubl.html - public static void Smsubl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - /* Operation */ - Bits operand1 = X(32, n); - Bits operand2 = X(32, m); - Bits operand3 = X(64, a); - - BigInteger result = Int(operand3, false) - (Int(operand1, false) * Int(operand2, false)); - - X(d, result.SubBigInteger(63, 0)); - } - - // umsubl.html - public static void Umsubl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - int a = (int)UInt(Ra); - - /* Operation */ - Bits operand1 = X(32, n); - Bits operand2 = X(32, m); - Bits operand3 = X(64, a); - - BigInteger result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); - - X(d, result.SubBigInteger(63, 0)); - } - - // smulh.html - public static void Smulh(Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* Operation */ - Bits operand1 = X(64, n); - Bits operand2 = X(64, m); - - BigInteger result = Int(operand1, false) * Int(operand2, false); - - X(d, result.SubBigInteger(127, 64)); - } - - // umulh.html - public static void Umulh(Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* Operation */ - Bits operand1 = X(64, n); - Bits operand2 = X(64, m); - - BigInteger result = Int(operand1, true) * Int(operand2, true); - - X(d, result.SubBigInteger(127, 64)); - } -#endregion - } - - // fpsimdindex.html - internal static class SimdFp - { -#region "Simd" - // abs_advsimd.html#ABS_asisdmisc_R - public static void Abs_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger element; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - Elem(result, e, esize, element.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // abs_advsimd.html#ABS_asimdmisc_R - public static void Abs_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger element; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - Elem(result, e, esize, element.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // addp_advsimd_pair.html - public static void Addp_S(Bits size, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize * 2; - // int elements = 2; - - ReduceOp op = ReduceOp.ReduceOp_ADD; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - - V(d, Reduce(op, operand, esize)); - } - - // addv_advsimd.html - public static void Addv_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '100' then ReservedValue(); */ - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - // int elements = datasize / esize; - - ReduceOp op = ReduceOp.ReduceOp_ADD; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - - V(d, Reduce(op, operand, esize)); - } - - // cls_advsimd.html - public static void Cls_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger count; - - for (int e = 0; e <= elements - 1; e++) - { - if (countop == CountOp.CountOp_CLS) - { - count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize)); - } - else - { - count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize)); - } - - Elem(result, e, esize, count.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // clz_advsimd.html - public static void Clz_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger count; - - for (int e = 0; e <= elements - 1; e++) - { - if (countop == CountOp.CountOp_CLS) - { - count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize)); - } - else - { - count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize)); - } - - Elem(result, e, esize, count.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // cmeq_advsimd_zero.html#CMEQ_asisdmisc_Z - public static void Cmeq_Zero_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - default: - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - default: - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmeq_advsimd_zero.html#CMEQ_asimdmisc_Z - public static void Cmeq_Zero_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - default: - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - default: - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmge_advsimd_zero.html#CMGE_asisdmisc_Z - public static void Cmge_Zero_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - default: - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - default: - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmge_advsimd_zero.html#CMGE_asimdmisc_Z - public static void Cmge_Zero_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - default: - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - default: - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmgt_advsimd_zero.html#CMGT_asisdmisc_Z - public static void Cmgt_Zero_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - default: - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - default: - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmgt_advsimd_zero.html#CMGT_asimdmisc_Z - public static void Cmgt_Zero_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - default: - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - default: - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmle_advsimd.html#CMLE_asisdmisc_Z - public static void Cmle_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - default: - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - default: - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmle_advsimd.html#CMLE_asimdmisc_Z - public static void Cmle_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CompareOp comparison; - - switch (Bits.Concat(op, U)) - { - case Bits bits when bits == "00": - comparison = CompareOp.CompareOp_GT; - break; - case Bits bits when bits == "01": - comparison = CompareOp.CompareOp_GE; - break; - case Bits bits when bits == "10": - comparison = CompareOp.CompareOp_EQ; - break; - default: - case Bits bits when bits == "11": - comparison = CompareOp.CompareOp_LE; - break; - } - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - default: - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmlt_advsimd.html#CMLT_asisdmisc_Z - public static void Cmlt_S(Bits size, Bits Rn, Bits Rd) - { - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - CompareOp comparison = CompareOp.CompareOp_LT; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - default: - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmlt_advsimd.html#CMLT_asimdmisc_Z - public static void Cmlt_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - CompareOp comparison = CompareOp.CompareOp_LT; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - switch (comparison) - { - case CompareOp.CompareOp_GT: - test_passed = (element > (BigInteger)0); - break; - case CompareOp.CompareOp_GE: - test_passed = (element >= (BigInteger)0); - break; - case CompareOp.CompareOp_EQ: - test_passed = (element == (BigInteger)0); - break; - case CompareOp.CompareOp_LE: - test_passed = (element <= (BigInteger)0); - break; - default: - case CompareOp.CompareOp_LT: - test_passed = (element < (BigInteger)0); - break; - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cnt_advsimd.html - public static void Cnt_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '00' then ReservedValue(); */ - - int esize = 8; - int datasize = (Q ? 128 : 64); - int elements = datasize / 8; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger count; - - for (int e = 0; e <= elements - 1; e++) - { - count = (BigInteger)BitCount(Elem(operand, e, esize)); - - Elem(result, e, esize, count.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // fcvtns_advsimd.html#FCVTNS_asisdmisc_R - public static void Fcvtns_S(Bits sz, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o2 = false; - const bool o1 = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 32 << (int)UInt(sz); - int datasize = esize; - int elements = 1; - - FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); - } - - V(d, result); - } - - // fcvtns_advsimd.html#FCVTNS_asimdmisc_R - public static void Fcvtns_V(bool Q, Bits sz, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o2 = false; - const bool o1 = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if sz:Q == '10' then ReservedValue(); */ - - int esize = 32 << (int)UInt(sz); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); - } - - V(d, result); - } - - // fcvtnu_advsimd.html#FCVTNU_asisdmisc_R - public static void Fcvtnu_S(Bits sz, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o2 = false; - const bool o1 = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 32 << (int)UInt(sz); - int datasize = esize; - int elements = 1; - - FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); - } - - V(d, result); - } - - // fcvtnu_advsimd.html#FCVTNU_asimdmisc_R - public static void Fcvtnu_V(bool Q, Bits sz, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o2 = false; - const bool o1 = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if sz:Q == '10' then ReservedValue(); */ - - int esize = 32 << (int)UInt(sz); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - FPRounding rounding = FPDecodeRounding(Bits.Concat(o1, o2)); - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - Elem(result, e, esize, FPToFixed(esize, element, 0, unsigned, FPCR, rounding)); - } - - V(d, result); - } - - // neg_advsimd.html#NEG_asisdmisc_R - public static void Neg_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger element; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - Elem(result, e, esize, element.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // neg_advsimd.html#NEG_asimdmisc_R - public static void Neg_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - BigInteger element; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - Elem(result, e, esize, element.SubBigInteger(esize - 1, 0)); - } - - V(d, result); - } - - // not_advsimd.html - public static void Not_V(bool Q, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8; - int datasize = (Q ? 128 : 64); - int elements = datasize / 8; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - Elem(result, e, esize, NOT(element)); - } - - V(d, result); - } - - // rbit_advsimd.html - public static void Rbit_V(bool Q, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8; - int datasize = (Q ? 128 : 64); - int elements = datasize / 8; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits element; - Bits rev = new Bits(esize); - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, esize); - - for (int i = 0; i <= esize - 1; i++) - { - rev[esize - 1 - i] = element[i]; - } - - Elem(result, e, esize, rev); - } - - V(d, result); - } - - // rev16_advsimd.html - public static void Rev16_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o0 = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - // size=esize: B(0), H(1), S(1), D(S) - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - - // op=REVx: 64(0), 32(1), 16(2) - Bits op = Bits.Concat(o0, U); - - // => op+size: - // 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X - // 32+B = 1, 32+H = 2, 32+S = X, 32+D = X - // 16+B = 2, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - // => 3-(op+size) (index bits in group) - // 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X - // 32+B = 2, 32+H = 1, 32+S = X, 32+D = X - // 16+B = 1, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - - // index bits within group: 1, 2, 3 - /* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */ - - int container_size; - - switch (op) - { - default: - case Bits bits when bits == "10": - container_size = 16; - break; - case Bits bits when bits == "01": - container_size = 32; - break; - case Bits bits when bits == "00": - container_size = 64; - break; - } - - int containers = datasize / container_size; - int elements_per_container = container_size / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - int element = 0; - int rev_element; - - for (int c = 0; c <= containers - 1; c++) - { - rev_element = element + elements_per_container - 1; - - for (int e = 0; e <= elements_per_container - 1; e++) - { - Elem(result, rev_element, esize, Elem(operand, element, esize)); - - element = element + 1; - rev_element = rev_element - 1; - } - } - - V(d, result); - } - - // rev32_advsimd.html - public static void Rev32_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o0 = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - // size=esize: B(0), H(1), S(1), D(S) - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - - // op=REVx: 64(0), 32(1), 16(2) - Bits op = Bits.Concat(o0, U); - - // => op+size: - // 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X - // 32+B = 1, 32+H = 2, 32+S = X, 32+D = X - // 16+B = 2, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - // => 3-(op+size) (index bits in group) - // 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X - // 32+B = 2, 32+H = 1, 32+S = X, 32+D = X - // 16+B = 1, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - - // index bits within group: 1, 2, 3 - /* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */ - - int container_size; - - switch (op) - { - case Bits bits when bits == "10": - container_size = 16; - break; - default: - case Bits bits when bits == "01": - container_size = 32; - break; - case Bits bits when bits == "00": - container_size = 64; - break; - } - - int containers = datasize / container_size; - int elements_per_container = container_size / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - int element = 0; - int rev_element; - - for (int c = 0; c <= containers - 1; c++) - { - rev_element = element + elements_per_container - 1; - - for (int e = 0; e <= elements_per_container - 1; e++) - { - Elem(result, rev_element, esize, Elem(operand, element, esize)); - - element = element + 1; - rev_element = rev_element - 1; - } - } - - V(d, result); - } - - // rev64_advsimd.html - public static void Rev64_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o0 = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - // size=esize: B(0), H(1), S(1), D(S) - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - - // op=REVx: 64(0), 32(1), 16(2) - Bits op = Bits.Concat(o0, U); - - // => op+size: - // 64+B = 0, 64+H = 1, 64+S = 2, 64+D = X - // 32+B = 1, 32+H = 2, 32+S = X, 32+D = X - // 16+B = 2, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - // => 3-(op+size) (index bits in group) - // 64/B = 3, 64+H = 2, 64+S = 1, 64+D = X - // 32+B = 2, 32+H = 1, 32+S = X, 32+D = X - // 16+B = 1, 16+H = X, 16+S = X, 16+D = X - // 8+B = X, 8+H = X, 8+S = X, 8+D = X - - // index bits within group: 1, 2, 3 - /* if UInt(op) + UInt(size) >= 3 then UnallocatedEncoding(); */ - - int container_size; - - switch (op) - { - case Bits bits when bits == "10": - container_size = 16; - break; - case Bits bits when bits == "01": - container_size = 32; - break; - default: - case Bits bits when bits == "00": - container_size = 64; - break; - } - - int containers = datasize / container_size; - int elements_per_container = container_size / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - - int element = 0; - int rev_element; - - for (int c = 0; c <= containers - 1; c++) - { - rev_element = element + elements_per_container - 1; - - for (int e = 0; e <= elements_per_container - 1; e++) - { - Elem(result, rev_element, esize, Elem(operand, element, esize)); - - element = element + 1; - rev_element = rev_element - 1; - } - } - - V(d, result); - } - - // sadalp_advsimd.html - public static void Sadalp_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / (2 * esize); - - bool acc = (op == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - Bits sum; - BigInteger op1; - BigInteger op2; - - Bits result = (acc ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned); - op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned); - - sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum); - } - - V(d, result); - } - - // saddlp_advsimd.html - public static void Saddlp_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / (2 * esize); - - bool acc = (op == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - Bits sum; - BigInteger op1; - BigInteger op2; - - Bits result = (acc ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned); - op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned); - - sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum); - } - - V(d, result); - } - - // sha256su0_advsimd.html - public static void Sha256su0_V(Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if !HaveCryptoExt() then UnallocatedEncoding(); */ - - /* Operation */ - /* CheckCryptoEnabled64(); */ - - Bits result = new Bits(128); - Bits operand1 = V(128, d); - Bits operand2 = V(128, n); - Bits T = Bits.Concat(operand2[31, 0], operand1[127, 32]); // bits(128) - Bits elt; // bits(32) - - for (int e = 0; e <= 3; e++) - { - elt = Elem(T, e, 32); - elt = EOR(EOR(ROR(elt, 7), ROR(elt, 18)), LSR(elt, 3)); - Elem(result, e, 32, elt + Elem(operand1, e, 32)); - } - - V(d, result); - } - - // sqabs_advsimd.html#SQABS_asisdmisc_R - public static void Sqabs_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - (Bits _result, bool _sat) = SignedSatQ(element, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqabs_advsimd.html#SQABS_asimdmisc_R - public static void Sqabs_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - (Bits _result, bool _sat) = SignedSatQ(element, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqneg_advsimd.html#SQNEG_asisdmisc_R - public static void Sqneg_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - (Bits _result, bool _sat) = SignedSatQ(element, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqneg_advsimd.html#SQNEG_asimdmisc_R - public static void Sqneg_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool neg = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - BigInteger element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = SInt(Elem(operand, e, esize)); - - if (neg) - { - element = -element; - } - else - { - element = Abs(element); - } - - (Bits _result, bool _sat) = SignedSatQ(element, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqxtn_advsimd.html#SQXTN_asisdmisc_N - public static void Sqxtn_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int part = 0; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = SatQ(Int(element, unsigned), esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // sqxtn_advsimd.html#SQXTN_asimdmisc_N - public static void Sqxtn_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = SatQ(Int(element, unsigned), esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // sqxtun_advsimd.html#SQXTUN_asisdmisc_N - public static void Sqxtun_S(Bits size, Bits Rn, Bits Rd) - { - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int part = 0; - int elements = 1; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // sqxtun_advsimd.html#SQXTUN_asimdmisc_N - public static void Sqxtun_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = UnsignedSatQ(SInt(element), esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // suqadd_advsimd.html#SUQADD_asisdmisc_R - public static void Suqadd_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits operand2 = V(datasize, d); - BigInteger op1; - BigInteger op2; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, e, esize), !unsigned); - op2 = Int(Elem(operand2, e, esize), unsigned); - - (Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // suqadd_advsimd.html#SUQADD_asimdmisc_R - public static void Suqadd_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits operand2 = V(datasize, d); - BigInteger op1; - BigInteger op2; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, e, esize), !unsigned); - op2 = Int(Elem(operand2, e, esize), unsigned); - - (Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // uadalp_advsimd.html - public static void Uadalp_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / (2 * esize); - - bool acc = (op == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - Bits sum; - BigInteger op1; - BigInteger op2; - - Bits result = (acc ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned); - op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned); - - sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum); - } - - V(d, result); - } - - // uaddlp_advsimd.html - public static void Uaddlp_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / (2 * esize); - - bool acc = (op == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand = V(datasize, n); - Bits sum; - BigInteger op1; - BigInteger op2; - - Bits result = (acc ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, 2 * e + 0, esize), unsigned); - op2 = Int(Elem(operand, 2 * e + 1, esize), unsigned); - - sum = (op1 + op2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + sum); - } - - V(d, result); - } - - // uqxtn_advsimd.html#UQXTN_asisdmisc_N - public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int part = 0; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = SatQ(Int(element, unsigned), esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // uqxtn_advsimd.html#UQXTN_asimdmisc_N - public static void Uqxtn_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - (Bits _result, bool _sat) = SatQ(Int(element, unsigned), esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - Vpart(d, part, result); - } - - // usqadd_advsimd.html#USQADD_asisdmisc_R - public static void Usqadd_S(Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits operand2 = V(datasize, d); - BigInteger op1; - BigInteger op2; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, e, esize), !unsigned); - op2 = Int(Elem(operand2, e, esize), unsigned); - - (Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // usqadd_advsimd.html#USQADD_asimdmisc_R - public static void Usqadd_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(datasize, n); - Bits operand2 = V(datasize, d); - BigInteger op1; - BigInteger op2; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - op1 = Int(Elem(operand, e, esize), !unsigned); - op2 = Int(Elem(operand2, e, esize), unsigned); - - (Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // xtn_advsimd.html - public static void Xtn_V(bool Q, Bits size, Bits Rn, Bits Rd) - { - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand = V(2 * datasize, n); - Bits element; - - for (int e = 0; e <= elements - 1; e++) - { - element = Elem(operand, e, 2 * esize); - - Elem(result, e, esize, element[esize - 1, 0]); - } - - Vpart(d, part, result); - } -#endregion - -#region "SimdReg" - // add_advsimd.html#ADD_asisdsame_only - public static void Add_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool sub_op = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (sub_op) - { - Elem(result, e, esize, element1 - element2); - } - else - { - Elem(result, e, esize, element1 + element2); - } - } - - V(d, result); - } - - // add_advsimd.html#ADD_asimdsame_only - public static void Add_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool sub_op = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (sub_op) - { - Elem(result, e, esize, element1 - element2); - } - else - { - Elem(result, e, esize, element1 + element2); - } - } - - V(d, result); - } - - // addhn_advsimd.html - public static void Addhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool round = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = V(2 * datasize, m); - BigInteger round_const = (round ? (BigInteger)1 << (esize - 1) : 0); - Bits sum; - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, 2 * esize); - element2 = Elem(operand2, e, 2 * esize); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - sum = sum + round_const; - - Elem(result, e, esize, sum[2 * esize - 1, esize]); - } - - Vpart(d, part, result); - } - - // addp_advsimd_vec.html - public static void Addp_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits concat = Bits.Concat(operand2, operand1); - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(concat, 2 * e, esize); - element2 = Elem(concat, (2 * e) + 1, esize); - - Elem(result, e, esize, element1 + element2); - } - - V(d, result); - } - - // and_advsimd.html - public static void And_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - Bits result = AND(operand1, operand2); - - V(d, result); - } - - // bic_advsimd_reg.html - public static void Bic_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - operand2 = NOT(operand2); - - Bits result = AND(operand1, operand2); - - V(d, result); - } - - // bif_advsimd.html - public static void Bif_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1; - Bits operand3; - Bits operand4 = V(datasize, n); - - operand1 = V(datasize, d); - operand3 = NOT(V(datasize, m)); - - V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3))); - } - - // bit_advsimd.html - public static void Bit_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1; - Bits operand3; - Bits operand4 = V(datasize, n); - - operand1 = V(datasize, d); - operand3 = V(datasize, m); - - V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3))); - } - - // bsl_advsimd.html - public static void Bsl_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1; - Bits operand3; - Bits operand4 = V(datasize, n); - - operand1 = V(datasize, m); - operand3 = V(datasize, d); - - V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3))); - } - - // cmeq_advsimd_reg.html#CMEQ_asisdsame_only - public static void Cmeq_Reg_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool and_test = (U == false); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (and_test) - { - test_passed = !IsZero(AND(element1, element2)); - } - else - { - test_passed = (element1 == element2); - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmeq_advsimd_reg.html#CMEQ_asimdsame_only - public static void Cmeq_Reg_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool and_test = (U == false); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (and_test) - { - test_passed = !IsZero(AND(element1, element2)); - } - else - { - test_passed = (element1 == element2); - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmge_advsimd_reg.html#CMGE_asisdsame_only - public static void Cmge_Reg_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool eq = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmge_advsimd_reg.html#CMGE_asimdsame_only - public static void Cmge_Reg_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool eq = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmgt_advsimd_reg.html#CMGT_asisdsame_only - public static void Cmgt_Reg_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool eq = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmgt_advsimd_reg.html#CMGT_asimdsame_only - public static void Cmgt_Reg_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool eq = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmhi_advsimd.html#CMHI_asisdsame_only - public static void Cmhi_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool eq = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmhi_advsimd.html#CMHI_asimdsame_only - public static void Cmhi_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool eq = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmhs_advsimd.html#CMHS_asisdsame_only - public static void Cmhs_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool eq = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmhs_advsimd.html#CMHS_asimdsame_only - public static void Cmhs_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool eq = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool cmp_eq = (eq == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - test_passed = (cmp_eq ? element1 >= element2 : element1 > element2); - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmtst_advsimd.html#CMTST_asisdsame_only - public static void Cmtst_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool and_test = (U == false); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (and_test) - { - test_passed = !IsZero(AND(element1, element2)); - } - else - { - test_passed = (element1 == element2); - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // cmtst_advsimd.html#CMTST_asimdsame_only - public static void Cmtst_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool and_test = (U == false); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - bool test_passed; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (and_test) - { - test_passed = !IsZero(AND(element1, element2)); - } - else - { - test_passed = (element1 == element2); - } - - Elem(result, e, esize, test_passed ? Ones(esize) : Zeros(esize)); - } - - V(d, result); - } - - // eor_advsimd.html - public static void Eor_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, m); - Bits operand2 = Zeros(datasize); - Bits operand3 = Ones(datasize); - Bits operand4 = V(datasize, n); - - Bits result = EOR(operand1, AND(EOR(operand2, operand4), operand3)); - - V(d, result); - } - - // orn_advsimd.html - public static void Orn_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - operand2 = NOT(operand2); - - Bits result = OR(operand1, operand2); - - V(d, result); - } - - // orr_advsimd_reg.html - public static void Orr_V(bool Q, Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int datasize = (Q ? 128 : 64); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - Bits result = OR(operand1, operand2); - - V(d, result); - } - - // raddhn_advsimd.html - public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool round = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = V(2 * datasize, m); - BigInteger round_const = (round ? (BigInteger)1 << (esize - 1) : 0); - Bits sum; - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, 2 * esize); - element2 = Elem(operand2, e, 2 * esize); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - sum = sum + round_const; - - Elem(result, e, esize, sum[2 * esize - 1, esize]); - } - - Vpart(d, part, result); - } - - // rsubhn_advsimd.html - public static void Rsubhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool round = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = V(2 * datasize, m); - BigInteger round_const = (round ? (BigInteger)1 << (esize - 1) : 0); - Bits sum; - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, 2 * esize); - element2 = Elem(operand2, e, 2 * esize); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - sum = sum + round_const; - - Elem(result, e, esize, sum[2 * esize - 1, esize]); - } - - Vpart(d, part, result); - } - - // saba_advsimd.html - public static void Saba_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool ac = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool accumulate = (ac == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0); - - Elem(result, e, esize, Elem(result, e, esize) + absdiff); - } - - V(d, result); - } - - // sabal_advsimd.html - public static void Sabal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool accumulate = (op == false); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff); - } - - V(d, result); - } - - // sabd_advsimd.html - public static void Sabd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool ac = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool accumulate = (ac == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0); - - Elem(result, e, esize, Elem(result, e, esize) + absdiff); - } - - V(d, result); - } - - // sabdl_advsimd.html - public static void Sabdl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool op = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool accumulate = (op == false); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff); - } - - V(d, result); - } - - // saddl_advsimd.html - public static void Saddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // saddw_advsimd.html - public static void Saddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, 2 * esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // sha256h_advsimd.html - public static void Sha256h_V(Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if !HaveCryptoExt() then UnallocatedEncoding(); */ - - /* Operation */ - /* CheckCryptoEnabled64(); */ - - Bits result = SHA256hash(V(128, d), V(128, n), V(128, m), true); - - V(d, result); - } - - // sha256h2_advsimd.html - public static void Sha256h2_V(Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if !HaveCryptoExt() then UnallocatedEncoding(); */ - - /* Operation */ - /* CheckCryptoEnabled64(); */ - - Bits result = SHA256hash(V(128, n), V(128, d), V(128, m), false); - - V(d, result); - } - - // sha256su1_advsimd.html - public static void Sha256su1_V(Bits Rm, Bits Rn, Bits Rd) - { - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if !HaveCryptoExt() then UnallocatedEncoding(); */ - - /* Operation */ - /* CheckCryptoEnabled64(); */ - - Bits result = new Bits(128); - Bits operand1 = V(128, d); - Bits operand2 = V(128, n); - Bits operand3 = V(128, m); - Bits T0 = Bits.Concat(operand3[31, 0], operand2[127, 32]); // bits(128) - Bits T1; // bits(64) - Bits elt; // bits(32) - - T1 = operand3[127, 64]; - for (int e = 0; e <= 1; e++) - { - elt = Elem(T1, e, 32); - elt = EOR(EOR(ROR(elt, 17), ROR(elt, 19)), LSR(elt, 10)); - elt = elt + Elem(operand1, e, 32) + Elem(T0, e, 32); - Elem(result, e, 32, elt); - } - - T1 = result[63, 0]; - for (int e = 2; e <= 3; e++) - { - elt = Elem(T1, e - 2, 32); - elt = EOR(EOR(ROR(elt, 17), ROR(elt, 19)), LSR(elt, 10)); - elt = elt + Elem(operand1, e, 32) + Elem(T0, e, 32); - Elem(result, e, 32, elt); - } - - V(d, result); - } - - // shadd_advsimd.html - public static void Shadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - Elem(result, e, esize, sum.SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // shsub_advsimd.html - public static void Shsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - Elem(result, e, esize, diff.SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // smlal_advsimd_vec.html - public static void Smlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - Bits operand3 = V(2 * datasize, d); - BigInteger element1; - BigInteger element2; - Bits product; - Bits accum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); - - if (sub_op) - { - accum = Elem(operand3, e, 2 * esize) - product; - } - else - { - accum = Elem(operand3, e, 2 * esize) + product; - } - - Elem(result, e, 2 * esize, accum); - } - - V(d, result); - } - - // smlsl_advsimd_vec.html - public static void Smlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - Bits operand3 = V(2 * datasize, d); - BigInteger element1; - BigInteger element2; - Bits product; - Bits accum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); - - if (sub_op) - { - accum = Elem(operand3, e, 2 * esize) - product; - } - else - { - accum = Elem(operand3, e, 2 * esize) + product; - } - - Elem(result, e, 2 * esize, accum); - } - - V(d, result); - } - - // sqadd_advsimd.html#SQADD_asisdsame_only - public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - (Bits _result, bool _sat) = SatQ(sum, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqadd_advsimd.html#SQADD_asimdsame_only - public static void Sqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - (Bits _result, bool _sat) = SatQ(sum, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only - public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' || size == '00' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool rounding = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); - BigInteger element1; - BigInteger element2; - BigInteger product; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = SInt(Elem(operand1, e, esize)); - element2 = SInt(Elem(operand2, e, esize)); - - product = (2 * element1 * element2) + round_const; - - (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only - public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' || size == '00' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool rounding = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); - BigInteger element1; - BigInteger element2; - BigInteger product; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = SInt(Elem(operand1, e, esize)); - element2 = SInt(Elem(operand2, e, esize)); - - product = (2 * element1 * element2) + round_const; - - (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only - public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' || size == '00' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool rounding = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); - BigInteger element1; - BigInteger element2; - BigInteger product; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = SInt(Elem(operand1, e, esize)); - element2 = SInt(Elem(operand2, e, esize)); - - product = (2 * element1 * element2) + round_const; - - (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only - public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' || size == '00' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool rounding = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); - BigInteger element1; - BigInteger element2; - BigInteger product; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = SInt(Elem(operand1, e, esize)); - element2 = SInt(Elem(operand2, e, esize)); - - product = (2 * element1 * element2) + round_const; - - (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqsub_advsimd.html#SQSUB_asisdsame_only - public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - (Bits _result, bool _sat) = SatQ(diff, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // sqsub_advsimd.html#SQSUB_asimdsame_only - public static void Sqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - (Bits _result, bool _sat) = SatQ(diff, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // srhadd_advsimd.html - public static void Srhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // ssubl_advsimd.html - public static void Ssubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // ssubw_advsimd.html - public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, 2 * esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // sub_advsimd.html#SUB_asisdsame_only - public static void Sub_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size != '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool sub_op = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (sub_op) - { - Elem(result, e, esize, element1 - element2); - } - else - { - Elem(result, e, esize, element1 + element2); - } - } - - V(d, result); - } - - // sub_advsimd.html#SUB_asimdsame_only - public static void Sub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool sub_op = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, esize); - element2 = Elem(operand2, e, esize); - - if (sub_op) - { - Elem(result, e, esize, element1 - element2); - } - else - { - Elem(result, e, esize, element1 + element2); - } - } - - V(d, result); - } - - // subhn_advsimd.html - public static void Subhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = false; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool round = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = V(2 * datasize, m); - BigInteger round_const = (round ? (BigInteger)1 << (esize - 1) : 0); - Bits sum; - Bits element1; - Bits element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Elem(operand1, e, 2 * esize); - element2 = Elem(operand2, e, 2 * esize); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - sum = sum + round_const; - - Elem(result, e, esize, sum[2 * esize - 1, esize]); - } - - Vpart(d, part, result); - } - - // trn1_advsimd.html - public static void Trn1_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - int pairs = elements / 2; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - for (int p = 0; p <= pairs - 1; p++) - { - Elem(result, 2 * p + 0, esize, Elem(operand1, 2 * p + part, esize)); - Elem(result, 2 * p + 1, esize, Elem(operand2, 2 * p + part, esize)); - } - - V(d, result); - } - - // trn2_advsimd.html - public static void Trn2_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - int pairs = elements / 2; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - for (int p = 0; p <= pairs - 1; p++) - { - Elem(result, 2 * p + 0, esize, Elem(operand1, 2 * p + part, esize)); - Elem(result, 2 * p + 1, esize, Elem(operand2, 2 * p + part, esize)); - } - - V(d, result); - } - - // uaba_advsimd.html - public static void Uaba_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool ac = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool accumulate = (ac == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0); - - Elem(result, e, esize, Elem(result, e, esize) + absdiff); - } - - V(d, result); - } - - // uabal_advsimd.html - public static void Uabal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool accumulate = (op == false); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff); - } - - V(d, result); - } - - // uabd_advsimd.html - public static void Uabd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool ac = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - bool accumulate = (ac == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(datasize, d) : Zeros(datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(esize - 1, 0); - - Elem(result, e, esize, Elem(result, e, esize) + absdiff); - } - - V(d, result); - } - - // uabdl_advsimd.html - public static void Uabdl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool op = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool accumulate = (op == false); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - Bits absdiff; - - Bits result = (accumulate ? V(2 * datasize, d) : Zeros(2 * datasize)); - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - absdiff = Abs(element1 - element2).SubBigInteger(2 * esize - 1, 0); - - Elem(result, e, 2 * esize, Elem(result, e, 2 * esize) + absdiff); - } - - V(d, result); - } - - // uaddl_advsimd.html - public static void Uaddl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // uaddw_advsimd.html - public static void Uaddw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, 2 * esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // uhadd_advsimd.html - public static void Uhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - Elem(result, e, esize, sum.SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // uhsub_advsimd.html - public static void Uhsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - Elem(result, e, esize, diff.SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // umlal_advsimd_vec.html - public static void Umlal_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - Bits operand3 = V(2 * datasize, d); - BigInteger element1; - BigInteger element2; - Bits product; - Bits accum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); - - if (sub_op) - { - accum = Elem(operand3, e, 2 * esize) - product; - } - else - { - accum = Elem(operand3, e, 2 * esize) + product; - } - - Elem(result, e, 2 * esize, accum); - } - - V(d, result); - } - - // umlsl_advsimd_vec.html - public static void Umlsl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - Bits operand3 = V(2 * datasize, d); - BigInteger element1; - BigInteger element2; - Bits product; - Bits accum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - product = (element1 * element2).SubBigInteger(2 * esize - 1, 0); - - if (sub_op) - { - accum = Elem(operand3, e, 2 * esize) - product; - } - else - { - accum = Elem(operand3, e, 2 * esize) + product; - } - - Elem(result, e, 2 * esize, accum); - } - - V(d, result); - } - - // uqadd_advsimd.html#UQADD_asisdsame_only - public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - (Bits _result, bool _sat) = SatQ(sum, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // uqadd_advsimd.html#UQADD_asimdsame_only - public static void Uqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger sum; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - sum = element1 + element2; - - (Bits _result, bool _sat) = SatQ(sum, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // uqsub_advsimd.html#UQSUB_asisdsame_only - public static void Uqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Scalar */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - int esize = 8 << (int)UInt(size); - int datasize = esize; - int elements = 1; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - (Bits _result, bool _sat) = SatQ(diff, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // uqsub_advsimd.html#UQSUB_asimdsame_only - public static void Uqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode Vector */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - BigInteger diff; - bool sat; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - diff = element1 - element2; - - (Bits _result, bool _sat) = SatQ(diff, esize, unsigned); - Elem(result, e, esize, _result); - sat = _sat; - - if (sat) - { - /* FPSR.QC = '1'; */ - FPSR[27] = true; // TODO: Add named fields. - } - } - - V(d, result); - } - - // urhadd_advsimd.html - public static void Urhadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - BigInteger element1; - BigInteger element2; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - Elem(result, e, esize, (element1 + element2 + 1).SubBigInteger(esize, 1)); - } - - V(d, result); - } - - // usubl_advsimd.html - public static void Usubl_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = Vpart(datasize, n, part); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // usubw_advsimd.html - public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool U = true; - const bool o1 = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size == '11' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = 64; - int part = (int)UInt(Q); - int elements = datasize / esize; - - bool sub_op = (o1 == true); - bool unsigned = (U == true); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(2 * datasize); - Bits operand1 = V(2 * datasize, n); - Bits operand2 = Vpart(datasize, m, part); - BigInteger element1; - BigInteger element2; - BigInteger sum; - - for (int e = 0; e <= elements - 1; e++) - { - element1 = Int(Elem(operand1, e, 2 * esize), unsigned); - element2 = Int(Elem(operand2, e, esize), unsigned); - - if (sub_op) - { - sum = element1 - element2; - } - else - { - sum = element1 + element2; - } - - Elem(result, e, 2 * esize, sum.SubBigInteger(2 * esize - 1, 0)); - } - - V(d, result); - } - - // uzp1_advsimd.html - public static void Uzp1_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operandl = V(datasize, n); - Bits operandh = V(datasize, m); - - Bits zipped = Bits.Concat(operandh, operandl); - - for (int e = 0; e <= elements - 1; e++) - { - Elem(result, e, esize, Elem(zipped, 2 * e + part, esize)); - } - - V(d, result); - } - - // uzp2_advsimd.html - public static void Uzp2_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operandl = V(datasize, n); - Bits operandh = V(datasize, m); - - Bits zipped = Bits.Concat(operandh, operandl); - - for (int e = 0; e <= elements - 1; e++) - { - Elem(result, e, esize, Elem(zipped, 2 * e + part, esize)); - } - - V(d, result); - } - - // zip1_advsimd.html - public static void Zip1_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = false; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - int pairs = elements / 2; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - int @base = part * pairs; - - for (int p = 0; p <= pairs - 1; p++) - { - Elem(result, 2 * p + 0, esize, Elem(operand1, @base + p, esize)); - Elem(result, 2 * p + 1, esize, Elem(operand2, @base + p, esize)); - } - - V(d, result); - } - - // zip2_advsimd.html - public static void Zip2_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) - { - const bool op = true; - - /* Decode */ - int d = (int)UInt(Rd); - int n = (int)UInt(Rn); - int m = (int)UInt(Rm); - - /* if size:Q == '110' then ReservedValue(); */ - - int esize = 8 << (int)UInt(size); - int datasize = (Q ? 128 : 64); - int elements = datasize / esize; - int part = (int)UInt(op); - int pairs = elements / 2; - - /* Operation */ - /* CheckFPAdvSIMDEnabled64(); */ - - Bits result = new Bits(datasize); - Bits operand1 = V(datasize, n); - Bits operand2 = V(datasize, m); - - int @base = part * pairs; - - for (int p = 0; p <= pairs - 1; p++) - { - Elem(result, 2 * p + 0, esize, Elem(operand1, @base + p, esize)); - Elem(result, 2 * p + 1, esize, Elem(operand2, @base + p, esize)); - } - - V(d, result); - } -#endregion - } -} diff --git a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs deleted file mode 100644 index f37774763..000000000 --- a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs +++ /dev/null @@ -1,1740 +0,0 @@ -// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Pseudocode.cs - -// https://developer.arm.com/products/architecture/a-profile/exploration-tools -// ..\A64_v83A_ISA_xml_00bet6.1\ISA_v83A_A64_xml_00bet6.1_OPT\xhtml\ - -// https://alastairreid.github.io/asl-lexical-syntax/ - -// | ------------------------|-------------------------------- | -// | ASL | C# | -// | ------------------------|-------------------------------- | -// | bit, bits(1); boolean | bool | -// | bits | Bits | -// | integer | BigInteger, int | -// | real | decimal; double, float | -// | ------------------------|-------------------------------- | -// | '0'; FALSE | false | -// | '1'; TRUE | true | -// | '010' | "010" | -// | DIV, MOD | /, % | -// | ------------------------|-------------------------------- | - -using System; -using System.Numerics; - -namespace Ryujinx.Tests.Cpu.Tester -{ - using Types; - - using static Shared; - - internal static class AArch64 - { -#region "exceptions/exceptions/" - /* shared_pseudocode.html#AArch64.ResetControlRegisters.1 */ - public static void ResetControlRegisters(bool cold_reset) - { - PSTATE.N = cold_reset; - PSTATE.Z = cold_reset; - PSTATE.C = cold_reset; - PSTATE.V = cold_reset; - } - - /* */ - public static void TakeReset(bool cold_reset) - { - /* assert !HighestELUsingAArch32(); */ - - // Enter the highest implemented Exception level in AArch64 state - if (HaveEL(EL3)) - { - PSTATE.EL = EL3; - } - else if (HaveEL(EL2)) - { - PSTATE.EL = EL2; - } - else - { - PSTATE.EL = EL1; - } - - // Reset the system registers and other system components - AArch64.ResetControlRegisters(cold_reset); - - // Reset all other PSTATE fields - PSTATE.SP = true; // Select stack pointer - - // All registers, bits and fields not reset by the above pseudocode or by the BranchTo() call - // below are UNKNOWN bitstrings after reset. In particular, the return information registers - // ELR_ELx and SPSR_ELx have UNKNOWN values, so that it - // is impossible to return from a reset in an architecturally defined way. - AArch64.ResetGeneralRegisters(); - AArch64.ResetSIMDFPRegisters(); - AArch64.ResetSpecialRegisters(); - } -#endregion - -#region "functions/registers/" - /* shared_pseudocode.html#AArch64.ResetGeneralRegisters.0 */ - public static void ResetGeneralRegisters() - { - for (int i = 0; i <= 30; i++) - { - /* X[i] = bits(64) UNKNOWN; */ - _R[i].SetAll(false); - } - } - - /* shared_pseudocode.html#AArch64.ResetSIMDFPRegisters.0 */ - public static void ResetSIMDFPRegisters() - { - for (int i = 0; i <= 31; i++) - { - /* V[i] = bits(128) UNKNOWN; */ - _V[i].SetAll(false); - } - } - - /* shared_pseudocode.html#AArch64.ResetSpecialRegisters.0 */ - public static void ResetSpecialRegisters() - { - // AArch64 special registers - /* SP_EL0 = bits(64) UNKNOWN; */ - SP_EL0.SetAll(false); - /* SP_EL1 = bits(64) UNKNOWN; */ - SP_EL1.SetAll(false); - - FPCR.SetAll(false); // TODO: Add named fields. - FPSR.SetAll(false); // TODO: Add named fields. - } - - // shared_pseudocode.html#impl-aarch64.SP.write.0 - public static void SP(Bits value) - { - /* int width = value.Count; */ - - /* assert width IN {32,64}; */ - - if (!PSTATE.SP) - { - SP_EL0 = ZeroExtend(64, value); - } - else - { - switch (PSTATE.EL) - { - case Bits bits when bits == EL0: - SP_EL0 = ZeroExtend(64, value); - break; - default: - case Bits bits when bits == EL1: - SP_EL1 = ZeroExtend(64, value); - break;/* - case Bits bits when bits == EL2: - SP_EL2 = ZeroExtend(64, value); - break; - case Bits bits when bits == EL3: - SP_EL3 = ZeroExtend(64, value); - break;*/ - } - } - } - - // shared_pseudocode.html#impl-aarch64.SP.read.0 - public static Bits SP(int width) - { - /* assert width IN {8,16,32,64}; */ - - if (!PSTATE.SP) - { - return SP_EL0[width - 1, 0]; - } - else - { - switch (PSTATE.EL) - { - case Bits bits when bits == EL0: - return SP_EL0[width - 1, 0]; - default: - case Bits bits when bits == EL1: - return SP_EL1[width - 1, 0];/* - case Bits bits when bits == EL2: - return SP_EL2[width - 1, 0]; - case Bits bits when bits == EL3: - return SP_EL3[width - 1, 0];*/ - } - } - } - - // shared_pseudocode.html#impl-aarch64.V.write.1 - public static void V(int n, Bits value) - { - /* int width = value.Count; */ - - /* assert n >= 0 && n <= 31; */ - /* assert width IN {8,16,32,64,128}; */ - - _V[n] = ZeroExtend(128, value); - } - - /* shared_pseudocode.html#impl-aarch64.V.read.1 */ - public static Bits V(int width, int n) - { - /* assert n >= 0 && n <= 31; */ - /* assert width IN {8,16,32,64,128}; */ - - return _V[n][width - 1, 0]; - } - - /* shared_pseudocode.html#impl-aarch64.Vpart.read.2 */ - public static Bits Vpart(int width, int n, int part) - { - /* assert n >= 0 && n <= 31; */ - /* assert part IN {0, 1}; */ - - if (part == 0) - { - /* assert width IN {8,16,32,64}; */ - return _V[n][width - 1, 0]; - } - else - { - /* assert width == 64; */ - return _V[n][(width * 2) - 1, width]; - } - } - - // shared_pseudocode.html#impl-aarch64.Vpart.write.2 - public static void Vpart(int n, int part, Bits value) - { - int width = value.Count; - - /* assert n >= 0 && n <= 31; */ - /* assert part IN {0, 1}; */ - - if (part == 0) - { - /* assert width IN {8,16,32,64}; */ - _V[n] = ZeroExtend(128, value); - } - else - { - /* assert width == 64; */ - _V[n][(width * 2) - 1, width] = value[width - 1, 0]; - } - } - - // shared_pseudocode.html#impl-aarch64.X.write.1 - public static void X(int n, Bits value) - { - /* int width = value.Count; */ - - /* assert n >= 0 && n <= 31; */ - /* assert width IN {32,64}; */ - - if (n != 31) - { - _R[n] = ZeroExtend(64, value); - } - } - - /* shared_pseudocode.html#impl-aarch64.X.read.1 */ - public static Bits X(int width, int n) - { - /* assert n >= 0 && n <= 31; */ - /* assert width IN {8,16,32,64}; */ - - if (n != 31) - { - return _R[n][width - 1, 0]; - } - else - { - return Zeros(width); - } - } -#endregion - -#region "instrs/countop/" - // shared_pseudocode.html#CountOp - public enum CountOp {CountOp_CLZ, CountOp_CLS, CountOp_CNT}; -#endregion - -#region "instrs/extendreg/" - /* shared_pseudocode.html#impl-aarch64.DecodeRegExtend.1 */ - public static ExtendType DecodeRegExtend(Bits op) - { - switch (op) - { - default: - case Bits bits when bits == "000": - return ExtendType.ExtendType_UXTB; - case Bits bits when bits == "001": - return ExtendType.ExtendType_UXTH; - case Bits bits when bits == "010": - return ExtendType.ExtendType_UXTW; - case Bits bits when bits == "011": - return ExtendType.ExtendType_UXTX; - case Bits bits when bits == "100": - return ExtendType.ExtendType_SXTB; - case Bits bits when bits == "101": - return ExtendType.ExtendType_SXTH; - case Bits bits when bits == "110": - return ExtendType.ExtendType_SXTW; - case Bits bits when bits == "111": - return ExtendType.ExtendType_SXTX; - } - } - - /* shared_pseudocode.html#impl-aarch64.ExtendReg.3 */ - public static Bits ExtendReg(int N, int reg, ExtendType type, int shift) - { - /* assert shift >= 0 && shift <= 4; */ - - Bits val = X(N, reg); - bool unsigned; - int len; - - switch (type) - { - default: - case ExtendType.ExtendType_SXTB: - unsigned = false; len = 8; - break; - case ExtendType.ExtendType_SXTH: - unsigned = false; len = 16; - break; - case ExtendType.ExtendType_SXTW: - unsigned = false; len = 32; - break; - case ExtendType.ExtendType_SXTX: - unsigned = false; len = 64; - break; - case ExtendType.ExtendType_UXTB: - unsigned = true; len = 8; - break; - case ExtendType.ExtendType_UXTH: - unsigned = true; len = 16; - break; - case ExtendType.ExtendType_UXTW: - unsigned = true; len = 32; - break; - case ExtendType.ExtendType_UXTX: - unsigned = true; len = 64; - break; - } - - // Note the extended width of the intermediate value and - // that sign extension occurs from bit , not - // from bit . This is equivalent to the instruction - // [SU]BFIZ Rtmp, Rreg, #shift, #len - // It may also be seen as a sign/zero extend followed by a shift: - // LSL(Extend(val, N, unsigned), shift); - - len = Min(len, N - shift); - return Extend(Bits.Concat(val[len - 1, 0], Zeros(shift)), N, unsigned); - } - - // shared_pseudocode.html#ExtendType - public enum ExtendType {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, - ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}; -#endregion - -#region "instrs/integer/bitmasks/" - /* shared_pseudocode.html#impl-aarch64.DecodeBitMasks.4 */ - public static (Bits, Bits) DecodeBitMasks(int M, bool immN, Bits imms, Bits immr, bool immediate) - { - Bits tmask, wmask; - Bits tmask_and, wmask_and; - Bits tmask_or, wmask_or; - Bits levels; - - // Compute log2 of element size - // 2^len must be in range [2, M] - int len = HighestSetBit(Bits.Concat(immN, NOT(imms))); - /* if len < 1 then ReservedValue(); */ - /* assert M >= (1 << len); */ - - // Determine S, R and S - R parameters - levels = ZeroExtend(Ones(len), 6); - - // For logical immediates an all-ones value of S is reserved - // since it would generate a useless all-ones result (many times) - /* if immediate && (imms AND levels) == levels then ReservedValue(); */ - - BigInteger S = UInt(AND(imms, levels)); - BigInteger R = UInt(AND(immr, levels)); - BigInteger diff = S - R; // 6-bit subtract with borrow - - // Compute "top mask" - tmask_and = OR(diff.SubBigInteger(5, 0), NOT(levels)); - tmask_or = AND(diff.SubBigInteger(5, 0), levels); - - tmask = Ones(64); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[0], 1), Ones( 1)), 32)), Replicate(Bits.Concat(Zeros( 1), Replicate(tmask_or[0], 1)), 32)); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[1], 2), Ones( 2)), 16)), Replicate(Bits.Concat(Zeros( 2), Replicate(tmask_or[1], 2)), 16)); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[2], 4), Ones( 4)), 8)), Replicate(Bits.Concat(Zeros( 4), Replicate(tmask_or[2], 4)), 8)); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[3], 8), Ones( 8)), 4)), Replicate(Bits.Concat(Zeros( 8), Replicate(tmask_or[3], 8)), 4)); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[4], 16), Ones(16)), 2)), Replicate(Bits.Concat(Zeros(16), Replicate(tmask_or[4], 16)), 2)); - tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[5], 32), Ones(32)), 1)), Replicate(Bits.Concat(Zeros(32), Replicate(tmask_or[5], 32)), 1)); - - // Compute "wraparound mask" - wmask_and = OR(immr, NOT(levels)); - wmask_or = AND(immr, levels); - - wmask = Zeros(64); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 1), Replicate(wmask_and[0], 1)), 32)), Replicate(Bits.Concat(Replicate(wmask_or[0], 1), Zeros( 1)), 32)); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 2), Replicate(wmask_and[1], 2)), 16)), Replicate(Bits.Concat(Replicate(wmask_or[1], 2), Zeros( 2)), 16)); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 4), Replicate(wmask_and[2], 4)), 8)), Replicate(Bits.Concat(Replicate(wmask_or[2], 4), Zeros( 4)), 8)); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 8), Replicate(wmask_and[3], 8)), 4)), Replicate(Bits.Concat(Replicate(wmask_or[3], 8), Zeros( 8)), 4)); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones(16), Replicate(wmask_and[4], 16)), 2)), Replicate(Bits.Concat(Replicate(wmask_or[4], 16), Zeros(16)), 2)); - wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones(32), Replicate(wmask_and[5], 32)), 1)), Replicate(Bits.Concat(Replicate(wmask_or[5], 32), Zeros(32)), 1)); - - if (diff.SubBigInteger(6)) // borrow from S - R - { - wmask = AND(wmask, tmask); - } - else - { - wmask = OR(wmask, tmask); - } - - return (wmask[M - 1, 0], tmask[M - 1, 0]); - } -#endregion - -#region "instrs/integer/shiftreg/" - /* shared_pseudocode.html#impl-aarch64.DecodeShift.1 */ - public static ShiftType DecodeShift(Bits op) - { - switch (op) - { - default: - case Bits bits when bits == "00": - return ShiftType.ShiftType_LSL; - case Bits bits when bits == "01": - return ShiftType.ShiftType_LSR; - case Bits bits when bits == "10": - return ShiftType.ShiftType_ASR; - case Bits bits when bits == "11": - return ShiftType.ShiftType_ROR; - } - } - - /* shared_pseudocode.html#impl-aarch64.ShiftReg.3 */ - public static Bits ShiftReg(int N, int reg, ShiftType type, int amount) - { - Bits result = X(N, reg); - - switch (type) - { - default: - case ShiftType.ShiftType_LSL: - result = LSL(result, amount); - break; - case ShiftType.ShiftType_LSR: - result = LSR(result, amount); - break; - case ShiftType.ShiftType_ASR: - result = ASR(result, amount); - break; - case ShiftType.ShiftType_ROR: - result = ROR(result, amount); - break; - } - - return result; - } - - // shared_pseudocode.html#ShiftType - public enum ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}; -#endregion - -#region "instrs/vector/arithmetic/unary/cmp/compareop/" - // shared_pseudocode.html#CompareOp - public enum CompareOp {CompareOp_GT, CompareOp_GE, CompareOp_EQ, CompareOp_LE, CompareOp_LT}; -#endregion - -#region "instrs/vector/reduce/reduceop/" - // shared_pseudocode.html#impl-aarch64.Reduce.3 - public static Bits Reduce(ReduceOp op, Bits input, int esize) - { - int N = input.Count; - - int half; - Bits hi; - Bits lo; - Bits result = new Bits(esize); - - if (N == esize) - { - return new Bits(input); // Clone. - } - - half = N / 2; - hi = Reduce(op, input[N - 1, half], esize); - lo = Reduce(op, input[half - 1, 0], esize); - - switch (op) - { - case ReduceOp.ReduceOp_FMINNUM: - /* result = FPMinNum(lo, hi, FPCR); */ - break; - case ReduceOp.ReduceOp_FMAXNUM: - /* result = FPMaxNum(lo, hi, FPCR); */ - break; - case ReduceOp.ReduceOp_FMIN: - /* result = FPMin(lo, hi, FPCR); */ - break; - case ReduceOp.ReduceOp_FMAX: - /* result = FPMax(lo, hi, FPCR); */ - break; - case ReduceOp.ReduceOp_FADD: - /* result = FPAdd(lo, hi, FPCR); */ - break; - default: - case ReduceOp.ReduceOp_ADD: - result = lo + hi; - break; - } - - return result; - } - - // shared_pseudocode.html#ReduceOp - public enum ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, - ReduceOp_FMIN, ReduceOp_FMAX, - ReduceOp_FADD, ReduceOp_ADD}; -#endregion - } - - internal static class Shared - { - static Shared() - { - _R = new Bits[31]; - for (int i = 0; i <= 30; i++) - { - _R[i] = new Bits(64, false); - } - - _V = new Bits[32]; - for (int i = 0; i <= 31; i++) - { - _V[i] = new Bits(128, false); - } - - SP_EL0 = new Bits(64, false); - SP_EL1 = new Bits(64, false); - - FPCR = new Bits(32, false); // TODO: Add named fields. - FPSR = new Bits(32, false); // TODO: Add named fields. - - PSTATE.N = false; - PSTATE.Z = false; - PSTATE.C = false; - PSTATE.V = false; - PSTATE.EL = EL1; - PSTATE.SP = true; - } - -#region "functions/common/" - /* */ - public static Bits AND(Bits x, Bits y) - { - return x.And(y); - } - - // shared_pseudocode.html#impl-shared.ASR.2 - public static Bits ASR(Bits x, int shift) - { - int N = x.Count; - - /* assert shift >= 0; */ - - Bits result; - - if (shift == 0) - { - result = new Bits(x); // Clone. - } - else - { - (result, _) = ASR_C(x, shift); - } - - return result; - } - - // shared_pseudocode.html#impl-shared.ASR_C.2 - public static (Bits, bool) ASR_C(Bits x, int shift) - { - int N = x.Count; - - /* assert shift > 0; */ - - Bits extended_x = SignExtend(x, shift + N); - Bits result = extended_x[shift + N - 1, shift]; - bool carry_out = extended_x[shift - 1]; - - return (result, carry_out); - } - - // shared_pseudocode.html#impl-shared.Abs.1 - public static BigInteger Abs(BigInteger x) - { - return (x >= 0 ? x : -x); - } - - // shared_pseudocode.html#impl-shared.BitCount.1 - public static int BitCount(Bits x) - { - int N = x.Count; - - int result = 0; - - for (int i = 0; i <= N - 1; i++) - { - if (x[i]) - { - result = result + 1; - } - } - - return result; - } - - // shared_pseudocode.html#impl-shared.CountLeadingSignBits.1 - public static int CountLeadingSignBits(Bits x) - { - int N = x.Count; - - return CountLeadingZeroBits(EOR(x[N - 1, 1], x[N - 2, 0])); - } - - // shared_pseudocode.html#impl-shared.CountLeadingZeroBits.1 - public static int CountLeadingZeroBits(Bits x) - { - int N = x.Count; - - return (N - 1 - HighestSetBit(x)); - } - - // shared_pseudocode.html#impl-shared.Elem.read.3 - public static Bits Elem(/*in */Bits vector, int e, int size) - { - /* int N = vector.Count; */ - - /* assert e >= 0 && (e+1)*size <= N; */ - - return vector[e * size + size - 1, e * size]; - } - - // shared_pseudocode.html#impl-shared.Elem.write.3 - public static void Elem(/*out */Bits vector, int e, int size, Bits value) - { - /* int N = vector.Count; */ - - /* assert e >= 0 && (e+1)*size <= N; */ - - vector[(e + 1) * size - 1, e * size] = value; - } - - /* */ - public static Bits EOR(Bits x, Bits y) - { - return x.Xor(y); - } - - // shared_pseudocode.html#impl-shared.Extend.3 - public static Bits Extend(Bits x, int N, bool unsigned) - { - if (unsigned) - { - return ZeroExtend(x, N); - } - else - { - return SignExtend(x, N); - } - } - - /* shared_pseudocode.html#impl-shared.Extend.2 */ - public static Bits Extend(int N, Bits x, bool unsigned) - { - return Extend(x, N, unsigned); - } - - // shared_pseudocode.html#impl-shared.HighestSetBit.1 - public static int HighestSetBit(Bits x) - { - int N = x.Count; - - for (int i = N - 1; i >= 0; i--) - { - if (x[i]) - { - return i; - } - } - - return -1; - } - - // shared_pseudocode.html#impl-shared.Int.2 - public static BigInteger Int(Bits x, bool unsigned) - { - return (unsigned ? UInt(x) : SInt(x)); - } - - // shared_pseudocode.html#impl-shared.IsOnes.1 - public static bool IsOnes(Bits x) - { - int N = x.Count; - - return (x == Ones(N)); - } - - // shared_pseudocode.html#impl-shared.IsZero.1 - public static bool IsZero(Bits x) - { - int N = x.Count; - - return (x == Zeros(N)); - } - - // shared_pseudocode.html#impl-shared.IsZeroBit.1 - public static bool IsZeroBit(Bits x) - { - return IsZero(x); - } - - // shared_pseudocode.html#impl-shared.LSL.2 - public static Bits LSL(Bits x, int shift) - { - int N = x.Count; - - /* assert shift >= 0; */ - - Bits result; - - if (shift == 0) - { - result = new Bits(x); // Clone. - } - else - { - (result, _) = LSL_C(x, shift); - } - - return result; - } - - // shared_pseudocode.html#impl-shared.LSL_C.2 - public static (Bits, bool) LSL_C(Bits x, int shift) - { - int N = x.Count; - - /* assert shift > 0; */ - - Bits extended_x = Bits.Concat(x, Zeros(shift)); - Bits result = extended_x[N - 1, 0]; - bool carry_out = extended_x[N]; - - return (result, carry_out); - } - - // shared_pseudocode.html#impl-shared.LSR.2 - public static Bits LSR(Bits x, int shift) - { - int N = x.Count; - - /* assert shift >= 0; */ - - Bits result; - - if (shift == 0) - { - result = new Bits(x); // Clone. - } - else - { - (result, _) = LSR_C(x, shift); - } - - return result; - } - - // shared_pseudocode.html#impl-shared.LSR_C.2 - public static (Bits, bool) LSR_C(Bits x, int shift) - { - int N = x.Count; - - /* assert shift > 0; */ - - Bits extended_x = ZeroExtend(x, shift + N); - Bits result = extended_x[shift + N - 1, shift]; - bool carry_out = extended_x[shift - 1]; - - return (result, carry_out); - } - - // shared_pseudocode.html#impl-shared.Min.2 - public static int Min(int a, int b) - { - if (a <= b) - { - return a; - } - else - { - return b; - } - } - - /* shared_pseudocode.html#impl-shared.NOT.1 */ - public static Bits NOT(Bits x) - { - return x.Not(); - } - - // shared_pseudocode.html#impl-shared.Ones.1 - /* shared_pseudocode.html#impl-shared.Ones.0 */ - public static Bits Ones(int N) - { - return Replicate(true, N); - } - - /* */ - public static Bits OR(Bits x, Bits y) - { - return x.Or(y); - } - - /* */ - public static decimal Real(BigInteger value) - { - return (decimal)value; - } - - /* */ - public static float Real_32(BigInteger value) - { - if (value == BigInteger.Pow((BigInteger)2.0f, 1000)) - { - return float.PositiveInfinity; - } - if (value == -BigInteger.Pow((BigInteger)2.0f, 1000)) - { - return float.NegativeInfinity; - } - - return (float)value; - } - - /* */ - public static double Real_64(BigInteger value) - { - if (value == BigInteger.Pow((BigInteger)2.0, 10000)) - { - return double.PositiveInfinity; - } - if (value == -BigInteger.Pow((BigInteger)2.0, 10000)) - { - return double.NegativeInfinity; - } - - return (double)value; - } - - // shared_pseudocode.html#impl-shared.ROR.2 - public static Bits ROR(Bits x, int shift) - { - /* assert shift >= 0; */ - - Bits result; - - if (shift == 0) - { - result = new Bits(x); // Clone. - } - else - { - (result, _) = ROR_C(x, shift); - } - - return result; - } - - // shared_pseudocode.html#impl-shared.ROR_C.2 - public static (Bits, bool) ROR_C(Bits x, int shift) - { - int N = x.Count; - - /* assert shift != 0; */ - - int m = shift % N; - Bits result = OR(LSR(x, m), LSL(x, N - m)); - bool carry_out = result[N - 1]; - - return (result, carry_out); - } - - /* shared_pseudocode.html#impl-shared.Replicate.1 */ - public static Bits Replicate(int N, Bits x) - { - int M = x.Count; - - /* assert N MOD M == 0; */ - - return Replicate(x, N / M); - } - - /* shared_pseudocode.html#impl-shared.Replicate.2 */ - public static Bits Replicate(Bits x, int N) - { - int M = x.Count; - - bool[] dst = new bool[M * N]; - - for (int i = 0; i < N; i++) - { - x.CopyTo(dst, i * M); - } - - return new Bits(dst); - } - - /* shared_pseudocode.html#impl-shared.RoundDown.1 */ - public static BigInteger RoundDown(decimal x) - { - return (BigInteger)Decimal.Floor(x); - } - - /* */ - public static BigInteger RoundDown_32(float x) - { - if (float.IsPositiveInfinity(x)) - { - return BigInteger.Pow((BigInteger)2.0f, 1000); - } - if (float.IsNegativeInfinity(x)) - { - return -BigInteger.Pow((BigInteger)2.0f, 1000); - } - - return (BigInteger)MathF.Floor(x); - } - - /* */ - public static BigInteger RoundDown_64(double x) - { - if (double.IsPositiveInfinity(x)) - { - return BigInteger.Pow((BigInteger)2.0, 10000); - } - if (double.IsNegativeInfinity(x)) - { - return -BigInteger.Pow((BigInteger)2.0, 10000); - } - - return (BigInteger)Math.Floor(x); - } - - // shared_pseudocode.html#impl-shared.RoundTowardsZero.1 - public static BigInteger RoundTowardsZero(decimal x) - { - if (x == 0.0m) - { - return (BigInteger)0m; - } - else if (x >= 0.0m) - { - return RoundDown(x); - } - else - { - return RoundUp(x); - } - } - - /* shared_pseudocode.html#impl-shared.RoundUp.1 */ - public static BigInteger RoundUp(decimal x) - { - return (BigInteger)Decimal.Ceiling(x); - } - - // shared_pseudocode.html#impl-shared.SInt.1 - public static BigInteger SInt(Bits x) - { - int N = x.Count; - - BigInteger result = 0; - - for (int i = 0; i <= N - 1; i++) - { - if (x[i]) - { - result = result + BigInteger.Pow(2, i); - } - } - - if (x[N - 1]) - { - result = result - BigInteger.Pow(2, N); - } - - return result; - } - - // shared_pseudocode.html#impl-shared.SignExtend.2 - public static Bits SignExtend(Bits x, int N) - { - int M = x.Count; - - /* assert N >= M; */ - - return Bits.Concat(Replicate(x[M - 1], N - M), x); - } - - /* shared_pseudocode.html#impl-shared.SignExtend.1 */ - public static Bits SignExtend(int N, Bits x) - { - return SignExtend(x, N); - } - - // shared_pseudocode.html#impl-shared.UInt.1 - public static BigInteger UInt(Bits x) - { - int N = x.Count; - - BigInteger result = 0; - - for (int i = 0; i <= N - 1; i++) - { - if (x[i]) - { - result = result + BigInteger.Pow(2, i); - } - } - - return result; - } - - // shared_pseudocode.html#impl-shared.ZeroExtend.2 - public static Bits ZeroExtend(Bits x, int N) - { - int M = x.Count; - - /* assert N >= M; */ - - return Bits.Concat(Zeros(N - M), x); - } - - /* shared_pseudocode.html#impl-shared.ZeroExtend.1 */ - public static Bits ZeroExtend(int N, Bits x) - { - return ZeroExtend(x, N); - } - - // shared_pseudocode.html#impl-shared.Zeros.1 - /* shared_pseudocode.html#impl-shared.Zeros.0 */ - public static Bits Zeros(int N) - { - return Replicate(false, N); - } -#endregion - -#region "functions/crc/" - // shared_pseudocode.html#impl-shared.BitReverse.1 - public static Bits BitReverse(Bits data) - { - int N = data.Count; - - Bits result = new Bits(N); - - for (int i = 0; i <= N - 1; i++) - { - result[N - i - 1] = data[i]; - } - - return result; - } - - // shared_pseudocode.html#impl-shared.Poly32Mod2.2 - public static Bits Poly32Mod2(Bits _data, Bits poly) - { - int N = _data.Count; - - /* assert N > 32; */ - - Bits data = new Bits(_data); // Clone. - - for (int i = N - 1; i >= 32; i--) - { - if (data[i]) - { - data[i - 1, 0] = EOR(data[i - 1, 0], Bits.Concat(poly, Zeros(i - 32))); - } - } - - return data[31, 0]; - } -#endregion - -#region "functions/crypto/" - // shared_pseudocode.html#impl-shared.ROL.2 - public static Bits ROL(Bits x, int shift) - { - int N = x.Count; - - /* assert shift >= 0 && shift <= N; */ - - if (shift == 0) - { - return new Bits(x); // Clone. - } - - return ROR(x, N - shift); - } - - // shared_pseudocode.html#impl-shared.SHA256hash.4 - public static Bits SHA256hash(Bits _X, Bits _Y, Bits W, bool part1) - { - Bits X = new Bits(_X); // Clone. - Bits Y = new Bits(_Y); // Clone. - - Bits chs, maj, t; // bits(32) - - for (int e = 0; e <= 3; e++) - { - chs = SHAchoose(Y[31, 0], Y[63, 32], Y[95, 64]); - maj = SHAmajority(X[31, 0], X[63, 32], X[95, 64]); - - t = Y[127, 96] + SHAhashSIGMA1(Y[31, 0]) + chs + Elem(W, e, 32); - - X[127, 96] = t + X[127, 96]; - Y[127, 96] = t + SHAhashSIGMA0(X[31, 0]) + maj; - - // TODO: Implement ASL: "<,>" as C#: "Bits.Split()". - /* = ROL(Y : X, 32); */ - Bits YX = ROL(Bits.Concat(Y, X), 32); - Y = YX[255, 128]; - X = YX[127, 0]; - } - - return (part1 ? X : Y); - } - - // shared_pseudocode.html#impl-shared.SHAchoose.3 - public static Bits SHAchoose(Bits x, Bits y, Bits z) - { - return EOR(AND(EOR(y, z), x), z); - } - - // shared_pseudocode.html#impl-shared.SHAhashSIGMA0.1 - public static Bits SHAhashSIGMA0(Bits x) - { - return EOR(EOR(ROR(x, 2), ROR(x, 13)), ROR(x, 22)); - } - - // shared_pseudocode.html#impl-shared.SHAhashSIGMA1.1 - public static Bits SHAhashSIGMA1(Bits x) - { - return EOR(EOR(ROR(x, 6), ROR(x, 11)), ROR(x, 25)); - } - - // shared_pseudocode.html#impl-shared.SHAmajority.3 - public static Bits SHAmajority(Bits x, Bits y, Bits z) - { - return OR(AND(x, y), AND(OR(x, y), z)); - } -#endregion - -#region "functions/float/fpdecoderounding/" - /* shared_pseudocode.html#impl-shared.FPDecodeRounding.1 */ - public static FPRounding FPDecodeRounding(Bits rmode) - { - switch (rmode) - { - default: - case Bits bits when bits == "00": - return FPRounding.FPRounding_TIEEVEN; // N - case Bits bits when bits == "01": - return FPRounding.FPRounding_POSINF; // P - case Bits bits when bits == "10": - return FPRounding.FPRounding_NEGINF; // M - case Bits bits when bits == "11": - return FPRounding.FPRounding_ZERO; // Z - } - } -#endregion - -#region "functions/float/fpexc/" - // shared_pseudocode.html#FPExc - public enum FPExc {FPExc_InvalidOp, FPExc_DivideByZero, FPExc_Overflow, - FPExc_Underflow, FPExc_Inexact, FPExc_InputDenorm}; -#endregion - -#region "functions/float/fpprocessexception/" - // shared_pseudocode.html#impl-shared.FPProcessException.2 - public static void FPProcessException(FPExc exception, Bits _fpcr) - { - Bits fpcr = new Bits(_fpcr); // Clone. - - int cumul; - - // Determine the cumulative exception bit number - switch (exception) - { - default: - case FPExc.FPExc_InvalidOp: cumul = 0; break; - case FPExc.FPExc_DivideByZero: cumul = 1; break; - case FPExc.FPExc_Overflow: cumul = 2; break; - case FPExc.FPExc_Underflow: cumul = 3; break; - case FPExc.FPExc_Inexact: cumul = 4; break; - case FPExc.FPExc_InputDenorm: cumul = 7; break; - } - - int enable = cumul + 8; - - if (fpcr[enable]) - { - // Trapping of the exception enabled. - // It is IMPLEMENTATION DEFINED whether the enable bit may be set at all, and - // if so then how exceptions may be accumulated before calling FPTrapException() - /* IMPLEMENTATION_DEFINED "floating-point trap handling"; */ - - throw new NotImplementedException(); - }/* - else if (UsingAArch32()) - { - // Set the cumulative exception bit - FPSCR = '1'; - }*/ - else - { - // Set the cumulative exception bit - FPSR[cumul] = true; - } - } -#endregion - -#region "functions/float/fprounding/" - // shared_pseudocode.html#FPRounding - public enum FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, - FPRounding_NEGINF, FPRounding_ZERO, - FPRounding_TIEAWAY, FPRounding_ODD}; -#endregion - -#region "functions/float/fptofixed/" - /* shared_pseudocode.html#impl-shared.FPToFixed.5 */ - public static Bits FPToFixed(int M, Bits op, int fbits, bool unsigned, Bits _fpcr, FPRounding rounding) - { - int N = op.Count; - - /* assert N IN {16,32,64}; */ - /* assert M IN {16,32,64}; */ - /* assert fbits >= 0; */ - /* assert rounding != FPRounding_ODD; */ - - Bits fpcr = new Bits(_fpcr); // Clone. - - if (N == 16) - { - throw new NotImplementedException(); - } - else if (N == 32) - { - // Unpack using fpcr to determine if subnormals are flushed-to-zero - (FPType type, bool sign, float value) = FPUnpack_32(op, fpcr); - - // If NaN, set cumulative flag or take exception - if (type == FPType.FPType_SNaN || type == FPType.FPType_QNaN) - { - FPProcessException(FPExc.FPExc_InvalidOp, fpcr); - } - - // Scale by fractional bits and produce integer rounded towards minus-infinity - value = value * MathF.Pow(2.0f, fbits); - BigInteger int_result = RoundDown_32(value); - float error = value - Real_32(int_result); - - if (float.IsNaN(error)) - { - error = 0.0f; - } - - // Determine whether supplied rounding mode requires an increment - bool round_up; - - switch (rounding) - { - default: - case FPRounding.FPRounding_TIEEVEN: - round_up = (error > 0.5f || (error == 0.5f && int_result.SubBigInteger(0))); - break; - case FPRounding.FPRounding_POSINF: - round_up = (error != 0.0f); - break; - case FPRounding.FPRounding_NEGINF: - round_up = false; - break; - case FPRounding.FPRounding_ZERO: - round_up = (error != 0.0f && int_result < (BigInteger)0); - break; - case FPRounding.FPRounding_TIEAWAY: - round_up = (error > 0.5f || (error == 0.5f && int_result >= (BigInteger)0)); - break; - } - - if (round_up) - { - int_result = int_result + 1; - } - - // Generate saturated result and exceptions - (Bits result, bool overflow) = SatQ(int_result, M, unsigned); - - if (overflow) - { - FPProcessException(FPExc.FPExc_InvalidOp, fpcr); - } - else if (error != 0.0f) - { - FPProcessException(FPExc.FPExc_Inexact, fpcr); - } - - return result; - } - else /* if (N == 64) */ - { - // Unpack using fpcr to determine if subnormals are flushed-to-zero - (FPType type, bool sign, double value) = FPUnpack_64(op, fpcr); - - // If NaN, set cumulative flag or take exception - if (type == FPType.FPType_SNaN || type == FPType.FPType_QNaN) - { - FPProcessException(FPExc.FPExc_InvalidOp, fpcr); - } - - // Scale by fractional bits and produce integer rounded towards minus-infinity - value = value * Math.Pow(2.0, fbits); - BigInteger int_result = RoundDown_64(value); - double error = value - Real_64(int_result); - - if (double.IsNaN(error)) - { - error = 0.0; - } - - // Determine whether supplied rounding mode requires an increment - bool round_up; - - switch (rounding) - { - default: - case FPRounding.FPRounding_TIEEVEN: - round_up = (error > 0.5 || (error == 0.5 && int_result.SubBigInteger(0))); - break; - case FPRounding.FPRounding_POSINF: - round_up = (error != 0.0); - break; - case FPRounding.FPRounding_NEGINF: - round_up = false; - break; - case FPRounding.FPRounding_ZERO: - round_up = (error != 0.0 && int_result < (BigInteger)0); - break; - case FPRounding.FPRounding_TIEAWAY: - round_up = (error > 0.5 || (error == 0.5 && int_result >= (BigInteger)0)); - break; - } - - if (round_up) - { - int_result = int_result + 1; - } - - // Generate saturated result and exceptions - (Bits result, bool overflow) = SatQ(int_result, M, unsigned); - - if (overflow) - { - FPProcessException(FPExc.FPExc_InvalidOp, fpcr); - } - else if (error != 0.0) - { - FPProcessException(FPExc.FPExc_Inexact, fpcr); - } - - return result; - } - } -#endregion - -#region "functions/float/fptype/" - // shared_pseudocode.html#FPType - public enum FPType {FPType_Nonzero, FPType_Zero, FPType_Infinity, - FPType_QNaN, FPType_SNaN}; -#endregion - -#region "functions/float/fpunpack/" - /* shared_pseudocode.html#impl-shared.FPUnpack.2 */ - /* shared_pseudocode.html#impl-shared.FPUnpackBase.2 */ - /*public static (FPType, bool, real) FPUnpack_16(Bits fpval, Bits _fpcr) - { - int N = fpval.Count; - - // assert N == 16; - - Bits fpcr = new Bits(_fpcr); // Clone. - - fpcr[26] = false; - - return FPUnpackBase_16(fpval, fpcr); - }*/ - public static (FPType, bool, float) FPUnpack_32(Bits fpval, Bits _fpcr) - { - int N = fpval.Count; - - /* assert N == 32; */ - - Bits fpcr = new Bits(_fpcr); // Clone. - - FPType type; - float value; - - bool sign = fpval[31]; - Bits exp32 = fpval[30, 23]; - Bits frac32 = fpval[22, 0]; - - if (IsZero(exp32)) - { - // Produce zero if value is zero or flush-to-zero is selected. - if (IsZero(frac32) || fpcr[24]) - { - type = FPType.FPType_Zero; - value = 0.0f; - - // Denormalized input flushed to zero - if (!IsZero(frac32)) - { - FPProcessException(FPExc.FPExc_InputDenorm, fpcr); - } - } - else - { - type = FPType.FPType_Nonzero; - value = MathF.Pow(2.0f, -126) * (Real_32(UInt(frac32)) * MathF.Pow(2.0f, -23)); - } - } - else if (IsOnes(exp32)) - { - if (IsZero(frac32)) - { - type = FPType.FPType_Infinity; - /* value = 2.0^1000000; */ - value = MathF.Pow(2.0f, 1000); - } - else - { - type = frac32[22] ? FPType.FPType_QNaN : FPType.FPType_SNaN; - value = 0.0f; - } - } - else - { - type = FPType.FPType_Nonzero; - value = MathF.Pow(2.0f, (int)UInt(exp32) - 127) * (1.0f + Real_32(UInt(frac32)) * MathF.Pow(2.0f, -23)); - } - - if (sign) - { - value = -value; - } - - return (type, sign, value); - } - public static (FPType, bool, double) FPUnpack_64(Bits fpval, Bits _fpcr) - { - int N = fpval.Count; - - /* assert N == 64; */ - - Bits fpcr = new Bits(_fpcr); // Clone. - - FPType type; - double value; - - bool sign = fpval[63]; - Bits exp64 = fpval[62, 52]; - Bits frac64 = fpval[51, 0]; - - if (IsZero(exp64)) - { - // Produce zero if value is zero or flush-to-zero is selected. - if (IsZero(frac64) || fpcr[24]) - { - type = FPType.FPType_Zero; - value = 0.0; - - // Denormalized input flushed to zero - if (!IsZero(frac64)) - { - FPProcessException(FPExc.FPExc_InputDenorm, fpcr); - } - } - else - { - type = FPType.FPType_Nonzero; - value = Math.Pow(2.0, -1022) * (Real_64(UInt(frac64)) * Math.Pow(2.0, -52)); - } - } - else if (IsOnes(exp64)) - { - if (IsZero(frac64)) - { - type = FPType.FPType_Infinity; - /* value = 2.0^1000000; */ - value = Math.Pow(2.0, 10000); - } - else - { - type = frac64[51] ? FPType.FPType_QNaN : FPType.FPType_SNaN; - value = 0.0; - } - } - else - { - type = FPType.FPType_Nonzero; - value = Math.Pow(2.0, (int)UInt(exp64) - 1023) * (1.0 + Real_64(UInt(frac64)) * Math.Pow(2.0, -52)); - } - - if (sign) - { - value = -value; - } - - return (type, sign, value); - } - - /* shared_pseudocode.html#impl-shared.FPUnpackCV.2 */ - /* shared_pseudocode.html#impl-shared.FPUnpackBase.2 */ - /*public static (FPType, bool, real) FPUnpackCV_16(Bits fpval, Bits _fpcr) - { - int N = fpval.Count; - - // assert N == 16; - - Bits fpcr = new Bits(_fpcr); // Clone. - - fpcr[19] = false; - - return FPUnpackBase_16(fpval, fpcr); - }*/ - public static (FPType, bool, float) FPUnpackCV_32(Bits fpval, Bits _fpcr) - { - return FPUnpack_32(fpval, _fpcr); - } - public static (FPType, bool, double) FPUnpackCV_64(Bits fpval, Bits _fpcr) - { - return FPUnpack_64(fpval, _fpcr); - } -#endregion - -#region "functions/integer/" - /* shared_pseudocode.html#impl-shared.AddWithCarry.3 */ - public static (Bits, Bits) AddWithCarry(int N, Bits x, Bits y, bool carry_in) - { - BigInteger unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); - BigInteger signed_sum = SInt(x) + SInt(y) + UInt(carry_in); - - Bits result = unsigned_sum.SubBigInteger(N - 1, 0); // same value as signed_sum - - bool n = result[N - 1]; - bool z = IsZero(result); - bool c = !(UInt(result) == unsigned_sum); - bool v = !(SInt(result) == signed_sum); - - return (result, Bits.Concat(n, z, c, v)); - } -#endregion - -#region "functions/registers/" - public static readonly Bits[] _R; - - public static readonly Bits[] _V; - - public static Bits SP_EL0; - public static Bits SP_EL1; - - public static Bits FPCR; // TODO: Add named fields. - // [ 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 22 | 21 20 | 19 | 18 17 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ] - // [ 0 | 0 | 0 | 0 | 0 | AHP | DN | FZ | RMode | Stride | FZ16 | Len | IDE | 0 | 0 | IXE | UFE | OFE | DZE | IOE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 ] - public static Bits FPSR; // TODO: Add named fields. - // [ 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ] - // [ N | Z | C | V | QC | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | IDC | 0 | 0 | IXC | UFC | OFC | DZC | IOC ] -#endregion - -#region "functions/system/" - // shared_pseudocode.html#impl-shared.ConditionHolds.1 - public static bool ConditionHolds(Bits cond) - { - bool result; - - // Evaluate base condition. - switch (cond[3, 1]) - { - case Bits bits when bits == "000": - result = (PSTATE.Z == true); // EQ or NE - break; - case Bits bits when bits == "001": - result = (PSTATE.C == true); // CS or CC - break; - case Bits bits when bits == "010": - result = (PSTATE.N == true); // MI or PL - break; - case Bits bits when bits == "011": - result = (PSTATE.V == true); // VS or VC - break; - case Bits bits when bits == "100": - result = (PSTATE.C == true && PSTATE.Z == false); // HI or LS - break; - case Bits bits when bits == "101": - result = (PSTATE.N == PSTATE.V); // GE or LT - break; - case Bits bits when bits == "110": - result = (PSTATE.N == PSTATE.V && PSTATE.Z == false); // GT or LE - break; - default: - case Bits bits when bits == "111": - result = true; // AL - break; - } - - // Condition flag values in the set '111x' indicate always true - // Otherwise, invert condition if necessary. - if (cond[0] == true && cond != "1111") - { - result = !result; - } - - return result; - } - - // shared_pseudocode.html#EL3 - public static readonly Bits EL3 = "11"; - // shared_pseudocode.html#EL2 - public static readonly Bits EL2 = "10"; - // shared_pseudocode.html#EL1 - public static readonly Bits EL1 = "01"; - // shared_pseudocode.html#EL0 - public static readonly Bits EL0 = "00"; - - /* shared_pseudocode.html#impl-shared.HaveEL.1 */ - public static bool HaveEL(Bits el) - { - // TODO: Implement ASL: "IN" as C#: "Bits.In()". - /* if el IN {EL1,EL0} then */ - if (el == EL1 || el == EL0) - { - return true; // EL1 and EL0 must exist - } - - /* return boolean IMPLEMENTATION_DEFINED; */ - return false; - } - - public static ProcState PSTATE; - - /* shared_pseudocode.html#ProcState */ - internal struct ProcState - { - public void NZCV(Bits nzcv) // ASL: ".<,,,>". - { - N = nzcv[3]; - Z = nzcv[2]; - C = nzcv[1]; - V = nzcv[0]; - } - - public void NZCV(bool n, bool z, bool c, bool v) // ASL: ".<,,,>". - { - N = n; - Z = z; - C = c; - V = v; - } - - public bool N; // Negative condition flag - public bool Z; // Zero condition flag - public bool C; // Carry condition flag - public bool V; // oVerflow condition flag - public Bits EL; // Exception Level - public bool SP; // Stack pointer select: 0=SP0, 1=SPx [AArch64 only] - } -#endregion - -#region "functions/vector/" - // shared_pseudocode.html#impl-shared.SatQ.3 - public static (Bits, bool) SatQ(BigInteger i, int N, bool unsigned) - { - (Bits result, bool sat) = (unsigned ? UnsignedSatQ(i, N) : SignedSatQ(i, N)); - - return (result, sat); - } - - // shared_pseudocode.html#impl-shared.SignedSatQ.2 - public static (Bits, bool) SignedSatQ(BigInteger i, int N) - { - BigInteger result; - bool saturated; - - if (i > BigInteger.Pow(2, N - 1) - 1) - { - result = BigInteger.Pow(2, N - 1) - 1; - saturated = true; - } - else if (i < -(BigInteger.Pow(2, N - 1))) - { - result = -(BigInteger.Pow(2, N - 1)); - saturated = true; - } - else - { - result = i; - saturated = false; - } - - return (result.SubBigInteger(N - 1, 0), saturated); - } - - // shared_pseudocode.html#impl-shared.UnsignedSatQ.2 - public static (Bits, bool) UnsignedSatQ(BigInteger i, int N) - { - BigInteger result; - bool saturated; - - if (i > BigInteger.Pow(2, N) - 1) - { - result = BigInteger.Pow(2, N) - 1; - saturated = true; - } - else if (i < (BigInteger)0) - { - result = (BigInteger)0; - saturated = true; - } - else - { - result = i; - saturated = false; - } - - return (result.SubBigInteger(N - 1, 0), saturated); - } -#endregion - } -} diff --git a/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs b/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs deleted file mode 100644 index 87cdfcd25..000000000 --- a/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs +++ /dev/null @@ -1,282 +0,0 @@ -// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Bits.cs - -// https://github.com/dotnet/corefx/blob/master/src/System.Collections/src/System/Collections/BitArray.cs - -using System; -using System.Collections; -using System.Numerics; - -namespace Ryujinx.Tests.Cpu.Tester.Types -{ - internal sealed class Bits : ICollection, IEnumerable, IEquatable - { - private BitArray bits; - - public Bits(bool[] values) => bits = new BitArray(values); - public Bits(byte[] bytes) => bits = new BitArray(bytes); - public Bits(Bits bits) => this.bits = new BitArray(bits.bits); // Clone: deep copy. - public Bits(int length) => bits = new BitArray(length); - public Bits(int length, bool defaultValue) => bits = new BitArray(length, defaultValue); - private Bits(BitArray bitArray) => bits = new BitArray(bitArray); - public Bits(ulong value) => bits = new BitArray(BitConverter.GetBytes(value)); - public Bits(uint value) => bits = new BitArray(BitConverter.GetBytes(value)); - public Bits(BigInteger value) => bits = new BitArray(value.ToByteArray()); - - private BitArray ToBitArray() => new BitArray(bits); - public ulong ToUInt64() - { - byte[] dst = new byte[8]; - - bits.CopyTo(dst, 0); - - return BitConverter.ToUInt64(dst, 0); - } - public uint ToUInt32() - { - byte[] dst = new byte[4]; - - bits.CopyTo(dst, 0); - - return BitConverter.ToUInt32(dst, 0); - } - public BigInteger ToBigInteger() - { - if (bits.Count != 64 && - bits.Count != 32 && - bits.Count != 16 && - bits.Count != 8) - { - throw new InvalidOperationException(); - } - - byte[] dst = new byte[bits.Count / 8]; - - bits.CopyTo(dst, 0); - - return new BigInteger(dst); - } - - public bool this[int index] // ASL: "<>". - { - get - { - return bits.Get(index); - } - set - { - bits.Set(index, value); - } - } - public Bits this[int highIndex, int lowIndex] // ASL: "<:>". - { - get - { - if (highIndex < lowIndex) - { - throw new IndexOutOfRangeException(); - } - - bool[] dst = new bool[highIndex - lowIndex + 1]; - - for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) - { - dst[n] = bits.Get(i); - } - - return new Bits(dst); - } - set - { - if (highIndex < lowIndex) - { - throw new IndexOutOfRangeException(); - } - - for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) - { - bits.Set(i, value.Get(n)); - } - } - } - - public bool IsReadOnly { get => false; } // Mutable. - public int Count { get => bits.Count; } // Not resizable. - public bool IsSynchronized { get => bits.IsSynchronized; } - public object SyncRoot { get => bits.SyncRoot; } - public Bits And(Bits value) => new Bits(new BitArray(this.bits).And(value.bits)); // Immutable. - public void CopyTo(Array array, int index) => bits.CopyTo(array, index); - public bool Get(int index) => bits.Get(index); - public IEnumerator GetEnumerator() => bits.GetEnumerator(); - //public Bits LeftShift(int count) => new Bits(new BitArray(bits).LeftShift(count)); // Immutable. - public Bits Not() => new Bits(new BitArray(bits).Not()); // Immutable. - public Bits Or(Bits value) => new Bits(new BitArray(this.bits).Or(value.bits)); // Immutable. - //public Bits RightShift(int count) => new Bits(new BitArray(bits).RightShift(count)); // Immutable. - public void Set(int index, bool value) => bits.Set(index, value); - public void SetAll(bool value) => bits.SetAll(value); - public Bits Xor(Bits value) => new Bits(new BitArray(this.bits).Xor(value.bits)); // Immutable. - - public static Bits Concat(Bits highBits, Bits lowBits) // ASL: ":". - { - if (((object)lowBits == null) || ((object)highBits == null)) - { - throw new ArgumentNullException(); - } - - bool[] dst = new bool[lowBits.Count + highBits.Count]; - - lowBits.CopyTo(dst, 0); - highBits.CopyTo(dst, lowBits.Count); - - return new Bits(dst); - } - public static Bits Concat(bool bit3, bool bit2, bool bit1, bool bit0) // ASL: ":::". - { - return new Bits(new bool[] {bit0, bit1, bit2, bit3}); - } - - public static implicit operator Bits(bool value) => new Bits(1, value); - public static implicit operator Bits(string value) - { - if (String.IsNullOrEmpty(value)) - { - throw new InvalidCastException(); - } - - bool[] dst = new bool[value.Length]; - - for (int i = value.Length - 1, n = 0; i >= 0; i--, n++) - { - if (value[i] == '1') - { - dst[n] = true; - } - else if (value[i] == '0') - { - dst[n] = false; - } - else - { - throw new InvalidCastException(); - } - } - - return new Bits(dst); - } - public static explicit operator bool(Bits bit) - { - if (((object)bit == null) || (bit.Count != 1)) - { - throw new InvalidCastException(); - } - - return bit.Get(0); - } - - public static Bits operator +(Bits left, BigInteger right) // ASL: "+". - { - if (((object)left == null) || ((object)right == null)) - { - throw new ArgumentNullException(); - } - - BigInteger dst = left.ToBigInteger() + right; - - return dst.SubBigInteger(left.Count - 1, 0); - } - public static Bits operator +(Bits left, Bits right) // ASL: "+". - { - if (((object)left == null) || ((object)right == null)) - { - throw new ArgumentNullException(); - } - - if (left.Count != right.Count) - { - throw new InvalidOperationException(); - } - - BigInteger dst = left.ToBigInteger() + right.ToBigInteger(); - - return dst.SubBigInteger(left.Count - 1, 0); - } - public static Bits operator -(Bits left, Bits right) // ASL: "-". - { - if (((object)left == null) || ((object)right == null)) - { - throw new ArgumentNullException(); - } - - if (left.Count != right.Count) - { - throw new InvalidOperationException(); - } - - BigInteger dst = left.ToBigInteger() - right.ToBigInteger(); - - return dst.SubBigInteger(left.Count - 1, 0); - } - public static bool operator ==(Bits left, Bits right) // ASL: "==". - { - if (((object)left == null) || ((object)right == null)) - { - throw new ArgumentNullException(); - } - - if (left.Count != right.Count) - { - return false; - } - - for (int i = 0; i <= left.Count - 1; i++) - { - if (left.Get(i) != right.Get(i)) - { - return false; - } - } - - return true; - } - public static bool operator !=(Bits left, Bits right) // ASL: "!=". - { - return !(left == right); - } - - public bool Equals(Bits right) // ASL: "==". - { - if ((object)right == null) - { - throw new ArgumentNullException(); - } - - Bits left = this; - - if (left.Count != right.Count) - { - return false; - } - - for (int i = 0; i <= left.Count - 1; i++) - { - if (left.Get(i) != right.Get(i)) - { - return false; - } - } - - return true; - } - public override bool Equals(object obj) - { - if (obj == null) - { - throw new ArgumentNullException(); - } - - Bits right = obj as Bits; - - return Equals(right); - } - public override int GetHashCode() => bits.GetHashCode(); - } -} diff --git a/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs b/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs deleted file mode 100644 index 49ba260c0..000000000 --- a/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs +++ /dev/null @@ -1,42 +0,0 @@ -// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Integer.cs - -using System; -using System.Numerics; - -namespace Ryujinx.Tests.Cpu.Tester.Types -{ - internal static class Integer - { - public static Bits SubBigInteger(this BigInteger x, int highIndex, int lowIndex) // ASL: "<:>". - { - if (highIndex < lowIndex) - { - throw new IndexOutOfRangeException(); - } - - Bits src = new Bits(x); - bool[] dst = new bool[highIndex - lowIndex + 1]; - - for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) - { - if (i <= src.Count - 1) - { - dst[n] = src[i]; - } - else - { - dst[n] = (x.Sign != -1 ? false : true); // Zero / Sign Extension. - } - } - - return new Bits(dst); - } - - public static bool SubBigInteger(this BigInteger x, int index) // ASL: "<>". - { - Bits dst = x.SubBigInteger(index, index); - - return (bool)dst; - } - } -} diff --git a/Ryujinx/Config.cs b/Ryujinx/Config.cs index 8975b52f2..8b85df9bb 100644 --- a/Ryujinx/Config.cs +++ b/Ryujinx/Config.cs @@ -36,6 +36,8 @@ namespace Ryujinx Device.System.State.DockedMode = Convert.ToBoolean(Parser.Value("Docked_Mode")); + Device.EnableDeviceVsync = Convert.ToBoolean(Parser.Value("Enable_Vsync")); + string[] FilteredLogClasses = Parser.Value("Logging_Filtered_Classes").Split(',', StringSplitOptions.RemoveEmptyEntries); GamePadEnable = Boolean.Parse(Parser.Value("GamePad_Enable")); diff --git a/Ryujinx/Ryujinx.conf b/Ryujinx/Ryujinx.conf index fb97cb317..23a128bfb 100644 --- a/Ryujinx/Ryujinx.conf +++ b/Ryujinx/Ryujinx.conf @@ -28,6 +28,9 @@ Docked_Mode = false #Whether or not to enable Controller support GamePad_Enable = true +#Enable Game Vsync +Enable_Vsync = true + #Device Mappings #Valid Mappings: diff --git a/Ryujinx/Ui/GLScreen.cs b/Ryujinx/Ui/GLScreen.cs index dbf59562c..f98edbc3a 100644 --- a/Ryujinx/Ui/GLScreen.cs +++ b/Ryujinx/Ui/GLScreen.cs @@ -75,7 +75,7 @@ namespace Ryujinx { ResizeEvent = false; - Renderer.FrameBuffer.SetWindowSize(Width, Height); + Renderer.RenderTarget.SetWindowSize(Width, Height); } Ticks += Chrono.ElapsedTicks; @@ -98,7 +98,7 @@ namespace Ryujinx Visible = true; - Renderer.FrameBuffer.SetWindowSize(Width, Height); + Renderer.RenderTarget.SetWindowSize(Width, Height); Context.MakeCurrent(null); @@ -295,20 +295,23 @@ namespace Ryujinx private new void RenderFrame() { - Renderer.FrameBuffer.Render(); + Renderer.RenderTarget.Render(); Device.Statistics.RecordSystemFrameTime(); double HostFps = Device.Statistics.GetSystemFrameRate(); double GameFps = Device.Statistics.GetGameFrameRate(); - NewTitle = $"Ryujinx | Host FPS: {HostFps:0.0} | Game FPS: {GameFps:0.0}"; + NewTitle = $"Ryujinx | Host FPS: {HostFps:0.0} | Game FPS: {GameFps:0.0} | Game Vsync: " + + (Device.EnableDeviceVsync ? "On" : "Off"); TitleEvent = true; SwapBuffers(); Device.System.SignalVsync(); + + Device.VsyncEvent.Set(); } protected override void OnUnload(EventArgs e) diff --git a/Ryujinx/Ui/Program.cs b/Ryujinx/Ui/Program.cs index 503125872..e0fca09e1 100644 --- a/Ryujinx/Ui/Program.cs +++ b/Ryujinx/Ui/Program.cs @@ -52,9 +52,25 @@ namespace Ryujinx } else if (File.Exists(args[0])) { - Console.WriteLine("Loading as homebrew."); - - Device.LoadProgram(args[0]); + switch (Path.GetExtension(args[0]).ToLowerInvariant()) + { + case ".xci": + Console.WriteLine("Loading as XCI."); + Device.LoadXci(args[0]); + break; + case ".nca": + Console.WriteLine("Loading as NCA."); + Device.LoadNca(args[0]); + break; + case ".nsp": + Console.WriteLine("Loading as NSP."); + Device.LoadNsp(args[0]); + break; + default: + Console.WriteLine("Loading as homebrew."); + Device.LoadProgram(args[0]); + break; + } } } else