From d86dcaa13d98db4167e37eb903384d80ea7a074b Mon Sep 17 00:00:00 2001 From: merry Date: Mon, 14 Feb 2022 21:48:10 +0000 Subject: [PATCH] Address nits --- ARMeilleure/Decoders/OpCodeT16AddSubSp.cs | 6 +++-- ARMeilleure/Decoders/OpCodeT16MemImm5.cs | 3 ++- ARMeilleure/Decoders/OpCodeT16MemLit.cs | 7 ++++-- ARMeilleure/Decoders/OpCodeT16MemMult.cs | 28 ++++++++--------------- ARMeilleure/Decoders/OpCodeT16MemSp.cs | 6 +++-- ARMeilleure/Decoders/OpCodeT16MemStack.cs | 7 +++--- ARMeilleure/Decoders/OpCodeT16SpRel.cs | 4 +++- 7 files changed, 32 insertions(+), 29 deletions(-) diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs b/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs index 8d60ab983..b66fe0cdf 100644 --- a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs +++ b/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs @@ -1,9 +1,11 @@ +using ARMeilleure.State; + namespace ARMeilleure.Decoders { class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm { - public int Rd => 13; - public int Rn => 13; + public int Rd => RegisterAlias.Aarch32Sp; + public int Rn => RegisterAlias.Aarch32Sp; public bool? SetFlags => false; diff --git a/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/ARMeilleure/Decoders/OpCodeT16MemImm5.cs index 13a16809d..20ef31e27 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemImm5.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemImm5.cs @@ -1,4 +1,5 @@ using ARMeilleure.Instructions; +using System; namespace ARMeilleure.Decoders { @@ -50,7 +51,7 @@ namespace ARMeilleure.Decoders Immediate = ((opCode >> 6) & 0x1f) << 1; break; default: - throw new System.InvalidOperationException(); + throw new InvalidOperationException(); } } } diff --git a/ARMeilleure/Decoders/OpCodeT16MemLit.cs b/ARMeilleure/Decoders/OpCodeT16MemLit.cs index 4be1ee84b..f8c16e299 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemLit.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemLit.cs @@ -1,9 +1,11 @@ -namespace ARMeilleure.Decoders +using ARMeilleure.State; + +namespace ARMeilleure.Decoders { class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem { public int Rt { get; } - public int Rn => 15; + public int Rn => RegisterAlias.Aarch32Pc; public bool WBack => false; public bool IsLoad => true; @@ -13,6 +15,7 @@ public int Immediate { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode); + public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt = (opCode >> 8) & 7; diff --git a/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/ARMeilleure/Decoders/OpCodeT16MemMult.cs index 841d0f852..c379c2817 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemMult.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemMult.cs @@ -11,31 +11,23 @@ namespace ARMeilleure.Decoders public int PostOffset { get; } public bool IsLoad { get; } public int Offset { get; } - + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemMult(inst, address, opCode); public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { + int regCount = BitOperations.PopCount((uint)RegisterMask); + RegisterMask = opCode & 0xff; Rn = (opCode >> 8) & 7; - - int regCount = BitOperations.PopCount((uint)RegisterMask); - - switch (inst.Name) + Offset = 0; + PostOffset = 4 * regCount; + IsLoad = inst.Name switch { - case InstName.Stm: - IsLoad = false; - Offset = 0; - PostOffset = 4 * regCount; - break; - case InstName.Ldm: - IsLoad = true; - Offset = 0; - PostOffset = 4 * regCount; - break; - default: - throw new InvalidOperationException(); - } + InstName.Ldm => true, + InstName.Stm => false, + _ => throw new InvalidOperationException() + }; } } } diff --git a/ARMeilleure/Decoders/OpCodeT16MemSp.cs b/ARMeilleure/Decoders/OpCodeT16MemSp.cs index 7b2956c86..a038b915b 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemSp.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemSp.cs @@ -1,9 +1,11 @@ -namespace ARMeilleure.Decoders +using ARMeilleure.State; + +namespace ARMeilleure.Decoders { class OpCodeT16MemSp : OpCodeT16, IOpCode32Mem { public int Rt { get; } - public int Rn => 13; + public int Rn => RegisterAlias.Aarch32Sp; public bool WBack => false; public bool IsLoad { get; } diff --git a/ARMeilleure/Decoders/OpCodeT16MemStack.cs b/ARMeilleure/Decoders/OpCodeT16MemStack.cs index c527e105a..9d7b0d203 100644 --- a/ARMeilleure/Decoders/OpCodeT16MemStack.cs +++ b/ARMeilleure/Decoders/OpCodeT16MemStack.cs @@ -1,4 +1,5 @@ using ARMeilleure.Instructions; +using ARMeilleure.State; using System; using System.Numerics; @@ -6,19 +7,19 @@ namespace ARMeilleure.Decoders { class OpCodeT16MemStack : OpCodeT16, IOpCode32MemMult { - public int Rn => 13; + public int Rn => RegisterAlias.Aarch32Sp; public int RegisterMask { get; } public int PostOffset { get; } public bool IsLoad { get; } public int Offset { get; } - + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemStack(inst, address, opCode); public OpCodeT16MemStack(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int extra = (opCode >> 8) & 1; int regCount = BitOperations.PopCount((uint)opCode & 0x1ff); - + switch (inst.Name) { case InstName.Push: diff --git a/ARMeilleure/Decoders/OpCodeT16SpRel.cs b/ARMeilleure/Decoders/OpCodeT16SpRel.cs index dc3c4cf54..d737f5bdd 100644 --- a/ARMeilleure/Decoders/OpCodeT16SpRel.cs +++ b/ARMeilleure/Decoders/OpCodeT16SpRel.cs @@ -1,9 +1,11 @@ +using ARMeilleure.State; + namespace ARMeilleure.Decoders { class OpCodeT16SpRel : OpCodeT16, IOpCode32AluImm { public int Rd { get; } - public int Rn => 13; + public int Rn => RegisterAlias.Aarch32Sp; public bool? SetFlags => false;