mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2024-11-15 09:35:27 +00:00
Initial support for shader half float instructions (#507)
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@ -63,6 +63,7 @@ namespace Ryujinx.Graphics.Gal.Shader
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private Dictionary<int, ShaderDeclInfo> m_OutAttributes;
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private Dictionary<int, ShaderDeclInfo> m_Gprs;
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private Dictionary<int, ShaderDeclInfo> m_GprsHalf;
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private Dictionary<int, ShaderDeclInfo> m_Preds;
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public IReadOnlyDictionary<ShaderIrOp, ShaderDeclInfo> CbTextures => m_CbTextures;
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@ -74,8 +75,9 @@ namespace Ryujinx.Graphics.Gal.Shader
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public IReadOnlyDictionary<int, ShaderDeclInfo> InAttributes => m_InAttributes;
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public IReadOnlyDictionary<int, ShaderDeclInfo> OutAttributes => m_OutAttributes;
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public IReadOnlyDictionary<int, ShaderDeclInfo> Gprs => m_Gprs;
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public IReadOnlyDictionary<int, ShaderDeclInfo> Preds => m_Preds;
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public IReadOnlyDictionary<int, ShaderDeclInfo> Gprs => m_Gprs;
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public IReadOnlyDictionary<int, ShaderDeclInfo> GprsHalf => m_GprsHalf;
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public IReadOnlyDictionary<int, ShaderDeclInfo> Preds => m_Preds;
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public GalShaderType ShaderType { get; private set; }
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@ -92,8 +94,9 @@ namespace Ryujinx.Graphics.Gal.Shader
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m_InAttributes = new Dictionary<int, ShaderDeclInfo>();
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m_OutAttributes = new Dictionary<int, ShaderDeclInfo>();
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m_Gprs = new Dictionary<int, ShaderDeclInfo>();
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m_Preds = new Dictionary<int, ShaderDeclInfo>();
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m_Gprs = new Dictionary<int, ShaderDeclInfo>();
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m_GprsHalf = new Dictionary<int, ShaderDeclInfo>();
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m_Preds = new Dictionary<int, ShaderDeclInfo>();
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}
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public GlslDecl(ShaderIrBlock[] Blocks, GalShaderType ShaderType, ShaderHeader Header) : this(ShaderType)
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@ -146,8 +149,9 @@ namespace Ryujinx.Graphics.Gal.Shader
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Merge(Combined.m_Attributes, VpA.m_Attributes, VpB.m_Attributes);
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Merge(Combined.m_OutAttributes, VpA.m_OutAttributes, VpB.m_OutAttributes);
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Merge(Combined.m_Gprs, VpA.m_Gprs, VpB.m_Gprs);
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Merge(Combined.m_Preds, VpA.m_Preds, VpB.m_Preds);
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Merge(Combined.m_Gprs, VpA.m_Gprs, VpB.m_Gprs);
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Merge(Combined.m_GprsHalf, VpA.m_GprsHalf, VpB.m_GprsHalf);
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Merge(Combined.m_Preds, VpA.m_Preds, VpB.m_Preds);
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//Merge input attributes.
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foreach (KeyValuePair<int, ShaderDeclInfo> KV in VpA.m_InAttributes)
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@ -343,7 +347,20 @@ namespace Ryujinx.Graphics.Gal.Shader
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{
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string Name = GetGprName(Gpr.Index);
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m_Gprs.TryAdd(Gpr.Index, new ShaderDeclInfo(Name, Gpr.Index));
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if (Gpr.RegisterSize == ShaderRegisterSize.Single)
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{
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m_Gprs.TryAdd(Gpr.Index, new ShaderDeclInfo(Name, Gpr.Index));
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}
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else if (Gpr.RegisterSize == ShaderRegisterSize.Half)
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{
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Name += "_h" + Gpr.HalfPart;
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m_GprsHalf.TryAdd((Gpr.Index << 1) | Gpr.HalfPart, new ShaderDeclInfo(Name, Gpr.Index));
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}
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else /* if (Gpr.RegisterSize == ShaderRegisterSize.Double) */
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{
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throw new NotImplementedException("Double types are not supported.");
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}
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}
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break;
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}
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@ -364,6 +364,7 @@ namespace Ryujinx.Graphics.Gal.Shader
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private void PrintDeclGprs()
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{
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PrintDecls(Decl.Gprs);
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PrintDecls(Decl.GprsHalf);
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}
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private void PrintDeclPreds()
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@ -897,7 +898,23 @@ namespace Ryujinx.Graphics.Gal.Shader
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private string GetName(ShaderIrOperGpr Gpr)
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{
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return Gpr.IsConst ? "0" : GetNameWithSwizzle(Decl.Gprs, Gpr.Index);
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if (Gpr.IsConst)
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{
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return "0";
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}
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if (Gpr.RegisterSize == ShaderRegisterSize.Single)
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{
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return GetNameWithSwizzle(Decl.Gprs, Gpr.Index);
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}
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else if (Gpr.RegisterSize == ShaderRegisterSize.Half)
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{
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return GetNameWithSwizzle(Decl.GprsHalf, (Gpr.Index << 1) | Gpr.HalfPart);
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}
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else /* if (Gpr.RegisterSize == ShaderRegisterSize.Double) */
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{
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throw new NotImplementedException("Double types are not supported.");
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}
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}
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private string GetValue(ShaderIrOperImm Imm)
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@ -6,6 +6,14 @@ namespace Ryujinx.Graphics.Gal.Shader
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{
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static partial class ShaderDecode
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{
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private enum HalfOutputType
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{
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PackedFp16,
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Fp32,
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MergeH0,
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MergeH1
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}
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public static void Bfe_C(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitBfe(Block, OpCode, ShaderOper.CR);
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@ -144,6 +152,16 @@ namespace Ryujinx.Graphics.Gal.Shader
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EmitFsetp(Block, OpCode, ShaderOper.RR);
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}
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public static void Hadd2_R(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitBinaryHalfOp(Block, OpCode, ShaderIrInst.Fadd);
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}
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public static void Hmul2_R(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitBinaryHalfOp(Block, OpCode, ShaderIrInst.Fmul);
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}
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public static void Iadd_C(ShaderIrBlock Block, long OpCode, int Position)
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{
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EmitIadd(Block, OpCode, ShaderOper.CR);
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@ -1041,6 +1059,47 @@ namespace Ryujinx.Graphics.Gal.Shader
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op)));
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}
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private static void EmitBinaryHalfOp(ShaderIrBlock Block, long OpCode, ShaderIrInst Inst)
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{
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bool AbsB = OpCode.Read(30);
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bool NegB = OpCode.Read(31);
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bool Sat = OpCode.Read(32);
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bool AbsA = OpCode.Read(44);
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ShaderIrOperGpr[] VecA = OpCode.GprHalfVec8();
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ShaderIrOperGpr[] VecB = OpCode.GprHalfVec20();
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HalfOutputType OutputType = (HalfOutputType)OpCode.Read(49, 3);
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int Elems = OutputType == HalfOutputType.PackedFp16 ? 2 : 1;
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int First = OutputType == HalfOutputType.MergeH1 ? 1 : 0;
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for (int Index = First; Index < Elems; Index++)
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{
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ShaderIrNode OperA = GetAluFabs (VecA[Index], AbsA);
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ShaderIrNode OperB = GetAluFabsFneg(VecB[Index], AbsB, NegB);
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ShaderIrNode Op = new ShaderIrOp(Inst, OperA, OperB);
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ShaderIrOperGpr Dst = GetHalfDst(OpCode, OutputType, Index);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, GetAluFsat(Op, Sat))));
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}
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}
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private static ShaderIrOperGpr GetHalfDst(long OpCode, HalfOutputType OutputType, int Index)
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{
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switch (OutputType)
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{
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case HalfOutputType.PackedFp16: return OpCode.GprHalf0(Index);
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case HalfOutputType.Fp32: return OpCode.Gpr0();
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case HalfOutputType.MergeH0: return OpCode.GprHalf0(0);
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case HalfOutputType.MergeH1: return OpCode.GprHalf0(1);
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}
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throw new ArgumentException(nameof(OutputType));
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}
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private static void EmitLop(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
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{
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int SubOp = OpCode.Read(41, 3);
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@ -6,8 +6,6 @@ namespace Ryujinx.Graphics.Gal.Shader
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{
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static partial class ShaderDecode
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{
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private const int TempRegStart = 0x100;
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private const int ____ = 0x0;
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private const int R___ = 0x1;
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private const int _G__ = 0x2;
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@ -149,14 +147,18 @@ namespace Ryujinx.Graphics.Gal.Shader
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for (int Index = 0; Index < Coords.Length; Index++)
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{
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Coords[Index] = OpCode.Gpr8();
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ShaderIrOperGpr CoordReg = OpCode.Gpr8();
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Coords[Index].Index += Index;
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CoordReg.Index += Index;
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if (Coords[Index].Index > ShaderIrOperGpr.ZRIndex)
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if (!CoordReg.IsValidRegister)
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{
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Coords[Index].Index = ShaderIrOperGpr.ZRIndex;
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CoordReg.Index = ShaderIrOperGpr.ZRIndex;
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}
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Coords[Index] = ShaderIrOperGpr.MakeTemporary(Index);
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Block.AddNode(new ShaderIrAsg(Coords[Index], CoordReg));
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}
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int ChMask = OpCode.Read(31, 0xf);
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@ -167,17 +169,6 @@ namespace Ryujinx.Graphics.Gal.Shader
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ShaderIrInst Inst = GprHandle ? ShaderIrInst.Texb : ShaderIrInst.Texs;
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for (int Ch = 0; Ch < 4; Ch++)
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{
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ShaderIrOperGpr Dst = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, Coords[0], Coords[1], OperC, Meta);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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int RegInc = 0;
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for (int Ch = 0; Ch < 4; Ch++)
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@ -187,18 +178,20 @@ namespace Ryujinx.Graphics.Gal.Shader
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continue;
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}
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrOperGpr Dst = OpCode.Gpr0();
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Dst.Index += RegInc++;
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if (Dst.Index >= ShaderIrOperGpr.ZRIndex)
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if (!Dst.IsValidRegister || Dst.IsConst)
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{
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continue;
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}
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, Coords[0], Coords[1], OperC, Meta);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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}
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@ -215,57 +208,81 @@ namespace Ryujinx.Graphics.Gal.Shader
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private static void EmitTexs(ShaderIrBlock Block, long OpCode, ShaderIrInst Inst)
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{
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//TODO: Support other formats.
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ShaderIrNode OperA = OpCode.Gpr8();
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ShaderIrNode OperB = OpCode.Gpr20();
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ShaderIrNode OperC = OpCode.Imm13_36();
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int LutIndex;
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LutIndex = OpCode.Gpr0 ().Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
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LutIndex |= OpCode.Gpr28().Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
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LutIndex = !OpCode.Gpr0().IsConst ? 1 : 0;
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LutIndex |= !OpCode.Gpr28().IsConst ? 2 : 0;
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if (LutIndex == 0)
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{
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//Both registers are RZ, color is not written anywhere.
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//So, the intruction is basically a no-op.
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//Both destination registers are RZ, do nothing.
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return;
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}
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int ChMask = MaskLut[LutIndex, OpCode.Read(50, 7)];
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bool Fp16 = !OpCode.Read(59);
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for (int Ch = 0; Ch < 4; Ch++)
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{
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ShaderIrOperGpr Dst = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB, OperC, Meta);
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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int RegInc = 0;
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int DstIncrement = 0;
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ShaderIrOperGpr GetDst()
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{
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ShaderIrOperGpr Dst;
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switch (LutIndex)
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if (Fp16)
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{
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case 1: Dst = OpCode.Gpr0(); break;
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case 2: Dst = OpCode.Gpr28(); break;
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case 3: Dst = (RegInc >> 1) != 0
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? OpCode.Gpr28()
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: OpCode.Gpr0 (); break;
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//FP16 mode, two components are packed on the two
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//halfs of a 32-bits register, as two half-float values.
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int HalfPart = DstIncrement & 1;
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default: throw new InvalidOperationException();
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switch (LutIndex)
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{
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case 1: Dst = OpCode.GprHalf0(HalfPart); break;
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case 2: Dst = OpCode.GprHalf28(HalfPart); break;
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case 3: Dst = (DstIncrement >> 1) != 0
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? OpCode.GprHalf28(HalfPart)
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: OpCode.GprHalf0(HalfPart); break;
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default: throw new InvalidOperationException();
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}
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}
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else
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{
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//32-bits mode, each component uses one register.
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//Two components uses two consecutive registers.
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switch (LutIndex)
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{
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case 1: Dst = OpCode.Gpr0(); break;
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case 2: Dst = OpCode.Gpr28(); break;
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case 3: Dst = (DstIncrement >> 1) != 0
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? OpCode.Gpr28()
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: OpCode.Gpr0(); break;
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default: throw new InvalidOperationException();
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}
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Dst.Index += DstIncrement & 1;
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}
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Dst.Index += RegInc++ & 1;
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DstIncrement++;
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return Dst;
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}
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int ChMask = MaskLut[LutIndex, OpCode.Read(50, 7)];
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if (ChMask == 0)
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{
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//All channels are disabled, do nothing.
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return;
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}
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ShaderIrNode OperC = OpCode.Imm13_36();
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ShaderIrOperGpr Coord0 = ShaderIrOperGpr.MakeTemporary(0);
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ShaderIrOperGpr Coord1 = ShaderIrOperGpr.MakeTemporary(1);
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Block.AddNode(new ShaderIrAsg(Coord0, OpCode.Gpr8()));
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Block.AddNode(new ShaderIrAsg(Coord1, OpCode.Gpr20()));
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for (int Ch = 0; Ch < 4; Ch++)
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{
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if (!IsChannelUsed(ChMask, Ch))
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@ -273,13 +290,15 @@ namespace Ryujinx.Graphics.Gal.Shader
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continue;
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}
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ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
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ShaderIrMetaTex Meta = new ShaderIrMetaTex(Ch);
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ShaderIrOp Op = new ShaderIrOp(Inst, Coord0, Coord1, OperC, Meta);
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ShaderIrOperGpr Dst = GetDst();
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if (Dst.Index != ShaderIrOperGpr.ZRIndex)
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if (Dst.IsValidRegister && !Dst.IsConst)
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{
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
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Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
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}
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}
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}
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@ -75,6 +75,49 @@ namespace Ryujinx.Graphics.Gal.Shader
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return new ShaderIrOperGpr(OpCode.Read(28, 0xff));
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}
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private static ShaderIrOperGpr[] GprHalfVec8(this long OpCode)
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{
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return GetGprHalfVec2(OpCode.Read(8, 0xff), OpCode.Read(47, 3));
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}
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private static ShaderIrOperGpr[] GprHalfVec20(this long OpCode)
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{
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return GetGprHalfVec2(OpCode.Read(20, 0xff), OpCode.Read(28, 3));
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}
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private static ShaderIrOperGpr[] GetGprHalfVec2(int Gpr, int Mask)
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{
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if (Mask == 1)
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{
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//This value is used for FP32, the whole 32-bits register
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//is used as each element on the vector.
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return new ShaderIrOperGpr[]
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{
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new ShaderIrOperGpr(Gpr),
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new ShaderIrOperGpr(Gpr)
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};
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}
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ShaderIrOperGpr Low = new ShaderIrOperGpr(Gpr, 0);
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ShaderIrOperGpr High = new ShaderIrOperGpr(Gpr, 1);
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return new ShaderIrOperGpr[]
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{
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(Mask & 1) != 0 ? High : Low,
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(Mask & 2) != 0 ? High : Low
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};
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}
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private static ShaderIrOperGpr GprHalf0(this long OpCode, int HalfPart)
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{
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return new ShaderIrOperGpr(OpCode.Read(0, 0xff), HalfPart);
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}
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private static ShaderIrOperGpr GprHalf28(this long OpCode, int HalfPart)
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{
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return new ShaderIrOperGpr(OpCode.Read(28, 0xff), HalfPart);
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}
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private static ShaderIrOperImm Imm5_39(this long OpCode)
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{
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return new ShaderIrOperImm(OpCode.Read(39, 0x1f));
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@ -6,13 +6,26 @@ namespace Ryujinx.Graphics.Gal.Shader
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public bool IsConst => Index == ZRIndex;
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public bool IsValidRegister => (Index <= ZRIndex);
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public bool IsValidRegister => (uint)Index <= ZRIndex;
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public int Index { get; set; }
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public int Index { get; set; }
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public int HalfPart { get; set; }
|
||||
|
||||
public ShaderRegisterSize RegisterSize { get; private set; }
|
||||
|
||||
public ShaderIrOperGpr(int Index)
|
||||
{
|
||||
this.Index = Index;
|
||||
|
||||
RegisterSize = ShaderRegisterSize.Single;
|
||||
}
|
||||
|
||||
public ShaderIrOperGpr(int Index, int HalfPart)
|
||||
{
|
||||
this.Index = Index;
|
||||
this.HalfPart = HalfPart;
|
||||
|
||||
RegisterSize = ShaderRegisterSize.Half;
|
||||
}
|
||||
|
||||
public static ShaderIrOperGpr MakeTemporary(int Index = 0)
|
||||
|
|
|
@ -58,6 +58,8 @@ namespace Ryujinx.Graphics.Gal.Shader
|
|||
Set("010010111011xx", ShaderDecode.Fsetp_C);
|
||||
Set("0011011x1011xx", ShaderDecode.Fsetp_I);
|
||||
Set("010110111011xx", ShaderDecode.Fsetp_R);
|
||||
Set("0101110100010x", ShaderDecode.Hadd2_R);
|
||||
Set("0101110100001x", ShaderDecode.Hmul2_R);
|
||||
Set("0100110010111x", ShaderDecode.I2f_C);
|
||||
Set("0011100x10111x", ShaderDecode.I2f_I);
|
||||
Set("0101110010111x", ShaderDecode.I2f_R);
|
||||
|
@ -118,7 +120,7 @@ namespace Ryujinx.Graphics.Gal.Shader
|
|||
Set("110000xxxx111x", ShaderDecode.Tex);
|
||||
Set("1101111010111x", ShaderDecode.Tex_B);
|
||||
Set("1101111101001x", ShaderDecode.Texq);
|
||||
Set("1101100xxxxxxx", ShaderDecode.Texs);
|
||||
Set("1101x00xxxxxxx", ShaderDecode.Texs);
|
||||
Set("1101101xxxxxxx", ShaderDecode.Tlds);
|
||||
Set("01011111xxxxxx", ShaderDecode.Vmad);
|
||||
Set("0100111xxxxxxx", ShaderDecode.Xmad_CR);
|
||||
|
|
9
Ryujinx.Graphics/Gal/Shader/ShaderRegisterSize.cs
Normal file
9
Ryujinx.Graphics/Gal/Shader/ShaderRegisterSize.cs
Normal file
|
@ -0,0 +1,9 @@
|
|||
namespace Ryujinx.Graphics.Gal.Shader
|
||||
{
|
||||
enum ShaderRegisterSize
|
||||
{
|
||||
Half,
|
||||
Single,
|
||||
Double
|
||||
}
|
||||
}
|
|
@ -39,7 +39,7 @@ namespace Ryujinx.Graphics.Gal
|
|||
ulong Instruction = 0;
|
||||
|
||||
//Dump until a NOP instruction is found
|
||||
while ((Instruction >> 52 & 0xfff8) != 0x50b0)
|
||||
while ((Instruction >> 48 & 0xfff8) != 0x50b0)
|
||||
{
|
||||
uint Word0 = (uint)Memory.ReadInt32(Position + 0x50 + Offset + 0);
|
||||
uint Word1 = (uint)Memory.ReadInt32(Position + 0x50 + Offset + 4);
|
||||
|
|
Loading…
Reference in a new issue