mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2025-03-14 22:20:18 +00:00
T16: Implement {LDR,STR}{,B,H} (immediate)
This commit is contained in:
parent
d3272c1498
commit
f3e068b94a
2 changed files with 63 additions and 0 deletions
57
ARMeilleure/Decoders/OpCodeT16MemImm5.cs
Normal file
57
ARMeilleure/Decoders/OpCodeT16MemImm5.cs
Normal file
|
@ -0,0 +1,57 @@
|
||||||
|
using ARMeilleure.Instructions;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemImm5 : OpCodeT16, IOpCode32Mem
|
||||||
|
{
|
||||||
|
public int Rt { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool WBack => false;
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public bool Index => true;
|
||||||
|
public bool Add => true;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16MemImm5(inst, address, opCode, inITBlock);
|
||||||
|
|
||||||
|
public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
|
||||||
|
{
|
||||||
|
Rt = (opCode >> 0) & 7;
|
||||||
|
Rn = (opCode >> 3) & 7;
|
||||||
|
|
||||||
|
switch (inst.Name)
|
||||||
|
{
|
||||||
|
case InstName.Ldr:
|
||||||
|
case InstName.Ldrb:
|
||||||
|
case InstName.Ldrh:
|
||||||
|
IsLoad = true;
|
||||||
|
break;
|
||||||
|
case InstName.Str:
|
||||||
|
case InstName.Strb:
|
||||||
|
case InstName.Strh:
|
||||||
|
IsLoad = false;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (inst.Name)
|
||||||
|
{
|
||||||
|
case InstName.Str:
|
||||||
|
case InstName.Ldr:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f) << 2;
|
||||||
|
break;
|
||||||
|
case InstName.Strb:
|
||||||
|
case InstName.Ldrb:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f);
|
||||||
|
break;
|
||||||
|
case InstName.Strh:
|
||||||
|
case InstName.Ldrh:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f) << 1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
throw new System.InvalidOperationException();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
|
@ -1013,6 +1013,12 @@ namespace ARMeilleure.Decoders
|
||||||
SetT16("0101101xxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT16MemReg.Create);
|
SetT16("0101101xxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT16MemReg.Create);
|
||||||
SetT16("0101110xxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT16MemReg.Create);
|
SetT16("0101110xxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT16MemReg.Create);
|
||||||
SetT16("0101111xxxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT16MemReg.Create);
|
SetT16("0101111xxxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("01100xxxxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01101xxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01110xxxxxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01111xxxxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("10000xxxxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("10001xxxxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT16MemImm5.Create);
|
||||||
#endregion
|
#endregion
|
||||||
|
|
||||||
FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
|
FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
|
||||||
|
|
Loading…
Reference in a new issue