From f68c8107a6badaedd89cbd001f35e7d4074fdab0 Mon Sep 17 00:00:00 2001 From: greggameplayer <33609333+greggameplayer@users.noreply.github.com> Date: Sun, 8 Jul 2018 20:51:34 +0200 Subject: [PATCH] Implement Fminnm_V & Fmls_Se & Smov --- ChocolArm64/AOpCodeTable.cs | 3 +++ ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs | 14 ++++++++++++++ ChocolArm64/Instruction/AInstEmitSimdMove.cs | 9 +++++++++ 3 files changed, 26 insertions(+) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index fb4763ef8..02de533c0 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -271,9 +271,11 @@ namespace ChocolArm64 SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg)); SetA64("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg)); SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg)); + SetA64("0x0011101x1xxxxx110001xxxxxxxxxx", AInstEmit.Fminnm_V, typeof(AOpCodeSimdReg)); SetA64("010111111<0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg)); SetA64("0x0011111<0011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V, typeof(AOpCodeSimdReg)); SetA64("0x0011111< + { + Context.Emit(OpCodes.Mul); + Context.Emit(OpCodes.Add); + }); + } public static void Fmls_V(AILEmitterCtx Context) { diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs index 95fe59499..6631cc454 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs @@ -220,6 +220,15 @@ namespace ChocolArm64.Instruction { EmitVectorImmUnaryOp(Context, () => Context.Emit(OpCodes.Not)); } + + public static void Smov(AILEmitterCtx Context) + { + AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp; + + EmitVectorExtractSx(Context, Op.Rn, Op.DstIndex, Op.Size); + + Context.EmitStintzr(Op.Rd); + } public static void Tbl_V(AILEmitterCtx Context) {