diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs
index 304b4d73c..a25c9c827 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Alu.cs
@@ -1,4 +1,4 @@
-// #define T32Alu
+#define T32Alu
 
 using Xunit;
 
@@ -8,18 +8,6 @@ namespace Ryujinx.Tests.Cpu
     public sealed class CpuTestT32Alu : CpuTest32
     {
 #if T32Alu
-        [Test]
-        public void TestT32AluRsImm([ValueSource(nameof(RsImmTestCases))] PrecomputedThumbTestCase test)
-        {
-            RunPrecomputedTestCase(test);
-        }
-
-        [Test]
-        public void TestT32AluImm([ValueSource(nameof(ImmTestCases))] PrecomputedThumbTestCase test)
-        {
-            RunPrecomputedTestCase(test);
-        }
-
         public static readonly PrecomputedThumbTestCase[] RsImmTestCases =
         {
             // TST (reg)
@@ -1013,6 +1001,23 @@ namespace Ryujinx.Tests.Cpu
                 FinalRegs = new uint[] { 0x2bb00694, 0x1c56a4c0, 0xc5cc4a3e, 0xc627c1ab, 0xe0cc0e5c, 0x1f3d71a4, 0x897d57b8, 0x0d4a7208, 0x433b7b88, 0xaaf24fd6, 0x2438f5f8, 0x9875e64a, 0xda475f22, 0x66d5e2e7, 0x00000001, 0x700001f0 },
             },
         };
+
+        public static readonly EnumerableTheoryData<PrecomputedThumbTestCase> TestData_RsImm = new(RsImmTestCases);
+        public static readonly EnumerableTheoryData<PrecomputedThumbTestCase> TestData_Imm = new(ImmTestCases);
+
+        [Theory]
+        [MemberData(nameof(TestData_RsImm))]
+        public void TestT32AluRsImm(PrecomputedThumbTestCase test)
+        {
+            RunPrecomputedTestCase(test);
+        }
+
+        [Theory]
+        [MemberData(nameof(TestData_Imm))]
+        public void TestT32AluImm(PrecomputedThumbTestCase test)
+        {
+            RunPrecomputedTestCase(test);
+        }
 #endif
     }
 }
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs
index 4b291b083..7670cfc3a 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Flow.cs
@@ -1,4 +1,4 @@
-// #define T32Flow
+#define T32Flow
 
 using ARMeilleure.State;
 using Xunit;
@@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
     public sealed class CpuTestT32Flow : CpuTest32
     {
 #if T32Flow
-        [Test]
+        [Fact]
         public void TestT32B1()
         {
             // BNE label
@@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu
             ExecuteOpcodes(runUnicorn: false);
         }
 
-        [Test]
+        [Fact]
         public void TestT32B2()
         {
             // BNE label1
@@ -51,7 +51,7 @@ namespace Ryujinx.Tests.Cpu
             ExecuteOpcodes(runUnicorn: false);
         }
 
-        [Test]
+        [Fact]
         public void TestT32B3()
         {
             // B.W label
@@ -69,7 +69,7 @@ namespace Ryujinx.Tests.Cpu
             ExecuteOpcodes(runUnicorn: false);
         }
 
-        [Test]
+        [Fact]
         public void TestT32B4()
         {
             // B.W label1
@@ -93,7 +93,7 @@ namespace Ryujinx.Tests.Cpu
             ExecuteOpcodes(runUnicorn: false);
         }
 
-        [Test]
+        [Fact]
         public void TestT32Bl()
         {
             // BL label
@@ -112,10 +112,10 @@ namespace Ryujinx.Tests.Cpu
 
             ExecuteOpcodes(runUnicorn: false);
 
-            Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
+            Assert.Equal(CodeBaseAddress + 0x5, GetContext().GetX(0));
         }
 
-        [Test]
+        [Fact]
         public void TestT32Blx1()
         {
             // BLX label
@@ -136,11 +136,11 @@ namespace Ryujinx.Tests.Cpu
 
             ExecuteOpcodes(runUnicorn: false);
 
-            Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
-            Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
+            Assert.Equal(CodeBaseAddress + 0x5, GetContext().GetX(0));
+            Assert.False(GetContext().GetPstateFlag(PState.TFlag));
         }
 
-        [Test]
+        [Fact]
         public void TestT32Blx2()
         {
             // NOP
@@ -163,8 +163,8 @@ namespace Ryujinx.Tests.Cpu
 
             ExecuteOpcodes(runUnicorn: false);
 
-            Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x7));
-            Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
+            Assert.Equal(CodeBaseAddress + 0x7, GetContext().GetX(0));
+            Assert.False(GetContext().GetPstateFlag(PState.TFlag));
         }
 #endif
     }
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs b/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs
index 97efbe322..47582be3c 100644
--- a/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs
+++ b/src/Ryujinx.Tests/Cpu/CpuTestT32Mem.cs
@@ -1,5 +1,6 @@
-// #define T32Mem
+#define T32Mem
 
+using System;
 using Xunit;
 
 namespace Ryujinx.Tests.Cpu
@@ -8,12 +9,6 @@ namespace Ryujinx.Tests.Cpu
     public sealed class CpuTestT32Mem : CpuTest32
     {
 #if T32Mem
-        [Test]
-        public void TestT32MemImm([ValueSource(nameof(ImmTestCases))] PrecomputedMemoryThumbTestCase test)
-        {
-            RunPrecomputedTestCase(test);
-        }
-
         public static readonly PrecomputedMemoryThumbTestCase[] ImmTestCases =
         {
             // STRB (imm8)
@@ -519,6 +514,15 @@ namespace Ryujinx.Tests.Cpu
                 MemoryDelta = Array.Empty<(ulong Address, ushort Value)>(),
             },
         };
+
+        public static readonly EnumerableTheoryData<PrecomputedMemoryThumbTestCase> TestData = new(ImmTestCases);
+
+        [Theory]
+        [MemberData(nameof(TestData))]
+        public void TestT32MemImm(PrecomputedMemoryThumbTestCase test)
+        {
+            RunPrecomputedTestCase(test);
+        }
 #endif
     }
 }