LDj3SNuD
4518c52c65
Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. ( #340 )
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* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
2018-08-13 18:10:02 -03:00
LDj3SNuD
02a6fdcd13
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. ( #334 )
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* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update CpuTestAlu.cs
* Update CpuTestAluImm.cs
* Update CpuTestAluRs.cs
* Update CpuTestAluRx.cs
* Update CpuTestBfm.cs
* Update CpuTestCcmpImm.cs
* Update CpuTestCcmpReg.cs
* Update CpuTestCsel.cs
* Update CpuTestMov.cs
* Update CpuTestMul.cs
* Update Ryujinx.Tests.csproj
* Update Ryujinx.csproj
* Update Luea.csproj
* Update Ryujinx.ShaderTools.csproj
* Address PR feedback (further tested).
* Address PR feedback.
2018-08-10 14:27:15 -03:00
gdkchan
221270db90
More accurate impl of FMINNM/FMAXNM, add vector variants ( #296 )
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* More accurate impl of FMINNM/FMAXNM, add vector variants
* Optimize for the 0 case when op1 != op2
* Address PR feedback
2018-08-05 02:54:21 -03:00
LDj3SNuD
5f34353dce
Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. ( #314 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Opt. (retest).
2018-08-04 16:58:54 -03:00
Arthur Chen
39d36145ba
update encoding for branch instruction ( #305 )
2018-07-26 13:46:05 -03:00
Merry
bdb6cbb435
AOpCodeTable: Speed up instruction decoding ( #284 )
2018-07-19 02:32:37 -03:00
LDj3SNuD
fa5545aab8
Implement Ssubw_V and Usubw_V instructions. ( #287 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdCmp.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-07-18 21:06:28 -03:00
gdkchan
514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits ( #225 )
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* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
* Address PR feedback
* Address PR feedback
* Remove another useless temp var
* nit: Alignment
* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()
* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
gdkchan
741773910d
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions ( #200 )
2018-07-03 03:31:48 -03:00
LDj3SNuD
c228cf320d
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. ( #212 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
LDj3SNuD
53934e8872
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. ( #204 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-06-30 12:40:41 -03:00
gdkchan
bc26aa558a
Add support for the FMLA (by element/scalar) instruction ( #187 )
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* Add support for the FMLA (by element/scalar) instruction
* Fix encoding
2018-06-28 20:51:38 -03:00
LDj3SNuD
8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. ( #183 )
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* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 22:32:29 -03:00
gdkchan
37a6e84fd4
Add REV16/32 (vector) instructions and fix REV64
2018-06-25 18:40:55 -03:00
Rygnus
0bec9d8439
Add opcodes SQXTUN_S and SQXTUN_V ( #184 )
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* Add SQXTUN_S and SQXTUN_V
Part 1/2 of commit
* Add SQXTUN_S and SQXTUN_V (2/2)
Part 2/2 of commit
2018-06-25 14:23:46 -03:00
LDj3SNuD
3bdd109f45
Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. ( #171 )
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* Add files via upload
* Add files via upload
* Delete CpuTestScalar.cs
* Update CpuTestSimdArithmetic.cs
2018-06-18 14:55:26 -03:00
gdkchan
b747b23607
Add the FADDP (scalar) instruction
2018-06-18 00:41:28 -03:00
Lordmau5
46dc89f8dd
Implement Fabs_V ( #146 )
2018-06-12 09:29:16 -03:00
gdkchan
9670c096e4
Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
2018-05-26 17:50:47 -03:00
gdkchan
7ac5f40532
Add scalar variants of FCVTZS/FCVTZU, fix a issue on Ryushader
2018-05-18 14:44:49 -03:00
LDj3SNuD
7cda630aba
Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). ( #110 )
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* Update ILGeneratorEx.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-29 20:39:58 -03:00
LDj3SNuD
2f1250ab04
Update AOpCodeTable.cs ( #108 )
2018-04-25 23:26:41 -03:00
LDj3SNuD
a5ad1e9a06
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. ( #104 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-25 23:20:22 -03:00
LDj3SNuD
302c1d2861
Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. ( #96 )
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* Update AOpCodeTable.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Revert "Started to work in improving the sync primitives"
2018-04-21 16:15:04 -03:00
LDj3SNuD
2ccd995cb2
Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. ( #92 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-04-20 12:40:15 -03:00
MS-DOS1999
76a5972378
Fix Fmin/max and add vector version, add and modifying fmin/max tests ( #89 )
2018-04-19 00:22:12 -03:00
LDj3SNuD
8b75080639
Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. ( #88 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AOpCodeTable.cs
2018-04-18 10:56:27 -03:00
LDj3SNuD
262b5b8054
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). ( #77 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
2018-04-12 11:52:00 -03:00
LDj3SNuD
7acd0e0122
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. ( #74 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimdArithmetic.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-08 16:08:57 -03:00
gdkchan
36d9130592
Add FMLS (vector) instruction
2018-04-06 01:41:54 -03:00
gdkchan
f15b1c76a1
Add FRSQRTS and FCM* instructions
2018-04-05 23:28:12 -03:00
Merry
39f20d8d1a
Implement Frsqrte_S ( #72 )
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* Implement Frsqrte_S
* Implement Frsqrte_V
* Add Frsqrte_S test
2018-04-05 20:36:19 -03:00
gdkchan
45c078d782
Add Faddp (vector) instruction
2018-04-04 22:13:10 -03:00
gdkchan
a20d6b34ab
Add PRFM (unscaled) instruction
2018-04-04 18:10:20 -03:00
gdkchan
7fe12ad169
Add FNEG (vector) instruction
2018-04-04 16:36:07 -03:00
gdkchan
53e2d34905
Enable all ld/st (single structure) instructions
2018-03-30 18:06:02 -03:00
gdkchan
76ac31add6
Add BIT instruction
2018-03-30 16:46:00 -03:00
gdkchan
19b8344568
Add UABD instruction
2018-03-30 16:30:23 -03:00
gdkchan
ba43af5765
Add UABDL instruction
2018-03-30 16:16:16 -03:00
gdkchan
f42f39fd90
Add UADDL instruction
2018-03-30 15:55:28 -03:00
gdkchan
9b6fa1f89e
Add UHADD instruction
2018-03-30 12:37:07 -03:00
gdkchan
b2549d83bf
Add FNMADD instruction
2018-03-24 00:28:23 -03:00
LDj3SNuD
873a7cd112
Add Cls Instruction. ( #67 )
...
* Update AInstEmitAlu.cs
* Update ASoftFallback.cs
* Update AOpCodeTable.cs
2018-03-23 22:06:05 -03:00
MS-DOS1999
ca6cf1cc90
Add Frint Instructions and Tests ( #62 )
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* add 'ADC 32bit and Overflow' test
* Add WZR/WSP tests
* fix ADC and ADDS
* add ADCS test
* add SBCS test
* indent my code and delete comment
* '/' <- i hate you x)
* remove spacebar char
* remove false tab
* add frintx_S test
* update frintx_S test
* add ASRV test
* fix new line
* fix PR
* fix indent
* Add add_V tests
* work on Frintx_V
* Add Frintx_V Instruction
* add some instruction and test
* Syntax + indent
* Delete Console Write
* Delete Console Write 2
* CR del
* Skip NaNs tests
* Skip NaNs tests 2
* Fix errors 1
* Fix errors 2
2018-03-23 07:40:23 -03:00
gdkchan
4940cf0ea5
Add BFI instruction, even more audout fixes
2018-03-16 00:42:44 -03:00
gdkchan
88c6160c62
Add MLA (vector by element), fixes some cases of MUL (vector by element)?
2018-03-15 22:36:47 -03:00
gdkchan
553ba659c4
Add CRC32 instruction and SLI (vector)
2018-03-14 00:12:05 -03:00
gdkchan
553f6c2976
Fix EmitScalarUnaryOpF and add SSRA (vector)
2018-03-10 00:00:31 -03:00
gdkchan
30bcb8da33
Add FRINTM (vector) instruction
2018-03-09 23:41:05 -03:00
gdkchan
aa2d2b3149
Add SHLL instruction
2018-03-09 23:28:38 -03:00
