8 commits

Author	SHA1	Message	Date
gdkchan	514218ab98	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) ... * Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop	2018-07-14 13:13:02 -03:00
gdkchan	0a36bfbf92	Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm (#239)	2018-07-09 22:48:28 -03:00
gdkchan	f9f111bc85	Add intrinsics support (#121) ... * Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake	2018-05-11 20:10:27 -03:00
LDj3SNuD	262b5b8054	Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) ... * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs	2018-04-12 11:52:00 -03:00
gdkchan	916540ff41	Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)	2018-03-30 17:37:31 -03:00
gdkchan	be0e4007dc	Add SMLAL (vector), fix EXT instruction	2018-03-06 21:36:49 -03:00
gdkchan	f39a864050	Add EXT, CMTST (vector) and UMULL (vector) instructions	2018-03-02 19:23:38 -03:00
emmauss	62b827f474	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/AInstEmitSimdMove.cs (Browse further)