Merry
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d0e2de6b37
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fixup
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2022-02-15 00:02:36 +00:00 |
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merry
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f5020e991c
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Reduce line noise
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2022-02-14 21:59:58 +00:00 |
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merry
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d2d71f93f0
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Use index to handle IfThenBlockState
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2022-02-14 21:48:28 +00:00 |
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merry
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d86dcaa13d
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Address nits
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2022-02-14 21:48:10 +00:00 |
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Merry
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4a257bf7a1
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Remove inITBlock argument
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2022-02-14 21:39:17 +00:00 |
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merry
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fbf224e023
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fixup! T16: Implement IT
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2022-02-13 19:40:53 +00:00 |
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merry
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e870d4e089
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fixup! T16: Implement Add to SP (immediate)
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2022-02-13 19:40:21 +00:00 |
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merry
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848ff31a19
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fixup! T16: Implement ADD/SUB (SP)
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2022-02-13 19:40:05 +00:00 |
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merry
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b6078d2c00
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T16: Implement IT
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2022-02-11 23:08:02 +00:00 |
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merry
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09c84d6e91
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T16: Implement B (unconditional)
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2022-02-11 23:08:02 +00:00 |
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merry
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9271abdff0
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T16: Implement B (conditional)
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2022-02-11 23:08:02 +00:00 |
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merry
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06f9a3dc60
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T16: Implement SVC
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2022-02-11 23:08:02 +00:00 |
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merry
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9c16e8695b
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T16: Implement LDM, STM
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2022-02-11 23:08:02 +00:00 |
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merry
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108a6886f9
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T16: Implement NOP
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2022-02-11 23:08:02 +00:00 |
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merry
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41eab68113
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T16: Implement REV, REV16, REVSH
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2022-02-11 23:08:02 +00:00 |
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merry
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34290d38e2
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T16: Implement PUSH, POP
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2022-02-11 23:08:02 +00:00 |
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merry
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dabb5f2449
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T16: Implement CBZ, CBNZ
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2022-02-11 23:08:02 +00:00 |
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merry
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2055622c84
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T16: Implement SXTH, SXTB, UXTH, UTXB
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2022-02-11 23:08:02 +00:00 |
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merry
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e11cd2e50a
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T16: Implement ADD/SUB (SP)
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2022-02-11 23:08:02 +00:00 |
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merry
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1a2ae16395
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T16: Implement Add to SP (immediate)
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2022-02-11 23:08:02 +00:00 |
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merry
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59e9c3d6b0
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T16: Implement ADR
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2022-02-11 23:08:02 +00:00 |
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merry
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baaf5e126e
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T16: Implement LDR/STR (SP)
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2022-02-11 23:08:02 +00:00 |
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merry
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f3e068b94a
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T16: Implement {LDR,STR}{,B,H} (immediate)
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2022-02-11 23:08:02 +00:00 |
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merry
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d3272c1498
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T16: Implement {LDR,STR}{,H,B,SB,SH} (register)
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2022-02-11 23:08:02 +00:00 |
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merry
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a9f952ad40
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T16: Implement LDR (literal)
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2022-02-11 23:08:02 +00:00 |
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merry
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d84c2417aa
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T16: Implement BLX (reg)
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2022-02-11 23:08:02 +00:00 |
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merry
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2876344cca
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T16: Implement ADD, CMP, MOV (high reg)
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2022-02-11 23:08:02 +00:00 |
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merry
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43feb68b11
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T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
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2022-02-11 23:08:02 +00:00 |
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merry
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284272854b
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T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)
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2022-02-11 23:08:02 +00:00 |
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merry
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7a09aea0dc
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T16: Implement ADDS, SUBS (3-bit immediate)
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2022-02-11 23:08:01 +00:00 |
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merry
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3d663a1c8c
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T16: Implement ADDS, SUBS (reg)
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2022-02-11 23:08:01 +00:00 |
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merry
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15ccdff751
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T16: Implement LSL/LSR/ASR (imm)
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2022-02-11 23:08:01 +00:00 |
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merry
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cb4ccec421
|
T16: Implement BX
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2022-02-11 23:08:01 +00:00 |
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merry
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e1bbf8d7b9
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OpCodeTables: Improve thumb fast lookup
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2022-02-11 23:08:01 +00:00 |
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merry
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19c6c1c11c
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OpCodeTable: Prepare for thumb instructions
|
2022-02-11 23:08:01 +00:00 |
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merry
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08e1e0c985
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OpCodeTable: Remove existing thumb instruction implementations
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2022-02-11 23:08:01 +00:00 |
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merry
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1379f41d5d
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OpCodeTable: Minor cleanup
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2022-02-11 23:08:01 +00:00 |
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merry
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5c2e780d40
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Decoders: Add InITBlock argument
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2022-02-11 23:08:01 +00:00 |
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merry
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ce71f9144e
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InstEmitMemory32: Literal loads always have word-aligned PC (#3104)
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2022-02-11 17:51:03 -03:00 |
|
gdkchan
|
c3c3914ed3
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Add a limit on the number of uses a constant may have (#3097)
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2022-02-09 17:42:47 -03:00 |
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merry
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86b37d0ff7
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ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)
* ARMeilleure: A32: Implement UHSUB8
* ARMeilleure: A32: Implement SHSUB8
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2022-02-08 10:46:42 +01:00 |
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merry
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88d3ffb97c
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ARMeilleure: A32: Implement SHADD8 (#3086)
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2022-02-06 12:25:45 -03:00 |
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merry
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222b1ad7da
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ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)
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2022-02-06 02:01:05 +01:00 |
|
gdkchan
|
bd412afb9f
|
Fix small precision error on CPU reciprocal estimate instructions (#3061)
* Fix small precision error on CPU reciprocal estimate instructions
* PPTC version bump
|
2022-01-29 23:59:34 +01:00 |
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gdkchan
|
f3bfd799e1
|
Fix calls passing V128 values on Linux (#3034)
* Fix calls passing V128 values on Linux
* PPTC version bump
|
2022-01-24 11:23:24 +01:00 |
|
gdkchan
|
f0824fde9f
|
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)
* Add host CPU memory barriers for DMB/DSB and ordered load/store
* PPTC version bump
* Revert to old barrier order
|
2022-01-21 12:47:34 -03:00 |
|
sharmander
|
60f7cba30a
|
Implement FCVTNS (Scalar GP) (#2953)
* Implement FCVTNS (Scalar GP)
* Update Ptc Version
|
2022-01-19 22:21:44 -03:00 |
|
gdkchan
|
bd215e447d
|
Fix return type mismatch on 32-bit titles (#3000)
|
2022-01-16 08:39:43 -03:00 |
|
sharmander
|
e5f7ff1eee
|
CPU - Implement FCVTMS (Vector) (#2937)
* Add FCVTMS_V Implementation to Armeilleure
* Fix opcode designation
* Add tests
* Amend Ptc version
* Fix OpCode / Tests
* Create Math.Floor helper method + Update implementation
* Address gdk comments
* Re-address gdk comments
* Update ARMeilleure/Decoders/OpCodeTable.cs
Co-authored-by: gdkchan <gab.dark.100@gmail.com>
* Update Tests to use 2S (4S) and 2D
Co-authored-by: gdkchan <gab.dark.100@gmail.com>
|
2022-01-04 16:45:28 -03:00 |
|
gdkchan
|
e24949ca2c
|
Implement CSDB instruction (#2927)
|
2021-12-19 11:19:05 -03:00 |
|