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2033 commits 10 branches 1391 tags 132 MiB
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211 commits

Author SHA1 Message Date
Merry
d0e2de6b37 fixup 2022-02-15 00:02:36 +00:00
merry
f5020e991c Reduce line noise 2022-02-14 21:59:58 +00:00
merry
d2d71f93f0 Use index to handle IfThenBlockState 2022-02-14 21:48:28 +00:00
merry
d86dcaa13d Address nits 2022-02-14 21:48:10 +00:00
Merry
4a257bf7a1 Remove inITBlock argument 2022-02-14 21:39:17 +00:00
merry
fbf224e023 fixup! T16: Implement IT 2022-02-13 19:40:53 +00:00
merry
e870d4e089 fixup! T16: Implement Add to SP (immediate) 2022-02-13 19:40:21 +00:00
merry
848ff31a19 fixup! T16: Implement ADD/SUB (SP) 2022-02-13 19:40:05 +00:00
merry
b6078d2c00 T16: Implement IT 2022-02-11 23:08:02 +00:00
merry
09c84d6e91 T16: Implement B (unconditional) 2022-02-11 23:08:02 +00:00
merry
9271abdff0 T16: Implement B (conditional) 2022-02-11 23:08:02 +00:00
merry
06f9a3dc60 T16: Implement SVC 2022-02-11 23:08:02 +00:00
merry
9c16e8695b T16: Implement LDM, STM 2022-02-11 23:08:02 +00:00
merry
108a6886f9 T16: Implement NOP 2022-02-11 23:08:02 +00:00
merry
41eab68113 T16: Implement REV, REV16, REVSH 2022-02-11 23:08:02 +00:00
merry
34290d38e2 T16: Implement PUSH, POP 2022-02-11 23:08:02 +00:00
merry
dabb5f2449 T16: Implement CBZ, CBNZ 2022-02-11 23:08:02 +00:00
merry
2055622c84 T16: Implement SXTH, SXTB, UXTH, UTXB 2022-02-11 23:08:02 +00:00
merry
e11cd2e50a T16: Implement ADD/SUB (SP) 2022-02-11 23:08:02 +00:00
merry
1a2ae16395 T16: Implement Add to SP (immediate) 2022-02-11 23:08:02 +00:00
merry
59e9c3d6b0 T16: Implement ADR 2022-02-11 23:08:02 +00:00
merry
baaf5e126e T16: Implement LDR/STR (SP) 2022-02-11 23:08:02 +00:00
merry
f3e068b94a T16: Implement {LDR,STR}{,B,H} (immediate) 2022-02-11 23:08:02 +00:00
merry
d3272c1498 T16: Implement {LDR,STR}{,H,B,SB,SH} (register) 2022-02-11 23:08:02 +00:00
merry
a9f952ad40 T16: Implement LDR (literal) 2022-02-11 23:08:02 +00:00
merry
d84c2417aa T16: Implement BLX (reg) 2022-02-11 23:08:02 +00:00
merry
2876344cca T16: Implement ADD, CMP, MOV (high reg) 2022-02-11 23:08:02 +00:00
merry
43feb68b11 T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) 2022-02-11 23:08:02 +00:00
merry
284272854b T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) 2022-02-11 23:08:02 +00:00
merry
7a09aea0dc T16: Implement ADDS, SUBS (3-bit immediate) 2022-02-11 23:08:01 +00:00
merry
3d663a1c8c T16: Implement ADDS, SUBS (reg) 2022-02-11 23:08:01 +00:00
merry
15ccdff751 T16: Implement LSL/LSR/ASR (imm) 2022-02-11 23:08:01 +00:00
merry
cb4ccec421 T16: Implement BX 2022-02-11 23:08:01 +00:00
merry
e1bbf8d7b9 OpCodeTables: Improve thumb fast lookup 2022-02-11 23:08:01 +00:00
merry
19c6c1c11c OpCodeTable: Prepare for thumb instructions 2022-02-11 23:08:01 +00:00
merry
08e1e0c985 OpCodeTable: Remove existing thumb instruction implementations 2022-02-11 23:08:01 +00:00
merry
1379f41d5d OpCodeTable: Minor cleanup 2022-02-11 23:08:01 +00:00
merry
5c2e780d40 Decoders: Add InITBlock argument 2022-02-11 23:08:01 +00:00
merry
ce71f9144e
InstEmitMemory32: Literal loads always have word-aligned PC (#3104) 2022-02-11 17:51:03 -03:00
gdkchan
c3c3914ed3
Add a limit on the number of uses a constant may have (#3097) 2022-02-09 17:42:47 -03:00
merry
86b37d0ff7
ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089) 
* ARMeilleure: A32: Implement UHSUB8

* ARMeilleure: A32: Implement SHSUB8
 2022-02-08 10:46:42 +01:00
merry
88d3ffb97c
ARMeilleure: A32: Implement SHADD8 (#3086) 2022-02-06 12:25:45 -03:00
merry
222b1ad7da
ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087) 2022-02-06 02:01:05 +01:00
gdkchan
bd412afb9f
Fix small precision error on CPU reciprocal estimate instructions (#3061) 
* Fix small precision error on CPU reciprocal estimate instructions

* PPTC version bump
 2022-01-29 23:59:34 +01:00
gdkchan
f3bfd799e1
Fix calls passing V128 values on Linux (#3034) 
* Fix calls passing V128 values on Linux

* PPTC version bump
 2022-01-24 11:23:24 +01:00
gdkchan
f0824fde9f
Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 
* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
 2022-01-21 12:47:34 -03:00
sharmander
60f7cba30a
Implement FCVTNS (Scalar GP) (#2953) 
* Implement FCVTNS (Scalar GP)

* Update Ptc Version
 2022-01-19 22:21:44 -03:00
gdkchan
bd215e447d
Fix return type mismatch on 32-bit titles (#3000) 2022-01-16 08:39:43 -03:00
sharmander
e5f7ff1eee
CPU - Implement FCVTMS (Vector) (#2937) 
* Add FCVTMS_V Implementation to Armeilleure

* Fix opcode designation

* Add tests

* Amend Ptc version

* Fix OpCode / Tests

* Create Math.Floor helper method + Update implementation

* Address gdk comments

* Re-address gdk comments

* Update ARMeilleure/Decoders/OpCodeTable.cs

Co-authored-by: gdkchan <gab.dark.100@gmail.com>

* Update Tests to use 2S (4S) and 2D

Co-authored-by: gdkchan <gab.dark.100@gmail.com>
 2022-01-04 16:45:28 -03:00
gdkchan
e24949ca2c
Implement CSDB instruction (#2927) 2021-12-19 11:19:05 -03:00