mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2024-11-16 10:05:25 +00:00
36b9ab0e48
* Remove ARM32 interpreter and add ARM32 support on the translator * Nits. * Rename Cond -> Condition * Align code again * Rename Data to Alu * Enable ARM32 support and handle undefined instructions * Use the IsThumb method to check if its a thumb opcode * Remove another 32-bits check
244 lines
7.9 KiB
C#
244 lines
7.9 KiB
C#
using ChocolArm64.Instructions;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using System;
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using System.Collections.Concurrent;
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using System.Collections.Generic;
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using System.Reflection.Emit;
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namespace ChocolArm64.Decoders
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{
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static class Decoder
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{
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private delegate object OpActivator(Inst inst, long position, int opCode);
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private static ConcurrentDictionary<Type, OpActivator> _opActivators;
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static Decoder()
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{
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_opActivators = new ConcurrentDictionary<Type, OpActivator>();
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}
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public static Block DecodeBasicBlock(MemoryManager memory, long start, ExecutionMode mode)
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{
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Block block = new Block(start);
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FillBlock(memory, mode, block);
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return block;
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}
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public static Block DecodeSubroutine(
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TranslatorCache cache,
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MemoryManager memory,
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long start,
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ExecutionMode mode)
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{
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Dictionary<long, Block> visited = new Dictionary<long, Block>();
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Dictionary<long, Block> visitedEnd = new Dictionary<long, Block>();
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Queue<Block> blocks = new Queue<Block>();
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Block Enqueue(long position)
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{
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if (!visited.TryGetValue(position, out Block output))
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{
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output = new Block(position);
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blocks.Enqueue(output);
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visited.Add(position, output);
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}
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return output;
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}
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Block entry = Enqueue(start);
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while (blocks.Count > 0)
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{
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Block current = blocks.Dequeue();
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FillBlock(memory, mode, current);
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//Set child blocks. "Branch" is the block the branch instruction
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//points to (when taken), "Next" is the block at the next address,
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//executed when the branch is not taken. For Unconditional Branches
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//(except BL/BLR that are sub calls) or end of executable, Next is null.
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if (current.OpCodes.Count > 0)
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{
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bool hasCachedSub = false;
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OpCode64 lastOp = current.GetLastOp();
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if (lastOp is IOpCodeBImm op)
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{
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if (op.Emitter == InstEmit.Bl)
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{
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hasCachedSub = cache.HasSubroutine(op.Imm);
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}
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else
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{
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current.Branch = Enqueue(op.Imm);
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}
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}
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if (!IsUnconditionalBranch(lastOp) || hasCachedSub)
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{
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current.Next = Enqueue(current.EndPosition);
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}
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}
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//If we have on the graph two blocks with the same end position,
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//then we need to split the bigger block and have two small blocks,
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//the end position of the bigger "Current" block should then be == to
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//the position of the "Smaller" block.
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while (visitedEnd.TryGetValue(current.EndPosition, out Block smaller))
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{
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if (current.Position > smaller.Position)
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{
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Block temp = smaller;
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smaller = current;
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current = temp;
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}
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current.EndPosition = smaller.Position;
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current.Next = smaller;
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current.Branch = null;
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current.OpCodes.RemoveRange(
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current.OpCodes.Count - smaller.OpCodes.Count,
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smaller.OpCodes.Count);
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visitedEnd[smaller.EndPosition] = smaller;
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}
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visitedEnd.Add(current.EndPosition, current);
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}
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return entry;
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}
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private static void FillBlock(MemoryManager memory, ExecutionMode mode, Block block)
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{
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long position = block.Position;
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OpCode64 opCode;
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do
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{
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opCode = DecodeOpCode(memory, position, mode);
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block.OpCodes.Add(opCode);
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position += opCode.OpCodeSizeInBytes;
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}
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while (!(IsBranch(opCode) || IsException(opCode)));
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block.EndPosition = position;
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}
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private static bool IsBranch(OpCode64 opCode)
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{
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return opCode is OpCodeBImm64 ||
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opCode is OpCodeBReg64 || IsAarch32Branch(opCode);
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}
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private static bool IsUnconditionalBranch(OpCode64 opCode)
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{
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return opCode is OpCodeBImmAl64 ||
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opCode is OpCodeBReg64 || IsAarch32UnconditionalBranch(opCode);
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}
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private static bool IsAarch32UnconditionalBranch(OpCode64 opCode)
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{
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if (!(opCode is OpCode32 op))
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{
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return false;
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}
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//Note: On ARM32, most instructions have conditional execution,
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//so there's no "Always" (unconditional) branch like on ARM64.
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//We need to check if the condition is "Always" instead.
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return IsAarch32Branch(op) && op.Cond >= Condition.Al;
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}
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private static bool IsAarch32Branch(OpCode64 opCode)
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{
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//Note: On ARM32, most ALU operations can write to R15 (PC),
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//so we must consider such operations as a branch in potential aswell.
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return opCode is IOpCodeBImm32 ||
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opCode is IOpCodeBReg32 ||
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(opCode is IOpCodeAlu32 op && op.Rd == RegisterAlias.Aarch32Pc);
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}
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private static bool IsException(OpCode64 opCode)
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{
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return opCode.Emitter == InstEmit.Brk ||
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opCode.Emitter == InstEmit.Svc ||
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opCode.Emitter == InstEmit.Und;
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}
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public static OpCode64 DecodeOpCode(MemoryManager memory, long position, ExecutionMode mode)
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{
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int opCode = memory.ReadInt32(position);
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Inst inst;
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if (mode == ExecutionMode.Aarch64)
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{
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inst = OpCodeTable.GetInstA64(opCode);
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}
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else
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{
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if (mode == ExecutionMode.Aarch32Arm)
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{
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inst = OpCodeTable.GetInstA32(opCode);
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}
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else /* if (mode == ExecutionMode.Aarch32Thumb) */
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{
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inst = OpCodeTable.GetInstT32(opCode);
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}
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}
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OpCode64 decodedOpCode = new OpCode64(Inst.Undefined, position, opCode);
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if (inst.Type != null)
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{
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decodedOpCode = MakeOpCode(inst.Type, inst, position, opCode);
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}
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return decodedOpCode;
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}
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private static OpCode64 MakeOpCode(Type type, Inst inst, long position, int opCode)
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{
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if (type == null)
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{
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throw new ArgumentNullException(nameof(type));
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}
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OpActivator createInstance = _opActivators.GetOrAdd(type, CacheOpActivator);
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return (OpCode64)createInstance(inst, position, opCode);
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}
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private static OpActivator CacheOpActivator(Type type)
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{
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Type[] argTypes = new Type[] { typeof(Inst), typeof(long), typeof(int) };
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DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes);
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ILGenerator generator = mthd.GetILGenerator();
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generator.Emit(OpCodes.Ldarg_0);
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generator.Emit(OpCodes.Ldarg_1);
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generator.Emit(OpCodes.Ldarg_2);
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generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes));
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generator.Emit(OpCodes.Ret);
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return (OpActivator)mthd.CreateDelegate(typeof(OpActivator));
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}
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}
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} |