mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2025-03-20 09:40:18 +00:00
b323a01738
* Add host tracked memory manager mode * Skipping flush is no longer needed * Formatting + revert unrelated change * LightningJit: Ensure that dest register is saved for load ops that do partial updates * avoid allocations when doing address space lookup Add missing improvement * IsRmwMemory -> IsPartialRegisterUpdateMemory * Ensure we iterate all private allocations in range * PR feedback and potential fixes * Simplified bridges a lot * Skip calling SignalMappingChanged if Guest is true * Late map bridge too * Force address masking for prefetch instructions * Reprotection for bridges * Move partition list validation to separate debug method * Move host tracked related classes to HostTracked folder * New HostTracked namespace * Move host tracked modes to the end of enum to avoid PPTC invalidation --------- Co-authored-by: riperiperi <rhy3756547@hotmail.com>
1167 lines
27 KiB
C#
1167 lines
27 KiB
C#
namespace Ryujinx.Cpu.LightningJit.Arm64
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{
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enum InstName
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{
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Abs,
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AbsAdvsimdS,
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AbsAdvsimdV,
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Adc,
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Adcs,
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AddAddsubExt,
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AddAddsubImm,
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AddAddsubShift,
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AddAdvsimdS,
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AddAdvsimdV,
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Addg,
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AddhnAdvsimd,
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AddpAdvsimdPair,
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AddpAdvsimdVec,
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AddsAddsubExt,
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AddsAddsubImm,
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AddsAddsubShift,
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AddvAdvsimd,
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Adr,
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Adrp,
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AesdAdvsimd,
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AeseAdvsimd,
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AesimcAdvsimd,
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AesmcAdvsimd,
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AndAdvsimd,
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AndLogImm,
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AndLogShift,
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AndsLogImm,
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AndsLogShift,
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Asrv,
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Autda,
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Autdb,
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AutiaGeneral,
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AutiaSystem,
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AutibGeneral,
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AutibSystem,
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Axflag,
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BcaxAdvsimd,
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BcCond,
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BCond,
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BfcvtFloat,
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BfcvtnAdvsimd,
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BfdotAdvsimdElt,
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BfdotAdvsimdVec,
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Bfm,
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BfmlalAdvsimdElt,
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BfmlalAdvsimdVec,
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BfmmlaAdvsimd,
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BicAdvsimdImm,
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BicAdvsimdReg,
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BicLogShift,
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Bics,
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BifAdvsimd,
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BitAdvsimd,
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Bl,
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Blr,
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Blra,
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Br,
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Bra,
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Brk,
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BslAdvsimd,
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Bti,
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BUncond,
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Cas,
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Casb,
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Cash,
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Casp,
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Cbnz,
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Cbz,
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CcmnImm,
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CcmnReg,
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CcmpImm,
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CcmpReg,
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Cfinv,
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Chkfeat,
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Clrbhb,
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Clrex,
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ClsAdvsimd,
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ClsInt,
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ClzAdvsimd,
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ClzInt,
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CmeqAdvsimdRegS,
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CmeqAdvsimdRegV,
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CmeqAdvsimdZeroS,
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CmeqAdvsimdZeroV,
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CmgeAdvsimdRegS,
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CmgeAdvsimdRegV,
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CmgeAdvsimdZeroS,
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CmgeAdvsimdZeroV,
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CmgtAdvsimdRegS,
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CmgtAdvsimdRegV,
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CmgtAdvsimdZeroS,
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CmgtAdvsimdZeroV,
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CmhiAdvsimdS,
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CmhiAdvsimdV,
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CmhsAdvsimdS,
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CmhsAdvsimdV,
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CmleAdvsimdS,
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CmleAdvsimdV,
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CmltAdvsimdS,
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CmltAdvsimdV,
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CmtstAdvsimdS,
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CmtstAdvsimdV,
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Cnt,
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CntAdvsimd,
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Cpyfp,
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Cpyfpn,
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Cpyfprn,
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Cpyfprt,
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Cpyfprtn,
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Cpyfprtrn,
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Cpyfprtwn,
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Cpyfpt,
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Cpyfptn,
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Cpyfptrn,
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Cpyfptwn,
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Cpyfpwn,
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Cpyfpwt,
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Cpyfpwtn,
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Cpyfpwtrn,
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Cpyfpwtwn,
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Cpyp,
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Cpypn,
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Cpyprn,
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Cpyprt,
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Cpyprtn,
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Cpyprtrn,
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Cpyprtwn,
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Cpypt,
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Cpyptn,
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Cpyptrn,
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Cpyptwn,
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Cpypwn,
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Cpypwt,
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Cpypwtn,
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Cpypwtrn,
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Cpypwtwn,
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Crc32,
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Crc32c,
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Csdb,
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Csel,
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Csinc,
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Csinv,
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Csneg,
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Ctz,
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Dcps1,
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Dcps2,
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Dcps3,
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Dgh,
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Dmb,
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Drps,
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DsbDsbMemory,
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DsbDsbNxs,
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DupAdvsimdEltScalarFromElement,
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DupAdvsimdEltVectorFromElement,
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DupAdvsimdGen,
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Eon,
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Eor3Advsimd,
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EorAdvsimd,
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EorLogImm,
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EorLogShift,
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Eret,
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Ereta,
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Esb,
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ExtAdvsimd,
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Extr,
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FabdAdvsimdS,
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FabdAdvsimdSH,
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FabdAdvsimdV,
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FabdAdvsimdVH,
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FabsAdvsimdHalf,
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FabsAdvsimdSingleAndDouble,
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FabsFloat,
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FacgeAdvsimdS,
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FacgeAdvsimdSH,
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FacgeAdvsimdV,
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FacgeAdvsimdVH,
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FacgtAdvsimdS,
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FacgtAdvsimdSH,
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FacgtAdvsimdV,
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FacgtAdvsimdVH,
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FaddAdvsimdHalf,
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FaddAdvsimdSingleAndDouble,
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FaddFloat,
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FaddpAdvsimdPairHalf,
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FaddpAdvsimdPairSingleAndDouble,
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FaddpAdvsimdVecHalf,
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FaddpAdvsimdVecSingleAndDouble,
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FcaddAdvsimdVec,
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FccmpeFloat,
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FccmpFloat,
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FcmeqAdvsimdRegS,
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FcmeqAdvsimdRegSH,
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FcmeqAdvsimdRegV,
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FcmeqAdvsimdRegVH,
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FcmeqAdvsimdZeroS,
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FcmeqAdvsimdZeroSH,
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FcmeqAdvsimdZeroV,
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FcmeqAdvsimdZeroVH,
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FcmgeAdvsimdRegS,
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FcmgeAdvsimdRegSH,
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FcmgeAdvsimdRegV,
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FcmgeAdvsimdRegVH,
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FcmgeAdvsimdZeroS,
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FcmgeAdvsimdZeroSH,
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FcmgeAdvsimdZeroV,
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FcmgeAdvsimdZeroVH,
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FcmgtAdvsimdRegS,
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FcmgtAdvsimdRegSH,
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FcmgtAdvsimdRegV,
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FcmgtAdvsimdRegVH,
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FcmgtAdvsimdZeroS,
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FcmgtAdvsimdZeroSH,
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FcmgtAdvsimdZeroV,
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FcmgtAdvsimdZeroVH,
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FcmlaAdvsimdElt,
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FcmlaAdvsimdVec,
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FcmleAdvsimdS,
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FcmleAdvsimdSH,
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FcmleAdvsimdV,
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FcmleAdvsimdVH,
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FcmltAdvsimdS,
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FcmltAdvsimdSH,
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FcmltAdvsimdV,
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FcmltAdvsimdVH,
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FcmpeFloat,
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FcmpFloat,
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FcselFloat,
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FcvtasAdvsimdS,
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FcvtasAdvsimdSH,
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FcvtasAdvsimdV,
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FcvtasAdvsimdVH,
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FcvtasFloat,
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FcvtauAdvsimdS,
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FcvtauAdvsimdSH,
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FcvtauAdvsimdV,
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FcvtauAdvsimdVH,
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FcvtauFloat,
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FcvtFloat,
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FcvtlAdvsimd,
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FcvtmsAdvsimdS,
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FcvtmsAdvsimdSH,
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FcvtmsAdvsimdV,
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FcvtmsAdvsimdVH,
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FcvtmsFloat,
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FcvtmuAdvsimdS,
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FcvtmuAdvsimdSH,
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FcvtmuAdvsimdV,
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FcvtmuAdvsimdVH,
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FcvtmuFloat,
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FcvtnAdvsimd,
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FcvtnsAdvsimdS,
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FcvtnsAdvsimdSH,
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FcvtnsAdvsimdV,
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FcvtnsAdvsimdVH,
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FcvtnsFloat,
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FcvtnuAdvsimdS,
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FcvtnuAdvsimdSH,
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FcvtnuAdvsimdV,
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FcvtnuAdvsimdVH,
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FcvtnuFloat,
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FcvtpsAdvsimdS,
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FcvtpsAdvsimdSH,
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FcvtpsAdvsimdV,
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FcvtpsAdvsimdVH,
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FcvtpsFloat,
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FcvtpuAdvsimdS,
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FcvtpuAdvsimdSH,
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FcvtpuAdvsimdV,
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FcvtpuAdvsimdVH,
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FcvtpuFloat,
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FcvtxnAdvsimdS,
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FcvtxnAdvsimdV,
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FcvtzsAdvsimdFixS,
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FcvtzsAdvsimdFixV,
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FcvtzsAdvsimdIntS,
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FcvtzsAdvsimdIntSH,
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FcvtzsAdvsimdIntV,
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FcvtzsAdvsimdIntVH,
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FcvtzsFloatFix,
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FcvtzsFloatInt,
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FcvtzuAdvsimdFixS,
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FcvtzuAdvsimdFixV,
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FcvtzuAdvsimdIntS,
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FcvtzuAdvsimdIntSH,
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FcvtzuAdvsimdIntV,
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FcvtzuAdvsimdIntVH,
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FcvtzuFloatFix,
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FcvtzuFloatInt,
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FdivAdvsimdHalf,
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FdivAdvsimdSingleAndDouble,
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FdivFloat,
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Fjcvtzs,
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FmaddFloat,
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FmaxAdvsimdHalf,
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FmaxAdvsimdSingleAndDouble,
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FmaxFloat,
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FmaxnmAdvsimdHalf,
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FmaxnmAdvsimdSingleAndDouble,
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FmaxnmFloat,
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FmaxnmpAdvsimdPairHalf,
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FmaxnmpAdvsimdPairSingleAndDouble,
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FmaxnmpAdvsimdVecHalf,
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FmaxnmpAdvsimdVecSingleAndDouble,
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FmaxnmvAdvsimdHalf,
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FmaxnmvAdvsimdSingleAndDouble,
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FmaxpAdvsimdPairHalf,
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FmaxpAdvsimdPairSingleAndDouble,
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FmaxpAdvsimdVecHalf,
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FmaxpAdvsimdVecSingleAndDouble,
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FmaxvAdvsimdHalf,
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FmaxvAdvsimdSingleAndDouble,
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FminAdvsimdHalf,
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FminAdvsimdSingleAndDouble,
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FminFloat,
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FminnmAdvsimdHalf,
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FminnmAdvsimdSingleAndDouble,
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FminnmFloat,
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FminnmpAdvsimdPairHalf,
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FminnmpAdvsimdPairSingleAndDouble,
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FminnmpAdvsimdVecHalf,
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FminnmpAdvsimdVecSingleAndDouble,
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FminnmvAdvsimdHalf,
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FminnmvAdvsimdSingleAndDouble,
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FminpAdvsimdPairHalf,
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FminpAdvsimdPairSingleAndDouble,
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FminpAdvsimdVecHalf,
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FminpAdvsimdVecSingleAndDouble,
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FminvAdvsimdHalf,
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FminvAdvsimdSingleAndDouble,
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FmlaAdvsimdElt2regElementHalf,
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FmlaAdvsimdElt2regElementSingleAndDouble,
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FmlaAdvsimdElt2regScalarHalf,
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FmlaAdvsimdElt2regScalarSingleAndDouble,
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FmlaAdvsimdVecHalf,
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FmlaAdvsimdVecSingleAndDouble,
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FmlalAdvsimdEltFmlal,
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FmlalAdvsimdEltFmlal2,
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FmlalAdvsimdVecFmlal,
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FmlalAdvsimdVecFmlal2,
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FmlsAdvsimdElt2regElementHalf,
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FmlsAdvsimdElt2regElementSingleAndDouble,
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FmlsAdvsimdElt2regScalarHalf,
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FmlsAdvsimdElt2regScalarSingleAndDouble,
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FmlsAdvsimdVecHalf,
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FmlsAdvsimdVecSingleAndDouble,
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FmlslAdvsimdEltFmlsl,
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FmlslAdvsimdEltFmlsl2,
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FmlslAdvsimdVecFmlsl,
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FmlslAdvsimdVecFmlsl2,
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FmovAdvsimdPerHalf,
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FmovAdvsimdSingleAndDouble,
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FmovFloat,
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FmovFloatGen,
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FmovFloatImm,
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FmsubFloat,
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FmulAdvsimdElt2regElementHalf,
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FmulAdvsimdElt2regElementSingleAndDouble,
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FmulAdvsimdElt2regScalarHalf,
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FmulAdvsimdElt2regScalarSingleAndDouble,
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FmulAdvsimdVecHalf,
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FmulAdvsimdVecSingleAndDouble,
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FmulFloat,
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FmulxAdvsimdElt2regElementHalf,
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FmulxAdvsimdElt2regElementSingleAndDouble,
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FmulxAdvsimdElt2regScalarHalf,
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FmulxAdvsimdElt2regScalarSingleAndDouble,
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FmulxAdvsimdVecS,
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FmulxAdvsimdVecSH,
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FmulxAdvsimdVecV,
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FmulxAdvsimdVecVH,
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FnegAdvsimdHalf,
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FnegAdvsimdSingleAndDouble,
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FnegFloat,
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FnmaddFloat,
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FnmsubFloat,
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FnmulFloat,
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FrecpeAdvsimdS,
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FrecpeAdvsimdSH,
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FrecpeAdvsimdV,
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FrecpeAdvsimdVH,
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FrecpsAdvsimdS,
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FrecpsAdvsimdSH,
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FrecpsAdvsimdV,
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FrecpsAdvsimdVH,
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FrecpxAdvsimdHalf,
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FrecpxAdvsimdSingleAndDouble,
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Frint32xAdvsimd,
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Frint32xFloat,
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Frint32zAdvsimd,
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Frint32zFloat,
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Frint64xAdvsimd,
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Frint64xFloat,
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Frint64zAdvsimd,
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Frint64zFloat,
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FrintaAdvsimdHalf,
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FrintaAdvsimdSingleAndDouble,
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FrintaFloat,
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FrintiAdvsimdHalf,
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FrintiAdvsimdSingleAndDouble,
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FrintiFloat,
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FrintmAdvsimdHalf,
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FrintmAdvsimdSingleAndDouble,
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FrintmFloat,
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FrintnAdvsimdHalf,
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FrintnAdvsimdSingleAndDouble,
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FrintnFloat,
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FrintpAdvsimdHalf,
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FrintpAdvsimdSingleAndDouble,
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FrintpFloat,
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FrintxAdvsimdHalf,
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FrintxAdvsimdSingleAndDouble,
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FrintxFloat,
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FrintzAdvsimdHalf,
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FrintzAdvsimdSingleAndDouble,
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FrintzFloat,
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FrsqrteAdvsimdS,
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FrsqrteAdvsimdSH,
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FrsqrteAdvsimdV,
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FrsqrteAdvsimdVH,
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FrsqrtsAdvsimdS,
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FrsqrtsAdvsimdSH,
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FrsqrtsAdvsimdV,
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FrsqrtsAdvsimdVH,
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FsqrtAdvsimdHalf,
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FsqrtAdvsimdSingleAndDouble,
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FsqrtFloat,
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FsubAdvsimdHalf,
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FsubAdvsimdSingleAndDouble,
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FsubFloat,
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Gcsb,
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Gcsstr,
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Gcssttr,
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Gmi,
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Hint,
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Hlt,
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Hvc,
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InsAdvsimdElt,
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InsAdvsimdGen,
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Irg,
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Isb,
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Ld1AdvsimdMultAsNoPostIndex,
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Ld1AdvsimdMultAsPostIndex,
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Ld1AdvsimdSnglAsNoPostIndex,
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Ld1AdvsimdSnglAsPostIndex,
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Ld1rAdvsimdAsNoPostIndex,
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Ld1rAdvsimdAsPostIndex,
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Ld2AdvsimdMultAsNoPostIndex,
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Ld2AdvsimdMultAsPostIndex,
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Ld2AdvsimdSnglAsNoPostIndex,
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Ld2AdvsimdSnglAsPostIndex,
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Ld2rAdvsimdAsNoPostIndex,
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Ld2rAdvsimdAsPostIndex,
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Ld3AdvsimdMultAsNoPostIndex,
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Ld3AdvsimdMultAsPostIndex,
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Ld3AdvsimdSnglAsNoPostIndex,
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Ld3AdvsimdSnglAsPostIndex,
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Ld3rAdvsimdAsNoPostIndex,
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Ld3rAdvsimdAsPostIndex,
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Ld4AdvsimdMultAsNoPostIndex,
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Ld4AdvsimdMultAsPostIndex,
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Ld4AdvsimdSnglAsNoPostIndex,
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Ld4AdvsimdSnglAsPostIndex,
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Ld4rAdvsimdAsNoPostIndex,
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Ld4rAdvsimdAsPostIndex,
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Ld64b,
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Ldadd,
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Ldaddb,
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Ldaddh,
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Ldap1AdvsimdSngl,
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Ldaprb,
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LdaprBaseRegister,
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Ldaprh,
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LdaprPostIndexed,
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Ldapurb,
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LdapurFpsimd,
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LdapurGen,
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Ldapurh,
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Ldapursb,
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Ldapursh,
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Ldapursw,
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Ldar,
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Ldarb,
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Ldarh,
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Ldaxp,
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Ldaxr,
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Ldaxrb,
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Ldaxrh,
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Ldclr,
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Ldclrb,
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Ldclrh,
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Ldclrp,
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Ldeor,
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Ldeorb,
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Ldeorh,
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Ldg,
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Ldgm,
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Ldiapp,
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Ldlar,
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Ldlarb,
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Ldlarh,
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LdnpFpsimd,
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LdnpGen,
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LdpFpsimdPostIndexed,
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LdpFpsimdPreIndexed,
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LdpFpsimdSignedScaledOffset,
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LdpGenPostIndexed,
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LdpGenPreIndexed,
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LdpGenSignedScaledOffset,
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LdpswPostIndexed,
|
|
LdpswPreIndexed,
|
|
LdpswSignedScaledOffset,
|
|
Ldra,
|
|
LdrbImmPostIndexed,
|
|
LdrbImmPreIndexed,
|
|
LdrbImmUnsignedScaledOffset,
|
|
LdrbReg,
|
|
LdrhImmPostIndexed,
|
|
LdrhImmPreIndexed,
|
|
LdrhImmUnsignedScaledOffset,
|
|
LdrhReg,
|
|
LdrImmFpsimdPostIndexed,
|
|
LdrImmFpsimdPreIndexed,
|
|
LdrImmFpsimdUnsignedScaledOffset,
|
|
LdrImmGenPostIndexed,
|
|
LdrImmGenPreIndexed,
|
|
LdrImmGenUnsignedScaledOffset,
|
|
LdrLitFpsimd,
|
|
LdrLitGen,
|
|
LdrRegFpsimd,
|
|
LdrRegGen,
|
|
LdrsbImmPostIndexed,
|
|
LdrsbImmPreIndexed,
|
|
LdrsbImmUnsignedScaledOffset,
|
|
LdrsbReg,
|
|
LdrshImmPostIndexed,
|
|
LdrshImmPreIndexed,
|
|
LdrshImmUnsignedScaledOffset,
|
|
LdrshReg,
|
|
LdrswImmPostIndexed,
|
|
LdrswImmPreIndexed,
|
|
LdrswImmUnsignedScaledOffset,
|
|
LdrswLit,
|
|
LdrswReg,
|
|
Ldset,
|
|
Ldsetb,
|
|
Ldseth,
|
|
Ldsetp,
|
|
Ldsmax,
|
|
Ldsmaxb,
|
|
Ldsmaxh,
|
|
Ldsmin,
|
|
Ldsminb,
|
|
Ldsminh,
|
|
Ldtr,
|
|
Ldtrb,
|
|
Ldtrh,
|
|
Ldtrsb,
|
|
Ldtrsh,
|
|
Ldtrsw,
|
|
Ldumax,
|
|
Ldumaxb,
|
|
Ldumaxh,
|
|
Ldumin,
|
|
Lduminb,
|
|
Lduminh,
|
|
Ldurb,
|
|
LdurFpsimd,
|
|
LdurGen,
|
|
Ldurh,
|
|
Ldursb,
|
|
Ldursh,
|
|
Ldursw,
|
|
Ldxp,
|
|
Ldxr,
|
|
Ldxrb,
|
|
Ldxrh,
|
|
Lslv,
|
|
Lsrv,
|
|
Madd,
|
|
MlaAdvsimdElt,
|
|
MlaAdvsimdVec,
|
|
MlsAdvsimdElt,
|
|
MlsAdvsimdVec,
|
|
MoviAdvsimd,
|
|
Movk,
|
|
Movn,
|
|
Movz,
|
|
Mrrs,
|
|
Mrs,
|
|
MsrImm,
|
|
Msrr,
|
|
MsrReg,
|
|
Msub,
|
|
MulAdvsimdElt,
|
|
MulAdvsimdVec,
|
|
MvniAdvsimd,
|
|
NegAdvsimdS,
|
|
NegAdvsimdV,
|
|
Nop,
|
|
NotAdvsimd,
|
|
OrnAdvsimd,
|
|
OrnLogShift,
|
|
OrrAdvsimdImm,
|
|
OrrAdvsimdReg,
|
|
OrrLogImm,
|
|
OrrLogShift,
|
|
Pacda,
|
|
Pacdb,
|
|
Pacga,
|
|
PaciaGeneral,
|
|
PaciaSystem,
|
|
PacibGeneral,
|
|
PacibSystem,
|
|
PmulAdvsimd,
|
|
PmullAdvsimd,
|
|
PrfmImm,
|
|
PrfmLit,
|
|
PrfmReg,
|
|
Prfum,
|
|
Psb,
|
|
RaddhnAdvsimd,
|
|
Rax1Advsimd,
|
|
RbitAdvsimd,
|
|
RbitInt,
|
|
Rcwcas,
|
|
Rcwcasp,
|
|
Rcwclr,
|
|
Rcwclrp,
|
|
Rcwscas,
|
|
Rcwscasp,
|
|
Rcwsclr,
|
|
Rcwsclrp,
|
|
Rcwset,
|
|
Rcwsetp,
|
|
Rcwsset,
|
|
Rcwssetp,
|
|
Rcwsswp,
|
|
Rcwsswpp,
|
|
Rcwswp,
|
|
Rcwswpp,
|
|
Ret,
|
|
Reta,
|
|
Rev,
|
|
Rev16Advsimd,
|
|
Rev16Int,
|
|
Rev32Advsimd,
|
|
Rev32Int,
|
|
Rev64Advsimd,
|
|
Rmif,
|
|
Rorv,
|
|
RprfmReg,
|
|
RshrnAdvsimd,
|
|
RsubhnAdvsimd,
|
|
SabaAdvsimd,
|
|
SabalAdvsimd,
|
|
SabdAdvsimd,
|
|
SabdlAdvsimd,
|
|
SadalpAdvsimd,
|
|
SaddlAdvsimd,
|
|
SaddlpAdvsimd,
|
|
SaddlvAdvsimd,
|
|
SaddwAdvsimd,
|
|
Sb,
|
|
Sbc,
|
|
Sbcs,
|
|
Sbfm,
|
|
ScvtfAdvsimdFixS,
|
|
ScvtfAdvsimdFixV,
|
|
ScvtfAdvsimdIntS,
|
|
ScvtfAdvsimdIntSH,
|
|
ScvtfAdvsimdIntV,
|
|
ScvtfAdvsimdIntVH,
|
|
ScvtfFloatFix,
|
|
ScvtfFloatInt,
|
|
Sdiv,
|
|
SdotAdvsimdElt,
|
|
SdotAdvsimdVec,
|
|
Setf,
|
|
Setgp,
|
|
Setgpn,
|
|
Setgpt,
|
|
Setgptn,
|
|
Setp,
|
|
Setpn,
|
|
Setpt,
|
|
Setptn,
|
|
Sev,
|
|
Sevl,
|
|
Sha1cAdvsimd,
|
|
Sha1hAdvsimd,
|
|
Sha1mAdvsimd,
|
|
Sha1pAdvsimd,
|
|
Sha1su0Advsimd,
|
|
Sha1su1Advsimd,
|
|
Sha256h2Advsimd,
|
|
Sha256hAdvsimd,
|
|
Sha256su0Advsimd,
|
|
Sha256su1Advsimd,
|
|
Sha512h2Advsimd,
|
|
Sha512hAdvsimd,
|
|
Sha512su0Advsimd,
|
|
Sha512su1Advsimd,
|
|
ShaddAdvsimd,
|
|
ShlAdvsimdS,
|
|
ShlAdvsimdV,
|
|
ShllAdvsimd,
|
|
ShrnAdvsimd,
|
|
ShsubAdvsimd,
|
|
SliAdvsimdS,
|
|
SliAdvsimdV,
|
|
Sm3partw1Advsimd,
|
|
Sm3partw2Advsimd,
|
|
Sm3ss1Advsimd,
|
|
Sm3tt1aAdvsimd,
|
|
Sm3tt1bAdvsimd,
|
|
Sm3tt2aAdvsimd,
|
|
Sm3tt2bAdvsimd,
|
|
Sm4eAdvsimd,
|
|
Sm4ekeyAdvsimd,
|
|
Smaddl,
|
|
SmaxAdvsimd,
|
|
SmaxImm,
|
|
SmaxpAdvsimd,
|
|
SmaxReg,
|
|
SmaxvAdvsimd,
|
|
Smc,
|
|
SminAdvsimd,
|
|
SminImm,
|
|
SminpAdvsimd,
|
|
SminReg,
|
|
SminvAdvsimd,
|
|
SmlalAdvsimdElt,
|
|
SmlalAdvsimdVec,
|
|
SmlslAdvsimdElt,
|
|
SmlslAdvsimdVec,
|
|
SmmlaAdvsimdVec,
|
|
SmovAdvsimd,
|
|
Smsubl,
|
|
Smulh,
|
|
SmullAdvsimdElt,
|
|
SmullAdvsimdVec,
|
|
SqabsAdvsimdS,
|
|
SqabsAdvsimdV,
|
|
SqaddAdvsimdS,
|
|
SqaddAdvsimdV,
|
|
SqdmlalAdvsimdElt2regElement,
|
|
SqdmlalAdvsimdElt2regScalar,
|
|
SqdmlalAdvsimdVecS,
|
|
SqdmlalAdvsimdVecV,
|
|
SqdmlslAdvsimdElt2regElement,
|
|
SqdmlslAdvsimdElt2regScalar,
|
|
SqdmlslAdvsimdVecS,
|
|
SqdmlslAdvsimdVecV,
|
|
SqdmulhAdvsimdElt2regElement,
|
|
SqdmulhAdvsimdElt2regScalar,
|
|
SqdmulhAdvsimdVecS,
|
|
SqdmulhAdvsimdVecV,
|
|
SqdmullAdvsimdElt2regElement,
|
|
SqdmullAdvsimdElt2regScalar,
|
|
SqdmullAdvsimdVecS,
|
|
SqdmullAdvsimdVecV,
|
|
SqnegAdvsimdS,
|
|
SqnegAdvsimdV,
|
|
SqrdmlahAdvsimdElt2regElement,
|
|
SqrdmlahAdvsimdElt2regScalar,
|
|
SqrdmlahAdvsimdVecS,
|
|
SqrdmlahAdvsimdVecV,
|
|
SqrdmlshAdvsimdElt2regElement,
|
|
SqrdmlshAdvsimdElt2regScalar,
|
|
SqrdmlshAdvsimdVecS,
|
|
SqrdmlshAdvsimdVecV,
|
|
SqrdmulhAdvsimdElt2regElement,
|
|
SqrdmulhAdvsimdElt2regScalar,
|
|
SqrdmulhAdvsimdVecS,
|
|
SqrdmulhAdvsimdVecV,
|
|
SqrshlAdvsimdS,
|
|
SqrshlAdvsimdV,
|
|
SqrshrnAdvsimdS,
|
|
SqrshrnAdvsimdV,
|
|
SqrshrunAdvsimdS,
|
|
SqrshrunAdvsimdV,
|
|
SqshlAdvsimdImmS,
|
|
SqshlAdvsimdImmV,
|
|
SqshlAdvsimdRegS,
|
|
SqshlAdvsimdRegV,
|
|
SqshluAdvsimdS,
|
|
SqshluAdvsimdV,
|
|
SqshrnAdvsimdS,
|
|
SqshrnAdvsimdV,
|
|
SqshrunAdvsimdS,
|
|
SqshrunAdvsimdV,
|
|
SqsubAdvsimdS,
|
|
SqsubAdvsimdV,
|
|
SqxtnAdvsimdS,
|
|
SqxtnAdvsimdV,
|
|
SqxtunAdvsimdS,
|
|
SqxtunAdvsimdV,
|
|
SrhaddAdvsimd,
|
|
SriAdvsimdS,
|
|
SriAdvsimdV,
|
|
SrshlAdvsimdS,
|
|
SrshlAdvsimdV,
|
|
SrshrAdvsimdS,
|
|
SrshrAdvsimdV,
|
|
SrsraAdvsimdS,
|
|
SrsraAdvsimdV,
|
|
SshlAdvsimdS,
|
|
SshlAdvsimdV,
|
|
SshllAdvsimd,
|
|
SshrAdvsimdS,
|
|
SshrAdvsimdV,
|
|
SsraAdvsimdS,
|
|
SsraAdvsimdV,
|
|
SsublAdvsimd,
|
|
SsubwAdvsimd,
|
|
St1AdvsimdMultAsNoPostIndex,
|
|
St1AdvsimdMultAsPostIndex,
|
|
St1AdvsimdSnglAsNoPostIndex,
|
|
St1AdvsimdSnglAsPostIndex,
|
|
St2AdvsimdMultAsNoPostIndex,
|
|
St2AdvsimdMultAsPostIndex,
|
|
St2AdvsimdSnglAsNoPostIndex,
|
|
St2AdvsimdSnglAsPostIndex,
|
|
St2gPostIndexed,
|
|
St2gPreIndexed,
|
|
St2gSignedScaledOffset,
|
|
St3AdvsimdMultAsNoPostIndex,
|
|
St3AdvsimdMultAsPostIndex,
|
|
St3AdvsimdSnglAsNoPostIndex,
|
|
St3AdvsimdSnglAsPostIndex,
|
|
St4AdvsimdMultAsNoPostIndex,
|
|
St4AdvsimdMultAsPostIndex,
|
|
St4AdvsimdSnglAsNoPostIndex,
|
|
St4AdvsimdSnglAsPostIndex,
|
|
St64b,
|
|
St64bv,
|
|
St64bv0,
|
|
Stgm,
|
|
StgPostIndexed,
|
|
StgpPostIndexed,
|
|
StgpPreIndexed,
|
|
StgPreIndexed,
|
|
StgpSignedScaledOffset,
|
|
StgSignedScaledOffset,
|
|
Stilp,
|
|
Stl1AdvsimdSngl,
|
|
Stllr,
|
|
Stllrb,
|
|
Stllrh,
|
|
Stlrb,
|
|
StlrBaseRegister,
|
|
Stlrh,
|
|
StlrPreIndexed,
|
|
Stlurb,
|
|
StlurFpsimd,
|
|
StlurGen,
|
|
Stlurh,
|
|
Stlxp,
|
|
Stlxr,
|
|
Stlxrb,
|
|
Stlxrh,
|
|
StnpFpsimd,
|
|
StnpGen,
|
|
StpFpsimdPostIndexed,
|
|
StpFpsimdPreIndexed,
|
|
StpFpsimdSignedScaledOffset,
|
|
StpGenPostIndexed,
|
|
StpGenPreIndexed,
|
|
StpGenSignedScaledOffset,
|
|
StrbImmPostIndexed,
|
|
StrbImmPreIndexed,
|
|
StrbImmUnsignedScaledOffset,
|
|
StrbReg,
|
|
StrhImmPostIndexed,
|
|
StrhImmPreIndexed,
|
|
StrhImmUnsignedScaledOffset,
|
|
StrhReg,
|
|
StrImmFpsimdPostIndexed,
|
|
StrImmFpsimdPreIndexed,
|
|
StrImmFpsimdUnsignedScaledOffset,
|
|
StrImmGenPostIndexed,
|
|
StrImmGenPreIndexed,
|
|
StrImmGenUnsignedScaledOffset,
|
|
StrRegFpsimd,
|
|
StrRegGen,
|
|
Sttr,
|
|
Sttrb,
|
|
Sttrh,
|
|
Sturb,
|
|
SturFpsimd,
|
|
SturGen,
|
|
Sturh,
|
|
Stxp,
|
|
Stxr,
|
|
Stxrb,
|
|
Stxrh,
|
|
Stz2gPostIndexed,
|
|
Stz2gPreIndexed,
|
|
Stz2gSignedScaledOffset,
|
|
Stzgm,
|
|
StzgPostIndexed,
|
|
StzgPreIndexed,
|
|
StzgSignedScaledOffset,
|
|
SubAddsubExt,
|
|
SubAddsubImm,
|
|
SubAddsubShift,
|
|
SubAdvsimdS,
|
|
SubAdvsimdV,
|
|
Subg,
|
|
SubhnAdvsimd,
|
|
Subp,
|
|
Subps,
|
|
SubsAddsubExt,
|
|
SubsAddsubImm,
|
|
SubsAddsubShift,
|
|
SudotAdvsimdElt,
|
|
SuqaddAdvsimdS,
|
|
SuqaddAdvsimdV,
|
|
Svc,
|
|
Swp,
|
|
Swpb,
|
|
Swph,
|
|
Swpp,
|
|
Sys,
|
|
Sysl,
|
|
Sysp,
|
|
TblAdvsimd,
|
|
Tbnz,
|
|
TbxAdvsimd,
|
|
Tbz,
|
|
Tcancel,
|
|
Tcommit,
|
|
Trn1Advsimd,
|
|
Trn2Advsimd,
|
|
Tsb,
|
|
Tstart,
|
|
Ttest,
|
|
UabaAdvsimd,
|
|
UabalAdvsimd,
|
|
UabdAdvsimd,
|
|
UabdlAdvsimd,
|
|
UadalpAdvsimd,
|
|
UaddlAdvsimd,
|
|
UaddlpAdvsimd,
|
|
UaddlvAdvsimd,
|
|
UaddwAdvsimd,
|
|
Ubfm,
|
|
UcvtfAdvsimdFixS,
|
|
UcvtfAdvsimdFixV,
|
|
UcvtfAdvsimdIntS,
|
|
UcvtfAdvsimdIntSH,
|
|
UcvtfAdvsimdIntV,
|
|
UcvtfAdvsimdIntVH,
|
|
UcvtfFloatFix,
|
|
UcvtfFloatInt,
|
|
UdfPermUndef,
|
|
Udiv,
|
|
UdotAdvsimdElt,
|
|
UdotAdvsimdVec,
|
|
UhaddAdvsimd,
|
|
UhsubAdvsimd,
|
|
Umaddl,
|
|
UmaxAdvsimd,
|
|
UmaxImm,
|
|
UmaxpAdvsimd,
|
|
UmaxReg,
|
|
UmaxvAdvsimd,
|
|
UminAdvsimd,
|
|
UminImm,
|
|
UminpAdvsimd,
|
|
UminReg,
|
|
UminvAdvsimd,
|
|
UmlalAdvsimdElt,
|
|
UmlalAdvsimdVec,
|
|
UmlslAdvsimdElt,
|
|
UmlslAdvsimdVec,
|
|
UmmlaAdvsimdVec,
|
|
UmovAdvsimd,
|
|
Umsubl,
|
|
Umulh,
|
|
UmullAdvsimdElt,
|
|
UmullAdvsimdVec,
|
|
UqaddAdvsimdS,
|
|
UqaddAdvsimdV,
|
|
UqrshlAdvsimdS,
|
|
UqrshlAdvsimdV,
|
|
UqrshrnAdvsimdS,
|
|
UqrshrnAdvsimdV,
|
|
UqshlAdvsimdImmS,
|
|
UqshlAdvsimdImmV,
|
|
UqshlAdvsimdRegS,
|
|
UqshlAdvsimdRegV,
|
|
UqshrnAdvsimdS,
|
|
UqshrnAdvsimdV,
|
|
UqsubAdvsimdS,
|
|
UqsubAdvsimdV,
|
|
UqxtnAdvsimdS,
|
|
UqxtnAdvsimdV,
|
|
UrecpeAdvsimd,
|
|
UrhaddAdvsimd,
|
|
UrshlAdvsimdS,
|
|
UrshlAdvsimdV,
|
|
UrshrAdvsimdS,
|
|
UrshrAdvsimdV,
|
|
UrsqrteAdvsimd,
|
|
UrsraAdvsimdS,
|
|
UrsraAdvsimdV,
|
|
UsdotAdvsimdElt,
|
|
UsdotAdvsimdVec,
|
|
UshlAdvsimdS,
|
|
UshlAdvsimdV,
|
|
UshllAdvsimd,
|
|
UshrAdvsimdS,
|
|
UshrAdvsimdV,
|
|
UsmmlaAdvsimdVec,
|
|
UsqaddAdvsimdS,
|
|
UsqaddAdvsimdV,
|
|
UsraAdvsimdS,
|
|
UsraAdvsimdV,
|
|
UsublAdvsimd,
|
|
UsubwAdvsimd,
|
|
Uzp1Advsimd,
|
|
Uzp2Advsimd,
|
|
Wfe,
|
|
Wfet,
|
|
Wfi,
|
|
Wfit,
|
|
Xaflag,
|
|
XarAdvsimd,
|
|
XpacGeneral,
|
|
XpacSystem,
|
|
XtnAdvsimd,
|
|
Yield,
|
|
Zip1Advsimd,
|
|
Zip2Advsimd,
|
|
}
|
|
|
|
static class InstNameExtensions
|
|
{
|
|
public static bool IsCall(this InstName name)
|
|
{
|
|
return name == InstName.Bl || name == InstName.Blr;
|
|
}
|
|
|
|
public static bool IsControlFlowOrException(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.BUncond:
|
|
case InstName.BCond:
|
|
case InstName.Bl:
|
|
case InstName.Blr:
|
|
case InstName.Br:
|
|
case InstName.Brk:
|
|
case InstName.Cbnz:
|
|
case InstName.Cbz:
|
|
case InstName.Ret:
|
|
case InstName.Tbnz:
|
|
case InstName.Tbz:
|
|
case InstName.Svc:
|
|
case InstName.UdfPermUndef:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public static bool IsException(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.Brk:
|
|
case InstName.Svc:
|
|
case InstName.UdfPermUndef:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public static bool IsSystem(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.Mrs:
|
|
case InstName.MsrImm:
|
|
case InstName.MsrReg:
|
|
return true;
|
|
}
|
|
|
|
return name.IsException();
|
|
}
|
|
|
|
public static bool IsSystemOrCall(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.Bl:
|
|
case InstName.Blr:
|
|
case InstName.Svc:
|
|
case InstName.Mrs:
|
|
case InstName.MsrImm:
|
|
case InstName.MsrReg:
|
|
case InstName.Sysl:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public static bool IsPrivileged(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.Dcps1:
|
|
case InstName.Dcps2:
|
|
case InstName.Dcps3:
|
|
case InstName.Drps:
|
|
case InstName.Eret:
|
|
case InstName.Ereta:
|
|
case InstName.Hvc:
|
|
case InstName.MsrImm:
|
|
case InstName.Smc:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public static bool IsPartialRegisterUpdateMemory(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.Ld1AdvsimdSnglAsNoPostIndex:
|
|
case InstName.Ld1AdvsimdSnglAsPostIndex:
|
|
case InstName.Ld2AdvsimdSnglAsNoPostIndex:
|
|
case InstName.Ld2AdvsimdSnglAsPostIndex:
|
|
case InstName.Ld3AdvsimdSnglAsNoPostIndex:
|
|
case InstName.Ld3AdvsimdSnglAsPostIndex:
|
|
case InstName.Ld4AdvsimdSnglAsNoPostIndex:
|
|
case InstName.Ld4AdvsimdSnglAsPostIndex:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
public static bool IsPrefetchMemory(this InstName name)
|
|
{
|
|
switch (name)
|
|
{
|
|
case InstName.PrfmImm:
|
|
case InstName.PrfmLit:
|
|
case InstName.PrfmReg:
|
|
case InstName.Prfum:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
}
|