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e9848339dd
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Fix new dotnet-format issues after rebase * Address review comments * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Format if-blocks correctly * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Add comments to disabled warnings * Simplify properties and array initialization, Use const when possible, Remove trailing commas * cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * Apply suggestions from code review Co-authored-by: Ac_K <Acoustik666@gmail.com> * First dotnet format pass * Fix naming rule violations * Remove naming rule violation exceptions * Fix comment style * Use targeted new * Remove redundant code * Remove comment alignment * Remove naming rule exceptions * Add trailing commas * Use nameof expression * Reformat to add remaining trailing commas --------- Co-authored-by: Ac_K <Acoustik666@gmail.com>
111 lines
4 KiB
C#
111 lines
4 KiB
C#
#define Misc32
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("Misc32")]
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public sealed class CpuTestMisc32 : CpuTest32
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{
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#if Misc32
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#region "ValueSource (Types)"
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private static IEnumerable<ulong> _1S_F_()
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{
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yield return 0x00000000FF7FFFFFul; // -Max Normal (float.MinValue)
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yield return 0x0000000080800000ul; // -Min Normal
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yield return 0x00000000807FFFFFul; // -Max Subnormal
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yield return 0x0000000080000001ul; // -Min Subnormal (-float.Epsilon)
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yield return 0x000000007F7FFFFFul; // +Max Normal (float.MaxValue)
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yield return 0x0000000000800000ul; // +Min Normal
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yield return 0x00000000007FFFFFul; // +Max Subnormal
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yield return 0x0000000000000001ul; // +Min Subnormal (float.Epsilon)
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if (!_noZeros)
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{
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yield return 0x0000000080000000ul; // -Zero
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yield return 0x0000000000000000ul; // +Zero
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}
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if (!_noInfs)
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{
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yield return 0x00000000FF800000ul; // -Infinity
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yield return 0x000000007F800000ul; // +Infinity
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}
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if (!_noNaNs)
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{
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yield return 0x00000000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
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yield return 0x00000000FFBFFFFFul; // -SNaN (all ones payload)
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yield return 0x000000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
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yield return 0x000000007FBFFFFFul; // +SNaN (all ones payload)
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}
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for (int cnt = 1; cnt <= RndCnt; cnt++)
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{
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ulong grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong rnd1 = GenNormalS();
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ulong rnd2 = GenSubnormalS();
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yield return (grbg << 32) | rnd1;
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yield return (grbg << 32) | rnd2;
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}
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}
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#endregion
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private const int RndCnt = 2;
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private static readonly bool _noZeros = false;
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private static readonly bool _noInfs = false;
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private static readonly bool _noNaNs = false;
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[Test, Pairwise]
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public void Vmsr_Vcmp_Vmrs([ValueSource(nameof(_1S_F_))] ulong a,
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[ValueSource(nameof(_1S_F_))] ulong b,
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[Values] bool mode1,
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[Values] bool mode2,
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[Values] bool mode3)
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{
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V128 v4 = MakeVectorE0(a);
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V128 v5 = MakeVectorE0(b);
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uint r0 = mode1
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? TestContext.CurrentContext.Random.NextUInt(0xf) << 28
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: TestContext.CurrentContext.Random.NextUInt();
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bool v = mode3 && TestContext.CurrentContext.Random.NextBool();
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bool c = mode3 && TestContext.CurrentContext.Random.NextBool();
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bool z = mode3 && TestContext.CurrentContext.Random.NextBool();
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bool n = mode3 && TestContext.CurrentContext.Random.NextBool();
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int fpscr = mode1
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? (int)TestContext.CurrentContext.Random.NextUInt()
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: (int)TestContext.CurrentContext.Random.NextUInt(0xf) << 28;
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SetContext(r0: r0, v4: v4, v5: v5, overflow: v, carry: c, zero: z, negative: n, fpscr: fpscr);
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if (mode1)
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{
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Opcode(0xEEE10A10); // VMSR FPSCR, R0
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}
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Opcode(0xEEB48A4A); // VCMP.F32 S16, S20
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if (mode2)
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{
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Opcode(0xEEF10A10); // VMRS R0, FPSCR
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Opcode(0xE200020F); // AND R0, #0xF0000000 // R0 &= "Fpsr.Nzcv".
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}
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if (mode3)
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{
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Opcode(0xEEF1FA10); // VMRS APSR_NZCV, FPSCR
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}
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Opcode(0xE12FFF1E); // BX LR
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ExecuteOpcodes();
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CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv);
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}
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#endif
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}
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}
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