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add Fmaxp_V & Fminp_V functions

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greggameplayer 2018-07-10 18:48:05 +02:00 committed by GitHub
parent 2b46158c55
commit 364f2c710d
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1 changed files with 87 additions and 0 deletions
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87
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@ -438,6 +438,49 @@ namespace ChocolArm64.Instruction
}
});
}
public static void Fmaxp_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int SizeF = Op.Size & 1;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Elems = Bytes >> SizeF + 2;
int Half = Elems >> 1;
for (int Index = 0; Index < Elems; Index++)
{
int Elem = (Index & (Half - 1)) << 1;
EmitVectorExtractF(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, SizeF);
EmitVectorExtractF(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, SizeF);
if (SizeF == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MaxF));
}
else if (SizeF == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Max));
}
else
{
throw new InvalidOperationException();
}
EmitVectorInsertTmpF(Context, Index, SizeF);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Fmin_S(AILEmitterCtx Context)
{
@ -482,6 +525,50 @@ namespace ChocolArm64.Instruction
}
});
}
public static void Fminp_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int SizeF = Op.Size & 1;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
int Elems = Bytes >> SizeF + 2;
int Half = Elems >> 1;
for (int Index = 0; Index < Elems; Index++)
{
int Elem = (Index & (Half - 1)) << 1;
EmitVectorExtractF(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 0, SizeF);
EmitVectorExtractF(Context, Index < Half ? Op.Rn : Op.Rm, Elem + 1, SizeF);
if (SizeF == 0)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.MinF));
}
else if (SizeF == 1)
{
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.Min));
}
else
{
throw new InvalidOperationException();
}
EmitVectorInsertTmpF(Context, Index, SizeF);
}
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Fmaxnm_S(AILEmitterCtx Context)
{