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Remove inITBlock argument

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This commit is contained in:
Merry 2022-02-14 21:06:24 +00:00 committed by merry
parent 31a6f64353
commit 4a257bf7a1
137 changed files with 405 additions and 409 deletions
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22
ARMeilleure/Decoders/Decoder.cs
View file

@ -195,18 +195,18 @@ namespace ARMeilleure.Decoders
ulong limitAddress)
{
ulong address = block.Address;
int inITBlock = 0;
int itBlockSize = 0;
OpCode opCode;
do
{
if (address >= limitAddress && inITBlock == 0)
if (address >= limitAddress && itBlockSize == 0)
{
break;
}
opCode = DecodeOpCode(memory, address, mode, inITBlock > 0);
opCode = DecodeOpCode(memory, address, mode);
block.OpCodes.Add(opCode);
@ -214,11 +214,11 @@ namespace ARMeilleure.Decoders
if (opCode is OpCodeT16IfThen it)
{
inITBlock = it.IfThenBlockSize;
itBlockSize = it.IfThenBlockSize;
}
else if (inITBlock > 0)
else if (itBlockSize > 0)
{
inITBlock--;
itBlockSize--;
}
}
while (!(IsBranch(opCode) || IsException(opCode)));
@ -325,7 +325,7 @@ namespace ARMeilleure.Decoders
opCode.Instruction.Name == InstName.Und;
}
public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode, bool inITBlock)
public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode)
{
int opCode = memory.Read<int>(address);
@ -351,19 +351,19 @@ namespace ARMeilleure.Decoders
if (makeOp != null)
{
return makeOp(inst, address, opCode, inITBlock);
return makeOp(inst, address, opCode);
}
else
{
if (mode == ExecutionMode.Aarch32Thumb)
{
return new OpCodeT16(inst, address, opCode, inITBlock);
return new OpCodeT16(inst, address, opCode);
}
else
{
return new OpCode(inst, address, opCode, inITBlock);
return new OpCode(inst, address, opCode);
}
}
}
}
}
}

4
ARMeilleure/Decoders/IOpCode32Alu.cs
View file

@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders
int Rd { get; }
int Rn { get; }
bool SetFlags { get; }
bool? SetFlags { get; }
}
}
}

9
ARMeilleure/Decoders/OpCode.cs
View file

@ -14,16 +14,13 @@ namespace ARMeilleure.Decoders
public RegisterSize RegisterSize { get; protected set; }
public bool InITBlock { get; }
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
public static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode(inst, address, opCode, inITBlock);
public OpCode(InstDescriptor inst, ulong address, int opCode, bool inITBlock)
public OpCode(InstDescriptor inst, ulong address, int opCode)
{
Instruction = inst;
Address = address;
RawOpCode = opCode;
InITBlock = inITBlock;
RegisterSize = RegisterSize.Int64;
}
@ -49,4 +46,4 @@ namespace ARMeilleure.Decoders
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
}
}
}
}

6
ARMeilleure/Decoders/OpCode32.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public Condition Cond { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32(inst, address, opCode);
public OpCode32(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
RegisterSize = RegisterSize.Int32;
@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders
return (uint)Address + (uint)OpCodeSizeInBytes * 2;
}
}
}
}

8
ARMeilleure/Decoders/OpCode32Alu.cs
View file

@ -5,11 +5,11 @@ namespace ARMeilleure.Decoders
public int Rd { get; }
public int Rn { get; }
public bool SetFlags { get; }
public bool? SetFlags { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Alu(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
public OpCode32Alu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
SetFlags = ((opCode >> 20) & 1) != 0;
}
}
}
}

4
ARMeilleure/Decoders/OpCode32AluBf.cs
View file

@ -12,9 +12,9 @@
public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluBf(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 12) & 0xf;
Rn = (opCode >> 0) & 0xf;

6
ARMeilleure/Decoders/OpCode32AluImm.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool IsRotated { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm(inst, address, opCode);
public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int value = (opCode >> 0) & 0xff;
int shift = (opCode >> 8) & 0xf;
@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders
IsRotated = shift != 0;
}
}
}
}

4
ARMeilleure/Decoders/OpCode32AluImm16.cs
View file

@ -4,9 +4,9 @@
{
public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluImm16(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluImm16(inst, address, opCode);
public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm12 = opCode & 0xfff;
int imm4 = (opCode >> 16) & 0xf;

6
ARMeilleure/Decoders/OpCode32AluMla.cs
View file

@ -10,11 +10,11 @@
public bool NHigh { get; }
public bool MHigh { get; }
public bool R { get; }
public bool SetFlags { get; }
public bool? SetFlags { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluMla(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 0) & 0xf;
Rm = (opCode >> 8) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluReg.cs
View file

@ -4,9 +4,9 @@
{
public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluReg(inst, address, opCode);
public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
}

6
ARMeilleure/Decoders/OpCode32AluRsImm.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsImm(inst, address, opCode);
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
Immediate = (opCode >> 7) & 0x1f;
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
ShiftType = (ShiftType)((opCode >> 5) & 3);
}
}
}
}

4
ARMeilleure/Decoders/OpCode32AluRsReg.cs
View file

@ -7,9 +7,9 @@
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluRsReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluRsReg(inst, address, opCode);
public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluRsReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
Rs = (opCode >> 8) & 0xf;

6
ARMeilleure/Decoders/OpCode32AluUmull.cs
View file

@ -10,12 +10,12 @@
public bool NHigh { get; }
public bool MHigh { get; }
public bool SetFlags { get; }
public bool? SetFlags { get; }
public DataOp DataOp { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUmull(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
RdLo = (opCode >> 12) & 0xf;
RdHi = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32AluUx.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public int RotateBits => Rotate * 8;
public bool Add => Rn != RegisterAlias.Aarch32Pc;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32AluUx(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUx(inst, address, opCode);
public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rotate = (opCode >> 10) & 0x3;
}

6
ARMeilleure/Decoders/OpCode32BImm.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BImm(inst, address, opCode);
public OpCode32BImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32BImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
uint pc = GetPc();
@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCode32BReg.cs
View file

@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders
{
public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32BReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32BReg(inst, address, opCode);
public OpCode32BReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32BReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = opCode & 0xf;
}
}
}
}

4
ARMeilleure/Decoders/OpCode32Exception.cs
View file

@ -4,9 +4,9 @@
{
public int Id { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Exception(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Exception(inst, address, opCode);
public OpCode32Exception(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Id = opCode & 0xFFFFFF;
}

6
ARMeilleure/Decoders/OpCode32Mem.cs
View file

@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders
public bool IsLoad { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Mem(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mem(inst, address, opCode);
public OpCode32Mem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Mem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 12) & 0xf;
Rn = (opCode >> 16) & 0xf;
@ -36,4 +36,4 @@ namespace ARMeilleure.Decoders
IsLoad = isLoad || inst.Name == InstName.Ldrd;
}
}
}
}

6
ARMeilleure/Decoders/OpCode32MemImm.cs
View file

@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders
{
class OpCode32MemImm : OpCode32Mem
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm(inst, address, opCode);
public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = opCode & 0xfff;
}
}
}
}

6
ARMeilleure/Decoders/OpCode32MemImm8.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCode32MemImm8 : OpCode32Mem
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemImm8(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemImm8(inst, address, opCode);
public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm4L = (opCode >> 0) & 0xf;
int imm4H = (opCode >> 8) & 0xf;
@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
Immediate = imm4L | (imm4H << 4);
}
}
}
}

4
ARMeilleure/Decoders/OpCode32MemLdEx.cs
View file

@ -4,9 +4,9 @@
{
public int Rd { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemLdEx(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemLdEx(inst, address, opCode);
public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0xf;
}

6
ARMeilleure/Decoders/OpCode32MemMult.cs
View file

@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders
public bool IsLoad { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemMult(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemMult(inst, address, opCode);
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 16) & 0xf;
@ -54,4 +54,4 @@ namespace ARMeilleure.Decoders
IsLoad = isLoad;
}
}
}
}

4
ARMeilleure/Decoders/OpCode32MemReg.cs
View file

@ -4,9 +4,9 @@
{
public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemReg(inst, address, opCode);
public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
}

4
ARMeilleure/Decoders/OpCode32MemRsImm.cs
View file

@ -5,9 +5,9 @@
public int Rm { get; }
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemRsImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemRsImm(inst, address, opCode);
public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 0) & 0xf;
Immediate = (opCode >> 7) & 0x1f;

4
ARMeilleure/Decoders/OpCode32MemStEx.cs
View file

@ -4,9 +4,9 @@
{
public int Rd { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MemStEx(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MemStEx(inst, address, opCode);
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 12) & 0xf;
Rt = (opCode >> 0) & 0xf;

4
ARMeilleure/Decoders/OpCode32MsrReg.cs
View file

@ -10,9 +10,9 @@ namespace ARMeilleure.Decoders
public bool Banked { get; }
public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32MsrReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode);
public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32MsrReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
R = ((opCode >> 22) & 1) != 0;
Mask = (opCode >> 16) & 0xf;

6
ARMeilleure/Decoders/OpCode32Sat.cs
View file

@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat(inst, address, opCode);
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Sat(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 0) & 0xf;
Imm5 = (opCode >> 7) & 0x1f;
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
ShiftType = (ShiftType)((opCode >> 5) & 2);
}
}
}
}

6
ARMeilleure/Decoders/OpCode32Sat16.cs
View file

@ -6,13 +6,13 @@ namespace ARMeilleure.Decoders
public int Rd { get; }
public int SatImm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Sat16(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Sat16(inst, address, opCode);
public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Sat16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 0) & 0xf;
Rd = (opCode >> 12) & 0xf;
SatImm = (opCode >> 16) & 0xf;
}
}
}
}

4
ARMeilleure/Decoders/OpCode32Simd.cs
View file

@ -7,9 +7,9 @@
public bool F { get; protected set; }
public bool U { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32Simd(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = (opCode >> 20) & 0x3;
Q = ((opCode >> 6) & 0x1) != 0;

2
ARMeilleure/Decoders/OpCode32SimdBase.cs
View file

@ -47,6 +47,6 @@ namespace ARMeilleure.Decoders
throw new InvalidOperationException();
}
public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}

4
ARMeilleure/Decoders/OpCode32SimdBinary.cs
View file

@ -5,9 +5,9 @@
/// </summary>
class OpCode32SimdBinary : OpCode32SimdReg
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdBinary(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = 3;

4
ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdCmpZ : OpCode32Simd
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCmpZ(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = (opCode >> 18) & 0x3;

4
ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdCvtFI : OpCode32SimdS
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdCvtFI(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Opc = (opCode >> 7) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdDupElem.cs
View file

@ -4,9 +4,9 @@
{
public int Index { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupElem(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
var opc = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdDupGP.cs
View file

@ -7,9 +7,9 @@
public int Rt { get; }
public bool Q { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdDupGP(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8.
if (Size == -1)

4
ARMeilleure/Decoders/OpCode32SimdExt.cs
View file

@ -4,9 +4,9 @@
{
public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdExt(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = (opCode >> 8) & 0xf;
Size = 0;

4
ARMeilleure/Decoders/OpCode32SimdImm.cs
View file

@ -6,9 +6,9 @@
public long Immediate { get; }
public int Elems => GetBytesCount() >> Size;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdImm44.cs
View file

@ -7,9 +7,9 @@
public int Size { get; }
public int Elems { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdImm44(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = (opCode >> 8) & 0x3;

4
ARMeilleure/Decoders/OpCode32SimdLong.cs
View file

@ -4,9 +4,9 @@
{
public bool U { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdLong(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm3h = (opCode >> 19) & 0x7;

4
ARMeilleure/Decoders/OpCode32SimdMemImm.cs
View file

@ -8,9 +8,9 @@
public bool Add { get; }
public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = opCode & 0xff;

4
ARMeilleure/Decoders/OpCode32SimdMemMult.cs
View file

@ -12,9 +12,9 @@
public bool DoubleWidth { get; }
public bool Add { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemMult(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rn = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdMemPair.cs
View file

@ -24,9 +24,9 @@ namespace ARMeilleure.Decoders
public int Regs { get; }
public int Increment { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemPair(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
View file

@ -15,9 +15,9 @@ namespace ARMeilleure.Decoders
public bool Replicate { get; }
public int Increment { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMemSingle(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10;

4
ARMeilleure/Decoders/OpCode32SimdMovGp.cs
View file

@ -11,9 +11,9 @@
public int Opc1 { get; }
public int Opc2 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGp(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
// Which one is used is instruction dependant.
Op = (opCode >> 20) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
View file

@ -9,9 +9,9 @@
public int Rt2 { get; }
public int Op { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpDouble(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
// Which one is used is instruction dependant.
Op = (opCode >> 20) & 0x1;

4
ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
View file

@ -11,9 +11,9 @@
public int Index { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdMovGpElem(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Op = (opCode >> 20) & 0x1;
U = ((opCode >> 23) & 1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdReg.cs
View file

@ -8,9 +8,9 @@
public int In => GetQuadwordSubindex(Vn) << (3 - Size);
public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);

4
ARMeilleure/Decoders/OpCode32SimdRegElem.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdRegElem : OpCode32SimdReg
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElem(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = ((opCode >> 24) & 0x1) != 0;
F = ((opCode >> 8) & 0x1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdRegElemLong : OpCode32SimdRegElem
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegElemLong(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
F = false;

4
ARMeilleure/Decoders/OpCode32SimdRegLong.cs
View file

@ -4,9 +4,9 @@
{
public bool Polynomial { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegLong(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdRegS.cs
View file

@ -4,9 +4,9 @@
{
public int Vn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegS(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
bool single = Size != 3;
if (single)

4
ARMeilleure/Decoders/OpCode32SimdRegWide.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdRegWide : OpCode32SimdReg
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRegWide(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdRev.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdRev : OpCode32SimdCmpZ
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdRev(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
if (Opc + Size >= 3)
{

4
ARMeilleure/Decoders/OpCode32SimdS.cs
View file

@ -8,9 +8,9 @@
public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
public int Size { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdS(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Opc = (opCode >> 15) & 0x3;
Opc2 = (opCode >> 16) & 0x7;

4
ARMeilleure/Decoders/OpCode32SimdSel.cs
View file

@ -4,9 +4,9 @@
{
public OpCode32SimdSelMode Cc { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSel(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
}

4
ARMeilleure/Decoders/OpCode32SimdShImm.cs
View file

@ -4,9 +4,9 @@
{
public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm6 = (opCode >> 16) & 0x3f;
int limm6 = ((opCode >> 1) & 0x40) | imm6;

4
ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
View file

@ -4,9 +4,9 @@
{
public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmLong(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Q = false;
RegisterSize = RegisterSize.Simd64;

4
ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
View file

@ -2,8 +2,8 @@
{
class OpCode32SimdShImmNarrow : OpCode32SimdShImm
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdShImmNarrow(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}

4
ARMeilleure/Decoders/OpCode32SimdSpecial.cs
View file

@ -5,9 +5,9 @@
public int Rt { get; }
public int Sreg { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSpecial(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 12) & 0xf;
Sreg = (opCode >> 16) & 0xf;

4
ARMeilleure/Decoders/OpCode32SimdSqrte.cs
View file

@ -2,9 +2,9 @@
{
class OpCode32SimdSqrte : OpCode32Simd
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdSqrte(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = (opCode >> 18) & 0x1;
F = ((opCode >> 8) & 0x1) != 0;

4
ARMeilleure/Decoders/OpCode32SimdTbl.cs
View file

@ -4,9 +4,9 @@
{
public int Length { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32SimdTbl(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Length = (opCode >> 8) & 3;
Size = 0;

4
ARMeilleure/Decoders/OpCode32System.cs
View file

@ -11,9 +11,9 @@
public int Coproc { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCode32System(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32System(inst, address, opCode);
public OpCode32System(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCode32System(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Opc1 = (opCode >> 21) & 0x7;
CRn = (opCode >> 16) & 0xf;

6
ARMeilleure/Decoders/OpCodeAdr.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAdr(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0x1f;
@ -16,4 +16,4 @@ namespace ARMeilleure.Decoders
Immediate |= ((long)opCode >> 29) & 3;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeAlu.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public DataOp DataOp { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAlu(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAlu(inst, address, opCode);
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders
: RegisterSize.Int32;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeAluBinary.cs
View file

@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders
{
public int Rm { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluBinary(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluBinary(inst, address, opCode);
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAluBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 16) & 0x1f;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeAluImm.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
{
public long Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluImm(inst, address, opCode);
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
if (DataOp == DataOp.Arithmetic)
{
@ -37,4 +37,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCodeAluRs.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRs(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRs(inst, address, opCode);
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAluRs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int shift = (opCode >> 10) & 0x3f;
@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders
ShiftType = (ShiftType)((opCode >> 22) & 0x3);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeAluRx.cs
View file

@ -7,13 +7,13 @@ namespace ARMeilleure.Decoders
public IntType IntType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeAluRx(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAluRx(inst, address, opCode);
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBImm.cs
View file

@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders
{
public long Immediate { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImm(inst, address, opCode);
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}
}

6
ARMeilleure/Decoders/OpCodeBImmAl.cs
View file

@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders
{
class OpCodeBImmAl : OpCodeBImm
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmAl(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmAl(inst, address, opCode);
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBImmAl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBImmCmp.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public int Rt { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCmp(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCmp(inst, address, opCode);
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
: RegisterSize.Int32;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBImmCond.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmCond(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmCond(inst, address, opCode);
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBImmCond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int o0 = (opCode >> 4) & 1;
@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBImmTest.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int Rt { get; }
public int Bit { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBImmTest(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBImmTest(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
Bit |= (opCode >> 26) & 0x20;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBReg.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public int Rn { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBReg(inst, address, opCode);
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int op4 = (opCode >> 0) & 0x1f;
int op2 = (opCode >> 16) & 0x1f;
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
Rn = (opCode >> 5) & 0x1f;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeBfm.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Pos { get; }
public int Shift { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeBfm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeBfm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
var bm = DecoderHelper.DecodeBitMask(opCode, false);
@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders
Shift = bm.Shift;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeCcmp.cs
View file

@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmp(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmp(inst, address, opCode);
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeCcmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int o3 = (opCode >> 4) & 1;
@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders
Rd = RegisterAlias.Zr;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeCcmpImm.cs
View file

@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders
{
public long Immediate => RmImm;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpImm(inst, address, opCode);
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}
}

6
ARMeilleure/Decoders/OpCodeCcmpReg.cs
View file

@ -8,8 +8,8 @@ namespace ARMeilleure.Decoders
public ShiftType ShiftType => ShiftType.Lsl;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCcmpReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCcmpReg(inst, address, opCode);
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock) { }
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
}
}
}

6
ARMeilleure/Decoders/OpCodeCsel.cs
View file

@ -6,12 +6,12 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeCsel(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeCsel(inst, address, opCode);
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rm = (opCode >> 16) & 0x1f;
Cond = (Condition)((opCode >> 12) & 0xf);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeException.cs
View file

@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders
{
public int Id { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeException(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeException(inst, address, opCode);
public OpCodeException(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeException(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Id = (opCode >> 5) & 0xffff;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMem.cs
View file

@ -7,13 +7,13 @@ namespace ARMeilleure.Decoders
public int Size { get; protected set; }
public bool Extend64 { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMem(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
public OpCodeMem(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
Size = (opCode >> 30) & 0x3;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMemEx.cs
View file

@ -5,12 +5,12 @@ namespace ARMeilleure.Decoders
public int Rt2 { get; }
public int Rs { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemEx(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
Rs = (opCode >> 16) & 0x1f;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMemImm.cs
View file

@ -16,9 +16,9 @@ namespace ARMeilleure.Decoders
Unsigned
}
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Extend64 = ((opCode >> 22) & 3) == 2;
WBack = ((opCode >> 24) & 1) == 0;
@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMemLit.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool Signed { get; }
public bool Prefetch { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemLit(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = opCode & 0x1f;
@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMemPair.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public int Rt2 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemPair(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemPair(inst, address, opCode);
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt2 = (opCode >> 10) & 0x1f;
WBack = ((opCode >> 23) & 0x1) != 0;
@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders
Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMemReg.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public IntType IntType { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMemReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemReg(inst, address, opCode);
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7);
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
Extend64 = ((opCode >> 22) & 0x3) == 2;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMov.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public int Bit { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMov(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMov(inst, address, opCode);
public OpCodeMov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int p1 = (opCode >> 22) & 1;
int sf = (opCode >> 31) & 1;
@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders
: RegisterSize.Int32;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeMul.cs
View file

@ -5,12 +5,12 @@ namespace ARMeilleure.Decoders
public int Rm { get; }
public int Ra { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeMul(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMul(inst, address, opCode);
public OpCodeMul(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeMul(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Ra = (opCode >> 10) & 0x1f;
Rm = (opCode >> 16) & 0x1f;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimd.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Opc { get; }
public int Size { get; protected set; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimd(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f;
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
: RegisterSize.Simd64;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdCvt.cs
View file

@ -4,9 +4,9 @@ namespace ARMeilleure.Decoders
{
public int FBits { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdCvt(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdCvt(inst, address, opCode);
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int scale = (opCode >> 10) & 0x3f;
int sf = (opCode >> 31) & 0x1;
@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders
: RegisterSize.Int32;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdExt.cs
View file

@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders
{
public int Imm4 { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdExt(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdExt(inst, address, opCode);
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Imm4 = (opCode >> 11) & 0xf;
}
}
}
}

4
ARMeilleure/Decoders/OpCodeSimdFcond.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public Condition Cond { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFcond(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFcond(inst, address, opCode);
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Nzcv = (opCode >> 0) & 0xf;
Cond = (Condition)((opCode >> 12) & 0xf);

6
ARMeilleure/Decoders/OpCodeSimdFmov.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; }
public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdFmov(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdFmov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int type = (opCode >> 22) & 0x3;
@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdImm.cs
View file

@ -6,9 +6,9 @@ namespace ARMeilleure.Decoders
public long Immediate { get; }
public int Size { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = opCode & 0x1f;
@ -104,4 +104,4 @@ namespace ARMeilleure.Decoders
}
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdIns.cs
View file

@ -5,9 +5,9 @@ namespace ARMeilleure.Decoders
public int SrcIndex { get; }
public int DstIndex { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdIns(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdIns(inst, address, opCode);
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdIns(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int imm4 = (opCode >> 11) & 0xf;
int imm5 = (opCode >> 16) & 0x1f;
@ -33,4 +33,4 @@ namespace ARMeilleure.Decoders
DstIndex = imm5 >> (Size + 1);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdMemImm.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemImm(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemImm(inst, address, opCode);
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size |= (opCode >> 21) & 4;
@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders
Extend64 = false;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdMemLit.cs
View file

@ -8,9 +8,9 @@ namespace ARMeilleure.Decoders
public bool Signed => false;
public bool Prefetch => false;
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemLit(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdMemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int opc = (opCode >> 30) & 3;
@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders
Size = opc + 2;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdMemMs.cs
View file

@ -7,9 +7,9 @@ namespace ARMeilleure.Decoders
public int Elems { get; }
public bool WBack { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemMs(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdMemMs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
switch ((opCode >> 12) & 0xf)
{
@ -45,4 +45,4 @@ namespace ARMeilleure.Decoders
Elems = (GetBitsCount() >> 3) >> Size;
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdMemPair.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemPair(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemPair(inst, address, opCode);
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size = ((opCode >> 30) & 3) + 2;
@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders
DecodeImm(opCode);
}
}
}
}

6
ARMeilleure/Decoders/OpCodeSimdMemReg.cs
View file

@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
{
class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeSimdMemReg(inst, address, opCode, inITBlock);
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemReg(inst, address, opCode);
public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
public OpCodeSimdMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Size |= (opCode >> 21) & 4;
@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders
Extend64 = false;
}
}
}
}

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