Disable all CPU tests

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TSR Berry 2023-07-08 20:36:40 +02:00
parent 7b178da1b2
commit 65c20a5360
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46 changed files with 152 additions and 223 deletions

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@ -1,11 +1,10 @@
#define Alu
// #define Alu
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Alu")]
[Collection("Alu")]
public sealed class CpuTestAlu : CpuTest
{
#if Alu

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@ -1,10 +1,10 @@
#define Alu32
// #define Alu32
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Alu32")]
[Collection("Alu32")]
public sealed class CpuTestAlu32 : CpuTest32
{
#if Alu32

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@ -1,11 +1,10 @@
#define AluBinary
// #define AluBinary
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluBinary")]
[Collection("AluBinary")]
public sealed class CpuTestAluBinary : CpuTest
{
#if AluBinary

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@ -1,12 +1,11 @@
#define AluBinary32
// #define AluBinary32
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluBinary32")]
[Collection("AluBinary32")]
public sealed class CpuTestAluBinary32 : CpuTest32
{
#if AluBinary32

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@ -1,10 +1,10 @@
#define AluImm
// #define AluImm
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluImm")]
[Collection("AluImm")]
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm

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@ -1,10 +1,10 @@
#define AluRs32
// #define AluRs32
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluImm32")]
[Collection("AluImm32")]
public sealed class CpuTestAluImm32 : CpuTest32
{
#if AluRs32

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@ -1,10 +1,10 @@
#define AluRs
// #define AluRs
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluRs")]
[Collection("AluRs")]
public sealed class CpuTestAluRs : CpuTest
{
#if AluRs

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@ -1,10 +1,10 @@
#define AluRs32
// #define AluRs32
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluRs32")]
[Collection("AluRs32")]
public sealed class CpuTestAluRs32 : CpuTest32
{
#if AluRs32

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@ -1,10 +1,10 @@
#define AluRx
// #define AluRx
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("AluRx")]
[Collection("AluRx")]
public sealed class CpuTestAluRx : CpuTest
{
#if AluRx

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@ -1,11 +1,10 @@
#define Bf32
// #define Bf32
using NUnit.Framework;
using System;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Bf32")]
[Collection("Bf32")]
public sealed class CpuTestBf32 : CpuTest32
{
#if Bf32

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@ -1,10 +1,10 @@
#define Bfm
// #define Bfm
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Bfm")]
[Collection("Bfm")]
public sealed class CpuTestBfm : CpuTest
{
#if Bfm

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@ -1,10 +1,10 @@
#define CcmpImm
// #define CcmpImm
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("CcmpImm")]
[Collection("CcmpImm")]
public sealed class CpuTestCcmpImm : CpuTest
{
#if CcmpImm

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@ -1,10 +1,10 @@
#define CcmpReg
// #define CcmpReg
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("CcmpReg")]
[Collection("CcmpReg")]
public sealed class CpuTestCcmpReg : CpuTest
{
#if CcmpReg

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@ -1,10 +1,10 @@
#define Csel
// #define Csel
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Csel")]
[Collection("Csel")]
public sealed class CpuTestCsel : CpuTest
{
#if Csel

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@ -1,13 +1,10 @@
#define Misc
// #define Misc
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Misc")]
[Collection("Misc")]
public sealed class CpuTestMisc : CpuTest
{
#if Misc

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@ -1,12 +1,10 @@
#define Misc32
// #define Misc32
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Misc32")]
[Collection("Misc32")]
public sealed class CpuTestMisc32 : CpuTest32
{
#if Misc32

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@ -1,10 +1,10 @@
#define Mov
// #define Mov
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Mov")]
[Collection("Mov")]
public sealed class CpuTestMov : CpuTest
{
#if Mov

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@ -1,10 +1,10 @@
#define Mul
// #define Mul
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Mul")]
[Collection("Mul")]
public sealed class CpuTestMul : CpuTest
{
#if Mul

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@ -1,10 +1,10 @@
#define Mul32
// #define Mul32
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Mul32")]
[Collection("Mul32")]
public sealed class CpuTestMul32 : CpuTest32
{
#if Mul32

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@ -1,13 +1,10 @@
#define Simd
// #define Simd
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Simd")]
[Collection("Simd")]
public sealed class CpuTestSimd : CpuTest
{
#if Simd

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@ -1,12 +1,10 @@
#define Simd32
// #define Simd32
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Simd32")]
[Collection("Simd32")]
public sealed class CpuTestSimd32 : CpuTest32
{
#if Simd32

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@ -1,12 +1,12 @@
// #define SimdCrypto
// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
using ARMeilleure.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdCrypto : CpuTest
{
#if SimdCrypto
[Test, Description("AESD <Vd>.16B, <Vn>.16B")]
public void Aesd_V([Values(0u)] uint rd,
[Values(1u)] uint rn,
@ -140,5 +140,6 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
#endif
}
}

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@ -1,12 +1,12 @@
// #define SimdCrypto32
// https://www.intel.com/content/dam/doc/white-paper/advanced-encryption-standard-new-instructions-set-paper.pdf
using ARMeilleure.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdCrypto32 : CpuTest32
{
#if SimdCrypto32
[Test, Description("AESD.8 <Qd>, <Qm>")]
public void Aesd_V([Values(0u)] uint rd,
[Values(2u)] uint rm,
@ -150,5 +150,6 @@ namespace Ryujinx.Tests.Cpu
// Unicorn does not yet support crypto instructions in A32.
// CompareAgainstUnicorn();
}
#endif
}
}

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@ -1,13 +1,10 @@
#define SimdCvt
// #define SimdCvt
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdCvt")]
[Collection("SimdCvt")]
public sealed class CpuTestSimdCvt : CpuTest
{
#if SimdCvt

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@ -1,13 +1,10 @@
#define SimdCvt32
// #define SimdCvt32
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdCvt32")]
[Collection("SimdCvt32")]
public sealed class CpuTestSimdCvt32 : CpuTest32
{
#if SimdCvt32

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@ -1,11 +1,10 @@
#define SimdExt
// #define SimdExt
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdExt")]
[Collection("SimdExt")]
public sealed class CpuTestSimdExt : CpuTest
{
#if SimdExt

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@ -1,12 +1,10 @@
#define SimdFcond
// #define SimdFcond
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdFcond")]
[Collection("SimdFcond")]
public sealed class CpuTestSimdFcond : CpuTest
{
#if SimdFcond

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@ -1,11 +1,10 @@
#define SimdFmov
// #define SimdFmov
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdFmov")]
[Collection("SimdFmov")]
public sealed class CpuTestSimdFmov : CpuTest
{
#if SimdFmov

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@ -1,12 +1,10 @@
#define SimdImm
// #define SimdImm
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdImm")]
[Collection("SimdImm")]
public sealed class CpuTestSimdImm : CpuTest
{
#if SimdImm

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@ -1,11 +1,10 @@
#define SimdIns
// #define SimdIns
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdIns")]
[Collection("SimdIns")]
public sealed class CpuTestSimdIns : CpuTest
{
#if SimdIns

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@ -1,11 +1,10 @@
#define SimdLogical32
// #define SimdLogical32
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdLogical32")]
[Collection("SimdLogical32")]
public sealed class CpuTestSimdLogical32 : CpuTest32
{
#if SimdLogical32

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@ -1,13 +1,10 @@
#define SimdMemory32
// #define SimdMemory32
using ARMeilleure.State;
using NUnit.Framework;
using Ryujinx.Memory;
using System;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdMemory32")]
[Collection("SimdMemory32")]
public sealed class CpuTestSimdMemory32 : CpuTest32
{
private static readonly uint _testOffset = DataBaseAddress + 0x500;

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@ -1,11 +1,10 @@
#define SimdMov32
// #define SimdMov32
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdMov32")]
[Collection("SimdMov32")]
public sealed class CpuTestSimdMov32 : CpuTest32
{
#if SimdMov32

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@ -1,12 +1,10 @@
#define SimdReg
// #define SimdReg
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdReg")]
[Collection("SimdReg")]
public sealed class CpuTestSimdReg : CpuTest
{
#if SimdReg

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@ -1,13 +1,10 @@
#define SimdReg32
// #define SimdReg32
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using System.Runtime.InteropServices;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdReg32")]
[Collection("SimdReg32")]
public sealed class CpuTestSimdReg32 : CpuTest32
{
#if SimdReg32
@ -908,44 +905,6 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void Vp_Add_Long_Accumulate([Values(0u, 2u, 4u, 8u)] uint rd,
[Values(0u, 2u, 4u, 8u)] uint rm,
[Values(0u, 1u, 2u)] uint size,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool q,
[Values] bool unsigned)
{
uint opcode = 0xF3B00600; // VPADAL.S8 D0, Q0
if (q)
{
opcode |= 1 << 6;
rm <<= 1;
rd <<= 1;
}
if (unsigned)
{
opcode |= 1 << 7;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= size << 18;
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
#endif
}
}

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@ -1,11 +1,10 @@
#define SimdRegElem
// #define SimdRegElem
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdRegElem")]
[Collection("SimdRegElem")]
public sealed class CpuTestSimdRegElem : CpuTest
{
#if SimdRegElem

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@ -1,11 +1,10 @@
#define SimdRegElem32
// #define SimdRegElem32
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdRegElem32")]
[Collection("SimdRegElem32")]
public sealed class CpuTestSimdRegElem32 : CpuTest32
{
#if SimdRegElem32

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@ -1,12 +1,10 @@
#define SimdRegElemF
// #define SimdRegElemF
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdRegElemF")]
[Collection("SimdRegElemF")]
public sealed class CpuTestSimdRegElemF : CpuTest
{
#if SimdRegElemF

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@ -1,13 +1,10 @@
#define SimdShImm
// #define SimdShImm
using ARMeilleure.State;
using NUnit.Framework;
using System;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdShImm")]
[Collection("SimdShImm")]
public sealed class CpuTestSimdShImm : CpuTest
{
#if SimdShImm

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@ -1,11 +1,10 @@
#define SimdShImm32
// #define SimdShImm32
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdShImm32")]
[Collection("SimdShImm32")]
public sealed class CpuTestSimdShImm32 : CpuTest32
{
#if SimdShImm32

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@ -1,12 +1,10 @@
#define SimdTbl
// #define SimdTbl
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdTbl")]
[Collection("SimdTbl")]
public sealed class CpuTestSimdTbl : CpuTest
{
#if SimdTbl

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@ -1,12 +1,10 @@
#define System
// #define System
using ARMeilleure.State;
using NUnit.Framework;
using System.Collections.Generic;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("System")]
[Collection("System")]
public sealed class CpuTestSystem : CpuTest
{
#if System

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@ -1,10 +1,13 @@
using NUnit.Framework;
// #define T32Alu
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("T32Alu")]
[Collection("T32Alu")]
public sealed class CpuTestT32Alu : CpuTest32
{
#if T32Alu
[Test]
public void TestT32AluRsImm([ValueSource(nameof(RsImmTestCases))] PrecomputedThumbTestCase test)
{
@ -1010,5 +1013,6 @@ namespace Ryujinx.Tests.Cpu
FinalRegs = new uint[] { 0x2bb00694, 0x1c56a4c0, 0xc5cc4a3e, 0xc627c1ab, 0xe0cc0e5c, 0x1f3d71a4, 0x897d57b8, 0x0d4a7208, 0x433b7b88, 0xaaf24fd6, 0x2438f5f8, 0x9875e64a, 0xda475f22, 0x66d5e2e7, 0x00000001, 0x700001f0 },
},
};
#endif
}
}

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@ -1,11 +1,14 @@
// #define T32Flow
using ARMeilleure.State;
using NUnit.Framework;
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("T32Flow")]
[Collection("T32Flow")]
public sealed class CpuTestT32Flow : CpuTest32
{
#if T32Flow
[Test]
public void TestT32B1()
{
@ -163,5 +166,6 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x7));
Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
}
#endif
}
}

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@ -1,11 +1,13 @@
using NUnit.Framework;
using System;
// #define T32Mem
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("T32Mem")]
[Collection("T32Mem")]
public sealed class CpuTestT32Mem : CpuTest32
{
#if T32Mem
[Test]
public void TestT32MemImm([ValueSource(nameof(ImmTestCases))] PrecomputedMemoryThumbTestCase test)
{
@ -517,5 +519,6 @@ namespace Ryujinx.Tests.Cpu
MemoryDelta = Array.Empty<(ulong Address, ushort Value)>(),
},
};
#endif
}
}

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@ -1,11 +1,13 @@
using ARMeilleure.State;
using NUnit.Framework;
// #define Thumb
using Xunit;
namespace Ryujinx.Tests.Cpu
{
[Category("Thumb")]
[Collection("Thumb")]
public sealed class CpuTestThumb : CpuTest32
{
#if Thumb
private const int RndCnt = 2;
public static uint RotateRight(uint value, int count)
@ -880,5 +882,6 @@ namespace Ryujinx.Tests.Cpu
FinalRegs = new uint[] { 0x000019d4, 0x00000000, 0x00001828, 0x7d000000, 0x977f681b, 0x0000182e, 0x00007d12, 0x00000067, 0x77b1c835, 0x00004100, 0x000010c8, 0x0000000e, 0x79708dab, 0x977f655b, 0x00000000, 0x200001d0 },
},
};
#endif
}
}