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T16: Implement ADDS, SUBS (3-bit immediate)

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merry 2022-02-10 19:59:17 +00:00
parent 3d663a1c8c
commit 7a09aea0dc
6 changed files with 61 additions and 2 deletions
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9
ARMeilleure/Decoders/IOpCode32AluImm.cs Normal file
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@ -0,0 +1,9 @@
namespace ARMeilleure.Decoders
{
interface IOpCode32AluImm : IOpCode32Alu
{
int Immediate { get; }
bool IsRotated { get; }
}
}

2
ARMeilleure/Decoders/OpCode32AluImm.cs
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@ -2,7 +2,7 @@ using ARMeilleure.Common;
namespace ARMeilleure.Decoders namespace ARMeilleure.Decoders
{ {
class OpCode32AluImm : OpCode32Alu class OpCode32AluImm : OpCode32Alu, IOpCode32AluImm
{ {
public int Immediate { get; } public int Immediate { get; }

26
ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs Normal file
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@ -0,0 +1,26 @@
namespace ARMeilleure.Decoders
{
class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
{
public int Rd { get; }
public int Rn { get; }
public bool SetFlags { get; }
public int Immediate { get; }
public bool IsRotated { get; }
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubImm3(inst, address, opCode, inITBlock);
public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
{
Rd = (opCode >> 0) & 0x7;
Rn = (opCode >> 3) & 0x7;
Immediate = (opCode >> 6) & 0x7;
IsRotated = false;
SetFlags = !inITBlock;
}
}
}

2
ARMeilleure/Decoders/OpCodeTable.cs
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@ -977,6 +977,8 @@ namespace ARMeilleure.Decoders
SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create); SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create);
SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create); SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create);
SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create); SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create);
SetT16("0001110xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubImm3.Create);
SetT16("0001111xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubImm3.Create);
SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create); SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
#endregion #endregion

2
ARMeilleure/Instructions/InstEmitAluHelper.cs
View file

@ -183,7 +183,7 @@ namespace ARMeilleure.Instructions
switch (context.CurrOp) switch (context.CurrOp)
{ {
// ARM32. // ARM32.
case OpCode32AluImm op: case IOpCode32AluImm op:
{ {
if (op.SetFlags && op.IsRotated) if (op.SetFlags && op.IsRotated)
{ {

22
Ryujinx.Tests/Cpu/CpuTestThumb.cs
View file

@ -55,5 +55,27 @@ namespace Ryujinx.Tests.Cpu
break; break;
} }
} }
[Test, Pairwise]
public void AddSubImm3([Range(0u, 1u)] uint op, [Range(0u, 7u)] uint imm, [Random(RndCnt)] uint w1)
{
uint opcode = 0x1c00; // ADDS <Rd>, <Rn>, #<imm3>
uint rd = 0;
uint rn = 1;
opcode |= ((rd & 7) << 0) | ((rn & 7) << 3) | ((imm & 7) << 6) | ((op & 1) << 9);
SingleThumbOpcode((ushort)opcode, r1: w1, runUnicorn: false);
switch (op)
{
case 0:
Assert.That(GetContext().GetX(0), Is.EqualTo((w1 + imm) & 0xffffffffu));
break;
case 1:
Assert.That(GetContext().GetX(0), Is.EqualTo((w1 - imm) & 0xffffffffu));
break;
}
}
} }
} }