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T16: Implement ADDS, SUBS (3-bit immediate)
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commit
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6 changed files with 61 additions and 2 deletions
9
ARMeilleure/Decoders/IOpCode32AluImm.cs
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ARMeilleure/Decoders/IOpCode32AluImm.cs
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@ -0,0 +1,9 @@
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namespace ARMeilleure.Decoders
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{
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interface IOpCode32AluImm : IOpCode32Alu
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{
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int Immediate { get; }
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bool IsRotated { get; }
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}
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}
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@ -2,7 +2,7 @@ using ARMeilleure.Common;
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namespace ARMeilleure.Decoders
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namespace ARMeilleure.Decoders
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{
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{
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class OpCode32AluImm : OpCode32Alu
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class OpCode32AluImm : OpCode32Alu, IOpCode32AluImm
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{
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{
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public int Immediate { get; }
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public int Immediate { get; }
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26
ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
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ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
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@ -0,0 +1,26 @@
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namespace ARMeilleure.Decoders
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{
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class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
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{
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public int Rd { get; }
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public int Rn { get; }
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public bool SetFlags { get; }
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public int Immediate { get; }
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public bool IsRotated { get; }
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public static new OpCode Create(InstDescriptor inst, ulong address, int opCode, bool inITBlock) => new OpCodeT16AddSubImm3(inst, address, opCode, inITBlock);
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public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode, bool inITBlock) : base(inst, address, opCode, inITBlock)
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{
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Rd = (opCode >> 0) & 0x7;
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Rn = (opCode >> 3) & 0x7;
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Immediate = (opCode >> 6) & 0x7;
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IsRotated = false;
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SetFlags = !inITBlock;
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}
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}
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}
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@ -977,6 +977,8 @@ namespace ARMeilleure.Decoders
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SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create);
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SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create);
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SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create);
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SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create);
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SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create);
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SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create);
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SetT16("0001110xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubImm3.Create);
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SetT16("0001111xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubImm3.Create);
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SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
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SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
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#endregion
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#endregion
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@ -183,7 +183,7 @@ namespace ARMeilleure.Instructions
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switch (context.CurrOp)
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switch (context.CurrOp)
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{
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{
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// ARM32.
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// ARM32.
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case OpCode32AluImm op:
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case IOpCode32AluImm op:
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{
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{
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if (op.SetFlags && op.IsRotated)
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if (op.SetFlags && op.IsRotated)
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{
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{
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@ -55,5 +55,27 @@ namespace Ryujinx.Tests.Cpu
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break;
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break;
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}
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}
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}
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}
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[Test, Pairwise]
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public void AddSubImm3([Range(0u, 1u)] uint op, [Range(0u, 7u)] uint imm, [Random(RndCnt)] uint w1)
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{
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uint opcode = 0x1c00; // ADDS <Rd>, <Rn>, #<imm3>
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uint rd = 0;
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uint rn = 1;
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opcode |= ((rd & 7) << 0) | ((rn & 7) << 3) | ((imm & 7) << 6) | ((op & 1) << 9);
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SingleThumbOpcode((ushort)opcode, r1: w1, runUnicorn: false);
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switch (op)
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{
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case 0:
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Assert.That(GetContext().GetX(0), Is.EqualTo((w1 + imm) & 0xffffffffu));
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break;
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case 1:
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Assert.That(GetContext().GetX(0), Is.EqualTo((w1 - imm) & 0xffffffffu));
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break;
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}
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}
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}
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}
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}
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}
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