mirror of
https://git.naxdy.org/Mirror/Ryujinx.git
synced 2025-01-08 20:02:39 +00:00
Convert ALU imm CPU tests to xUnit
This commit is contained in:
TSR Berry
parent
f16119c183
commit
8e40b7ba80
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@ -1,5 +1,6 @@
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// #define AluImm
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#define AluImm
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using System;
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using Xunit;
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namespace Ryujinx.Tests.Cpu
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@ -9,13 +10,39 @@ namespace Ryujinx.Tests.Cpu
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{
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#if AluImm
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[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
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public void Add_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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private static readonly uint[] _testData_rd =
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{
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0u, 31u,
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};
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private static readonly uint[] _testData_rn =
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{
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1u, 31u,
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};
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private static readonly ulong[] _testData_xnSp =
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{
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0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
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};
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private static readonly uint[] _testData_imm =
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{
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0u, 4095u,
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};
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private static readonly uint[] _testData_shift =
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{
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0b00u, 0b01u, // <LSL #0, LSL #12>
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};
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private static readonly uint[] _testData_wnWsp =
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{
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0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu,
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};
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public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_64 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_imm, _testData_shift);
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public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_32 = new(_testData_rd, _testData_rn, _testData_wnWsp, _testData_imm, _testData_shift);
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[Theory(DisplayName = "ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
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[MemberData(nameof(TestData_64))]
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public void Add_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
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{
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uint opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -33,13 +60,9 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
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public void Add_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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[Theory(DisplayName = "ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
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[MemberData(nameof(TestData_32))]
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public void Add_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
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{
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uint opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -57,13 +80,9 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
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public void Adds_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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[Theory(DisplayName = "ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
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[MemberData(nameof(TestData_64))]
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public void Adds_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
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{
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uint opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -81,13 +100,9 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
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public void Adds_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
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[Values(0u, 4095u)] uint imm,
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[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
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[Theory(DisplayName = "ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
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[MemberData(nameof(TestData_32))]
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public void Adds_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
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{
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uint opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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@ -105,241 +120,224 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
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public void And_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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private static readonly uint[] _testData_N1_imms =
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{
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0u, 31u, 32u, 62u, // <imm>
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};
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private static readonly uint[] _testData_N1_immr =
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{
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0u, 31u, 32u, 63u, // <imm>
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};
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public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_N1 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_N1_imms, _testData_N1_immr);
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[Theory(DisplayName = "AND <Xd|SP>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N1))]
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public void And_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0x92400000; // AND X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
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public void And_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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private static uint[] _testData_N0_imms =
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{
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0u, 15u, 16u, 30u, // <imm>
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};
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private static uint[] _testData_N0_immr =
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{
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0u, 15u, 16u, 31u, // <imm>
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};
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public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_N0 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_N0_imms, _testData_N0_immr);
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[Theory(DisplayName = "AND <Xd|SP>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N0))]
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public void And_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0x92000000; // AND X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("AND <Wd|WSP>, <Wn>, #<imm>")]
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public void And_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_Add32 = new(_testData_rd, _testData_rd, _testData_wnWsp, _testData_N0_imms, _testData_N0_immr);
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[Theory(DisplayName = "AND <Wd|WSP>, <Wn>, #<imm>")]
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[MemberData(nameof(TestData_Add32))]
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public void And_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
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{
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uint opcode = 0x12000000; // AND W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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uint w31 = Random.Shared.NextUInt();
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SingleOpcode(opcode, x1: wn, x31: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
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public void Ands_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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[Theory(DisplayName = "ANDS <Xd>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N1))]
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public void Ands_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0xF2400000; // ANDS X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
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public void Ands_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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[Theory(DisplayName = "ANDS <Xd>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N1))]
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public void Ands_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ANDS <Wd>, <Wn>, #<imm>")]
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public void Ands_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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[Theory(DisplayName = "ANDS <Wd>, <Wn>, #<imm>")]
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[MemberData(nameof(TestData_Add32))]
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public void Ands_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
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{
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uint opcode = 0x72000000; // ANDS W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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uint w31 = Random.Shared.NextUInt();
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SingleOpcode(opcode, x1: wn, x31: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
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public void Eor_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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[Theory(DisplayName = "EOR <Xd|SP>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N1))]
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public void Eor_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0xD2400000; // EOR X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
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public void Eor_N0_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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[Theory(DisplayName = "EOR <Xd|SP>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N0))]
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public void Eor_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0xD2000000; // EOR X0, X0, #0x100000001
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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ulong x31 = TestContext.CurrentContext.Random.NextULong();
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ulong x31 = Random.Shared.NextULong();
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SingleOpcode(opcode, x1: xn, x31: x31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("EOR <Wd>, <Wn>, #<imm>")]
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public void Eor_32bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x00000000u, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu)] uint wn,
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[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
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[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
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[Theory(DisplayName = "EOR <Wd>, <Wn>, #<imm>")]
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[MemberData(nameof(TestData_Add32))]
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public void Eor_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
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{
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uint opcode = 0x52000000; // EOR W0, W0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
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uint w31 = TestContext.CurrentContext.Random.NextUInt();
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uint w31 = Random.Shared.NextUInt();
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SingleOpcode(opcode, x1: wn, x31: w31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
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public void Orr_N1_64bit([Values(0u, 31u)] uint rd,
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[Values(1u, 31u)] uint rn,
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[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
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[Values(0u, 31u, 32u, 62u)] uint imms, // <imm>
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[Values(0u, 31u, 32u, 63u)] uint immr) // <imm>
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[Theory(DisplayName = "ORR <Xd|SP>, <Xn>, #<imm>")]
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[MemberData(nameof(TestData_N1))]
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public void Orr_N1_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
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{
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uint opcode = 0xB2400000; // ORR X0, X0, #0x1
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opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
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||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = Random.Shared.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
|
||||
public void Orr_N0_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
[Theory(DisplayName = "ORR <Xd|SP>, <Xn>, #<imm>")]
|
||||
[MemberData(nameof(TestData_N0))]
|
||||
public void Orr_N0_64bit(uint rd, uint rn, ulong xn, uint imms, uint immr)
|
||||
{
|
||||
uint opcode = 0xB2000000; // ORR X0, X0, #0x100000001
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
ulong x31 = TestContext.CurrentContext.Random.NextULong();
|
||||
ulong x31 = Random.Shared.NextULong();
|
||||
|
||||
SingleOpcode(opcode, x1: xn, x31: x31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("ORR <Wd|WSP>, <Wn>, #<imm>")]
|
||||
public void Orr_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wn,
|
||||
[Values(0u, 15u, 16u, 30u)] uint imms, // <imm>
|
||||
[Values(0u, 15u, 16u, 31u)] uint immr) // <imm>
|
||||
[Theory(DisplayName = "ORR <Wd|WSP>, <Wn>, #<imm>")]
|
||||
[MemberData(nameof(TestData_Add32))]
|
||||
public void Orr_32bit(uint rd, uint rn, uint wn, uint imms, uint immr)
|
||||
{
|
||||
uint opcode = 0x32000000; // ORR W0, W0, #0x1
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
|
||||
|
||||
uint w31 = TestContext.CurrentContext.Random.NextUInt();
|
||||
uint w31 = Random.Shared.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, x1: wn, x31: w31);
|
||||
|
||||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
public void Sub_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
private static readonly uint[] _testData_Sub_imm =
|
||||
{
|
||||
0u, 4095u,
|
||||
};
|
||||
private static readonly uint[] _testData_Sub_shift =
|
||||
{
|
||||
0b00u, 0b01u, // <LSL #0, LSL #12>
|
||||
};
|
||||
|
||||
public static readonly MatrixTheoryData<uint, uint, ulong, uint, uint> TestData_Sub64 = new(_testData_rd, _testData_rn, _testData_xnSp, _testData_Sub_imm, _testData_Sub_shift);
|
||||
|
||||
[Theory(DisplayName = "SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
[MemberData(nameof(TestData_Sub64))]
|
||||
public void Sub_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
|
||||
{
|
||||
uint opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
|
@ -357,13 +355,11 @@ namespace Ryujinx.Tests.Cpu
|
|||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
public void Sub_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
public static readonly MatrixTheoryData<uint, uint, uint, uint, uint> TestData_Sub32 = new(_testData_rd, _testData_rn, _testData_wnWsp, _testData_Sub_imm, _testData_Sub_shift);
|
||||
|
||||
[Theory(DisplayName = "SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
[MemberData(nameof(TestData_Sub32))]
|
||||
public void Sub_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
|
||||
{
|
||||
uint opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
|
@ -381,13 +377,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
public void Subs_64bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] ulong xnSp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
[Theory(DisplayName = "SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
|
||||
[MemberData(nameof(TestData_Sub64))]
|
||||
public void Subs_64bit(uint rd, uint rn, ulong xnSp, uint imm, uint shift)
|
||||
{
|
||||
uint opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
|
@ -405,13 +397,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
CompareAgainstUnicorn();
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
public void Subs_32bit([Values(0u, 31u)] uint rd,
|
||||
[Values(1u, 31u)] uint rn,
|
||||
[Values(0x00000000u, 0x7FFFFFFFu,
|
||||
0x80000000u, 0xFFFFFFFFu)] uint wnWsp,
|
||||
[Values(0u, 4095u)] uint imm,
|
||||
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
|
||||
[Theory(DisplayName = "SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
|
||||
[MemberData(nameof(TestData_Sub32))]
|
||||
public void Subs_32bit(uint rd, uint rn, uint wnWsp, uint imm, uint shift)
|
||||
{
|
||||
uint opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
|
||||
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
// #define AluRs32
|
||||
#define AluImm32
|
||||
|
||||
using System;
|
||||
using Xunit;
|
||||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
|
|
@ -7,7 +8,7 @@ namespace Ryujinx.Tests.Cpu
|
|||
[Collection("AluImm32")]
|
||||
public sealed class CpuTestAluImm32 : CpuTest32
|
||||
{
|
||||
#if AluRs32
|
||||
#if AluImm32
|
||||
|
||||
#region "ValueSource (Opcodes)"
|
||||
private static uint[] Opcodes()
|
||||
|
|
@ -34,17 +35,29 @@ namespace Ryujinx.Tests.Cpu
|
|||
|
||||
private const int RndCnt = 2;
|
||||
|
||||
[Test, Pairwise]
|
||||
public void TestCpuTestAluImm32([ValueSource(nameof(Opcodes))] uint opcode,
|
||||
[Values(0u, 13u)] uint rd,
|
||||
[Values(1u, 13u)] uint rn,
|
||||
[Random(RndCnt)] uint imm,
|
||||
[Random(RndCnt)] uint wn,
|
||||
[Values(true, false)] bool carryIn)
|
||||
private static readonly uint[] _testData_rd =
|
||||
{
|
||||
0u, 13u,
|
||||
};
|
||||
private static readonly uint[] _testData_rn =
|
||||
{
|
||||
1u, 13u,
|
||||
};
|
||||
private static readonly bool[] _testData_carry =
|
||||
{
|
||||
false,
|
||||
true,
|
||||
};
|
||||
|
||||
public static readonly MatrixTheoryData<uint, uint, uint, uint, uint, bool> TestData = new(Opcodes(), _testData_rd, _testData_rn, Random.Shared.NextUIntEnumerable(RndCnt), Random.Shared.NextUIntEnumerable(RndCnt), _testData_carry);
|
||||
|
||||
[Theory]
|
||||
[MemberData(nameof(TestData))]
|
||||
public void TestCpuTestAluImm32(uint opcode, uint rd, uint rn, uint imm, uint wn, bool carryIn)
|
||||
{
|
||||
opcode |= ((imm & 0xfff) << 0) | ((rn & 15) << 16) | ((rd & 15) << 12);
|
||||
|
||||
uint sp = TestContext.CurrentContext.Random.NextUInt();
|
||||
uint sp = Random.Shared.NextUInt();
|
||||
|
||||
SingleOpcode(opcode, r1: wn, sp: sp, carry: carryIn);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue