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Merge branch 'master' into CoOp

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Dudejoe870 2018-09-10 12:10:39 -05:00 committed by GitHub
commit d427959cd8
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101 changed files with 6004 additions and 18953 deletions
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6
ChocolArm64/ABitUtils.cs
View file

@ -27,6 +27,10 @@ namespace ChocolArm64
return -1;
}
private static readonly sbyte[] HbsNibbleTbl = { -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
public static int HighestBitSetNibble(int Value) => HbsNibbleTbl[Value & 0b1111];
public static long Replicate(long Bits, int Size)
{
long Output = 0;
@ -54,4 +58,4 @@ namespace ChocolArm64
return Value != 0 && (Value & (Value - 1)) == 0;
}
}
}
}

18
ChocolArm64/AOpCodeTable.cs
View file

@ -343,6 +343,7 @@ namespace ChocolArm64
SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg));
SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem));
SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg));
SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", AInstEmit.Mls_Ve, typeof(AOpCodeSimdRegElem));
SetA64("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
SetA64("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm));
@ -380,8 +381,9 @@ namespace ChocolArm64
SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd));
SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg));
SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg));
SetA64("010111110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
SetA64("0x0011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd));
SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg));
@ -415,13 +417,18 @@ namespace ChocolArm64
SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd));
SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg));
SetA64("0101111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm));
SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg));
SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm));
SetA64("0101111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_S, typeof(AOpCodeSimdShImm));
SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm));
SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V, typeof(AOpCodeSimdReg));
@ -474,6 +481,12 @@ namespace ChocolArm64
SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd));
SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd));
SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg));
SetA64("0111111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm));
SetA64("0111111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm));
SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg));
SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm));
SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm));
@ -481,6 +494,7 @@ namespace ChocolArm64
SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm));
SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd));
SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd));
SetA64("0111111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_S, typeof(AOpCodeSimdShImm));
SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm));
SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V, typeof(AOpCodeSimdReg));

4
ChocolArm64/Decoder/AOpCodeSimdShImm.cs
View file

@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder
{
Imm = (OpCode >> 16) & 0x7f;
Size = ABitUtils.HighestBitSet32(Imm >> 3);
Size = ABitUtils.HighestBitSetNibble(Imm >> 3);
}
}
}
}

9
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -957,6 +957,15 @@ namespace ChocolArm64.Instruction
});
}
public static void Mls_Ve(AILEmitterCtx Context)
{
EmitVectorTernaryOpByElemZx(Context, () =>
{
Context.Emit(OpCodes.Mul);
Context.Emit(OpCodes.Sub);
});
}
public static void Mul_V(AILEmitterCtx Context)
{
EmitVectorBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));

5
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -626,6 +626,9 @@ namespace ChocolArm64.Instruction
int Bytes = Op.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
Context.EmitSttmp();
for (int Index = 0; Index < Elems; Index++)
{
if (Ternary)
@ -634,7 +637,7 @@ namespace ChocolArm64.Instruction
}
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
EmitVectorExtract(Context, Op.Rm, Elem, Op.Size, Signed);
Context.EmitLdtmp();
Emit();

225
ChocolArm64/Instruction/AInstEmitSimdShift.cs
View file

@ -14,20 +14,24 @@ namespace ChocolArm64.Instruction
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitVectorExtractZx(Context, Op.Rn, 0, Op.Size);
EmitScalarUnaryOpZx(Context, () =>
{
Context.EmitLdc_I4(GetImmShl(Op));
Context.EmitLdc_I4(GetImmShl(Op));
Context.Emit(OpCodes.Shl);
EmitScalarSet(Context, Op.Rd, Op.Size);
Context.Emit(OpCodes.Shl);
});
}
public static void Shl_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitVectorShImmBinaryZx(Context, () => Context.Emit(OpCodes.Shl), GetImmShl(Op));
EmitVectorUnaryOpZx(Context, () =>
{
Context.EmitLdc_I4(GetImmShl(Op));
Context.Emit(OpCodes.Shl);
});
}
public static void Shll_V(AILEmitterCtx Context)
@ -103,15 +107,24 @@ namespace ChocolArm64.Instruction
EmitVectorSaturatingNarrowOpSxSx(Context, Emit);
}
public static void Srshr_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpSx(Context, ShrImmFlags.Round);
}
public static void Srshr_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitVectorShrImmOpSx(Context, ShrImmFlags.Round);
}
int Shift = GetImmShr(Op);
public static void Srsra_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
}
long RoundConst = 1L << (Shift - 1);
EmitVectorRoundShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), Shift, RoundConst);
public static void Srsra_V(AILEmitterCtx Context)
{
EmitVectorShrImmOpSx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
}
public static void Sshl_V(AILEmitterCtx Context)
@ -128,35 +141,42 @@ namespace ChocolArm64.Instruction
public static void Sshr_S(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitVectorExtractSx(Context, Op.Rn, 0, Op.Size);
Context.EmitLdc_I4(GetImmShr(Op));
Context.Emit(OpCodes.Shr);
EmitScalarSet(Context, Op.Rd, Op.Size);
EmitShrImmOp(Context, ShrImmFlags.ScalarSx);
}
public static void Sshr_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitShrImmOp(Context, ShrImmFlags.VectorSx);
}
EmitVectorShImmBinarySx(Context, () => Context.Emit(OpCodes.Shr), GetImmShr(Op));
public static void Ssra_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpSx(Context, ShrImmFlags.Accumulate);
}
public static void Ssra_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitVectorShrImmOpSx(Context, ShrImmFlags.Accumulate);
}
Action Emit = () =>
{
Context.Emit(OpCodes.Shr);
Context.Emit(OpCodes.Add);
};
public static void Urshr_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpZx(Context, ShrImmFlags.Round);
}
EmitVectorShImmTernarySx(Context, Emit, GetImmShr(Op));
public static void Urshr_V(AILEmitterCtx Context)
{
EmitVectorShrImmOpZx(Context, ShrImmFlags.Round);
}
public static void Ursra_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
}
public static void Ursra_V(AILEmitterCtx Context)
{
EmitVectorShrImmOpZx(Context, ShrImmFlags.Round | ShrImmFlags.Accumulate);
}
public static void Ushl_V(AILEmitterCtx Context)
@ -173,41 +193,22 @@ namespace ChocolArm64.Instruction
public static void Ushr_S(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitScalarUnaryOpZx(Context, () =>
{
Context.EmitLdc_I4(GetImmShr(Op));
Context.Emit(OpCodes.Shr_Un);
});
EmitShrImmOp(Context, ShrImmFlags.ScalarZx);
}
public static void Ushr_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
EmitShrImmOp(Context, ShrImmFlags.VectorZx);
}
EmitVectorUnaryOpZx(Context, () =>
{
Context.EmitLdc_I4(GetImmShr(Op));
Context.Emit(OpCodes.Shr_Un);
});
public static void Usra_S(AILEmitterCtx Context)
{
EmitScalarShrImmOpZx(Context, ShrImmFlags.Accumulate);
}
public static void Usra_V(AILEmitterCtx Context)
{
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
Action Emit = () =>
{
Context.EmitLdc_I4(GetImmShr(Op));
Context.Emit(OpCodes.Shr_Un);
Context.Emit(OpCodes.Add);
};
EmitVectorOp(Context, Emit, OperFlags.RdRn, Signed: false);
EmitVectorShrImmOpZx(Context, ShrImmFlags.Accumulate);
}
private static void EmitVectorShl(AILEmitterCtx Context, bool Signed)
@ -274,78 +275,118 @@ namespace ChocolArm64.Instruction
}
[Flags]
private enum ShImmFlags
private enum ShrImmFlags
{
None = 0,
Scalar = 1 << 0,
Signed = 1 << 1,
Signed = 1 << 0,
Ternary = 1 << 1,
Rounded = 1 << 2,
Round = 1 << 2,
Accumulate = 1 << 3,
SignedTernary = Signed | Ternary,
SignedRounded = Signed | Rounded
ScalarSx = Scalar | Signed,
ScalarZx = Scalar,
VectorSx = Signed,
VectorZx = 0
}
private static void EmitVectorShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
private static void EmitScalarShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
{
EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.Signed);
EmitShrImmOp(Context, ShrImmFlags.ScalarSx | Flags);
}
private static void EmitVectorShImmTernarySx(AILEmitterCtx Context, Action Emit, int Imm)
private static void EmitScalarShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
{
EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedTernary);
EmitShrImmOp(Context, ShrImmFlags.ScalarZx | Flags);
}
private static void EmitVectorShImmBinaryZx(AILEmitterCtx Context, Action Emit, int Imm)
private static void EmitVectorShrImmOpSx(AILEmitterCtx Context, ShrImmFlags Flags)
{
EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.None);
EmitShrImmOp(Context, ShrImmFlags.VectorSx | Flags);
}
private static void EmitVectorRoundShImmBinarySx(AILEmitterCtx Context, Action Emit, int Imm, long Rc)
private static void EmitVectorShrImmOpZx(AILEmitterCtx Context, ShrImmFlags Flags)
{
EmitVectorShImmOp(Context, Emit, Imm, ShImmFlags.SignedRounded, Rc);
EmitShrImmOp(Context, ShrImmFlags.VectorZx | Flags);
}
private static void EmitVectorShImmOp(AILEmitterCtx Context, Action Emit, int Imm, ShImmFlags Flags, long Rc = 0)
private static void EmitShrImmOp(AILEmitterCtx Context, ShrImmFlags Flags)
{
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
AOpCodeSimdShImm Op = (AOpCodeSimdShImm)Context.CurrOp;
bool Scalar = (Flags & ShrImmFlags.Scalar) != 0;
bool Signed = (Flags & ShrImmFlags.Signed) != 0;
bool Round = (Flags & ShrImmFlags.Round) != 0;
bool Accumulate = (Flags & ShrImmFlags.Accumulate) != 0;
int Shift = GetImmShr(Op);
long RoundConst = 1L << (Shift - 1);
int Bytes = Op.GetBitsCount() >> 3;
int Elems = Bytes >> Op.Size;
bool Signed = (Flags & ShImmFlags.Signed) != 0;
bool Ternary = (Flags & ShImmFlags.Ternary) != 0;
bool Rounded = (Flags & ShImmFlags.Rounded) != 0;
int Elems = !Scalar ? Bytes >> Op.Size : 1;
for (int Index = 0; Index < Elems; Index++)
{
if (Ternary)
{
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
}
EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed);
if (Rounded)
if (Op.Size <= 2)
{
Context.EmitLdc_I8(Rc);
if (Round)
{
Context.EmitLdc_I8(RoundConst);
Context.Emit(OpCodes.Add);
}
Context.EmitLdc_I4(Shift);
Context.Emit(Signed ? OpCodes.Shr : OpCodes.Shr_Un);
}
else /* if (Op.Size == 3) */
{
EmitShrImm_64(Context, Signed, Round ? RoundConst : 0L, Shift);
}
if (Accumulate)
{
EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed);
Context.Emit(OpCodes.Add);
}
Context.EmitLdc_I4(Imm);
Emit();
EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
EmitVectorInsertTmp(Context, Index, Op.Size);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
Context.EmitLdvectmp();
Context.EmitStvec(Op.Rd);
if ((Op.RegisterSize == ARegisterSize.SIMD64) || Scalar)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
// Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift;
private static void EmitShrImm_64(
AILEmitterCtx Context,
bool Signed,
long RoundConst,
int Shift)
{
if (((AOpCodeSimd)Context.CurrOp).Size < 3)
{
throw new InvalidOperationException();
}
Context.EmitLdc_I8(RoundConst);
Context.EmitLdc_I4(Shift);
ASoftFallback.EmitCall(Context, Signed
? nameof(ASoftFallback.SignedShrImm_64)
: nameof(ASoftFallback.UnsignedShrImm_64));
}
private static void EmitVectorShImmNarrowBinarySx(AILEmitterCtx Context, Action Emit, int Imm)
{
EmitVectorShImmNarrowBinaryOp(Context, Emit, Imm, true);
@ -414,4 +455,4 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Op.Rd);
}
}
}
}

86
ChocolArm64/Instruction/ASoftFallback.cs
View file

@ -16,6 +16,92 @@ namespace ChocolArm64.Instruction
Context.EmitCall(typeof(ASoftFallback), MthdName);
}
#region "ShrImm_64"
public static long SignedShrImm_64(long Value, long RoundConst, int Shift)
{
if (RoundConst == 0L)
{
if (Shift <= 63)
{
return Value >> Shift;
}
else /* if (Shift == 64) */
{
if (Value < 0L)
{
return -1L;
}
else
{
return 0L;
}
}
}
else /* if (RoundConst == 1L << (Shift - 1)) */
{
if (Shift <= 63)
{
long Add = Value + RoundConst;
if ((~Value & (Value ^ Add)) < 0L)
{
return (long)((ulong)Add >> Shift);
}
else
{
return Add >> Shift;
}
}
else /* if (Shift == 64) */
{
return 0L;
}
}
}
public static ulong UnsignedShrImm_64(ulong Value, long RoundConst, int Shift)
{
if (RoundConst == 0L)
{
if (Shift <= 63)
{
return Value >> Shift;
}
else /* if (Shift == 64) */
{
return 0UL;
}
}
else /* if (RoundConst == 1L << (Shift - 1)) */
{
ulong Add = Value + (ulong)RoundConst;
if ((Add < Value) && (Add < (ulong)RoundConst))
{
if (Shift <= 63)
{
return (Add >> Shift) | (0x8000000000000000UL >> (Shift - 1));
}
else /* if (Shift == 64) */
{
return 1UL;
}
}
else
{
if (Shift <= 63)
{
return Add >> Shift;
}
else /* if (Shift == 64) */
{
return 0UL;
}
}
}
}
#endregion
#region "Saturating"
public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State)
{

104
KEYS.md Normal file
View file

@ -0,0 +1,104 @@
# Keys
Keys are required for decrypting most of the file formats used by the Nintendo Switch.
Keysets are stored as text files. These 3 filenames are automatically read:
`prod.keys` - Contains common keys usedy by all Switch devices.
`console.keys` - Contains console-unique keys.
`title.keys` - Contains game-specific keys.
Ryujinx will first look for keys in `RyuFS/system`, and if it doesn't find any there it will look in `$HOME/.switch`.
A guide to assist with dumping your own keys can be found [here](https://gist.github.com/roblabla/d8358ab058bbe3b00614740dcba4f208).
## Common keys
Here is a template for a key file containing the main keys Ryujinx uses to read content files.
Both `prod.keys` and `console.keys` use this format.
```
master_key_00 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
master_key_01 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
master_key_02 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
master_key_03 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
master_key_04 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
master_key_05 = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
titlekek_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
key_area_key_application_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
key_area_key_ocean_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
key_area_key_system_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
aes_kek_generation_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
aes_key_generation_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
header_kek_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
header_key_source = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
```
## Title keys
Title keys are stored in the format `rights_id,key`.
For example:
```
01000000000100000000000000000003,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
01000000000108000000000000000003,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
01000000000108000000000000000004,XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
```
## Complete key list
Below is a complete list of keys that are currently recognized.
\## represents a hexadecimal number between 00 and 1F
@@ represents a hexadecimal number between 00 and 03
### Common keys
```
master_key_source
keyblob_mac_key_source
package2_key_source
aes_kek_generation_source
aes_key_generation_source
key_area_key_application_source
key_area_key_ocean_source
key_area_key_system_source
titlekek_source
header_kek_source
header_key_source
sd_card_kek_source
sd_card_nca_key_source
sd_card_save_key_source
retail_specific_aes_key_source
per_console_key_source
bis_kek_source
bis_key_source_@@
header_key
xci_header_key
eticket_rsa_kek
master_key_##
package1_key_##
package2_key_##
titlekek_##
key_area_key_application_##
key_area_key_ocean_##
key_area_key_system_##
keyblob_key_source_##
keyblob_##
```
### Console-unique keys
```
secure_boot_key
tsec_key
device_key
bis_key_@@
keyblob_key_##
keyblob_mac_key_##
encrypted_keyblob_##
sd_seed
```

2
Ryujinx.Graphics/Gal/GalFrameBufferFormat.cs
View file

@ -1,6 +1,6 @@
namespace Ryujinx.Graphics.Gal
{
public enum GalFrameBufferFormat
public enum GalSurfaceFormat
{
Bitmap = 0x1c,
Unknown1D = 0x1d,

275
Ryujinx.Graphics/Gal/GalImageFormat.cs
View file

@ -1,204 +1,93 @@
namespace Ryujinx.Graphics.Gal
using System;
namespace Ryujinx.Graphics.Gal
{
//These are Vulkan-based enumerations, do not take them as Tegra values
[Flags]
public enum GalImageFormat
{
Undefined = 0,
Snorm = 1 << 27,
Unorm = 1 << 28,
Sint = 1 << 29,
Uint = 1 << 30,
Sfloat = 1 << 31,
R4G4_UNORM_PACK8 = 1,
R4G4B4A4_UNORM_PACK16 = 2,
B4G4R4A4_UNORM_PACK16 = 3,
R5G6B5_UNORM_PACK16 = 4,
B5G6R5_UNORM_PACK16 = 5,
R5G5B5A1_UNORM_PACK16 = 6,
B5G5R5A1_UNORM_PACK16 = 7,
A1R5G5B5_UNORM_PACK16 = 8,
R8_UNORM = 9,
R8_SNORM = 10,
R8_USCALED = 11,
R8_SSCALED = 12,
R8_UINT = 13,
R8_SINT = 14,
R8_SRGB = 15,
R8G8_UNORM = 16,
R8G8_SNORM = 17,
R8G8_USCALED = 18,
R8G8_SSCALED = 19,
R8G8_UINT = 20,
R8G8_SINT = 21,
R8G8_SRGB = 22,
R8G8B8_UNORM = 23,
R8G8B8_SNORM = 24,
R8G8B8_USCALED = 25,
R8G8B8_SSCALED = 26,
R8G8B8_UINT = 27,
R8G8B8_SINT = 28,
R8G8B8_SRGB = 29,
B8G8R8_UNORM = 30,
B8G8R8_SNORM = 31,
B8G8R8_USCALED = 32,
B8G8R8_SSCALED = 33,
B8G8R8_UINT = 34,
B8G8R8_SINT = 35,
B8G8R8_SRGB = 36,
R8G8B8A8_UNORM = 37,
R8G8B8A8_SNORM = 38,
R8G8B8A8_USCALED = 39,
R8G8B8A8_SSCALED = 40,
R8G8B8A8_UINT = 41,
R8G8B8A8_SINT = 42,
R8G8B8A8_SRGB = 43,
B8G8R8A8_UNORM = 44,
B8G8R8A8_SNORM = 45,
B8G8R8A8_USCALED = 46,
B8G8R8A8_SSCALED = 47,
B8G8R8A8_UINT = 48,
B8G8R8A8_SINT = 49,
B8G8R8A8_SRGB = 50,
A8B8G8R8_UNORM_PACK32 = 51,
A8B8G8R8_SNORM_PACK32 = 52,
A8B8G8R8_USCALED_PACK32 = 53,
A8B8G8R8_SSCALED_PACK32 = 54,
A8B8G8R8_UINT_PACK32 = 55,
A8B8G8R8_SINT_PACK32 = 56,
A8B8G8R8_SRGB_PACK32 = 57,
A2R10G10B10_UNORM_PACK32 = 58,
A2R10G10B10_SNORM_PACK32 = 59,
A2R10G10B10_USCALED_PACK32 = 60,
A2R10G10B10_SSCALED_PACK32 = 61,
A2R10G10B10_UINT_PACK32 = 62,
A2R10G10B10_SINT_PACK32 = 63,
A2B10G10R10_UNORM_PACK32 = 64,
A2B10G10R10_SNORM_PACK32 = 65,
A2B10G10R10_USCALED_PACK32 = 66,
A2B10G10R10_SSCALED_PACK32 = 67,
A2B10G10R10_UINT_PACK32 = 68,
A2B10G10R10_SINT_PACK32 = 69,
R16_UNORM = 70,
R16_SNORM = 71,
R16_USCALED = 72,
R16_SSCALED = 73,
R16_UINT = 74,
R16_SINT = 75,
R16_SFLOAT = 76,
R16G16_UNORM = 77,
R16G16_SNORM = 78,
R16G16_USCALED = 79,
R16G16_SSCALED = 80,
R16G16_UINT = 81,
R16G16_SINT = 82,
R16G16_SFLOAT = 83,
R16G16B16_UNORM = 84,
R16G16B16_SNORM = 85,
R16G16B16_USCALED = 86,
R16G16B16_SSCALED = 87,
R16G16B16_UINT = 88,
R16G16B16_SINT = 89,
R16G16B16_SFLOAT = 90,
R16G16B16A16_UNORM = 91,
R16G16B16A16_SNORM = 92,
R16G16B16A16_USCALED = 93,
R16G16B16A16_SSCALED = 94,
R16G16B16A16_UINT = 95,
R16G16B16A16_SINT = 96,
R16G16B16A16_SFLOAT = 97,
R32_UINT = 98,
R32_SINT = 99,
R32_SFLOAT = 100,
R32G32_UINT = 101,
R32G32_SINT = 102,
R32G32_SFLOAT = 103,
R32G32B32_UINT = 104,
R32G32B32_SINT = 105,
R32G32B32_SFLOAT = 106,
R32G32B32A32_UINT = 107,
R32G32B32A32_SINT = 108,
R32G32B32A32_SFLOAT = 109,
R64_UINT = 110,
R64_SINT = 111,
R64_SFLOAT = 112,
R64G64_UINT = 113,
R64G64_SINT = 114,
R64G64_SFLOAT = 115,
R64G64B64_UINT = 116,
R64G64B64_SINT = 117,
R64G64B64_SFLOAT = 118,
R64G64B64A64_UINT = 119,
R64G64B64A64_SINT = 120,
R64G64B64A64_SFLOAT = 121,
B10G11R11_UFLOAT_PACK32 = 122,
E5B9G9R9_UFLOAT_PACK32 = 123,
D16_UNORM = 124,
X8_D24_UNORM_PACK32 = 125,
D32_SFLOAT = 126,
S8_UINT = 127,
D16_UNORM_S8_UINT = 128,
D24_UNORM_S8_UINT = 129,
D32_SFLOAT_S8_UINT = 130,
BC1_RGB_UNORM_BLOCK = 131,
BC1_RGB_SRGB_BLOCK = 132,
BC1_RGBA_UNORM_BLOCK = 133,
BC1_RGBA_SRGB_BLOCK = 134,
BC2_UNORM_BLOCK = 135,
BC2_SRGB_BLOCK = 136,
BC3_UNORM_BLOCK = 137,
BC3_SRGB_BLOCK = 138,
BC4_UNORM_BLOCK = 139,
BC4_SNORM_BLOCK = 140,
BC5_UNORM_BLOCK = 141,
BC5_SNORM_BLOCK = 142,
BC6H_UFLOAT_BLOCK = 143,
BC6H_SFLOAT_BLOCK = 144,
BC7_UNORM_BLOCK = 145,
BC7_SRGB_BLOCK = 146,
ETC2_R8G8B8_UNORM_BLOCK = 147,
ETC2_R8G8B8_SRGB_BLOCK = 148,
ETC2_R8G8B8A1_UNORM_BLOCK = 149,
ETC2_R8G8B8A1_SRGB_BLOCK = 150,
ETC2_R8G8B8A8_UNORM_BLOCK = 151,
ETC2_R8G8B8A8_SRGB_BLOCK = 152,
EAC_R11_UNORM_BLOCK = 153,
EAC_R11_SNORM_BLOCK = 154,
EAC_R11G11_UNORM_BLOCK = 155,
EAC_R11G11_SNORM_BLOCK = 156,
TypeMask = Snorm | Unorm | Sint | Uint | Sfloat,
ASTC_BEGIN = ASTC_4x4_UNORM_BLOCK,
FormatMask = ~TypeMask,
ASTC_4x4_UNORM_BLOCK = 157,
ASTC_4x4_SRGB_BLOCK = 158,
ASTC_5x4_UNORM_BLOCK = 159,
ASTC_5x4_SRGB_BLOCK = 160,
ASTC_5x5_UNORM_BLOCK = 161,
ASTC_5x5_SRGB_BLOCK = 162,
ASTC_6x5_UNORM_BLOCK = 163,
ASTC_6x5_SRGB_BLOCK = 164,
ASTC_6x6_UNORM_BLOCK = 165,
ASTC_6x6_SRGB_BLOCK = 166,
ASTC_8x5_UNORM_BLOCK = 167,
ASTC_8x5_SRGB_BLOCK = 168,
ASTC_8x6_UNORM_BLOCK = 169,
ASTC_8x6_SRGB_BLOCK = 170,
ASTC_8x8_UNORM_BLOCK = 171,
ASTC_8x8_SRGB_BLOCK = 172,
ASTC_10x5_UNORM_BLOCK = 173,
ASTC_10x5_SRGB_BLOCK = 174,
ASTC_10x6_UNORM_BLOCK = 175,
ASTC_10x6_SRGB_BLOCK = 176,
ASTC_10x8_UNORM_BLOCK = 177,
ASTC_10x8_SRGB_BLOCK = 178,
ASTC_10x10_UNORM_BLOCK = 179,
ASTC_10x10_SRGB_BLOCK = 180,
ASTC_12x10_UNORM_BLOCK = 181,
ASTC_12x10_SRGB_BLOCK = 182,
ASTC_12x12_UNORM_BLOCK = 183,
ASTC_12x12_SRGB_BLOCK = 184,
ASTC_BEGIN = ASTC_4x4,
ASTC_END = ASTC_12x12_SRGB_BLOCK,
ASTC_4x4 = 1,
ASTC_5x4,
ASTC_5x5,
ASTC_6x5,
ASTC_6x6,
ASTC_8x5,
ASTC_8x6,
ASTC_8x8,
ASTC_10x5,
ASTC_10x6,
ASTC_10x8,
ASTC_10x10,
ASTC_12x10,
ASTC_12x12,
REVERSED_BEGIN,
ASTC_END = ASTC_12x12,
R4G4B4A4_UNORM_PACK16_REVERSED = REVERSED_BEGIN,
REVERSED_END
R4G4,
R4G4B4A4,
B4G4R4A4,
A4B4G4R4,
R5G6B5,
B5G6R5,
R5G5B5A1,
B5G5R5A1,
A1R5G5B5,
R8,
R8G8,
G8R8,
R8G8B8,
B8G8R8,
R8G8B8A8,
B8G8R8A8,
A8B8G8R8,
A8B8G8R8_SRGB,
A2R10G10B10,
A2B10G10R10,
R16,
R16G16,
R16G16B16,
R16G16B16A16,
R32,
R32G32,
R32G32B32,
R32G32B32A32,
R64,
R64G64,
R64G64B64,
R64G64B64A64,
B10G11R11,
E5B9G9R9,
D16,
X8_D24,
D32,
S8,
D16_S8,
D24_S8,
D32_S8,
BC1_RGB,
BC1_RGBA,
BC2,
BC3,
BC4,
BC5,
BC6H_SF16,
BC6H_UF16,
BC7,
ETC2_R8G8B8,
ETC2_R8G8B8A1,
ETC2_R8G8B8A8,
EAC_R11,
EAC_R11G11,
}
}

2
Ryujinx.Graphics/Gal/IGalFrameBuffer.cs → Ryujinx.Graphics/Gal/IGalRenderTarget.cs
View file

@ -2,7 +2,7 @@ using System;
namespace Ryujinx.Graphics.Gal
{
public interface IGalFrameBuffer
public interface IGalRenderTarget
{
void BindColor(long Key, int Attachment);

2
Ryujinx.Graphics/Gal/IGalRenderer.cs
View file

@ -10,7 +10,7 @@ namespace Ryujinx.Graphics.Gal
IGalConstBuffer Buffer { get; }
IGalFrameBuffer FrameBuffer { get; }
IGalRenderTarget RenderTarget { get; }
IGalRasterizer Rasterizer { get; }

279
Ryujinx.Graphics/Gal/ImageFormatConverter.cs
View file

@ -1,279 +0,0 @@
using System;
namespace Ryujinx.Graphics.Gal
{
public static class ImageFormatConverter
{
public static GalImageFormat ConvertTexture(
GalTextureFormat Format,
GalTextureType RType,
GalTextureType GType,
GalTextureType BType,
GalTextureType AType)
{
if (RType != GType || RType != BType || RType != AType)
{
throw new NotImplementedException("Per component types are not implemented");
}
GalTextureType Type = RType;
switch (Type)
{
case GalTextureType.Snorm:
switch (Format)
{
case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SNORM;
case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_SNORM_PACK32;
case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_SNORM_PACK32;
case GalTextureFormat.G8R8: return GalImageFormat.R8G8_SNORM;
case GalTextureFormat.R16: return GalImageFormat.R16_SNORM;
case GalTextureFormat.R8: return GalImageFormat.R8_SNORM;
case GalTextureFormat.BC4: return GalImageFormat.BC4_SNORM_BLOCK;
case GalTextureFormat.BC5: return GalImageFormat.BC5_SNORM_BLOCK;
}
break;
case GalTextureType.Unorm:
switch (Format)
{
case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_UNORM;
case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_UNORM_PACK32;
case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_UNORM_PACK32;
case GalTextureFormat.A4B4G4R4: return GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED;
case GalTextureFormat.A1B5G5R5: return GalImageFormat.A1R5G5B5_UNORM_PACK16;
case GalTextureFormat.B5G6R5: return GalImageFormat.B5G6R5_UNORM_PACK16;
case GalTextureFormat.BC7U: return GalImageFormat.BC7_UNORM_BLOCK;
case GalTextureFormat.G8R8: return GalImageFormat.R8G8_UNORM;
case GalTextureFormat.R16: return GalImageFormat.R16_UNORM;
case GalTextureFormat.R8: return GalImageFormat.R8_UNORM;
case GalTextureFormat.BC1: return GalImageFormat.BC1_RGBA_UNORM_BLOCK;
case GalTextureFormat.BC2: return GalImageFormat.BC2_UNORM_BLOCK;
case GalTextureFormat.BC3: return GalImageFormat.BC3_UNORM_BLOCK;
case GalTextureFormat.BC4: return GalImageFormat.BC4_UNORM_BLOCK;
case GalTextureFormat.BC5: return GalImageFormat.BC5_UNORM_BLOCK;
case GalTextureFormat.Z24S8: return GalImageFormat.D24_UNORM_S8_UINT;
case GalTextureFormat.ZF32_X24S8: return GalImageFormat.D32_SFLOAT_S8_UINT;
case GalTextureFormat.Astc2D4x4: return GalImageFormat.ASTC_4x4_UNORM_BLOCK;
case GalTextureFormat.Astc2D5x5: return GalImageFormat.ASTC_5x5_UNORM_BLOCK;
case GalTextureFormat.Astc2D6x6: return GalImageFormat.ASTC_6x6_UNORM_BLOCK;
case GalTextureFormat.Astc2D8x8: return GalImageFormat.ASTC_8x8_UNORM_BLOCK;
case GalTextureFormat.Astc2D10x10: return GalImageFormat.ASTC_10x10_UNORM_BLOCK;
case GalTextureFormat.Astc2D12x12: return GalImageFormat.ASTC_12x12_UNORM_BLOCK;
case GalTextureFormat.Astc2D5x4: return GalImageFormat.ASTC_5x4_UNORM_BLOCK;
case GalTextureFormat.Astc2D6x5: return GalImageFormat.ASTC_6x5_UNORM_BLOCK;
case GalTextureFormat.Astc2D8x6: return GalImageFormat.ASTC_8x6_UNORM_BLOCK;
case GalTextureFormat.Astc2D10x8: return GalImageFormat.ASTC_10x8_UNORM_BLOCK;
case GalTextureFormat.Astc2D12x10: return GalImageFormat.ASTC_12x10_UNORM_BLOCK;
case GalTextureFormat.Astc2D8x5: return GalImageFormat.ASTC_8x5_UNORM_BLOCK;
case GalTextureFormat.Astc2D10x5: return GalImageFormat.ASTC_10x5_UNORM_BLOCK;
case GalTextureFormat.Astc2D10x6: return GalImageFormat.ASTC_10x6_UNORM_BLOCK;
}
break;
case GalTextureType.Sint:
switch (Format)
{
case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_SINT;
case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SINT;
case GalTextureFormat.R32G32: return GalImageFormat.R32G32_SINT;
case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_SINT_PACK32;
case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_SINT_PACK32;
case GalTextureFormat.R32: return GalImageFormat.R32_SINT;
case GalTextureFormat.G8R8: return GalImageFormat.R8G8_SINT;
case GalTextureFormat.R16: return GalImageFormat.R16_SINT;
case GalTextureFormat.R8: return GalImageFormat.R8_SINT;
}
break;
case GalTextureType.Uint:
switch (Format)
{
case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_UINT;
case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_UINT;
case GalTextureFormat.R32G32: return GalImageFormat.R32G32_UINT;
case GalTextureFormat.A8B8G8R8: return GalImageFormat.A8B8G8R8_UINT_PACK32;
case GalTextureFormat.A2B10G10R10: return GalImageFormat.A2B10G10R10_UINT_PACK32;
case GalTextureFormat.R32: return GalImageFormat.R32_UINT;
case GalTextureFormat.G8R8: return GalImageFormat.R8G8_UINT;
case GalTextureFormat.R16: return GalImageFormat.R16_UINT;
case GalTextureFormat.R8: return GalImageFormat.R8_UINT;
}
break;
case GalTextureType.Snorm_Force_Fp16:
//TODO
break;
case GalTextureType.Unorm_Force_Fp16:
//TODO
break;
case GalTextureType.Float:
switch (Format)
{
case GalTextureFormat.R32G32B32A32: return GalImageFormat.R32G32B32A32_SFLOAT;
case GalTextureFormat.R16G16B16A16: return GalImageFormat.R16G16B16A16_SFLOAT;
case GalTextureFormat.R32G32: return GalImageFormat.R32G32_SFLOAT;
case GalTextureFormat.R32: return GalImageFormat.R32_SFLOAT;
case GalTextureFormat.BC6H_SF16: return GalImageFormat.BC6H_SFLOAT_BLOCK;
case GalTextureFormat.BC6H_UF16: return GalImageFormat.BC6H_UFLOAT_BLOCK;
case GalTextureFormat.R16: return GalImageFormat.R16_SFLOAT;
case GalTextureFormat.BF10GF11RF11: return GalImageFormat.B10G11R11_UFLOAT_PACK32;
case GalTextureFormat.ZF32: return GalImageFormat.D32_SFLOAT;
}
break;
}
throw new NotImplementedException("0x" + ((int)Format).ToString("x2") + " " + Type.ToString());
}
public static GalImageFormat ConvertFrameBuffer(GalFrameBufferFormat Format)
{
switch (Format)
{
case GalFrameBufferFormat.R32Float: return GalImageFormat.R32_SFLOAT;
case GalFrameBufferFormat.RGB10A2Unorm: return GalImageFormat.A2B10G10R10_UNORM_PACK32;
case GalFrameBufferFormat.RGBA8Srgb: return GalImageFormat.A8B8G8R8_SRGB_PACK32;
case GalFrameBufferFormat.RGBA16Float: return GalImageFormat.R16G16B16A16_SFLOAT;
case GalFrameBufferFormat.R16Float: return GalImageFormat.R16_SFLOAT;
case GalFrameBufferFormat.R8Unorm: return GalImageFormat.R8_UNORM;
case GalFrameBufferFormat.RGBA8Unorm: return GalImageFormat.A8B8G8R8_UNORM_PACK32;
case GalFrameBufferFormat.R11G11B10Float: return GalImageFormat.B10G11R11_UFLOAT_PACK32;
case GalFrameBufferFormat.RGBA32Float: return GalImageFormat.R32G32B32A32_SFLOAT;
case GalFrameBufferFormat.RG16Snorm: return GalImageFormat.R16G16_SNORM;
case GalFrameBufferFormat.RG16Float: return GalImageFormat.R16G16_SFLOAT;
case GalFrameBufferFormat.RG8Snorm: return GalImageFormat.R8_SNORM;
case GalFrameBufferFormat.RGBA8Snorm: return GalImageFormat.A8B8G8R8_SNORM_PACK32;
case GalFrameBufferFormat.RG8Unorm: return GalImageFormat.R8G8_UNORM;
case GalFrameBufferFormat.BGRA8Unorm: return GalImageFormat.A8B8G8R8_UNORM_PACK32;
case GalFrameBufferFormat.BGRA8Srgb: return GalImageFormat.A8B8G8R8_SRGB_PACK32;
case GalFrameBufferFormat.RG32Float: return GalImageFormat.R32G32_SFLOAT;
case GalFrameBufferFormat.RG32Sint: return GalImageFormat.R32G32_SINT;
case GalFrameBufferFormat.RG32Uint: return GalImageFormat.R32G32_UINT;
}
throw new NotImplementedException(Format.ToString());
}
public static GalImageFormat ConvertZeta(GalZetaFormat Format)
{
switch (Format)
{
case GalZetaFormat.Z32Float: return GalImageFormat.D32_SFLOAT;
case GalZetaFormat.S8Z24Unorm: return GalImageFormat.D24_UNORM_S8_UINT;
case GalZetaFormat.Z16Unorm: return GalImageFormat.D16_UNORM;
case GalZetaFormat.Z32S8X24Float: return GalImageFormat.D32_SFLOAT_S8_UINT;
}
throw new NotImplementedException(Format.ToString());
}
public static bool HasColor(GalImageFormat Format)
{
switch (Format)
{
case GalImageFormat.R32G32B32A32_SFLOAT:
case GalImageFormat.R32G32B32A32_SINT:
case GalImageFormat.R32G32B32A32_UINT:
case GalImageFormat.R16G16B16A16_SFLOAT:
case GalImageFormat.R16G16B16A16_SINT:
case GalImageFormat.R16G16B16A16_UINT:
case GalImageFormat.R32G32_SFLOAT:
case GalImageFormat.R32G32_SINT:
case GalImageFormat.R32G32_UINT:
case GalImageFormat.A8B8G8R8_SNORM_PACK32:
case GalImageFormat.A8B8G8R8_UNORM_PACK32:
case GalImageFormat.A8B8G8R8_SINT_PACK32:
case GalImageFormat.A8B8G8R8_UINT_PACK32:
case GalImageFormat.A2B10G10R10_SINT_PACK32:
case GalImageFormat.A2B10G10R10_SNORM_PACK32:
case GalImageFormat.A2B10G10R10_UINT_PACK32:
case GalImageFormat.A2B10G10R10_UNORM_PACK32:
case GalImageFormat.R32_SFLOAT:
case GalImageFormat.R32_SINT:
case GalImageFormat.R32_UINT:
case GalImageFormat.BC6H_SFLOAT_BLOCK:
case GalImageFormat.BC6H_UFLOAT_BLOCK:
case GalImageFormat.A1R5G5B5_UNORM_PACK16:
case GalImageFormat.B5G6R5_UNORM_PACK16:
case GalImageFormat.BC7_UNORM_BLOCK:
case GalImageFormat.R16G16_SFLOAT:
case GalImageFormat.R16G16_SINT:
case GalImageFormat.R16G16_SNORM:
case GalImageFormat.R16G16_UNORM:
case GalImageFormat.R8G8_SINT:
case GalImageFormat.R8G8_SNORM:
case GalImageFormat.R8G8_UINT:
case GalImageFormat.R8G8_UNORM:
case GalImageFormat.R16_SFLOAT:
case GalImageFormat.R16_SINT:
case GalImageFormat.R16_SNORM:
case GalImageFormat.R16_UINT:
case GalImageFormat.R16_UNORM:
case GalImageFormat.R8_SINT:
case GalImageFormat.R8_SNORM:
case GalImageFormat.R8_UINT:
case GalImageFormat.R8_UNORM:
case GalImageFormat.B10G11R11_UFLOAT_PACK32:
case GalImageFormat.BC1_RGBA_UNORM_BLOCK:
case GalImageFormat.BC2_UNORM_BLOCK:
case GalImageFormat.BC3_UNORM_BLOCK:
case GalImageFormat.BC4_UNORM_BLOCK:
case GalImageFormat.BC5_UNORM_BLOCK:
case GalImageFormat.ASTC_4x4_UNORM_BLOCK:
case GalImageFormat.ASTC_5x5_UNORM_BLOCK:
case GalImageFormat.ASTC_6x6_UNORM_BLOCK:
case GalImageFormat.ASTC_8x8_UNORM_BLOCK:
case GalImageFormat.ASTC_10x10_UNORM_BLOCK:
case GalImageFormat.ASTC_12x12_UNORM_BLOCK:
case GalImageFormat.ASTC_5x4_UNORM_BLOCK:
case GalImageFormat.ASTC_6x5_UNORM_BLOCK:
case GalImageFormat.ASTC_8x6_UNORM_BLOCK:
case GalImageFormat.ASTC_10x8_UNORM_BLOCK:
case GalImageFormat.ASTC_12x10_UNORM_BLOCK:
case GalImageFormat.ASTC_8x5_UNORM_BLOCK:
case GalImageFormat.ASTC_10x5_UNORM_BLOCK:
case GalImageFormat.ASTC_10x6_UNORM_BLOCK:
case GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED:
return true;
case GalImageFormat.D24_UNORM_S8_UINT:
case GalImageFormat.D32_SFLOAT:
case GalImageFormat.D16_UNORM:
case GalImageFormat.D32_SFLOAT_S8_UINT:
return false;
}
throw new NotImplementedException(Format.ToString());
}
public static bool HasDepth(GalImageFormat Format)
{
switch (Format)
{
case GalImageFormat.D24_UNORM_S8_UINT:
case GalImageFormat.D32_SFLOAT:
case GalImageFormat.D16_UNORM:
case GalImageFormat.D32_SFLOAT_S8_UINT:
return true;
}
//Depth formats are fewer than colors, so it's harder to miss one
//Instead of checking for individual formats, return false
return false;
}
public static bool HasStencil(GalImageFormat Format)
{
switch (Format)
{
case GalImageFormat.D24_UNORM_S8_UINT:
case GalImageFormat.D32_SFLOAT_S8_UINT:
return true;
}
return false;
}
}
}

165
Ryujinx.Graphics/Gal/OpenGL/ImageHandler.cs
View file

@ -1,13 +1,11 @@
using OpenTK.Graphics.OpenGL;
using Ryujinx.Graphics.Texture;
using System;
namespace Ryujinx.Graphics.Gal.OpenGL
{
class ImageHandler
{
//TODO: Use a variable value here
public const int MaxBpp = 16;
private static int CopyBuffer = 0;
private static int CopyBufferSize = 0;
@ -38,87 +36,124 @@ namespace Ryujinx.Graphics.Gal.OpenGL
this.Image = Image;
}
public void EnsureSetup(GalImage Image)
public void EnsureSetup(GalImage NewImage)
{
if (Width != Image.Width ||
Height != Image.Height ||
Format != Image.Format ||
!Initialized)
if (Width == NewImage.Width &&
Height == NewImage.Height &&
Format == NewImage.Format &&
Initialized)
{
(PixelInternalFormat InternalFormat, PixelFormat PixelFormat, PixelType PixelType) =
OGLEnumConverter.GetImageFormat(Image.Format);
return;
}
GL.BindTexture(TextureTarget.Texture2D, Handle);
PixelInternalFormat InternalFmt;
PixelFormat PixelFormat;
PixelType PixelType;
if (Initialized)
if (ImageUtils.IsCompressed(NewImage.Format))
{
InternalFmt = (PixelInternalFormat)OGLEnumConverter.GetCompressedImageFormat(NewImage.Format);
PixelFormat = default(PixelFormat);
PixelType = default(PixelType);
}
else
{
(InternalFmt, PixelFormat, PixelType) = OGLEnumConverter.GetImageFormat(NewImage.Format);
}
GL.BindTexture(TextureTarget.Texture2D, Handle);
if (Initialized)
{
if (CopyBuffer == 0)
{
if (CopyBuffer == 0)
{
CopyBuffer = GL.GenBuffer();
}
int MaxWidth = Math.Max(Image.Width, Width);
int MaxHeight = Math.Max(Image.Height, Height);
int CurrentSize = MaxWidth * MaxHeight * MaxBpp;
GL.BindBuffer(BufferTarget.PixelPackBuffer, CopyBuffer);
GL.BindBuffer(BufferTarget.PixelUnpackBuffer, CopyBuffer);
if (CopyBufferSize < CurrentSize)
{
CopyBufferSize = CurrentSize;
GL.BufferData(BufferTarget.PixelPackBuffer, CurrentSize, IntPtr.Zero, BufferUsageHint.StreamCopy);
}
GL.GetTexImage(TextureTarget.Texture2D, 0, this.PixelFormat, this.PixelType, IntPtr.Zero);
GL.DeleteTexture(Handle);
Handle = GL.GenTexture();
GL.BindTexture(TextureTarget.Texture2D, Handle);
CopyBuffer = GL.GenBuffer();
}
const int MinFilter = (int)TextureMinFilter.Linear;
const int MagFilter = (int)TextureMagFilter.Linear;
int CurrentSize = Math.Max(ImageUtils.GetSize(NewImage),
ImageUtils.GetSize(Image));
GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMinFilter, MinFilter);
GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMagFilter, MagFilter);
GL.BindBuffer(BufferTarget.PixelPackBuffer, CopyBuffer);
GL.BindBuffer(BufferTarget.PixelUnpackBuffer, CopyBuffer);
const int Level = 0;
const int Border = 0;
if (CopyBufferSize < CurrentSize)
{
CopyBufferSize = CurrentSize;
GL.BufferData(BufferTarget.PixelPackBuffer, CurrentSize, IntPtr.Zero, BufferUsageHint.StreamCopy);
}
if (ImageUtils.IsCompressed(Image.Format))
{
GL.GetCompressedTexImage(TextureTarget.Texture2D, 0, IntPtr.Zero);
}
else
{
GL.GetTexImage(TextureTarget.Texture2D, 0, this.PixelFormat, this.PixelType, IntPtr.Zero);
}
GL.DeleteTexture(Handle);
Handle = GL.GenTexture();
GL.BindTexture(TextureTarget.Texture2D, Handle);
}
const int MinFilter = (int)TextureMinFilter.Linear;
const int MagFilter = (int)TextureMagFilter.Linear;
GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMinFilter, MinFilter);
GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureMagFilter, MagFilter);
const int Level = 0;
const int Border = 0;
if (ImageUtils.IsCompressed(NewImage.Format))
{
Console.WriteLine("Hit");
GL.CompressedTexImage2D(
TextureTarget.Texture2D,
Level,
(InternalFormat)InternalFmt,
NewImage.Width,
NewImage.Height,
Border,
ImageUtils.GetSize(NewImage),
IntPtr.Zero);
}
else
{
GL.TexImage2D(
TextureTarget.Texture2D,
Level,
InternalFormat,
Image.Width,
Image.Height,
InternalFmt,
NewImage.Width,
NewImage.Height,
Border,
PixelFormat,
PixelType,
IntPtr.Zero);
if (Initialized)
{
GL.BindBuffer(BufferTarget.PixelPackBuffer, 0);
GL.BindBuffer(BufferTarget.PixelUnpackBuffer, 0);
}
this.Image = Image;
this.InternalFormat = InternalFormat;
this.PixelFormat = PixelFormat;
this.PixelType = PixelType;
Initialized = true;
}
if (Initialized)
{
GL.BindBuffer(BufferTarget.PixelPackBuffer, 0);
GL.BindBuffer(BufferTarget.PixelUnpackBuffer, 0);
}
Image = NewImage;
this.InternalFormat = InternalFmt;
this.PixelFormat = PixelFormat;
this.PixelType = PixelType;
Initialized = true;
}
public bool HasColor { get => ImageFormatConverter.HasColor(Format); }
public bool HasDepth { get => ImageFormatConverter.HasDepth(Format); }
public bool HasStencil { get => ImageFormatConverter.HasStencil(Format); }
public bool HasColor => ImageUtils.HasColor(Image.Format);
public bool HasDepth => ImageUtils.HasDepth(Image.Format);
public bool HasStencil => ImageUtils.HasStencil(Image.Format);
}
}

109
Ryujinx.Graphics/Gal/OpenGL/OGLEnumConverter.cs
View file

@ -129,52 +129,51 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
switch (Format)
{
case GalImageFormat.R32G32B32A32_SFLOAT: return (PixelInternalFormat.Rgba32f, PixelFormat.Rgba, PixelType.Float);
case GalImageFormat.R32G32B32A32_SINT: return (PixelInternalFormat.Rgba32i, PixelFormat.RgbaInteger, PixelType.Int);
case GalImageFormat.R32G32B32A32_UINT: return (PixelInternalFormat.Rgba32ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt);
case GalImageFormat.R16G16B16A16_SFLOAT: return (PixelInternalFormat.Rgba16f, PixelFormat.Rgba, PixelType.HalfFloat);
case GalImageFormat.R16G16B16A16_SINT: return (PixelInternalFormat.Rgba16i, PixelFormat.RgbaInteger, PixelType.Short);
case GalImageFormat.R16G16B16A16_UINT: return (PixelInternalFormat.Rgba16ui, PixelFormat.RgbaInteger, PixelType.UnsignedShort);
case GalImageFormat.R32G32_SFLOAT: return (PixelInternalFormat.Rg32f, PixelFormat.Rg, PixelType.Float);
case GalImageFormat.R32G32_SINT: return (PixelInternalFormat.Rg32i, PixelFormat.RgInteger, PixelType.Int);
case GalImageFormat.R32G32_UINT: return (PixelInternalFormat.Rg32ui, PixelFormat.RgInteger, PixelType.UnsignedInt);
case GalImageFormat.A8B8G8R8_SNORM_PACK32: return (PixelInternalFormat.Rgba8Snorm, PixelFormat.Rgba, PixelType.Byte);
case GalImageFormat.A8B8G8R8_UNORM_PACK32: return (PixelInternalFormat.Rgba8, PixelFormat.Rgba, PixelType.UnsignedByte);
case GalImageFormat.A8B8G8R8_SINT_PACK32: return (PixelInternalFormat.Rgba8i, PixelFormat.RgbaInteger, PixelType.Byte);
case GalImageFormat.A8B8G8R8_UINT_PACK32: return (PixelInternalFormat.Rgba8ui, PixelFormat.RgbaInteger, PixelType.UnsignedByte);
case GalImageFormat.A8B8G8R8_SRGB_PACK32: return (PixelInternalFormat.Srgb8Alpha8, PixelFormat.Rgba, PixelType.UnsignedByte);
case GalImageFormat.A2B10G10R10_UINT_PACK32: return (PixelInternalFormat.Rgb10A2ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt2101010Reversed);
case GalImageFormat.A2B10G10R10_UNORM_PACK32: return (PixelInternalFormat.Rgb10A2, PixelFormat.Rgba, PixelType.UnsignedInt2101010Reversed);
case GalImageFormat.R32_SFLOAT: return (PixelInternalFormat.R32f, PixelFormat.Red, PixelType.Float);
case GalImageFormat.R32_SINT: return (PixelInternalFormat.R32i, PixelFormat.Red, PixelType.Int);
case GalImageFormat.R32_UINT: return (PixelInternalFormat.R32ui, PixelFormat.Red, PixelType.UnsignedInt);
case GalImageFormat.A1R5G5B5_UNORM_PACK16: return (PixelInternalFormat.Rgb5A1, PixelFormat.Rgba, PixelType.UnsignedShort5551);
case GalImageFormat.B5G6R5_UNORM_PACK16: return (PixelInternalFormat.Rgba, PixelFormat.Rgb, PixelType.UnsignedShort565);
case GalImageFormat.R16G16_SFLOAT: return (PixelInternalFormat.Rg16f, PixelFormat.Rg, PixelType.HalfFloat);
case GalImageFormat.R16G16_SINT: return (PixelInternalFormat.Rg16i, PixelFormat.RgInteger, PixelType.Short);
case GalImageFormat.R16G16_SNORM: return (PixelInternalFormat.Rg16Snorm, PixelFormat.Rg, PixelType.Byte);
case GalImageFormat.R16G16_UNORM: return (PixelInternalFormat.Rg16, PixelFormat.Rg, PixelType.UnsignedShort);
case GalImageFormat.R8G8_SINT: return (PixelInternalFormat.Rg8i, PixelFormat.RgInteger, PixelType.Byte);
case GalImageFormat.R8G8_SNORM: return (PixelInternalFormat.Rg8Snorm, PixelFormat.Rg, PixelType.Byte);
case GalImageFormat.R8G8_UINT: return (PixelInternalFormat.Rg8ui, PixelFormat.RgInteger, PixelType.UnsignedByte);
case GalImageFormat.R8G8_UNORM: return (PixelInternalFormat.Rg8, PixelFormat.Rg, PixelType.UnsignedByte);
case GalImageFormat.R16_SFLOAT: return (PixelInternalFormat.R16f, PixelFormat.Red, PixelType.HalfFloat);
case GalImageFormat.R16_SINT: return (PixelInternalFormat.R16i, PixelFormat.RedInteger, PixelType.Short);
case GalImageFormat.R16_SNORM: return (PixelInternalFormat.R16Snorm, PixelFormat.Red, PixelType.Byte);
case GalImageFormat.R16_UINT: return (PixelInternalFormat.R16ui, PixelFormat.RedInteger, PixelType.UnsignedShort);
case GalImageFormat.R16_UNORM: return (PixelInternalFormat.R16, PixelFormat.Red, PixelType.UnsignedShort);
case GalImageFormat.R8_SINT: return (PixelInternalFormat.R8i, PixelFormat.RedInteger, PixelType.Byte);
case GalImageFormat.R8_SNORM: return (PixelInternalFormat.R8Snorm, PixelFormat.Red, PixelType.Byte);
case GalImageFormat.R8_UINT: return (PixelInternalFormat.R8ui, PixelFormat.RedInteger, PixelType.UnsignedByte);
case GalImageFormat.R8_UNORM: return (PixelInternalFormat.R8, PixelFormat.Red, PixelType.UnsignedByte);
case GalImageFormat.B10G11R11_UFLOAT_PACK32: return (PixelInternalFormat.R11fG11fB10f, PixelFormat.Rgb, PixelType.UnsignedInt10F11F11FRev);
case GalImageFormat.R32G32B32A32 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rgba32f, PixelFormat.Rgba, PixelType.Float);
case GalImageFormat.R32G32B32A32 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba32i, PixelFormat.RgbaInteger, PixelType.Int);
case GalImageFormat.R32G32B32A32 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba32ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt);
case GalImageFormat.R16G16B16A16 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rgba16f, PixelFormat.Rgba, PixelType.HalfFloat);
case GalImageFormat.R16G16B16A16 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba16i, PixelFormat.RgbaInteger, PixelType.Short);
case GalImageFormat.R16G16B16A16 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba16ui, PixelFormat.RgbaInteger, PixelType.UnsignedShort);
case GalImageFormat.R32G32 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rg32f, PixelFormat.Rg, PixelType.Float);
case GalImageFormat.R32G32 | GalImageFormat.Sint: return (PixelInternalFormat.Rg32i, PixelFormat.RgInteger, PixelType.Int);
case GalImageFormat.R32G32 | GalImageFormat.Uint: return (PixelInternalFormat.Rg32ui, PixelFormat.RgInteger, PixelType.UnsignedInt);
case GalImageFormat.A8B8G8R8 | GalImageFormat.Snorm: return (PixelInternalFormat.Rgba8Snorm, PixelFormat.Rgba, PixelType.Byte);
case GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba8, PixelFormat.Rgba, PixelType.UnsignedByte);
case GalImageFormat.A8B8G8R8 | GalImageFormat.Sint: return (PixelInternalFormat.Rgba8i, PixelFormat.RgbaInteger, PixelType.Byte);
case GalImageFormat.A8B8G8R8 | GalImageFormat.Uint: return (PixelInternalFormat.Rgba8ui, PixelFormat.RgbaInteger, PixelType.UnsignedByte);
case GalImageFormat.A8B8G8R8_SRGB: return (PixelInternalFormat.Srgb8Alpha8, PixelFormat.Rgba, PixelType.UnsignedByte);
case GalImageFormat.A4B4G4R4 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba4, PixelFormat.Rgba, PixelType.UnsignedShort4444Reversed);
case GalImageFormat.A2B10G10R10 | GalImageFormat.Uint: return (PixelInternalFormat.Rgb10A2ui, PixelFormat.RgbaInteger, PixelType.UnsignedInt2101010Reversed);
case GalImageFormat.A2B10G10R10 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgb10A2, PixelFormat.Rgba, PixelType.UnsignedInt2101010Reversed);
case GalImageFormat.R32 | GalImageFormat.Sfloat: return (PixelInternalFormat.R32f, PixelFormat.Red, PixelType.Float);
case GalImageFormat.R32 | GalImageFormat.Sint: return (PixelInternalFormat.R32i, PixelFormat.Red, PixelType.Int);
case GalImageFormat.R32 | GalImageFormat.Uint: return (PixelInternalFormat.R32ui, PixelFormat.Red, PixelType.UnsignedInt);
case GalImageFormat.A1R5G5B5 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgb5A1, PixelFormat.Rgba, PixelType.UnsignedShort5551);
case GalImageFormat.B5G6R5 | GalImageFormat.Unorm: return (PixelInternalFormat.Rgba, PixelFormat.Rgb, PixelType.UnsignedShort565);
case GalImageFormat.R16G16 | GalImageFormat.Sfloat: return (PixelInternalFormat.Rg16f, PixelFormat.Rg, PixelType.HalfFloat);
case GalImageFormat.R16G16 | GalImageFormat.Sint: return (PixelInternalFormat.Rg16i, PixelFormat.RgInteger, PixelType.Short);
case GalImageFormat.R16G16 | GalImageFormat.Snorm: return (PixelInternalFormat.Rg16Snorm, PixelFormat.Rg, PixelType.Byte);
case GalImageFormat.R16G16 | GalImageFormat.Unorm: return (PixelInternalFormat.Rg16, PixelFormat.Rg, PixelType.UnsignedShort);
case GalImageFormat.R8G8 | GalImageFormat.Sint: return (PixelInternalFormat.Rg8i, PixelFormat.RgInteger, PixelType.Byte);
case GalImageFormat.R8G8 | GalImageFormat.Snorm: return (PixelInternalFormat.Rg8Snorm, PixelFormat.Rg, PixelType.Byte);
case GalImageFormat.R8G8 | GalImageFormat.Uint: return (PixelInternalFormat.Rg8ui, PixelFormat.RgInteger, PixelType.UnsignedByte);
case GalImageFormat.R8G8 | GalImageFormat.Unorm: return (PixelInternalFormat.Rg8, PixelFormat.Rg, PixelType.UnsignedByte);
case GalImageFormat.R16 | GalImageFormat.Sfloat: return (PixelInternalFormat.R16f, PixelFormat.Red, PixelType.HalfFloat);
case GalImageFormat.R16 | GalImageFormat.Sint: return (PixelInternalFormat.R16i, PixelFormat.RedInteger, PixelType.Short);
case GalImageFormat.R16 | GalImageFormat.Snorm: return (PixelInternalFormat.R16Snorm, PixelFormat.Red, PixelType.Byte);
case GalImageFormat.R16 | GalImageFormat.Uint: return (PixelInternalFormat.R16ui, PixelFormat.RedInteger, PixelType.UnsignedShort);
case GalImageFormat.R16 | GalImageFormat.Unorm: return (PixelInternalFormat.R16, PixelFormat.Red, PixelType.UnsignedShort);
case GalImageFormat.R8 | GalImageFormat.Sint: return (PixelInternalFormat.R8i, PixelFormat.RedInteger, PixelType.Byte);
case GalImageFormat.R8 | GalImageFormat.Snorm: return (PixelInternalFormat.R8Snorm, PixelFormat.Red, PixelType.Byte);
case GalImageFormat.R8 | GalImageFormat.Uint: return (PixelInternalFormat.R8ui, PixelFormat.RedInteger, PixelType.UnsignedByte);
case GalImageFormat.R8 | GalImageFormat.Unorm: return (PixelInternalFormat.R8, PixelFormat.Red, PixelType.UnsignedByte);
case GalImageFormat.B10G11R11 | GalImageFormat.Sfloat: return (PixelInternalFormat.R11fG11fB10f, PixelFormat.Rgb, PixelType.UnsignedInt10F11F11FRev);
case GalImageFormat.R4G4B4A4_UNORM_PACK16_REVERSED: return (PixelInternalFormat.Rgba4, PixelFormat.Rgba, PixelType.UnsignedShort4444Reversed);
case GalImageFormat.D24_UNORM_S8_UINT: return (PixelInternalFormat.Depth24Stencil8, PixelFormat.DepthStencil, PixelType.UnsignedInt248);
case GalImageFormat.D32_SFLOAT: return (PixelInternalFormat.DepthComponent32f, PixelFormat.DepthComponent, PixelType.Float);
case GalImageFormat.D16_UNORM: return (PixelInternalFormat.DepthComponent16, PixelFormat.DepthComponent, PixelType.UnsignedShort);
case GalImageFormat.D32_SFLOAT_S8_UINT: return (PixelInternalFormat.Depth32fStencil8, PixelFormat.DepthStencil, PixelType.Float32UnsignedInt248Rev);
case GalImageFormat.D24_S8 | GalImageFormat.Unorm: return (PixelInternalFormat.Depth24Stencil8, PixelFormat.DepthStencil, PixelType.UnsignedInt248);
case GalImageFormat.D32 | GalImageFormat.Sfloat: return (PixelInternalFormat.DepthComponent32f, PixelFormat.DepthComponent, PixelType.Float);
case GalImageFormat.D16 | GalImageFormat.Unorm: return (PixelInternalFormat.DepthComponent16, PixelFormat.DepthComponent, PixelType.UnsignedShort);
case GalImageFormat.D32_S8 | GalImageFormat.Uint: return (PixelInternalFormat.Depth32fStencil8, PixelFormat.DepthStencil, PixelType.Float32UnsignedInt248Rev);
}
throw new NotImplementedException(Format.ToString());
@ -184,16 +183,16 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
switch (Format)
{
case GalImageFormat.BC6H_UFLOAT_BLOCK: return InternalFormat.CompressedRgbBptcUnsignedFloat;
case GalImageFormat.BC6H_SFLOAT_BLOCK: return InternalFormat.CompressedRgbBptcSignedFloat;
case GalImageFormat.BC7_UNORM_BLOCK: return InternalFormat.CompressedRgbaBptcUnorm;
case GalImageFormat.BC1_RGBA_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt1Ext;
case GalImageFormat.BC2_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt3Ext;
case GalImageFormat.BC3_UNORM_BLOCK: return InternalFormat.CompressedRgbaS3tcDxt5Ext;
case GalImageFormat.BC4_SNORM_BLOCK: return InternalFormat.CompressedSignedRedRgtc1;
case GalImageFormat.BC4_UNORM_BLOCK: return InternalFormat.CompressedRedRgtc1;
case GalImageFormat.BC5_SNORM_BLOCK: return InternalFormat.CompressedSignedRgRgtc2;
case GalImageFormat.BC5_UNORM_BLOCK: return InternalFormat.CompressedRgRgtc2;
case GalImageFormat.BC6H_UF16 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbBptcUnsignedFloat;
case GalImageFormat.BC6H_SF16 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbBptcSignedFloat;
case GalImageFormat.BC7 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaBptcUnorm;
case GalImageFormat.BC1_RGBA | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt1Ext;
case GalImageFormat.BC2 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt3Ext;
case GalImageFormat.BC3 | GalImageFormat.Unorm: return InternalFormat.CompressedRgbaS3tcDxt5Ext;
case GalImageFormat.BC4 | GalImageFormat.Snorm: return InternalFormat.CompressedSignedRedRgtc1;
case GalImageFormat.BC4 | GalImageFormat.Unorm: return InternalFormat.CompressedRedRgtc1;
case GalImageFormat.BC5 | GalImageFormat.Snorm: return InternalFormat.CompressedSignedRgRgtc2;
case GalImageFormat.BC5 | GalImageFormat.Unorm: return InternalFormat.CompressedRgRgtc2;
}
throw new NotImplementedException(Format.ToString());

9
Ryujinx.Graphics/Gal/OpenGL/OGLFrameBuffer.cs → Ryujinx.Graphics/Gal/OpenGL/OGLRenderTarget.cs
View file

@ -1,9 +1,10 @@
using OpenTK.Graphics.OpenGL;
using Ryujinx.Graphics.Texture;
using System;
namespace Ryujinx.Graphics.Gal.OpenGL
{
class OGLFrameBuffer : IGalFrameBuffer
class OGLRenderTarget : IGalRenderTarget
{
private struct Rect
{
@ -24,7 +25,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
private const int NativeWidth = 1280;
private const int NativeHeight = 720;
private const GalImageFormat RawFormat = GalImageFormat.A8B8G8R8_UNORM_PACK32;
private const GalImageFormat RawFormat = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm;
private OGLTexture Texture;
@ -56,7 +57,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
private int DepthAttachment;
private int StencilAttachment;
public OGLFrameBuffer(OGLTexture Texture)
public OGLRenderTarget(OGLTexture Texture)
{
ColorAttachments = new int[8];
@ -379,7 +380,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
if (Texture.TryGetImage(Key, out ImageHandler Tex))
{
byte[] Data = new byte[Tex.Width * Tex.Height * ImageHandler.MaxBpp];
byte[] Data = new byte[ImageUtils.GetSize(Tex.Image)];
GL.BindTexture(TextureTarget.Texture2D, Tex.Handle);

4
Ryujinx.Graphics/Gal/OpenGL/OGLRenderer.cs
View file

@ -7,7 +7,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
public IGalConstBuffer Buffer { get; private set; }
public IGalFrameBuffer FrameBuffer { get; private set; }
public IGalRenderTarget RenderTarget { get; private set; }
public IGalRasterizer Rasterizer { get; private set; }
@ -25,7 +25,7 @@ namespace Ryujinx.Graphics.Gal.OpenGL
Texture = new OGLTexture();
FrameBuffer = new OGLFrameBuffer(Texture as OGLTexture);
RenderTarget = new OGLRenderTarget(Texture as OGLTexture);
Rasterizer = new OGLRasterizer();

99
Ryujinx.Graphics/Gal/OpenGL/OGLTexture.cs
View file

@ -1,5 +1,5 @@
using OpenTK.Graphics.OpenGL;
using Ryujinx.Graphics.Gal.Texture;
using Ryujinx.Graphics.Texture;
using System;
namespace Ryujinx.Graphics.Gal.OpenGL
@ -39,7 +39,11 @@ namespace Ryujinx.Graphics.Gal.OpenGL
const int Level = 0; //TODO: Support mipmap textures.
const int Border = 0;
if (IsCompressedTextureFormat(Image.Format))
GalImageFormat TypeLess = Image.Format & GalImageFormat.FormatMask;
bool IsASTC = TypeLess >= GalImageFormat.ASTC_BEGIN && TypeLess <= GalImageFormat.ASTC_END;
if (ImageUtils.IsCompressed(Image.Format) && !IsASTC)
{
InternalFormat InternalFmt = OGLEnumConverter.GetCompressedImageFormat(Image.Format);
@ -55,7 +59,8 @@ namespace Ryujinx.Graphics.Gal.OpenGL
}
else
{
if (Image.Format >= GalImageFormat.ASTC_BEGIN && Image.Format <= GalImageFormat.ASTC_END)
//TODO: Use KHR_texture_compression_astc_hdr when available
if (IsASTC)
{
int TextureBlockWidth = GetAstcBlockWidth(Image.Format);
int TextureBlockHeight = GetAstcBlockHeight(Image.Format);
@ -67,7 +72,17 @@ namespace Ryujinx.Graphics.Gal.OpenGL
Image.Width,
Image.Height, 1);
Image.Format = GalImageFormat.A8B8G8R8_UNORM_PACK32;
Image.Format = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm;
}
else if (TypeLess == GalImageFormat.G8R8)
{
Data = ImageConverter.G8R8ToR8G8(
Data,
Image.Width,
Image.Height,
1);
Image.Format = GalImageFormat.R8G8 | (Image.Format & GalImageFormat.FormatMask);
}
(PixelInternalFormat InternalFormat, PixelFormat Format, PixelType Type) = OGLEnumConverter.GetImageFormat(Image.Format);
@ -123,20 +138,20 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
switch (Format)
{
case GalImageFormat.ASTC_4x4_UNORM_BLOCK: return 4;
case GalImageFormat.ASTC_5x5_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_6x6_UNORM_BLOCK: return 6;
case GalImageFormat.ASTC_8x8_UNORM_BLOCK: return 8;
case GalImageFormat.ASTC_10x10_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_12x12_UNORM_BLOCK: return 12;
case GalImageFormat.ASTC_5x4_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_6x5_UNORM_BLOCK: return 6;
case GalImageFormat.ASTC_8x6_UNORM_BLOCK: return 8;
case GalImageFormat.ASTC_10x8_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_12x10_UNORM_BLOCK: return 12;
case GalImageFormat.ASTC_8x5_UNORM_BLOCK: return 8;
case GalImageFormat.ASTC_10x5_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_10x6_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_4x4 | GalImageFormat.Unorm: return 4;
case GalImageFormat.ASTC_5x5 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_6x6 | GalImageFormat.Unorm: return 6;
case GalImageFormat.ASTC_8x8 | GalImageFormat.Unorm: return 8;
case GalImageFormat.ASTC_10x10 | GalImageFormat.Unorm: return 10;
case GalImageFormat.ASTC_12x12 | GalImageFormat.Unorm: return 12;
case GalImageFormat.ASTC_5x4 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_6x5 | GalImageFormat.Unorm: return 6;
case GalImageFormat.ASTC_8x6 | GalImageFormat.Unorm: return 8;
case GalImageFormat.ASTC_10x8 | GalImageFormat.Unorm: return 10;
case GalImageFormat.ASTC_12x10 | GalImageFormat.Unorm: return 12;
case GalImageFormat.ASTC_8x5 | GalImageFormat.Unorm: return 8;
case GalImageFormat.ASTC_10x5 | GalImageFormat.Unorm: return 10;
case GalImageFormat.ASTC_10x6 | GalImageFormat.Unorm: return 10;
}
throw new ArgumentException(nameof(Format));
@ -146,20 +161,20 @@ namespace Ryujinx.Graphics.Gal.OpenGL
{
switch (Format)
{
case GalImageFormat.ASTC_4x4_UNORM_BLOCK: return 4;
case GalImageFormat.ASTC_5x5_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_6x6_UNORM_BLOCK: return 6;
case GalImageFormat.ASTC_8x8_UNORM_BLOCK: return 8;
case GalImageFormat.ASTC_10x10_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_12x12_UNORM_BLOCK: return 12;
case GalImageFormat.ASTC_5x4_UNORM_BLOCK: return 4;
case GalImageFormat.ASTC_6x5_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_8x6_UNORM_BLOCK: return 6;
case GalImageFormat.ASTC_10x8_UNORM_BLOCK: return 8;
case GalImageFormat.ASTC_12x10_UNORM_BLOCK: return 10;
case GalImageFormat.ASTC_8x5_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_10x5_UNORM_BLOCK: return 5;
case GalImageFormat.ASTC_10x6_UNORM_BLOCK: return 6;
case GalImageFormat.ASTC_4x4 | GalImageFormat.Unorm: return 4;
case GalImageFormat.ASTC_5x5 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_6x6 | GalImageFormat.Unorm: return 6;
case GalImageFormat.ASTC_8x8 | GalImageFormat.Unorm: return 8;
case GalImageFormat.ASTC_10x10 | GalImageFormat.Unorm: return 10;
case GalImageFormat.ASTC_12x12 | GalImageFormat.Unorm: return 12;
case GalImageFormat.ASTC_5x4 | GalImageFormat.Unorm: return 4;
case GalImageFormat.ASTC_6x5 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_8x6 | GalImageFormat.Unorm: return 6;
case GalImageFormat.ASTC_10x8 | GalImageFormat.Unorm: return 8;
case GalImageFormat.ASTC_12x10 | GalImageFormat.Unorm: return 10;
case GalImageFormat.ASTC_8x5 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_10x5 | GalImageFormat.Unorm: return 5;
case GalImageFormat.ASTC_10x6 | GalImageFormat.Unorm: return 6;
}
throw new ArgumentException(nameof(Format));
@ -216,25 +231,5 @@ namespace Ryujinx.Graphics.Gal.OpenGL
GL.TexParameter(TextureTarget.Texture2D, TextureParameterName.TextureBorderColor, Color);
}
private static bool IsCompressedTextureFormat(GalImageFormat Format)
{
switch (Format)
{
case GalImageFormat.BC6H_UFLOAT_BLOCK:
case GalImageFormat.BC6H_SFLOAT_BLOCK:
case GalImageFormat.BC7_UNORM_BLOCK:
case GalImageFormat.BC1_RGBA_UNORM_BLOCK:
case GalImageFormat.BC2_UNORM_BLOCK:
case GalImageFormat.BC3_UNORM_BLOCK:
case GalImageFormat.BC4_SNORM_BLOCK:
case GalImageFormat.BC4_UNORM_BLOCK:
case GalImageFormat.BC5_SNORM_BLOCK:
case GalImageFormat.BC5_UNORM_BLOCK:
return true;
}
return false;
}
}
}

400
Ryujinx.Graphics/Gal/Shader/ShaderDecodeAlu.cs
View file

@ -33,20 +33,20 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Fadd_I32(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperA = GetOperGpr8 (OpCode);
ShaderIrNode OperB = GetOperImmf32_20(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB = OpCode.Immf32_20();
bool NegB = ((OpCode >> 53) & 1) != 0;
bool AbsA = ((OpCode >> 54) & 1) != 0;
bool NegA = ((OpCode >> 56) & 1) != 0;
bool AbsB = ((OpCode >> 57) & 1) != 0;
bool NegB = OpCode.Read(53);
bool AbsA = OpCode.Read(54);
bool NegA = OpCode.Read(56);
bool AbsB = OpCode.Read(57);
OperA = GetAluFabsFneg(OperA, AbsA, NegA);
OperB = GetAluFabsFneg(OperB, AbsB, NegB);
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Fadd, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
public static void Fadd_R(ShaderIrBlock Block, long OpCode, long Position)
@ -91,12 +91,12 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Fmul_I32(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperA = GetOperGpr8 (OpCode);
ShaderIrNode OperB = GetOperImmf32_20(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB = OpCode.Immf32_20();
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Fmul, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
public static void Fmul_C(ShaderIrBlock Block, long OpCode, long Position)
@ -156,16 +156,16 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Iadd_I32(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperA = GetOperGpr8 (OpCode);
ShaderIrNode OperB = GetOperImm32_20(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB = OpCode.Imm32_20();
bool NegA = ((OpCode >> 56) & 1) != 0;
bool NegA = OpCode.Read(56);
OperA = GetAluIneg(OperA, NegA);
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Add, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
public static void Iadd_R(ShaderIrBlock Block, long OpCode, long Position)
@ -205,16 +205,16 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Ipa(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperA = GetOperAbuf28(OpCode);
ShaderIrNode OperB = GetOperGpr20 (OpCode);
ShaderIrNode OperA = OpCode.Abuf28();
ShaderIrNode OperB = OpCode.Gpr20();
ShaderIpaMode Mode = (ShaderIpaMode)((OpCode >> 54) & 3);
ShaderIpaMode Mode = (ShaderIpaMode)(OpCode.Read(54, 3));
ShaderIrMetaIpa Meta = new ShaderIrMetaIpa(Mode);
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Ipa, OperA, OperB, null, Meta);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
public static void Iscadd_C(ShaderIrBlock Block, long OpCode, long Position)
@ -264,10 +264,10 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Lop_I32(ShaderIrBlock Block, long OpCode, long Position)
{
int SubOp = (int)(OpCode >> 53) & 3;
int SubOp = OpCode.Read(53, 3);
bool InvA = ((OpCode >> 55) & 1) != 0;
bool InvB = ((OpCode >> 56) & 1) != 0;
bool InvA = OpCode.Read(55);
bool InvB = OpCode.Read(56);
ShaderIrInst Inst = 0;
@ -278,21 +278,21 @@ namespace Ryujinx.Graphics.Gal.Shader
case 2: Inst = ShaderIrInst.Xor; break;
}
ShaderIrNode OperB = GetAluNot(GetOperImm32_20(OpCode), InvB);
ShaderIrNode OperB = GetAluNot(OpCode.Imm32_20(), InvB);
//SubOp == 3 is pass, used by the not instruction
//which just moves the inverted register value.
if (SubOp < 3)
{
ShaderIrNode OperA = GetAluNot(GetOperGpr8(OpCode), InvA);
ShaderIrNode OperA = GetAluNot(OpCode.Gpr8(), InvA);
ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
else
{
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperB), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperB)));
}
}
@ -313,10 +313,10 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Mufu(ShaderIrBlock Block, long OpCode, long Position)
{
int SubOp = (int)(OpCode >> 20) & 0xf;
int SubOp = OpCode.Read(20, 0xf);
bool AbsA = ((OpCode >> 46) & 1) != 0;
bool NegA = ((OpCode >> 48) & 1) != 0;
bool AbsA = OpCode.Read(46);
bool NegA = OpCode.Read(48);
ShaderIrInst Inst = 0;
@ -333,23 +333,23 @@ namespace Ryujinx.Graphics.Gal.Shader
default: throw new NotImplementedException(SubOp.ToString());
}
ShaderIrNode OperA = GetOperGpr8(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrOp Op = new ShaderIrOp(Inst, GetAluFabsFneg(OperA, AbsA, NegA));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
public static void Psetp(ShaderIrBlock Block, long OpCode, long Position)
{
bool NegA = ((OpCode >> 15) & 1) != 0;
bool NegB = ((OpCode >> 32) & 1) != 0;
bool NegP = ((OpCode >> 42) & 1) != 0;
bool NegA = OpCode.Read(15);
bool NegB = OpCode.Read(32);
bool NegP = OpCode.Read(42);
ShaderIrInst LopInst = GetBLop24(OpCode);
ShaderIrInst LopInst = OpCode.BLop24();
ShaderIrNode OperA = GetOperPred12(OpCode);
ShaderIrNode OperB = GetOperPred29(OpCode);
ShaderIrNode OperA = OpCode.Pred12();
ShaderIrNode OperB = OpCode.Pred29();
if (NegA)
{
@ -363,13 +363,13 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOp Op = new ShaderIrOp(LopInst, OperA, OperB);
ShaderIrOperPred P0Node = GetOperPred3 (OpCode);
ShaderIrOperPred P1Node = GetOperPred0 (OpCode);
ShaderIrOperPred P2Node = GetOperPred39(OpCode);
ShaderIrOperPred P0Node = OpCode.Pred3();
ShaderIrOperPred P1Node = OpCode.Pred0();
ShaderIrOperPred P2Node = OpCode.Pred39();
Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op)));
LopInst = GetBLop45(OpCode);
LopInst = OpCode.BLop45();
if (LopInst == ShaderIrInst.Band && P1Node.IsConst && P2Node.IsConst)
{
@ -387,11 +387,11 @@ namespace Ryujinx.Graphics.Gal.Shader
Op = new ShaderIrOp(LopInst, Op, P2NNode);
Block.AddNode(GetPredNode(new ShaderIrAsg(P1Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P1Node, Op)));
Op = new ShaderIrOp(LopInst, P0Node, P2NNode);
Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op)));
}
public static void Rro_C(ShaderIrBlock Block, long OpCode, long Position)
@ -441,33 +441,33 @@ namespace Ryujinx.Graphics.Gal.Shader
private static ShaderIrInst GetShrInst(long OpCode)
{
bool Signed = ((OpCode >> 48) & 1) != 0;
bool Signed = OpCode.Read(48);
return Signed ? ShaderIrInst.Asr : ShaderIrInst.Lsr;
}
public static void Vmad(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperA = GetOperGpr8(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB;
if (((OpCode >> 50) & 1) != 0)
if (OpCode.Read(50))
{
OperB = GetOperGpr20(OpCode);
OperB = OpCode.Gpr20();
}
else
{
OperB = GetOperImm19_20(OpCode);
OperB = OpCode.Imm19_20();
}
ShaderIrOperGpr OperC = GetOperGpr39(OpCode);
ShaderIrOperGpr OperC = OpCode.Gpr39();
ShaderIrNode Tmp = new ShaderIrOp(ShaderIrInst.Mul, OperA, OperB);
ShaderIrNode Final = new ShaderIrOp(ShaderIrInst.Add, Tmp, OperC);
int Shr = (int)((OpCode >> 51) & 3);
int Shr = OpCode.Read(51, 3);
if (Shr != 0)
{
@ -478,7 +478,7 @@ namespace Ryujinx.Graphics.Gal.Shader
Block.AddNode(new ShaderIrCmnt("Stubbed. Instruction is reduced to a * b + c"));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Final), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Final)));
}
public static void Xmad_CR(ShaderIrBlock Block, long OpCode, long Position)
@ -507,20 +507,20 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderOper Oper,
ShaderIrInst Inst)
{
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
ShaderIrNode Op = new ShaderIrOp(Inst, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitBfe(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -528,23 +528,23 @@ namespace Ryujinx.Graphics.Gal.Shader
//TODO: Handle the case where position + length
//is greater than the word size, in this case the sign bit
//needs to be replicated to fill the remaining space.
bool NegB = ((OpCode >> 48) & 1) != 0;
bool NegA = ((OpCode >> 49) & 1) != 0;
bool NegB = OpCode.Read(48);
bool NegA = OpCode.Read(49);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
ShaderIrNode Op;
bool Signed = ((OpCode >> 48) & 1) != 0; //?
bool Signed = OpCode.Read(48); //?
if (OperB is ShaderIrOperImm PosLen)
{
@ -576,25 +576,25 @@ namespace Ryujinx.Graphics.Gal.Shader
Op = ExtendTo32(Op, Signed, OpLen);
}
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitFadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
bool NegB = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 46) & 1) != 0;
bool NegA = ((OpCode >> 48) & 1) != 0;
bool AbsB = ((OpCode >> 49) & 1) != 0;
bool NegB = OpCode.Read(45);
bool AbsA = OpCode.Read(46);
bool NegA = OpCode.Read(48);
bool AbsB = OpCode.Read(49);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
OperA = GetAluFabsFneg(OperA, AbsA, NegA);
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -603,20 +603,20 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fadd, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitFmul(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
bool NegB = ((OpCode >> 48) & 1) != 0;
bool NegB = OpCode.Read(48);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -625,22 +625,22 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrNode Op = new ShaderIrOp(ShaderIrInst.Fmul, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitFfma(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
bool NegB = ((OpCode >> 48) & 1) != 0;
bool NegC = ((OpCode >> 49) & 1) != 0;
bool NegB = OpCode.Read(48);
bool NegC = OpCode.Read(49);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB, OperC;
ShaderIrNode OperA = OpCode.Gpr8(), OperB, OperC;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RC: OperB = GetOperGpr39 (OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RC: OperB = OpCode.Gpr39(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -649,62 +649,62 @@ namespace Ryujinx.Graphics.Gal.Shader
if (Oper == ShaderOper.RC)
{
OperC = GetAluFneg(GetOperCbuf34(OpCode), NegC);
OperC = GetAluFneg(OpCode.Cbuf34(), NegC);
}
else
{
OperC = GetAluFneg(GetOperGpr39(OpCode), NegC);
OperC = GetAluFneg(OpCode.Gpr39(), NegC);
}
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Ffma, OperA, OperB, OperC);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitIadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
ShaderIrNode OperA = GetOperGpr8(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
bool NegA = ((OpCode >> 49) & 1) != 0;
bool NegB = ((OpCode >> 48) & 1) != 0;
bool NegA = OpCode.Read(49);
bool NegB = OpCode.Read(48);
OperA = GetAluIneg(OperA, NegA);
OperB = GetAluIneg(OperB, NegB);
ShaderIrOp Op = new ShaderIrOp(ShaderIrInst.Add, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitIadd3(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
int Mode = (int)((OpCode >> 37) & 3);
int Mode = OpCode.Read(37, 3);
bool Neg1 = ((OpCode >> 51) & 1) != 0;
bool Neg2 = ((OpCode >> 50) & 1) != 0;
bool Neg3 = ((OpCode >> 49) & 1) != 0;
bool Neg1 = OpCode.Read(51);
bool Neg2 = OpCode.Read(50);
bool Neg3 = OpCode.Read(49);
int Height1 = (int)((OpCode >> 35) & 3);
int Height2 = (int)((OpCode >> 33) & 3);
int Height3 = (int)((OpCode >> 31) & 3);
int Height1 = OpCode.Read(35, 3);
int Height2 = OpCode.Read(33, 3);
int Height3 = OpCode.Read(31, 3);
ShaderIrNode OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -726,9 +726,9 @@ namespace Ryujinx.Graphics.Gal.Shader
}
}
ShaderIrNode Src1 = GetAluIneg(ApplyHeight(GetOperGpr8(OpCode), Height1), Neg1);
ShaderIrNode Src1 = GetAluIneg(ApplyHeight(OpCode.Gpr8(), Height1), Neg1);
ShaderIrNode Src2 = GetAluIneg(ApplyHeight(OperB, Height2), Neg2);
ShaderIrNode Src3 = GetAluIneg(ApplyHeight(GetOperGpr39(OpCode), Height3), Neg3);
ShaderIrNode Src3 = GetAluIneg(ApplyHeight(OpCode.Gpr39(), Height3), Neg3);
ShaderIrOp Sum = new ShaderIrOp(ShaderIrInst.Add, Src1, Src2);
@ -744,23 +744,23 @@ namespace Ryujinx.Graphics.Gal.Shader
//Note: Here there should be a "+ 1" when carry flag is set
//but since carry is mostly ignored by other instructions, it's excluded for now
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), new ShaderIrOp(ShaderIrInst.Add, Sum, Src3)), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), new ShaderIrOp(ShaderIrInst.Add, Sum, Src3))));
}
private static void EmitIscadd(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
bool NegB = ((OpCode >> 48) & 1) != 0;
bool NegA = ((OpCode >> 49) & 1) != 0;
bool NegB = OpCode.Read(48);
bool NegA = OpCode.Read(49);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
ShaderIrOperImm Scale = GetOperImm5_39(OpCode);
ShaderIrOperImm Scale = OpCode.Imm5_39();
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -771,7 +771,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOp ScaleOp = new ShaderIrOp(ShaderIrInst.Lsl, OperA, Scale);
ShaderIrOp AddOp = new ShaderIrOp(ShaderIrInst.Add, OperB, ScaleOp);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), AddOp), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), AddOp)));
}
private static void EmitFmnmx(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -786,12 +786,12 @@ namespace Ryujinx.Graphics.Gal.Shader
private static void EmitMnmx(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper)
{
bool NegB = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 46) & 1) != 0;
bool NegA = ((OpCode >> 48) & 1) != 0;
bool AbsB = ((OpCode >> 49) & 1) != 0;
bool NegB = OpCode.Read(45);
bool AbsA = OpCode.Read(46);
bool NegA = OpCode.Read(48);
bool AbsB = OpCode.Read(49);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
if (IsFloat)
{
@ -804,10 +804,10 @@ namespace Ryujinx.Graphics.Gal.Shader
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -821,7 +821,7 @@ namespace Ryujinx.Graphics.Gal.Shader
OperB = GetAluIabsIneg(OperB, AbsB, NegB);
}
ShaderIrOperPred Pred = GetOperPred39(OpCode);
ShaderIrOperPred Pred = OpCode.Pred39();
ShaderIrOp Op;
@ -830,26 +830,26 @@ namespace Ryujinx.Graphics.Gal.Shader
if (Pred.IsConst)
{
bool IsMax = ((OpCode >> 42) & 1) != 0;
bool IsMax = OpCode.Read(42);
Op = new ShaderIrOp(IsMax
? MaxInst
: MinInst, OperA, OperB);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
else
{
ShaderIrNode PredN = GetOperPred39N(OpCode);
ShaderIrNode PredN = OpCode.Pred39N();
ShaderIrOp OpMax = new ShaderIrOp(MaxInst, OperA, OperB);
ShaderIrOp OpMin = new ShaderIrOp(MinInst, OperA, OperB);
ShaderIrAsg AsgMax = new ShaderIrAsg(GetOperGpr0(OpCode), OpMax);
ShaderIrAsg AsgMin = new ShaderIrAsg(GetOperGpr0(OpCode), OpMin);
ShaderIrAsg AsgMax = new ShaderIrAsg(OpCode.Gpr0(), OpMax);
ShaderIrAsg AsgMin = new ShaderIrAsg(OpCode.Gpr0(), OpMin);
Block.AddNode(GetPredNode(new ShaderIrCond(PredN, AsgMax, Not: true), OpCode));
Block.AddNode(GetPredNode(new ShaderIrCond(PredN, AsgMin, Not: false), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrCond(PredN, AsgMax, Not: true)));
Block.AddNode(OpCode.PredNode(new ShaderIrCond(PredN, AsgMin, Not: false)));
}
}
@ -857,16 +857,16 @@ namespace Ryujinx.Graphics.Gal.Shader
{
//Note: this is a range reduction instruction and is supposed to
//be used with Mufu, here it just moves the value and ignores the operation.
bool NegA = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 49) & 1) != 0;
bool NegA = OpCode.Read(45);
bool AbsA = OpCode.Read(49);
ShaderIrNode OperA;
switch (Oper)
{
case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperA = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperA = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -875,7 +875,7 @@ namespace Ryujinx.Graphics.Gal.Shader
Block.AddNode(new ShaderIrCmnt("Stubbed."));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA)));
}
private static void EmitFset(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -890,21 +890,21 @@ namespace Ryujinx.Graphics.Gal.Shader
private static void EmitSet(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper)
{
bool NegA = ((OpCode >> 43) & 1) != 0;
bool AbsB = ((OpCode >> 44) & 1) != 0;
bool NegB = ((OpCode >> 53) & 1) != 0;
bool AbsA = ((OpCode >> 54) & 1) != 0;
bool NegA = OpCode.Read(43);
bool AbsB = OpCode.Read(44);
bool NegB = OpCode.Read(53);
bool AbsA = OpCode.Read(54);
bool BoolFloat = ((OpCode >> (IsFloat ? 52 : 44)) & 1) != 0;
bool BoolFloat = OpCode.Read(IsFloat ? 52 : 44);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -916,18 +916,18 @@ namespace Ryujinx.Graphics.Gal.Shader
OperA = GetAluFabsFneg(OperA, AbsA, NegA);
OperB = GetAluFabsFneg(OperB, AbsB, NegB);
CmpInst = GetCmpF(OpCode);
CmpInst = OpCode.CmpF();
}
else
{
CmpInst = GetCmp(OpCode);
CmpInst = OpCode.Cmp();
}
ShaderIrOp Op = new ShaderIrOp(CmpInst, OperA, OperB);
ShaderIrInst LopInst = GetBLop45(OpCode);
ShaderIrInst LopInst = OpCode.BLop45();
ShaderIrOperPred PNode = GetOperPred39(OpCode);
ShaderIrOperPred PNode = OpCode.Pred39();
ShaderIrNode Imm0, Imm1;
@ -942,8 +942,8 @@ namespace Ryujinx.Graphics.Gal.Shader
Imm1 = new ShaderIrOperImm(-1);
}
ShaderIrNode Asg0 = new ShaderIrAsg(GetOperGpr0(OpCode), Imm0);
ShaderIrNode Asg1 = new ShaderIrAsg(GetOperGpr0(OpCode), Imm1);
ShaderIrNode Asg0 = new ShaderIrAsg(OpCode.Gpr0(), Imm0);
ShaderIrNode Asg1 = new ShaderIrAsg(OpCode.Gpr0(), Imm1);
if (LopInst != ShaderIrInst.Band || !PNode.IsConst)
{
@ -958,8 +958,8 @@ namespace Ryujinx.Graphics.Gal.Shader
Asg1 = new ShaderIrCond(Op, Asg1, Not: false);
}
Block.AddNode(GetPredNode(Asg0, OpCode));
Block.AddNode(GetPredNode(Asg1, OpCode));
Block.AddNode(OpCode.PredNode(Asg0));
Block.AddNode(OpCode.PredNode(Asg1));
}
private static void EmitFsetp(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -974,19 +974,19 @@ namespace Ryujinx.Graphics.Gal.Shader
private static void EmitSetp(ShaderIrBlock Block, long OpCode, bool IsFloat, ShaderOper Oper)
{
bool AbsA = ((OpCode >> 7) & 1) != 0;
bool NegP = ((OpCode >> 42) & 1) != 0;
bool NegA = ((OpCode >> 43) & 1) != 0;
bool AbsB = ((OpCode >> 44) & 1) != 0;
bool AbsA = OpCode.Read(7);
bool NegP = OpCode.Read(42);
bool NegA = OpCode.Read(43);
bool AbsB = OpCode.Read(44);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB;
ShaderIrNode OperA = OpCode.Gpr8(), OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20 (OpCode); break;
case ShaderOper.Immf: OperB = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.Immf: OperB = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -998,22 +998,22 @@ namespace Ryujinx.Graphics.Gal.Shader
OperA = GetAluFabsFneg(OperA, AbsA, NegA);
OperB = GetAluFabs (OperB, AbsB);
CmpInst = GetCmpF(OpCode);
CmpInst = OpCode.CmpF();
}
else
{
CmpInst = GetCmp(OpCode);
CmpInst = OpCode.Cmp();
}
ShaderIrOp Op = new ShaderIrOp(CmpInst, OperA, OperB);
ShaderIrOperPred P0Node = GetOperPred3 (OpCode);
ShaderIrOperPred P1Node = GetOperPred0 (OpCode);
ShaderIrOperPred P2Node = GetOperPred39(OpCode);
ShaderIrOperPred P0Node = OpCode.Pred3();
ShaderIrOperPred P1Node = OpCode.Pred0();
ShaderIrOperPred P2Node = OpCode.Pred39();
Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op)));
ShaderIrInst LopInst = GetBLop45(OpCode);
ShaderIrInst LopInst = OpCode.BLop45();
if (LopInst == ShaderIrInst.Band && P1Node.IsConst && P2Node.IsConst)
{
@ -1031,19 +1031,19 @@ namespace Ryujinx.Graphics.Gal.Shader
Op = new ShaderIrOp(LopInst, Op, P2NNode);
Block.AddNode(GetPredNode(new ShaderIrAsg(P1Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P1Node, Op)));
Op = new ShaderIrOp(LopInst, P0Node, P2NNode);
Block.AddNode(GetPredNode(new ShaderIrAsg(P0Node, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(P0Node, Op)));
}
private static void EmitLop(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
int SubOp = (int)(OpCode >> 41) & 3;
int SubOp = OpCode.Read(41, 3);
bool InvA = ((OpCode >> 39) & 1) != 0;
bool InvB = ((OpCode >> 40) & 1) != 0;
bool InvA = OpCode.Read(39);
bool InvB = OpCode.Read(40);
ShaderIrInst Inst = 0;
@ -1054,14 +1054,14 @@ namespace Ryujinx.Graphics.Gal.Shader
case 2: Inst = ShaderIrInst.Xor; break;
}
ShaderIrNode OperA = GetAluNot(GetOperGpr8(OpCode), InvA);
ShaderIrNode OperA = GetAluNot(OpCode.Gpr8(), InvA);
ShaderIrNode OperB;
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -1081,23 +1081,23 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrNode Compare = new ShaderIrOp(ShaderIrInst.Cne, Op, new ShaderIrOperImm(0));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperPred48(OpCode), Compare), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Pred48(), Compare)));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitXmad(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
//TODO: Confirm SignAB/C, it is just a guess.
//TODO: Implement Mode 3 (CSFU), what it does?
bool SignAB = ((OpCode >> 48) & 1) != 0;
bool SignC = ((OpCode >> 49) & 1) != 0;
bool HighB = ((OpCode >> 52) & 1) != 0;
bool HighA = ((OpCode >> 53) & 1) != 0;
bool SignAB = OpCode.Read(48);
bool SignC = OpCode.Read(49);
bool HighB = OpCode.Read(52);
bool HighA = OpCode.Read(53);
int Mode = (int)(OpCode >> 50) & 7;
int Mode = OpCode.Read(50, 7);
ShaderIrNode OperA = GetOperGpr8(OpCode), OperB, OperC;
ShaderIrNode OperA = OpCode.Gpr8(), OperB, OperC;
ShaderIrOperImm Imm16 = new ShaderIrOperImm(16);
ShaderIrOperImm ImmMsk = new ShaderIrOperImm(0xffff);
@ -1112,10 +1112,10 @@ namespace Ryujinx.Graphics.Gal.Shader
switch (Oper)
{
case ShaderOper.CR: OperB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperB = GetOperImm19_20(OpCode); break;
case ShaderOper.RC: OperB = GetOperGpr39 (OpCode); break;
case ShaderOper.RR: OperB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperB = OpCode.Imm19_20(); break;
case ShaderOper.RC: OperB = OpCode.Gpr39(); break;
case ShaderOper.RR: OperB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -1124,14 +1124,14 @@ namespace Ryujinx.Graphics.Gal.Shader
if (Oper == ShaderOper.RC)
{
OperC = GetOperCbuf34(OpCode);
OperC = OpCode.Cbuf34();
}
else
{
OperC = GetOperGpr39(OpCode);
OperC = OpCode.Gpr39();
ProductShiftLeft = ((OpCode >> 36) & 1) != 0;
Merge = ((OpCode >> 37) & 1) != 0;
ProductShiftLeft = OpCode.Read(36);
Merge = OpCode.Read(37);
}
switch (Mode)
@ -1172,7 +1172,7 @@ namespace Ryujinx.Graphics.Gal.Shader
AddOp = new ShaderIrOp(ShaderIrInst.Or, AddOp, OperB);
}
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), AddOp), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), AddOp)));
}
}
}

12
Ryujinx.Graphics/Gal/Shader/ShaderDecodeFlow.cs
View file

@ -15,11 +15,11 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new NotImplementedException();
}
int Target = ((int)(OpCode >> 20) << 8) >> 8;
int Target = OpCode.Branch();
ShaderIrOperImm Imm = new ShaderIrOperImm(Target);
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Bra, Imm), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Bra, Imm)));
}
public static void Exit(ShaderIrBlock Block, long OpCode, long Position)
@ -29,14 +29,14 @@ namespace Ryujinx.Graphics.Gal.Shader
//TODO: Figure out what the other condition codes mean...
if (CCode == 0xf)
{
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Exit), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Exit)));
}
}
public static void Kil(ShaderIrBlock Block, long OpCode, long Position)
{
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Kil), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Kil)));
}
public static void Ssy(ShaderIrBlock Block, long OpCode, long Position)
@ -48,7 +48,7 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new NotImplementedException();
}
int Offset = ((int)(OpCode >> 20) << 8) >> 8;
int Offset = OpCode.Branch();
int Target = (int)(Position + Offset);
@ -61,7 +61,7 @@ namespace Ryujinx.Graphics.Gal.Shader
{
//TODO: Implement Sync condition codes
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Sync), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Sync)));
}
}
}

238
Ryujinx.Graphics/Gal/Shader/ShaderDecodeHelper.cs
View file

@ -4,244 +4,6 @@ namespace Ryujinx.Graphics.Gal.Shader
{
static class ShaderDecodeHelper
{
public static ShaderIrOperAbuf[] GetOperAbuf20(long OpCode)
{
int Abuf = (int)(OpCode >> 20) & 0x3ff;
int Size = (int)(OpCode >> 47) & 3;
ShaderIrOperGpr Vertex = GetOperGpr39(OpCode);
ShaderIrOperAbuf[] Opers = new ShaderIrOperAbuf[Size + 1];
for (int Index = 0; Index <= Size; Index++)
{
Opers[Index] = new ShaderIrOperAbuf(Abuf + Index * 4, Vertex);
}
return Opers;
}
public static ShaderIrOperAbuf GetOperAbuf28(long OpCode)
{
int Abuf = (int)(OpCode >> 28) & 0x3ff;
return new ShaderIrOperAbuf(Abuf, GetOperGpr39(OpCode));
}
public static ShaderIrOperCbuf GetOperCbuf34(long OpCode)
{
return new ShaderIrOperCbuf(
(int)(OpCode >> 34) & 0x1f,
(int)(OpCode >> 20) & 0x3fff);
}
public static ShaderIrOperGpr GetOperGpr8(long OpCode)
{
return new ShaderIrOperGpr((int)(OpCode >> 8) & 0xff);
}
public static ShaderIrOperGpr GetOperGpr20(long OpCode)
{
return new ShaderIrOperGpr((int)(OpCode >> 20) & 0xff);
}
public static ShaderIrOperGpr GetOperGpr39(long OpCode)
{
return new ShaderIrOperGpr((int)(OpCode >> 39) & 0xff);
}
public static ShaderIrOperGpr GetOperGpr0(long OpCode)
{
return new ShaderIrOperGpr((int)(OpCode >> 0) & 0xff);
}
public static ShaderIrOperGpr GetOperGpr28(long OpCode)
{
return new ShaderIrOperGpr((int)(OpCode >> 28) & 0xff);
}
public static ShaderIrOperImm GetOperImm5_39(long OpCode)
{
return new ShaderIrOperImm((int)(OpCode >> 39) & 0x1f);
}
public static ShaderIrOperImm GetOperImm13_36(long OpCode)
{
return new ShaderIrOperImm((int)(OpCode >> 36) & 0x1fff);
}
public static ShaderIrOperImm GetOperImm32_20(long OpCode)
{
return new ShaderIrOperImm((int)(OpCode >> 20));
}
public static ShaderIrOperImmf GetOperImmf32_20(long OpCode)
{
return new ShaderIrOperImmf(BitConverter.Int32BitsToSingle((int)(OpCode >> 20)));
}
public static ShaderIrOperImm GetOperImm19_20(long OpCode)
{
int Value = (int)(OpCode >> 20) & 0x7ffff;
bool Neg = ((OpCode >> 56) & 1) != 0;
if (Neg)
{
Value = -Value;
}
return new ShaderIrOperImm((int)Value);
}
public static ShaderIrOperImmf GetOperImmf19_20(long OpCode)
{
uint Imm = (uint)(OpCode >> 20) & 0x7ffff;
bool Neg = ((OpCode >> 56) & 1) != 0;
Imm <<= 12;
if (Neg)
{
Imm |= 0x80000000;
}
float Value = BitConverter.Int32BitsToSingle((int)Imm);
return new ShaderIrOperImmf(Value);
}
public static ShaderIrOperPred GetOperPred0(long OpCode)
{
return new ShaderIrOperPred((int)(OpCode >> 0) & 7);
}
public static ShaderIrOperPred GetOperPred3(long OpCode)
{
return new ShaderIrOperPred((int)(OpCode >> 3) & 7);
}
public static ShaderIrOperPred GetOperPred12(long OpCode)
{
return new ShaderIrOperPred((int)(OpCode >> 12) & 7);
}
public static ShaderIrOperPred GetOperPred29(long OpCode)
{
return new ShaderIrOperPred((int)(OpCode >> 29) & 7);
}
public static ShaderIrNode GetOperPred39N(long OpCode)
{
ShaderIrNode Node = GetOperPred39(OpCode);
if (((OpCode >> 42) & 1) != 0)
{
Node = new ShaderIrOp(ShaderIrInst.Bnot, Node);
}
return Node;
}
public static ShaderIrOperPred GetOperPred39(long OpCode)
{
return new ShaderIrOperPred((int)(OpCode >> 39) & 7);
}
public static ShaderIrOperPred GetOperPred48(long OpCode)
{
return new ShaderIrOperPred((int)((OpCode >> 48) & 7));
}
public static ShaderIrInst GetCmp(long OpCode)
{
switch ((int)(OpCode >> 49) & 7)
{
case 1: return ShaderIrInst.Clt;
case 2: return ShaderIrInst.Ceq;
case 3: return ShaderIrInst.Cle;
case 4: return ShaderIrInst.Cgt;
case 5: return ShaderIrInst.Cne;
case 6: return ShaderIrInst.Cge;
}
throw new ArgumentException(nameof(OpCode));
}
public static ShaderIrInst GetCmpF(long OpCode)
{
switch ((int)(OpCode >> 48) & 0xf)
{
case 0x1: return ShaderIrInst.Fclt;
case 0x2: return ShaderIrInst.Fceq;
case 0x3: return ShaderIrInst.Fcle;
case 0x4: return ShaderIrInst.Fcgt;
case 0x5: return ShaderIrInst.Fcne;
case 0x6: return ShaderIrInst.Fcge;
case 0x7: return ShaderIrInst.Fcnum;
case 0x8: return ShaderIrInst.Fcnan;
case 0x9: return ShaderIrInst.Fcltu;
case 0xa: return ShaderIrInst.Fcequ;
case 0xb: return ShaderIrInst.Fcleu;
case 0xc: return ShaderIrInst.Fcgtu;
case 0xd: return ShaderIrInst.Fcneu;
case 0xe: return ShaderIrInst.Fcgeu;
}
throw new ArgumentException(nameof(OpCode));
}
public static ShaderIrInst GetBLop45(long OpCode)
{
switch ((int)(OpCode >> 45) & 3)
{
case 0: return ShaderIrInst.Band;
case 1: return ShaderIrInst.Bor;
case 2: return ShaderIrInst.Bxor;
}
throw new ArgumentException(nameof(OpCode));
}
public static ShaderIrInst GetBLop24(long OpCode)
{
switch ((int)(OpCode >> 24) & 3)
{
case 0: return ShaderIrInst.Band;
case 1: return ShaderIrInst.Bor;
case 2: return ShaderIrInst.Bxor;
}
throw new ArgumentException(nameof(OpCode));
}
public static ShaderIrNode GetPredNode(ShaderIrNode Node, long OpCode)
{
ShaderIrOperPred Pred = GetPredNode(OpCode);
if (Pred.Index != ShaderIrOperPred.UnusedIndex)
{
bool Inv = ((OpCode >> 19) & 1) != 0;
Node = new ShaderIrCond(Pred, Node, Inv);
}
return Node;
}
private static ShaderIrOperPred GetPredNode(long OpCode)
{
int Pred = (int)(OpCode >> 16) & 0xf;
if (Pred != 0xf)
{
Pred &= 7;
}
return new ShaderIrOperPred(Pred);
}
public static ShaderIrNode GetAluFabsFneg(ShaderIrNode Node, bool Abs, bool Neg)
{
return GetAluFneg(GetAluFabs(Node, Abs), Neg);

76
Ryujinx.Graphics/Gal/Shader/ShaderDecodeMem.cs
View file

@ -33,28 +33,28 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Ld_A(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode[] Opers = GetOperAbuf20(OpCode);
ShaderIrNode[] Opers = OpCode.Abuf20();
//Used by GS
ShaderIrOperGpr Vertex = GetOperGpr39(OpCode);
ShaderIrOperGpr Vertex = OpCode.Gpr39();
int Index = 0;
foreach (ShaderIrNode OperA in Opers)
{
ShaderIrOperGpr OperD = GetOperGpr0(OpCode);
ShaderIrOperGpr OperD = OpCode.Gpr0();
OperD.Index += Index++;
Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, OperA), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, OperA)));
}
}
public static void Ld_C(ShaderIrBlock Block, long OpCode, long Position)
{
int CbufPos = (int)(OpCode >> 22) & 0x3fff;
int CbufIndex = (int)(OpCode >> 36) & 0x1f;
int Type = (int)(OpCode >> 48) & 7;
int CbufPos = OpCode.Read(22, 0x3fff);
int CbufIndex = OpCode.Read(36, 0x1f);
int Type = OpCode.Read(48, 7);
if (Type > 5)
{
@ -63,7 +63,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOperGpr Temp = ShaderIrOperGpr.MakeTemporary();
Block.AddNode(new ShaderIrAsg(Temp, GetOperGpr8(OpCode)));
Block.AddNode(new ShaderIrAsg(Temp, OpCode.Gpr8()));
int Count = Type == 5 ? 2 : 1;
@ -71,7 +71,7 @@ namespace Ryujinx.Graphics.Gal.Shader
{
ShaderIrOperCbuf OperA = new ShaderIrOperCbuf(CbufIndex, CbufPos, Temp);
ShaderIrOperGpr OperD = GetOperGpr0(OpCode);
ShaderIrOperGpr OperD = OpCode.Gpr0();
OperA.Pos += Index;
OperD.Index += Index;
@ -93,43 +93,43 @@ namespace Ryujinx.Graphics.Gal.Shader
Node = ExtendTo32(Node, Signed, Size);
}
Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, Node), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Node)));
}
}
public static void St_A(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode[] Opers = GetOperAbuf20(OpCode);
ShaderIrNode[] Opers = OpCode.Abuf20();
int Index = 0;
foreach (ShaderIrNode OperA in Opers)
{
ShaderIrOperGpr OperD = GetOperGpr0(OpCode);
ShaderIrOperGpr OperD = OpCode.Gpr0();
OperD.Index += Index++;
Block.AddNode(GetPredNode(new ShaderIrAsg(OperA, OperD), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, OperD)));
}
}
public static void Texq(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrNode OperD = GetOperGpr0(OpCode);
ShaderIrNode OperA = GetOperGpr8(OpCode);
ShaderIrNode OperD = OpCode.Gpr0();
ShaderIrNode OperA = OpCode.Gpr8();
ShaderTexqInfo Info = (ShaderTexqInfo)((OpCode >> 22) & 0x1f);
ShaderTexqInfo Info = (ShaderTexqInfo)(OpCode.Read(22, 0x1f));
ShaderIrMetaTexq Meta0 = new ShaderIrMetaTexq(Info, 0);
ShaderIrMetaTexq Meta1 = new ShaderIrMetaTexq(Info, 1);
ShaderIrNode OperC = GetOperImm13_36(OpCode);
ShaderIrNode OperC = OpCode.Imm13_36();
ShaderIrOp Op0 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta0);
ShaderIrOp Op1 = new ShaderIrOp(ShaderIrInst.Texq, OperA, null, OperC, Meta1);
Block.AddNode(GetPredNode(new ShaderIrAsg(OperD, Op0), OpCode));
Block.AddNode(GetPredNode(new ShaderIrAsg(OperA, Op1), OpCode)); //Is this right?
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperD, Op0)));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OperA, Op1))); //Is this right?
}
public static void Tex(ShaderIrBlock Block, long OpCode, long Position)
@ -149,7 +149,7 @@ namespace Ryujinx.Graphics.Gal.Shader
for (int Index = 0; Index < Coords.Length; Index++)
{
Coords[Index] = GetOperGpr8(OpCode);
Coords[Index] = OpCode.Gpr8();
Coords[Index].Index += Index;
@ -159,11 +159,11 @@ namespace Ryujinx.Graphics.Gal.Shader
}
}
int ChMask = (int)(OpCode >> 31) & 0xf;
int ChMask = OpCode.Read(31, 0xf);
ShaderIrNode OperC = GprHandle
? (ShaderIrNode)GetOperGpr20 (OpCode)
: (ShaderIrNode)GetOperImm13_36(OpCode);
? (ShaderIrNode)OpCode.Gpr20()
: (ShaderIrNode)OpCode.Imm13_36();
ShaderIrInst Inst = GprHandle ? ShaderIrInst.Texb : ShaderIrInst.Texs;
@ -175,7 +175,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOp Op = new ShaderIrOp(Inst, Coords[0], Coords[1], OperC, Meta);
Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
}
int RegInc = 0;
@ -189,7 +189,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOperGpr Src = new ShaderIrOperGpr(TempRegStart + Ch);
ShaderIrOperGpr Dst = GetOperGpr0(OpCode);
ShaderIrOperGpr Dst = OpCode.Gpr0();
Dst.Index += RegInc++;
@ -198,7 +198,7 @@ namespace Ryujinx.Graphics.Gal.Shader
continue;
}
Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
}
}
@ -215,14 +215,14 @@ namespace Ryujinx.Graphics.Gal.Shader
private static void EmitTexs(ShaderIrBlock Block, long OpCode, ShaderIrInst Inst)
{
//TODO: Support other formats.
ShaderIrNode OperA = GetOperGpr8 (OpCode);
ShaderIrNode OperB = GetOperGpr20 (OpCode);
ShaderIrNode OperC = GetOperImm13_36(OpCode);
ShaderIrNode OperA = OpCode.Gpr8();
ShaderIrNode OperB = OpCode.Gpr20();
ShaderIrNode OperC = OpCode.Imm13_36();
int LutIndex;
LutIndex = GetOperGpr0 (OpCode).Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
LutIndex |= GetOperGpr28(OpCode).Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
LutIndex = OpCode.Gpr0 ().Index != ShaderIrOperGpr.ZRIndex ? 1 : 0;
LutIndex |= OpCode.Gpr28().Index != ShaderIrOperGpr.ZRIndex ? 2 : 0;
if (LutIndex == 0)
{
@ -231,7 +231,7 @@ namespace Ryujinx.Graphics.Gal.Shader
return;
}
int ChMask = MaskLut[LutIndex, (OpCode >> 50) & 7];
int ChMask = MaskLut[LutIndex, OpCode.Read(50, 7)];
for (int Ch = 0; Ch < 4; Ch++)
{
@ -241,7 +241,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrOp Op = new ShaderIrOp(Inst, OperA, OperB, OperC, Meta);
Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Op)));
}
int RegInc = 0;
@ -252,11 +252,11 @@ namespace Ryujinx.Graphics.Gal.Shader
switch (LutIndex)
{
case 1: Dst = GetOperGpr0 (OpCode); break;
case 2: Dst = GetOperGpr28(OpCode); break;
case 1: Dst = OpCode.Gpr0(); break;
case 2: Dst = OpCode.Gpr28(); break;
case 3: Dst = (RegInc >> 1) != 0
? GetOperGpr28(OpCode)
: GetOperGpr0 (OpCode); break;
? OpCode.Gpr28()
: OpCode.Gpr0 (); break;
default: throw new InvalidOperationException();
}
@ -279,7 +279,7 @@ namespace Ryujinx.Graphics.Gal.Shader
if (Dst.Index != ShaderIrOperGpr.ZRIndex)
{
Block.AddNode(GetPredNode(new ShaderIrAsg(Dst, Src), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(Dst, Src)));
}
}
}

98
Ryujinx.Graphics/Gal/Shader/ShaderDecodeMove.cs
View file

@ -92,35 +92,35 @@ namespace Ryujinx.Graphics.Gal.Shader
Block.AddNode(new ShaderIrCmnt("Stubbed."));
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), GetOperGpr8(OpCode)), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OpCode.Gpr8())));
}
public static void Mov_C(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrOperCbuf Cbuf = GetOperCbuf34(OpCode);
ShaderIrOperCbuf Cbuf = OpCode.Cbuf34();
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Cbuf), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Cbuf)));
}
public static void Mov_I(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrOperImm Imm = GetOperImm19_20(OpCode);
ShaderIrOperImm Imm = OpCode.Imm19_20();
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Imm), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Imm)));
}
public static void Mov_I32(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrOperImm Imm = GetOperImm32_20(OpCode);
ShaderIrOperImm Imm = OpCode.Imm32_20();
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Imm), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Imm)));
}
public static void Mov_R(ShaderIrBlock Block, long OpCode, long Position)
{
ShaderIrOperGpr Gpr = GetOperGpr20(OpCode);
ShaderIrOperGpr Gpr = OpCode.Gpr20();
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Gpr), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Gpr)));
}
public static void Sel_C(ShaderIrBlock Block, long OpCode, long Position)
@ -145,21 +145,21 @@ namespace Ryujinx.Graphics.Gal.Shader
//Zero is used as a special number to get a valid "0 * 0 + VertexIndex" in a GS
ShaderIrNode Source = new ShaderIrOperImm(0);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Source), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Source)));
}
private static void EmitF2f(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
bool NegA = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 49) & 1) != 0;
bool NegA = OpCode.Read(45);
bool AbsA = OpCode.Read(49);
ShaderIrNode OperA;
switch (Oper)
{
case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperA = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperA = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -173,7 +173,7 @@ namespace Ryujinx.Graphics.Gal.Shader
OperA = new ShaderIrOp(RoundInst, OperA);
}
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA)));
}
private static void EmitF2i(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -188,16 +188,16 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new NotImplementedException();
}
bool NegA = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 49) & 1) != 0;
bool NegA = OpCode.Read(45);
bool AbsA = OpCode.Read(49);
ShaderIrNode OperA;
switch (Oper)
{
case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperA = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperA = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -242,7 +242,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrNode Op = new ShaderIrOp(Inst, OperA);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitI2f(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -257,18 +257,18 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new NotImplementedException();
}
int Sel = (int)(OpCode >> 41) & 3;
int Sel = OpCode.Read(41, 3);
bool NegA = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 49) & 1) != 0;
bool NegA = OpCode.Read(45);
bool AbsA = OpCode.Read(49);
ShaderIrNode OperA;
switch (Oper)
{
case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: OperA = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperA = OpCode.Cbuf34(); break;
case ShaderOper.Imm: OperA = OpCode.Imm19_20(); break;
case ShaderOper.RR: OperA = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -297,7 +297,7 @@ namespace Ryujinx.Graphics.Gal.Shader
ShaderIrNode Op = new ShaderIrOp(Inst, OperA);
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), Op), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), Op)));
}
private static void EmitI2i(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
@ -312,19 +312,19 @@ namespace Ryujinx.Graphics.Gal.Shader
throw new NotImplementedException();
}
int Sel = (int)(OpCode >> 41) & 3;
int Sel = OpCode.Read(41, 3);
bool NegA = ((OpCode >> 45) & 1) != 0;
bool AbsA = ((OpCode >> 49) & 1) != 0;
bool SatA = ((OpCode >> 50) & 1) != 0;
bool NegA = OpCode.Read(45);
bool AbsA = OpCode.Read(49);
bool SatA = OpCode.Read(50);
ShaderIrNode OperA;
switch (Oper)
{
case ShaderOper.CR: OperA = GetOperCbuf34 (OpCode); break;
case ShaderOper.Immf: OperA = GetOperImmf19_20(OpCode); break;
case ShaderOper.RR: OperA = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: OperA = OpCode.Cbuf34(); break;
case ShaderOper.Immf: OperA = OpCode.Immf19_20(); break;
case ShaderOper.RR: OperA = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
@ -372,36 +372,36 @@ namespace Ryujinx.Graphics.Gal.Shader
}
}
Block.AddNode(GetPredNode(new ShaderIrAsg(GetOperGpr0(OpCode), OperA), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrAsg(OpCode.Gpr0(), OperA)));
}
private static void EmitSel(ShaderIrBlock Block, long OpCode, ShaderOper Oper)
{
ShaderIrOperGpr Dst = GetOperGpr0 (OpCode);
ShaderIrNode Pred = GetOperPred39N(OpCode);
ShaderIrOperGpr Dst = OpCode.Gpr0();
ShaderIrNode Pred = OpCode.Pred39N();
ShaderIrNode ResultA = GetOperGpr8(OpCode);
ShaderIrNode ResultA = OpCode.Gpr8();
ShaderIrNode ResultB;
switch (Oper)
{
case ShaderOper.CR: ResultB = GetOperCbuf34 (OpCode); break;
case ShaderOper.Imm: ResultB = GetOperImm19_20(OpCode); break;
case ShaderOper.RR: ResultB = GetOperGpr20 (OpCode); break;
case ShaderOper.CR: ResultB = OpCode.Cbuf34(); break;
case ShaderOper.Imm: ResultB = OpCode.Imm19_20(); break;
case ShaderOper.RR: ResultB = OpCode.Gpr20(); break;
default: throw new ArgumentException(nameof(Oper));
}
Block.AddNode(GetPredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultA), false), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultA), false)));
Block.AddNode(GetPredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultB), true), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrCond(Pred, new ShaderIrAsg(Dst, ResultB), true)));
}
private static IntType GetIntType(long OpCode)
{
bool Signed = ((OpCode >> 13) & 1) != 0;
bool Signed = OpCode.Read(13);
IntType Type = (IntType)((OpCode >> 10) & 3);
IntType Type = (IntType)(OpCode.Read(10, 3));
if (Signed)
{
@ -413,12 +413,12 @@ namespace Ryujinx.Graphics.Gal.Shader
private static FloatType GetFloatType(long OpCode)
{
return (FloatType)((OpCode >> 8) & 3);
return (FloatType)(OpCode.Read(8, 3));
}
private static ShaderIrInst GetRoundInst(long OpCode)
{
switch ((OpCode >> 39) & 3)
switch (OpCode.Read(39, 3))
{
case 1: return ShaderIrInst.Floor;
case 2: return ShaderIrInst.Ceil;

260
Ryujinx.Graphics/Gal/Shader/ShaderDecodeOpCode.cs Normal file
View file

@ -0,0 +1,260 @@
using System;
namespace Ryujinx.Graphics.Gal.Shader
{
static partial class ShaderDecode
{
private static int Read(this long OpCode, int Position, int Mask)
{
return (int)(OpCode >> Position) & Mask;
}
private static bool Read(this long OpCode, int Position)
{
return ((OpCode >> Position) & 1) != 0;
}
private static int Branch(this long OpCode)
{
return ((int)(OpCode >> 20) << 8) >> 8;
}
private static ShaderIrOperAbuf[] Abuf20(this long OpCode)
{
int Abuf = OpCode.Read(20, 0x3ff);
int Size = OpCode.Read(47, 3);
ShaderIrOperGpr Vertex = OpCode.Gpr39();
ShaderIrOperAbuf[] Opers = new ShaderIrOperAbuf[Size + 1];
for (int Index = 0; Index <= Size; Index++)
{
Opers[Index] = new ShaderIrOperAbuf(Abuf + Index * 4, Vertex);
}
return Opers;
}
private static ShaderIrOperAbuf Abuf28(this long OpCode)
{
int Abuf = OpCode.Read(28, 0x3ff);
return new ShaderIrOperAbuf(Abuf, OpCode.Gpr39());
}
private static ShaderIrOperCbuf Cbuf34(this long OpCode)
{
return new ShaderIrOperCbuf(
OpCode.Read(34, 0x1f),
OpCode.Read(20, 0x3fff));
}
private static ShaderIrOperGpr Gpr8(this long OpCode)
{
return new ShaderIrOperGpr(OpCode.Read(8, 0xff));
}
private static ShaderIrOperGpr Gpr20(this long OpCode)
{
return new ShaderIrOperGpr(OpCode.Read(20, 0xff));
}
private static ShaderIrOperGpr Gpr39(this long OpCode)
{
return new ShaderIrOperGpr(OpCode.Read(39, 0xff));
}
private static ShaderIrOperGpr Gpr0(this long OpCode)
{
return new ShaderIrOperGpr(OpCode.Read(0, 0xff));
}
private static ShaderIrOperGpr Gpr28(this long OpCode)
{
return new ShaderIrOperGpr(OpCode.Read(28, 0xff));
}
private static ShaderIrOperImm Imm5_39(this long OpCode)
{
return new ShaderIrOperImm(OpCode.Read(39, 0x1f));
}
private static ShaderIrOperImm Imm13_36(this long OpCode)
{
return new ShaderIrOperImm(OpCode.Read(36, 0x1fff));
}
private static ShaderIrOperImm Imm32_20(this long OpCode)
{
return new ShaderIrOperImm((int)(OpCode >> 20));
}
private static ShaderIrOperImmf Immf32_20(this long OpCode)
{
return new ShaderIrOperImmf(BitConverter.Int32BitsToSingle((int)(OpCode >> 20)));
}
private static ShaderIrOperImm Imm19_20(this long OpCode)
{
int Value = OpCode.Read(20, 0x7ffff);
bool Neg = OpCode.Read(56);
if (Neg)
{
Value = -Value;
}
return new ShaderIrOperImm(Value);
}
private static ShaderIrOperImmf Immf19_20(this long OpCode)
{
uint Imm = (uint)(OpCode >> 20) & 0x7ffff;
bool Neg = OpCode.Read(56);
Imm <<= 12;
if (Neg)
{
Imm |= 0x80000000;
}
float Value = BitConverter.Int32BitsToSingle((int)Imm);
return new ShaderIrOperImmf(Value);
}
private static ShaderIrOperPred Pred0(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(0, 7));
}
private static ShaderIrOperPred Pred3(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(3, 7));
}
private static ShaderIrOperPred Pred12(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(12, 7));
}
private static ShaderIrOperPred Pred29(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(29, 7));
}
private static ShaderIrNode Pred39N(this long OpCode)
{
ShaderIrNode Node = OpCode.Pred39();
if (OpCode.Read(42))
{
Node = new ShaderIrOp(ShaderIrInst.Bnot, Node);
}
return Node;
}
private static ShaderIrOperPred Pred39(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(39, 7));
}
private static ShaderIrOperPred Pred48(this long OpCode)
{
return new ShaderIrOperPred(OpCode.Read(48, 7));
}
private static ShaderIrInst Cmp(this long OpCode)
{
switch (OpCode.Read(49, 7))
{
case 1: return ShaderIrInst.Clt;
case 2: return ShaderIrInst.Ceq;
case 3: return ShaderIrInst.Cle;
case 4: return ShaderIrInst.Cgt;
case 5: return ShaderIrInst.Cne;
case 6: return ShaderIrInst.Cge;
}
throw new ArgumentException(nameof(OpCode));
}
private static ShaderIrInst CmpF(this long OpCode)
{
switch (OpCode.Read(48, 0xf))
{
case 0x1: return ShaderIrInst.Fclt;
case 0x2: return ShaderIrInst.Fceq;
case 0x3: return ShaderIrInst.Fcle;
case 0x4: return ShaderIrInst.Fcgt;
case 0x5: return ShaderIrInst.Fcne;
case 0x6: return ShaderIrInst.Fcge;
case 0x7: return ShaderIrInst.Fcnum;
case 0x8: return ShaderIrInst.Fcnan;
case 0x9: return ShaderIrInst.Fcltu;
case 0xa: return ShaderIrInst.Fcequ;
case 0xb: return ShaderIrInst.Fcleu;
case 0xc: return ShaderIrInst.Fcgtu;
case 0xd: return ShaderIrInst.Fcneu;
case 0xe: return ShaderIrInst.Fcgeu;
}
throw new ArgumentException(nameof(OpCode));
}
private static ShaderIrInst BLop45(this long OpCode)
{
switch (OpCode.Read(45, 3))
{
case 0: return ShaderIrInst.Band;
case 1: return ShaderIrInst.Bor;
case 2: return ShaderIrInst.Bxor;
}
throw new ArgumentException(nameof(OpCode));
}
private static ShaderIrInst BLop24(this long OpCode)
{
switch (OpCode.Read(24, 3))
{
case 0: return ShaderIrInst.Band;
case 1: return ShaderIrInst.Bor;
case 2: return ShaderIrInst.Bxor;
}
throw new ArgumentException(nameof(OpCode));
}
private static ShaderIrNode PredNode(this long OpCode, ShaderIrNode Node)
{
ShaderIrOperPred Pred = OpCode.PredNode();
if (Pred.Index != ShaderIrOperPred.UnusedIndex)
{
bool Inv = OpCode.Read(19);
Node = new ShaderIrCond(Pred, Node, Inv);
}
return Node;
}
private static ShaderIrOperPred PredNode(this long OpCode)
{
int Pred = OpCode.Read(16, 0xf);
if (Pred != 0xf)
{
Pred &= 7;
}
return new ShaderIrOperPred(Pred);
}
}
}

12
Ryujinx.Graphics/Gal/Shader/ShaderDecodeSpecial.cs
View file

@ -7,20 +7,20 @@ namespace Ryujinx.Graphics.Gal.Shader
public static void Out_R(ShaderIrBlock Block, long OpCode, long Position)
{
//TODO: Those registers have to be used for something
ShaderIrOperGpr Gpr0 = GetOperGpr0(OpCode);
ShaderIrOperGpr Gpr8 = GetOperGpr8(OpCode);
ShaderIrOperGpr Gpr20 = GetOperGpr20(OpCode);
ShaderIrOperGpr Gpr0 = OpCode.Gpr0();
ShaderIrOperGpr Gpr8 = OpCode.Gpr8();
ShaderIrOperGpr Gpr20 = OpCode.Gpr20();
int Type = (int)((OpCode >> 39) & 3);
int Type = OpCode.Read(39, 3);
if ((Type & 1) != 0)
{
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Emit), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Emit)));
}
if ((Type & 2) != 0)
{
Block.AddNode(GetPredNode(new ShaderIrOp(ShaderIrInst.Cut), OpCode));
Block.AddNode(OpCode.PredNode(new ShaderIrOp(ShaderIrInst.Cut)));
}
}
}

4
Ryujinx.HLE/Gpu/Engines/INvGpuEngine.cs → Ryujinx.Graphics/INvGpuEngine.cs
View file

@ -1,6 +1,6 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
interface INvGpuEngine
{

4
Ryujinx.HLE/Gpu/Engines/MacroInterpreter.cs → Ryujinx.Graphics/MacroInterpreter.cs
View file

@ -1,8 +1,8 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using System;
using System.Collections.Generic;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
class MacroInterpreter
{

4
Ryujinx.HLE/Gpu/Memory/NvGpuBufferType.cs → Ryujinx.Graphics/Memory/NvGpuBufferType.cs
View file

@ -1,6 +1,6 @@
namespace Ryujinx.HLE.Gpu.Memory
namespace Ryujinx.Graphics.Memory
{
enum NvGpuBufferType
public enum NvGpuBufferType
{
Index,
Vertex,

4
Ryujinx.HLE/Gpu/Memory/NvGpuPBEntry.cs → Ryujinx.Graphics/Memory/NvGpuPBEntry.cs
View file

@ -1,9 +1,9 @@
using System;
using System.Collections.ObjectModel;
namespace Ryujinx.HLE.Gpu.Memory
namespace Ryujinx.Graphics.Memory
{
struct NvGpuPBEntry
public struct NvGpuPBEntry
{
public int Method { get; private set; }

4
Ryujinx.HLE/Gpu/Memory/NvGpuPushBuffer.cs → Ryujinx.Graphics/Memory/NvGpuPushBuffer.cs
View file

@ -1,9 +1,9 @@
using System.Collections.Generic;
using System.IO;
namespace Ryujinx.HLE.Gpu.Memory
namespace Ryujinx.Graphics.Memory
{
static class NvGpuPushBuffer
public static class NvGpuPushBuffer
{
private enum SubmissionMode
{

4
Ryujinx.HLE/Gpu/Memory/NvGpuVmm.cs → Ryujinx.Graphics/Memory/NvGpuVmm.cs
View file

@ -2,9 +2,9 @@ using ChocolArm64.Memory;
using Ryujinx.Graphics.Gal;
using System;
namespace Ryujinx.HLE.Gpu.Memory
namespace Ryujinx.Graphics.Memory
{
class NvGpuVmm : IAMemory, IGalMemory
public class NvGpuVmm : IAMemory, IGalMemory
{
public const long AddrSize = 1L << 40;

7
Ryujinx.HLE/Gpu/Memory/NvGpuVmmCache.cs → Ryujinx.Graphics/Memory/NvGpuVmmCache.cs
View file

@ -1,12 +1,13 @@
using ChocolArm64.Memory;
using Ryujinx.HLE.Memory;
using System;
using System.Collections.Generic;
namespace Ryujinx.HLE.Gpu.Memory
namespace Ryujinx.Graphics.Memory
{
class NvGpuVmmCache
{
private const long RamSize = 4L * 1024 * 1024 * 1024;
private const int MaxCpCount = 10000;
private const int MaxCpTimeDelta = 60000;
@ -226,7 +227,7 @@ namespace Ryujinx.HLE.Gpu.Memory
{
if (Residency == null)
{
Residency = new HashSet<long>[DeviceMemory.RamSize / PageSize];
Residency = new HashSet<long>[RamSize / PageSize];
for (int i = 0; i < Residency.Length; i++)
{

6
Ryujinx.HLE/Gpu/NvGpu.cs → Ryujinx.Graphics/NvGpu.cs
View file

@ -1,9 +1,9 @@
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Engines;
using Ryujinx.Graphics;
namespace Ryujinx.HLE.Gpu
namespace Ryujinx.Graphics
{
class NvGpu
public class NvGpu
{
public IGalRenderer Renderer { get; private set; }

2
Ryujinx.HLE/Gpu/Engines/NvGpuEngine.cs → Ryujinx.Graphics/NvGpuEngine.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
enum NvGpuEngine
{

18
Ryujinx.HLE/Gpu/Engines/NvGpuEngine2d.cs → Ryujinx.Graphics/NvGpuEngine2d.cs
View file

@ -1,12 +1,12 @@
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.HLE.Gpu.Texture;
using Ryujinx.Graphics.Memory;
using Ryujinx.Graphics.Texture;
using System;
using System.Collections.Generic;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
class NvGpuEngine2d : INvGpuEngine
public class NvGpuEngine2d : INvGpuEngine
{
private enum CopyOperation
{
@ -103,7 +103,7 @@ namespace Ryujinx.HLE.Gpu.Engines
SrcPitch,
SrcBlockHeight, 1,
SrcSwizzle,
GalTextureFormat.A8B8G8R8);
GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm);
}
TextureInfo DstTexture()
@ -115,7 +115,7 @@ namespace Ryujinx.HLE.Gpu.Engines
DstPitch,
DstBlockHeight, 1,
DstSwizzle,
GalTextureFormat.A8B8G8R8);
GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm);
}
//TODO: fb -> fb copies, tex -> fb copies, formats other than RGBA8,
@ -123,7 +123,7 @@ namespace Ryujinx.HLE.Gpu.Engines
if (IsSrcFb && IsDstFb)
{
//Frame Buffer -> Frame Buffer copy.
Gpu.Renderer.FrameBuffer.Copy(
Gpu.Renderer.RenderTarget.Copy(
SrcKey,
DstKey,
0,
@ -138,7 +138,7 @@ namespace Ryujinx.HLE.Gpu.Engines
if (IsSrcFb)
{
//Frame Buffer -> Texture copy.
Gpu.Renderer.FrameBuffer.GetBufferData(SrcKey, (byte[] Buffer) =>
Gpu.Renderer.RenderTarget.GetBufferData(SrcKey, (byte[] Buffer) =>
{
TextureInfo Src = SrcTexture();
TextureInfo Dst = DstTexture();
@ -156,7 +156,7 @@ namespace Ryujinx.HLE.Gpu.Engines
{
byte[] Buffer = TextureReader.Read(Vmm, SrcTexture());
Gpu.Renderer.FrameBuffer.SetBufferData(
Gpu.Renderer.RenderTarget.SetBufferData(
DstKey,
DstWidth,
DstHeight,

2
Ryujinx.HLE/Gpu/Engines/NvGpuEngine2dReg.cs → Ryujinx.Graphics/NvGpuEngine2dReg.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
enum NvGpuEngine2dReg
{

37
Ryujinx.HLE/Gpu/Engines/NvGpuEngine3d.cs → Ryujinx.Graphics/NvGpuEngine3d.cs
View file

@ -1,12 +1,12 @@
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.HLE.Gpu.Texture;
using Ryujinx.Graphics.Memory;
using Ryujinx.Graphics.Texture;
using System;
using System.Collections.Generic;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
class NvGpuEngine3d : INvGpuEngine
public class NvGpuEngine3d : INvGpuEngine
{
public int[] Registers { get; private set; }
@ -158,6 +158,7 @@ namespace Ryujinx.HLE.Gpu.Engines
int Stencil = ReadRegister(NvGpuEngine3dReg.ClearStencil);
SetFrameBuffer(Vmm, FbIndex);
SetZeta(Vmm);
Gpu.Renderer.Rasterizer.ClearBuffers(
@ -176,7 +177,7 @@ namespace Ryujinx.HLE.Gpu.Engines
if (VA == 0 || Format == 0)
{
Gpu.Renderer.FrameBuffer.UnbindColor(FbIndex);
Gpu.Renderer.RenderTarget.UnbindColor(FbIndex);
return;
}
@ -200,16 +201,17 @@ namespace Ryujinx.HLE.Gpu.Engines
int VpW = (int)(TX + MathF.Abs(SX)) - VpX;
int VpH = (int)(TY + MathF.Abs(SY)) - VpY;
GalImageFormat ImageFormat = ImageFormatConverter.ConvertFrameBuffer((GalFrameBufferFormat)Format);
GalImageFormat ImageFormat = ImageUtils.ConvertSurface((GalSurfaceFormat)Format);
GalImage Image = new GalImage(Width, Height, ImageFormat);
long Size = TextureHelper.GetTextureSize(Image);
long Size = ImageUtils.GetSize(Image);
Gpu.Renderer.Texture.CreateFb(Key, Size, Image);
Gpu.Renderer.FrameBuffer.BindColor(Key, FbIndex);
Gpu.Renderer.FrameBuffer.SetViewport(VpX, VpY, VpW, VpH);
Gpu.Renderer.RenderTarget.BindColor(Key, FbIndex);
Gpu.Renderer.RenderTarget.SetViewport(VpX, VpY, VpW, VpH);
}
private void SetZeta(NvGpuVmm Vmm)
@ -222,7 +224,7 @@ namespace Ryujinx.HLE.Gpu.Engines
if (ZA == 0 || Format == 0 || !ZetaEnable)
{
Gpu.Renderer.FrameBuffer.UnbindZeta();
Gpu.Renderer.RenderTarget.UnbindZeta();
return;
}
@ -232,14 +234,15 @@ namespace Ryujinx.HLE.Gpu.Engines
int Width = ReadRegister(NvGpuEngine3dReg.ZetaHoriz);
int Height = ReadRegister(NvGpuEngine3dReg.ZetaVert);
GalImageFormat ImageFormat = ImageFormatConverter.ConvertZeta((GalZetaFormat)Format);
GalImageFormat ImageFormat = ImageUtils.ConvertZeta((GalZetaFormat)Format);
GalImage Image = new GalImage(Width, Height, ImageFormat);
long Size = TextureHelper.GetTextureSize(Image);
long Size = ImageUtils.GetSize(Image);
Gpu.Renderer.Texture.CreateFb(Key, Size, Image);
Gpu.Renderer.FrameBuffer.BindZeta(Key);
Gpu.Renderer.RenderTarget.BindZeta(Key);
}
private long[] UploadShaders(NvGpuVmm Vmm)
@ -441,11 +444,11 @@ namespace Ryujinx.HLE.Gpu.Engines
Map[i] = (int)((Control >> Shift) & 7);
}
Gpu.Renderer.FrameBuffer.SetMap(Map);
Gpu.Renderer.RenderTarget.SetMap(Map);
}
else
{
Gpu.Renderer.FrameBuffer.SetMap(null);
Gpu.Renderer.RenderTarget.SetMap(null);
}
}
@ -519,13 +522,13 @@ namespace Ryujinx.HLE.Gpu.Engines
//we shouldn't read anything from memory and bind
//the frame buffer texture instead, since we're not
//really writing anything to memory.
Gpu.Renderer.FrameBuffer.BindTexture(Key, TexIndex);
Gpu.Renderer.RenderTarget.BindTexture(Key, TexIndex);
}
else
{
GalImage NewImage = TextureFactory.MakeTexture(Vmm, TicPosition);
long Size = (uint)TextureHelper.GetTextureSize(NewImage);
long Size = (uint)ImageUtils.GetSize(NewImage);
bool HasCachedTexture = false;

2
Ryujinx.HLE/Gpu/Engines/NvGpuEngine3dReg.cs → Ryujinx.Graphics/NvGpuEngine3dReg.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
enum NvGpuEngine3dReg
{

8
Ryujinx.HLE/Gpu/Engines/NvGpuEngineDma.cs → Ryujinx.Graphics/NvGpuEngineDma.cs
View file

@ -1,10 +1,10 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.HLE.Gpu.Texture;
using Ryujinx.Graphics.Memory;
using Ryujinx.Graphics.Texture;
using System.Collections.Generic;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
class NvGpuEngineDma : INvGpuEngine
public class NvGpuEngineDma : INvGpuEngine
{
public int[] Registers { get; private set; }

2
Ryujinx.HLE/Gpu/Engines/NvGpuEngineDmaReg.cs → Ryujinx.Graphics/NvGpuEngineDmaReg.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
enum NvGpuEngineDmaReg
{

6
Ryujinx.HLE/Gpu/Engines/NvGpuFifo.cs → Ryujinx.Graphics/NvGpuFifo.cs
View file

@ -1,10 +1,10 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using System.Collections.Concurrent;
using System.Threading;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
class NvGpuFifo
public class NvGpuFifo
{
private const int MacrosCount = 0x80;
private const int MacroIndexMask = MacrosCount - 1;

2
Ryujinx.HLE/Gpu/Engines/NvGpuFifoMeth.cs → Ryujinx.Graphics/NvGpuFifoMeth.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
enum NvGpuFifoMeth
{

4
Ryujinx.HLE/Gpu/Engines/NvGpuMethod.cs → Ryujinx.Graphics/NvGpuMethod.cs
View file

@ -1,6 +1,6 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
namespace Ryujinx.HLE.Gpu.Engines
namespace Ryujinx.Graphics
{
delegate void NvGpuMethod(NvGpuVmm Vmm, NvGpuPBEntry PBEntry);
}

2768
Ryujinx.Graphics/Gal/Texture/ASTCDecoder.cs → Ryujinx.Graphics/Texture/ASTCDecoder.cs
View file

File diff suppressed because it is too large Load diff

276
Ryujinx.Graphics/Gal/Texture/ASTCPixel.cs → Ryujinx.Graphics/Texture/ASTCPixel.cs
View file

@ -1,138 +1,138 @@
using System;
using System.Diagnostics;
namespace Ryujinx.Graphics.Gal.Texture
{
class ASTCPixel
{
public short R { get; set; }
public short G { get; set; }
public short B { get; set; }
public short A { get; set; }
byte[] BitDepth = new byte[4];
public ASTCPixel(short _A, short _R, short _G, short _B)
{
A = _A;
R = _R;
G = _G;
B = _B;
for (int i = 0; i < 4; i++)
BitDepth[i] = 8;
}
public void ClampByte()
{
R = Math.Min(Math.Max(R, (short)0), (short)255);
G = Math.Min(Math.Max(G, (short)0), (short)255);
B = Math.Min(Math.Max(B, (short)0), (short)255);
A = Math.Min(Math.Max(A, (short)0), (short)255);
}
public short GetComponent(int Index)
{
switch(Index)
{
case 0: return A;
case 1: return R;
case 2: return G;
case 3: return B;
}
return 0;
}
public void SetComponent(int Index, int Value)
{
switch (Index)
{
case 0:
A = (short)Value;
break;
case 1:
R = (short)Value;
break;
case 2:
G = (short)Value;
break;
case 3:
B = (short)Value;
break;
}
}
public void ChangeBitDepth(byte[] Depth)
{
for(int i = 0; i< 4; i++)
{
int Value = ChangeBitDepth(GetComponent(i), BitDepth[i], Depth[i]);
SetComponent(i, Value);
BitDepth[i] = Depth[i];
}
}
short ChangeBitDepth(short Value, byte OldDepth, byte NewDepth)
{
Debug.Assert(NewDepth <= 8);
Debug.Assert(OldDepth <= 8);
if (OldDepth == NewDepth)
{
// Do nothing
return Value;
}
else if (OldDepth == 0 && NewDepth != 0)
{
return (short)((1 << NewDepth) - 1);
}
else if (NewDepth > OldDepth)
{
return (short)BitArrayStream.Replicate(Value, OldDepth, NewDepth);
}
else
{
// oldDepth > newDepth
if (NewDepth == 0)
{
return 0xFF;
}
else
{
byte BitsWasted = (byte)(OldDepth - NewDepth);
short TempValue = Value;
TempValue = (short)((TempValue + (1 << (BitsWasted - 1))) >> BitsWasted);
TempValue = Math.Min(Math.Max((short)0, TempValue), (short)((1 << NewDepth) - 1));
return (byte)(TempValue);
}
}
}
public int Pack()
{
ASTCPixel NewPixel = new ASTCPixel(A, R, G, B);
byte[] eightBitDepth = { 8, 8, 8, 8 };
NewPixel.ChangeBitDepth(eightBitDepth);
return (byte)NewPixel.A << 24 |
(byte)NewPixel.B << 16 |
(byte)NewPixel.G << 8 |
(byte)NewPixel.R << 0;
}
// Adds more precision to the blue channel as described
// in C.2.14
public static ASTCPixel BlueContract(int a, int r, int g, int b)
{
return new ASTCPixel((short)(a),
(short)((r + b) >> 1),
(short)((g + b) >> 1),
(short)(b));
}
}
}
using System;
using System.Diagnostics;
namespace Ryujinx.Graphics.Texture
{
class ASTCPixel
{
public short R { get; set; }
public short G { get; set; }
public short B { get; set; }
public short A { get; set; }
byte[] BitDepth = new byte[4];
public ASTCPixel(short _A, short _R, short _G, short _B)
{
A = _A;
R = _R;
G = _G;
B = _B;
for (int i = 0; i < 4; i++)
BitDepth[i] = 8;
}
public void ClampByte()
{
R = Math.Min(Math.Max(R, (short)0), (short)255);
G = Math.Min(Math.Max(G, (short)0), (short)255);
B = Math.Min(Math.Max(B, (short)0), (short)255);
A = Math.Min(Math.Max(A, (short)0), (short)255);
}
public short GetComponent(int Index)
{
switch(Index)
{
case 0: return A;
case 1: return R;
case 2: return G;
case 3: return B;
}
return 0;
}
public void SetComponent(int Index, int Value)
{
switch (Index)
{
case 0:
A = (short)Value;
break;
case 1:
R = (short)Value;
break;
case 2:
G = (short)Value;
break;
case 3:
B = (short)Value;
break;
}
}
public void ChangeBitDepth(byte[] Depth)
{
for(int i = 0; i< 4; i++)
{
int Value = ChangeBitDepth(GetComponent(i), BitDepth[i], Depth[i]);
SetComponent(i, Value);
BitDepth[i] = Depth[i];
}
}
short ChangeBitDepth(short Value, byte OldDepth, byte NewDepth)
{
Debug.Assert(NewDepth <= 8);
Debug.Assert(OldDepth <= 8);
if (OldDepth == NewDepth)
{
// Do nothing
return Value;
}
else if (OldDepth == 0 && NewDepth != 0)
{
return (short)((1 << NewDepth) - 1);
}
else if (NewDepth > OldDepth)
{
return (short)BitArrayStream.Replicate(Value, OldDepth, NewDepth);
}
else
{
// oldDepth > newDepth
if (NewDepth == 0)
{
return 0xFF;
}
else
{
byte BitsWasted = (byte)(OldDepth - NewDepth);
short TempValue = Value;
TempValue = (short)((TempValue + (1 << (BitsWasted - 1))) >> BitsWasted);
TempValue = Math.Min(Math.Max((short)0, TempValue), (short)((1 << NewDepth) - 1));
return (byte)(TempValue);
}
}
}
public int Pack()
{
ASTCPixel NewPixel = new ASTCPixel(A, R, G, B);
byte[] eightBitDepth = { 8, 8, 8, 8 };
NewPixel.ChangeBitDepth(eightBitDepth);
return (byte)NewPixel.A << 24 |
(byte)NewPixel.B << 16 |
(byte)NewPixel.G << 8 |
(byte)NewPixel.R << 0;
}
// Adds more precision to the blue channel as described
// in C.2.14
public static ASTCPixel BlueContract(int a, int r, int g, int b)
{
return new ASTCPixel((short)(a),
(short)((r + b) >> 1),
(short)((g + b) >> 1),
(short)(b));
}
}
}

241
Ryujinx.Graphics/Gal/Texture/BitArrayStream.cs → Ryujinx.Graphics/Texture/BitArrayStream.cs
View file

@ -1,120 +1,121 @@
using System;
using System.Collections;
namespace Ryujinx.Graphics.Gal.Texture
{
public class BitArrayStream
{
public BitArray BitsArray;
public int Position { get; private set; }
public BitArrayStream(BitArray BitArray)
{
BitsArray = BitArray;
Position = 0;
}
public short ReadBits(int Length)
{
int RetValue = 0;
for (int i = Position; i < Position + Length; i++)
{
if (BitsArray[i])
{
RetValue |= 1 << (i - Position);
}
}
Position += Length;
return (short)RetValue;
}
public int ReadBits(int Start, int End)
{
int RetValue = 0;
for (int i = Start; i <= End; i++)
{
if (BitsArray[i])
{
RetValue |= 1 << (i - Start);
}
}
return RetValue;
}
public int ReadBit(int Index)
{
return Convert.ToInt32(BitsArray[Index]);
}
public void WriteBits(int Value, int Length)
{
for (int i = Position; i < Position + Length; i++)
{
BitsArray[i] = ((Value >> (i - Position)) & 1) != 0;
}
Position += Length;
}
public byte[] ToByteArray()
{
byte[] RetArray = new byte[(BitsArray.Length + 7) / 8];
BitsArray.CopyTo(RetArray, 0);
return RetArray;
}
public static int Replicate(int Value, int NumberBits, int ToBit)
{
if (NumberBits == 0) return 0;
if (ToBit == 0) return 0;
int TempValue = Value & ((1 << NumberBits) - 1);
int RetValue = TempValue;
int ResLength = NumberBits;
while (ResLength < ToBit)
{
int Comp = 0;
if (NumberBits > ToBit - ResLength)
{
int NewShift = ToBit - ResLength;
Comp = NumberBits - NewShift;
NumberBits = NewShift;
}
RetValue <<= NumberBits;
RetValue |= TempValue >> Comp;
ResLength += NumberBits;
}
return RetValue;
}
public static int PopCnt(int Number)
{
int Counter;
for (Counter = 0; Number != 0; Counter++)
{
Number &= Number - 1;
}
return Counter;
}
public static void Swap<T>(ref T lhs, ref T rhs)
{
T Temp = lhs;
lhs = rhs;
rhs = Temp;
}
// Transfers a bit as described in C.2.14
public static void BitTransferSigned(ref int a, ref int b)
{
b >>= 1;
b |= a & 0x80;
a >>= 1;
a &= 0x3F;
if ((a & 0x20) != 0) a -= 0x40;
}
}
}
using System;
using System.Collections;
namespace Ryujinx.Graphics.Texture
{
public class BitArrayStream
{
public BitArray BitsArray;
public int Position { get; private set; }
public BitArrayStream(BitArray BitArray)
{
BitsArray = BitArray;
Position = 0;
}
public short ReadBits(int Length)
{
int RetValue = 0;
for (int i = Position; i < Position + Length; i++)
{
if (BitsArray[i])
{
RetValue |= 1 << (i - Position);
}
}
Position += Length;
return (short)RetValue;
}
public int ReadBits(int Start, int End)
{
int RetValue = 0;
for (int i = Start; i <= End; i++)
{
if (BitsArray[i])
{
RetValue |= 1 << (i - Start);
}
}
return RetValue;
}
public int ReadBit(int Index)
{
return Convert.ToInt32(BitsArray[Index]);
}
public void WriteBits(int Value, int Length)
{
for (int i = Position; i < Position + Length; i++)
{
BitsArray[i] = ((Value >> (i - Position)) & 1) != 0;
}
Position += Length;
}
public byte[] ToByteArray()
{
byte[] RetArray = new byte[(BitsArray.Length + 7) / 8];
BitsArray.CopyTo(RetArray, 0);
return RetArray;
}
public static int Replicate(int Value, int NumberBits, int ToBit)
{
if (NumberBits == 0) return 0;
if (ToBit == 0) return 0;
int TempValue = Value & ((1 << NumberBits) - 1);
int RetValue = TempValue;
int ResLength = NumberBits;
while (ResLength < ToBit)
{
int Comp = 0;
if (NumberBits > ToBit - ResLength)
{
int NewShift = ToBit - ResLength;
Comp = NumberBits - NewShift;
NumberBits = NewShift;
}
RetValue <<= NumberBits;
RetValue |= TempValue >> Comp;
ResLength += NumberBits;
}
return RetValue;
}
public static int PopCnt(int Number)
{
int Counter;
for (Counter = 0; Number != 0; Counter++)
{
Number &= Number - 1;
}
return Counter;
}
public static void Swap<T>(ref T lhs, ref T rhs)
{
T Temp = lhs;
lhs = rhs;
rhs = Temp;
}
// Transfers a bit as described in C.2.14
public static void BitTransferSigned(ref int a, ref int b)
{
b >>= 1;
b |= a & 0x80;
a >>= 1;
a &= 0x3F;
if ((a & 0x20) != 0) a -= 0x40;
}
}
}

2
Ryujinx.HLE/Gpu/Texture/BlockLinearSwizzle.cs → Ryujinx.Graphics/Texture/BlockLinearSwizzle.cs
View file

@ -1,6 +1,6 @@
using System;
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
class BlockLinearSwizzle : ISwizzle
{

2
Ryujinx.HLE/Gpu/Texture/ISwizzle.cs → Ryujinx.Graphics/Texture/ISwizzle.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
interface ISwizzle
{

24
Ryujinx.Graphics/Texture/ImageConverter.cs Normal file
View file

@ -0,0 +1,24 @@
namespace Ryujinx.Graphics.Texture
{
static class ImageConverter
{
public static byte[] G8R8ToR8G8(
byte[] Data,
int Width,
int Height,
int Depth)
{
int Texels = Width * Height * Depth;
byte[] Output = new byte[Texels * 2];
for (int Texel = 0; Texel < Texels; Texel++)
{
Output[Texel * 2 + 0] = Data[Texel * 2 + 1];
Output[Texel * 2 + 1] = Data[Texel * 2 + 0];
}
return Output;
}
}
}

357
Ryujinx.Graphics/Texture/ImageUtils.cs Normal file
View file

@ -0,0 +1,357 @@
using Ryujinx.Graphics.Gal;
using System;
using System.Collections.Generic;
namespace Ryujinx.Graphics.Texture
{
static class ImageUtils
{
struct ImageDescriptor
{
public TextureReaderDelegate Reader;
public bool HasColor;
public bool HasDepth;
public bool HasStencil;
public bool Compressed;
public ImageDescriptor(
TextureReaderDelegate Reader,
bool HasColor,
bool HasDepth,
bool HasStencil,
bool Compressed)
{
this.Reader = Reader;
this.HasColor = HasColor;
this.HasDepth = HasDepth;
this.HasStencil = HasStencil;
this.Compressed = Compressed;
}
}
private const GalImageFormat Snorm = GalImageFormat.Snorm;
private const GalImageFormat Unorm = GalImageFormat.Unorm;
private const GalImageFormat Sint = GalImageFormat.Sint;
private const GalImageFormat Uint = GalImageFormat.Uint;
private const GalImageFormat Sfloat = GalImageFormat.Sfloat;
private static readonly Dictionary<GalTextureFormat, GalImageFormat> s_TextureTable =
new Dictionary<GalTextureFormat, GalImageFormat>()
{
{ GalTextureFormat.R32G32B32A32, GalImageFormat.R32G32B32A32 | Sint | Uint | Sfloat },
{ GalTextureFormat.R16G16B16A16, GalImageFormat.R16G16B16A16 | Snorm | Unorm | Sint | Uint | Sfloat },
{ GalTextureFormat.R32G32, GalImageFormat.R32G32 | Sint | Uint | Sfloat },
{ GalTextureFormat.A8B8G8R8, GalImageFormat.A8B8G8R8 | Snorm | Unorm | Sint | Uint },
{ GalTextureFormat.A2B10G10R10, GalImageFormat.A2B10G10R10 | Snorm | Unorm | Sint | Uint },
{ GalTextureFormat.G8R8, GalImageFormat.G8R8 | Snorm | Unorm | Sint | Uint },
{ GalTextureFormat.R16, GalImageFormat.R16 | Snorm | Unorm | Sint | Uint | Sfloat },
{ GalTextureFormat.R8, GalImageFormat.R8 | Snorm | Unorm | Sint | Uint },
{ GalTextureFormat.R32, GalImageFormat.R32 | Sint | Uint | Sfloat },
{ GalTextureFormat.A4B4G4R4, GalImageFormat.A4B4G4R4 | Unorm },
{ GalTextureFormat.A1B5G5R5, GalImageFormat.A1R5G5B5 | Unorm },
{ GalTextureFormat.B5G6R5, GalImageFormat.B5G6R5 | Unorm },
{ GalTextureFormat.BF10GF11RF11, GalImageFormat.B10G11R11 | Sfloat },
{ GalTextureFormat.Z24S8, GalImageFormat.D24_S8 | Unorm },
{ GalTextureFormat.ZF32, GalImageFormat.D32 | Sfloat },
{ GalTextureFormat.ZF32_X24S8, GalImageFormat.D32_S8 | Unorm },
//Compressed formats
{ GalTextureFormat.BC6H_SF16, GalImageFormat.BC6H_SF16 | Unorm },
{ GalTextureFormat.BC6H_UF16, GalImageFormat.BC6H_UF16 | Unorm },
{ GalTextureFormat.BC7U, GalImageFormat.BC7 | Unorm },
{ GalTextureFormat.BC1, GalImageFormat.BC1_RGBA | Unorm },
{ GalTextureFormat.BC2, GalImageFormat.BC2 | Unorm },
{ GalTextureFormat.BC3, GalImageFormat.BC3 | Unorm },
{ GalTextureFormat.BC4, GalImageFormat.BC4 | Unorm | Snorm },
{ GalTextureFormat.BC5, GalImageFormat.BC5 | Unorm | Snorm },
{ GalTextureFormat.Astc2D4x4, GalImageFormat.ASTC_4x4 | Unorm },
{ GalTextureFormat.Astc2D5x5, GalImageFormat.ASTC_5x5 | Unorm },
{ GalTextureFormat.Astc2D6x6, GalImageFormat.ASTC_6x6 | Unorm },
{ GalTextureFormat.Astc2D8x8, GalImageFormat.ASTC_8x8 | Unorm },
{ GalTextureFormat.Astc2D10x10, GalImageFormat.ASTC_10x10 | Unorm },
{ GalTextureFormat.Astc2D12x12, GalImageFormat.ASTC_12x12 | Unorm },
{ GalTextureFormat.Astc2D5x4, GalImageFormat.ASTC_5x4 | Unorm },
{ GalTextureFormat.Astc2D6x5, GalImageFormat.ASTC_6x5 | Unorm },
{ GalTextureFormat.Astc2D8x6, GalImageFormat.ASTC_8x6 | Unorm },
{ GalTextureFormat.Astc2D10x8, GalImageFormat.ASTC_10x8 | Unorm },
{ GalTextureFormat.Astc2D12x10, GalImageFormat.ASTC_12x10 | Unorm },
{ GalTextureFormat.Astc2D8x5, GalImageFormat.ASTC_8x5 | Unorm },
{ GalTextureFormat.Astc2D10x5, GalImageFormat.ASTC_10x5 | Unorm },
{ GalTextureFormat.Astc2D10x6, GalImageFormat.ASTC_10x6 | Unorm }
};
private static readonly Dictionary<GalImageFormat, ImageDescriptor> s_ImageTable =
new Dictionary<GalImageFormat, ImageDescriptor>()
{
{ GalImageFormat.R32G32B32A32, new ImageDescriptor(TextureReader.Read16Bpp, true, false, false, false) },
{ GalImageFormat.R16G16B16A16, new ImageDescriptor(TextureReader.Read8Bpp, true, false, false, false) },
{ GalImageFormat.R32G32, new ImageDescriptor(TextureReader.Read8Bpp, true, false, false, false) },
{ GalImageFormat.A8B8G8R8, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.A2B10G10R10, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.R32, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.A4B4G4R4, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) },
{ GalImageFormat.BC6H_SF16, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.BC6H_UF16, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.A1R5G5B5, new ImageDescriptor(TextureReader.Read5551, true, false, false, false) },
{ GalImageFormat.B5G6R5, new ImageDescriptor(TextureReader.Read565, true, false, false, false) },
{ GalImageFormat.BC7, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.R16G16, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.R8G8, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) },
{ GalImageFormat.G8R8, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) },
{ GalImageFormat.R16, new ImageDescriptor(TextureReader.Read2Bpp, true, false, false, false) },
{ GalImageFormat.R8, new ImageDescriptor(TextureReader.Read1Bpp, true, false, false, false) },
{ GalImageFormat.B10G11R11, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.A8B8G8R8_SRGB, new ImageDescriptor(TextureReader.Read4Bpp, true, false, false, false) },
{ GalImageFormat.BC1_RGBA, new ImageDescriptor(TextureReader.Read8Bpt4x4, true, false, false, true) },
{ GalImageFormat.BC2, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.BC3, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.BC4, new ImageDescriptor(TextureReader.Read8Bpt4x4, true, false, false, true) },
{ GalImageFormat.BC5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.ASTC_4x4, new ImageDescriptor(TextureReader.Read16BptCompressedTexture4x4, true, false, false, true) },
{ GalImageFormat.ASTC_5x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture5x5, true, false, false, true) },
{ GalImageFormat.ASTC_6x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture6x6, true, false, false, true) },
{ GalImageFormat.ASTC_8x8, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x8, true, false, false, true) },
{ GalImageFormat.ASTC_10x10, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x10, true, false, false, true) },
{ GalImageFormat.ASTC_12x12, new ImageDescriptor(TextureReader.Read16BptCompressedTexture12x12, true, false, false, true) },
{ GalImageFormat.ASTC_5x4, new ImageDescriptor(TextureReader.Read16BptCompressedTexture5x4, true, false, false, true) },
{ GalImageFormat.ASTC_6x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture6x5, true, false, false, true) },
{ GalImageFormat.ASTC_8x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x6, true, false, false, true) },
{ GalImageFormat.ASTC_10x8, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x8, true, false, false, true) },
{ GalImageFormat.ASTC_12x10, new ImageDescriptor(TextureReader.Read16BptCompressedTexture12x10, true, false, false, true) },
{ GalImageFormat.ASTC_8x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture8x5, true, false, false, true) },
{ GalImageFormat.ASTC_10x5, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x5, true, false, false, true) },
{ GalImageFormat.ASTC_10x6, new ImageDescriptor(TextureReader.Read16BptCompressedTexture10x6, true, false, false, true) },
{ GalImageFormat.D24_S8, new ImageDescriptor(TextureReader.Read4Bpp, false, true, true, false) },
{ GalImageFormat.D32, new ImageDescriptor(TextureReader.Read4Bpp, false, true, false, false) },
{ GalImageFormat.D16, new ImageDescriptor(TextureReader.Read2Bpp, false, true, false, false) },
{ GalImageFormat.D32_S8, new ImageDescriptor(TextureReader.Read8Bpp, false, true, true, false) },
};
public static GalImageFormat ConvertTexture(
GalTextureFormat Format,
GalTextureType RType,
GalTextureType GType,
GalTextureType BType,
GalTextureType AType)
{
if (RType != GType || RType != BType || RType != AType)
{
throw new NotImplementedException("Per component types are not implemented");
}
if (!s_TextureTable.TryGetValue(Format, out GalImageFormat ImageFormat))
{
throw new NotImplementedException("Texture with format " + ((int)Format).ToString("x2") + " not implemented");
}
GalTextureType Type = RType;
GalImageFormat FormatType = GetFormatType(RType);
if (ImageFormat.HasFlag(FormatType))
{
return (ImageFormat & GalImageFormat.FormatMask) | FormatType;
}
else
{
throw new NotImplementedException("Texture with format " + Format +
" and component type " + Type + " is not implemented");
}
}
public static GalImageFormat ConvertSurface(GalSurfaceFormat Format)
{
switch (Format)
{
case GalSurfaceFormat.RGBA32Float: return GalImageFormat.R32G32B32A32 | Sfloat;
case GalSurfaceFormat.RGBA16Float: return GalImageFormat.R16G16B16A16 | Sfloat;
case GalSurfaceFormat.RG32Float: return GalImageFormat.R32G32 | Sfloat;
case GalSurfaceFormat.RG32Sint: return GalImageFormat.R32G32 | Sint;
case GalSurfaceFormat.RG32Uint: return GalImageFormat.R32G32 | Uint;
case GalSurfaceFormat.BGRA8Unorm: return GalImageFormat.R8G8B8A8 | Unorm; //Is this right?
case GalSurfaceFormat.BGRA8Srgb: return GalImageFormat.A8B8G8R8_SRGB; //This one might be wrong
case GalSurfaceFormat.RGB10A2Unorm: return GalImageFormat.A2B10G10R10 | Unorm;
case GalSurfaceFormat.RGBA8Unorm: return GalImageFormat.A8B8G8R8 | Unorm;
case GalSurfaceFormat.RGBA8Srgb: return GalImageFormat.A8B8G8R8_SRGB;
case GalSurfaceFormat.RGBA8Snorm: return GalImageFormat.A8B8G8R8 | Snorm;
case GalSurfaceFormat.RG16Snorm: return GalImageFormat.R16G16 | Snorm;
case GalSurfaceFormat.RG16Float: return GalImageFormat.R16G16 | Sfloat;
case GalSurfaceFormat.R11G11B10Float: return GalImageFormat.B10G11R11 | Sfloat;
case GalSurfaceFormat.R32Float: return GalImageFormat.R32 | Sfloat;
case GalSurfaceFormat.RG8Unorm: return GalImageFormat.R8G8 | Unorm;
case GalSurfaceFormat.RG8Snorm: return GalImageFormat.R8 | Snorm;
case GalSurfaceFormat.R16Float: return GalImageFormat.R16 | Sfloat;
case GalSurfaceFormat.R8Unorm: return GalImageFormat.R8 | Unorm;
}
throw new NotImplementedException(Format.ToString());
}
public static GalImageFormat ConvertZeta(GalZetaFormat Format)
{
switch (Format)
{
case GalZetaFormat.Z32Float: return GalImageFormat.D32 | Sfloat;
case GalZetaFormat.S8Z24Unorm: return GalImageFormat.D24_S8 | Unorm;
case GalZetaFormat.Z16Unorm: return GalImageFormat.D16 | Unorm;
//This one might not be Uint, change when a texture uses this format
case GalZetaFormat.Z32S8X24Float: return GalImageFormat.D32_S8 | Uint;
}
throw new NotImplementedException(Format.ToString());
}
public static TextureReaderDelegate GetReader(GalImageFormat Format)
{
return GetImageDescriptor(Format).Reader;
}
public static int GetSize(GalImage Image)
{
switch (Image.Format & GalImageFormat.FormatMask)
{
case GalImageFormat.R32G32B32A32:
return Image.Width * Image.Height * 16;
case GalImageFormat.R16G16B16A16:
case GalImageFormat.D32_S8:
case GalImageFormat.R32G32:
return Image.Width * Image.Height * 8;
case GalImageFormat.A8B8G8R8:
case GalImageFormat.A8B8G8R8_SRGB:
case GalImageFormat.A2B10G10R10:
case GalImageFormat.R16G16:
case GalImageFormat.R32:
case GalImageFormat.D32:
case GalImageFormat.B10G11R11:
case GalImageFormat.D24_S8:
return Image.Width * Image.Height * 4;
case GalImageFormat.B4G4R4A4:
case GalImageFormat.A1R5G5B5:
case GalImageFormat.B5G6R5:
case GalImageFormat.R8G8:
case GalImageFormat.R16:
case GalImageFormat.D16:
return Image.Width * Image.Height * 2;
case GalImageFormat.R8:
return Image.Width * Image.Height;
case GalImageFormat.BC1_RGBA:
case GalImageFormat.BC4:
{
return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 8);
}
case GalImageFormat.BC6H_SF16:
case GalImageFormat.BC6H_UF16:
case GalImageFormat.BC7:
case GalImageFormat.BC2:
case GalImageFormat.BC3:
case GalImageFormat.BC5:
case GalImageFormat.ASTC_4x4:
return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 16);
case GalImageFormat.ASTC_5x5:
return CompressedTextureSize(Image.Width, Image.Height, 5, 5, 16);
case GalImageFormat.ASTC_6x6:
return CompressedTextureSize(Image.Width, Image.Height, 6, 6, 16);
case GalImageFormat.ASTC_8x8:
return CompressedTextureSize(Image.Width, Image.Height, 8, 8, 16);
case GalImageFormat.ASTC_10x10:
return CompressedTextureSize(Image.Width, Image.Height, 10, 10, 16);
case GalImageFormat.ASTC_12x12:
return CompressedTextureSize(Image.Width, Image.Height, 12, 12, 16);
case GalImageFormat.ASTC_5x4:
return CompressedTextureSize(Image.Width, Image.Height, 5, 4, 16);
case GalImageFormat.ASTC_6x5:
return CompressedTextureSize(Image.Width, Image.Height, 6, 5, 16);
case GalImageFormat.ASTC_8x6:
return CompressedTextureSize(Image.Width, Image.Height, 8, 6, 16);
case GalImageFormat.ASTC_10x8:
return CompressedTextureSize(Image.Width, Image.Height, 10, 8, 16);
case GalImageFormat.ASTC_12x10:
return CompressedTextureSize(Image.Width, Image.Height, 12, 10, 16);
case GalImageFormat.ASTC_8x5:
return CompressedTextureSize(Image.Width, Image.Height, 8, 5, 16);
case GalImageFormat.ASTC_10x5:
return CompressedTextureSize(Image.Width, Image.Height, 10, 5, 16);
case GalImageFormat.ASTC_10x6:
return CompressedTextureSize(Image.Width, Image.Height, 10, 6, 16);
}
throw new NotImplementedException((Image.Format & GalImageFormat.FormatMask).ToString());
}
public static bool HasColor(GalImageFormat Format)
{
return GetImageDescriptor(Format).HasColor;
}
public static bool HasDepth(GalImageFormat Format)
{
return GetImageDescriptor(Format).HasDepth;
}
public static bool HasStencil(GalImageFormat Format)
{
return GetImageDescriptor(Format).HasStencil;
}
public static bool IsCompressed(GalImageFormat Format)
{
return GetImageDescriptor(Format).Compressed;
}
private static ImageDescriptor GetImageDescriptor(GalImageFormat Format)
{
GalImageFormat TypeLess = (Format & GalImageFormat.FormatMask);
if (s_ImageTable.TryGetValue(TypeLess, out ImageDescriptor Descriptor))
{
return Descriptor;
}
throw new NotImplementedException("Image with format " + TypeLess.ToString() + " not implemented");
}
private static GalImageFormat GetFormatType(GalTextureType Type)
{
switch (Type)
{
case GalTextureType.Snorm: return Snorm;
case GalTextureType.Unorm: return Unorm;
case GalTextureType.Sint: return Sint;
case GalTextureType.Uint: return Uint;
case GalTextureType.Float: return Sfloat;
default: throw new NotImplementedException(((int)Type).ToString());
}
}
private static int CompressedTextureSize(int TextureWidth, int TextureHeight, int BlockWidth, int BlockHeight, int Bpb)
{
int W = (TextureWidth + (BlockWidth - 1)) / BlockWidth;
int H = (TextureHeight + (BlockHeight - 1)) / BlockHeight;
return W * H * Bpb;
}
}
}

538
Ryujinx.Graphics/Gal/Texture/IntegerEncoded.cs → Ryujinx.Graphics/Texture/IntegerEncoded.cs
View file

@ -1,269 +1,269 @@
using System.Collections;
using System.Collections.Generic;
namespace Ryujinx.Graphics.Gal.Texture
{
public struct IntegerEncoded
{
public enum EIntegerEncoding
{
JustBits,
Quint,
Trit
}
EIntegerEncoding Encoding;
public int NumberBits { get; private set; }
public int BitValue { get; private set; }
public int TritValue { get; private set; }
public int QuintValue { get; private set; }
public IntegerEncoded(EIntegerEncoding _Encoding, int NumBits)
{
Encoding = _Encoding;
NumberBits = NumBits;
BitValue = 0;
TritValue = 0;
QuintValue = 0;
}
public bool MatchesEncoding(IntegerEncoded Other)
{
return Encoding == Other.Encoding && NumberBits == Other.NumberBits;
}
public EIntegerEncoding GetEncoding()
{
return Encoding;
}
public int GetBitLength(int NumberVals)
{
int TotalBits = NumberBits * NumberVals;
if (Encoding == EIntegerEncoding.Trit)
{
TotalBits += (NumberVals * 8 + 4) / 5;
}
else if (Encoding == EIntegerEncoding.Quint)
{
TotalBits += (NumberVals * 7 + 2) / 3;
}
return TotalBits;
}
public static IntegerEncoded CreateEncoding(int MaxVal)
{
while (MaxVal > 0)
{
int Check = MaxVal + 1;
// Is maxVal a power of two?
if ((Check & (Check - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.JustBits, BitArrayStream.PopCnt(MaxVal));
}
// Is maxVal of the type 3*2^n - 1?
if ((Check % 3 == 0) && ((Check / 3) & ((Check / 3) - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.Trit, BitArrayStream.PopCnt(Check / 3 - 1));
}
// Is maxVal of the type 5*2^n - 1?
if ((Check % 5 == 0) && ((Check / 5) & ((Check / 5) - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.Quint, BitArrayStream.PopCnt(Check / 5 - 1));
}
// Apparently it can't be represented with a bounded integer sequence...
// just iterate.
MaxVal--;
}
return new IntegerEncoded(EIntegerEncoding.JustBits, 0);
}
public static void DecodeTritBlock(
BitArrayStream BitStream,
List<IntegerEncoded> ListIntegerEncoded,
int NumberBitsPerValue)
{
// Implement the algorithm in section C.2.12
int[] m = new int[5];
int[] t = new int[5];
int T;
// Read the trit encoded block according to
// table C.2.14
m[0] = BitStream.ReadBits(NumberBitsPerValue);
T = BitStream.ReadBits(2);
m[1] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(2) << 2;
m[2] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(1) << 4;
m[3] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(2) << 5;
m[4] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(1) << 7;
int C = 0;
BitArrayStream Tb = new BitArrayStream(new BitArray(new int[] { T }));
if (Tb.ReadBits(2, 4) == 7)
{
C = (Tb.ReadBits(5, 7) << 2) | Tb.ReadBits(0, 1);
t[4] = t[3] = 2;
}
else
{
C = Tb.ReadBits(0, 4);
if (Tb.ReadBits(5, 6) == 3)
{
t[4] = 2;
t[3] = Tb.ReadBit(7);
}
else
{
t[4] = Tb.ReadBit(7);
t[3] = Tb.ReadBits(5, 6);
}
}
BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C }));
if (Cb.ReadBits(0, 1) == 3)
{
t[2] = 2;
t[1] = Cb.ReadBit(4);
t[0] = (Cb.ReadBit(3) << 1) | (Cb.ReadBit(2) & ~Cb.ReadBit(3));
}
else if (Cb.ReadBits(2, 3) == 3)
{
t[2] = 2;
t[1] = 2;
t[0] = Cb.ReadBits(0, 1);
}
else
{
t[2] = Cb.ReadBit(4);
t[1] = Cb.ReadBits(2, 3);
t[0] = (Cb.ReadBit(1) << 1) | (Cb.ReadBit(0) & ~Cb.ReadBit(1));
}
for (int i = 0; i < 5; i++)
{
IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Trit, NumberBitsPerValue)
{
BitValue = m[i],
TritValue = t[i]
};
ListIntegerEncoded.Add(IntEncoded);
}
}
public static void DecodeQuintBlock(
BitArrayStream BitStream,
List<IntegerEncoded> ListIntegerEncoded,
int NumberBitsPerValue)
{
// Implement the algorithm in section C.2.12
int[] m = new int[3];
int[] q = new int[3];
int Q;
// Read the trit encoded block according to
// table C.2.15
m[0] = BitStream.ReadBits(NumberBitsPerValue);
Q = BitStream.ReadBits(3);
m[1] = BitStream.ReadBits(NumberBitsPerValue);
Q |= BitStream.ReadBits(2) << 3;
m[2] = BitStream.ReadBits(NumberBitsPerValue);
Q |= BitStream.ReadBits(2) << 5;
BitArrayStream Qb = new BitArrayStream(new BitArray(new int[] { Q }));
if (Qb.ReadBits(1, 2) == 3 && Qb.ReadBits(5, 6) == 0)
{
q[0] = q[1] = 4;
q[2] = (Qb.ReadBit(0) << 2) | ((Qb.ReadBit(4) & ~Qb.ReadBit(0)) << 1) | (Qb.ReadBit(3) & ~Qb.ReadBit(0));
}
else
{
int C = 0;
if (Qb.ReadBits(1, 2) == 3)
{
q[2] = 4;
C = (Qb.ReadBits(3, 4) << 3) | ((~Qb.ReadBits(5, 6) & 3) << 1) | Qb.ReadBit(0);
}
else
{
q[2] = Qb.ReadBits(5, 6);
C = Qb.ReadBits(0, 4);
}
BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C }));
if (Cb.ReadBits(0, 2) == 5)
{
q[1] = 4;
q[0] = Cb.ReadBits(3, 4);
}
else
{
q[1] = Cb.ReadBits(3, 4);
q[0] = Cb.ReadBits(0, 2);
}
}
for (int i = 0; i < 3; i++)
{
IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Quint, NumberBitsPerValue)
{
BitValue = m[i],
QuintValue = q[i]
};
ListIntegerEncoded.Add(IntEncoded);
}
}
public static void DecodeIntegerSequence(
List<IntegerEncoded> DecodeIntegerSequence,
BitArrayStream BitStream,
int MaxRange,
int NumberValues)
{
// Determine encoding parameters
IntegerEncoded IntEncoded = CreateEncoding(MaxRange);
// Start decoding
int NumberValuesDecoded = 0;
while (NumberValuesDecoded < NumberValues)
{
switch (IntEncoded.GetEncoding())
{
case EIntegerEncoding.Quint:
{
DecodeQuintBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits);
NumberValuesDecoded += 3;
break;
}
case EIntegerEncoding.Trit:
{
DecodeTritBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits);
NumberValuesDecoded += 5;
break;
}
case EIntegerEncoding.JustBits:
{
IntEncoded.BitValue = BitStream.ReadBits(IntEncoded.NumberBits);
DecodeIntegerSequence.Add(IntEncoded);
NumberValuesDecoded++;
break;
}
}
}
}
}
}
using System.Collections;
using System.Collections.Generic;
namespace Ryujinx.Graphics.Texture
{
public struct IntegerEncoded
{
public enum EIntegerEncoding
{
JustBits,
Quint,
Trit
}
EIntegerEncoding Encoding;
public int NumberBits { get; private set; }
public int BitValue { get; private set; }
public int TritValue { get; private set; }
public int QuintValue { get; private set; }
public IntegerEncoded(EIntegerEncoding _Encoding, int NumBits)
{
Encoding = _Encoding;
NumberBits = NumBits;
BitValue = 0;
TritValue = 0;
QuintValue = 0;
}
public bool MatchesEncoding(IntegerEncoded Other)
{
return Encoding == Other.Encoding && NumberBits == Other.NumberBits;
}
public EIntegerEncoding GetEncoding()
{
return Encoding;
}
public int GetBitLength(int NumberVals)
{
int TotalBits = NumberBits * NumberVals;
if (Encoding == EIntegerEncoding.Trit)
{
TotalBits += (NumberVals * 8 + 4) / 5;
}
else if (Encoding == EIntegerEncoding.Quint)
{
TotalBits += (NumberVals * 7 + 2) / 3;
}
return TotalBits;
}
public static IntegerEncoded CreateEncoding(int MaxVal)
{
while (MaxVal > 0)
{
int Check = MaxVal + 1;
// Is maxVal a power of two?
if ((Check & (Check - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.JustBits, BitArrayStream.PopCnt(MaxVal));
}
// Is maxVal of the type 3*2^n - 1?
if ((Check % 3 == 0) && ((Check / 3) & ((Check / 3) - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.Trit, BitArrayStream.PopCnt(Check / 3 - 1));
}
// Is maxVal of the type 5*2^n - 1?
if ((Check % 5 == 0) && ((Check / 5) & ((Check / 5) - 1)) == 0)
{
return new IntegerEncoded(EIntegerEncoding.Quint, BitArrayStream.PopCnt(Check / 5 - 1));
}
// Apparently it can't be represented with a bounded integer sequence...
// just iterate.
MaxVal--;
}
return new IntegerEncoded(EIntegerEncoding.JustBits, 0);
}
public static void DecodeTritBlock(
BitArrayStream BitStream,
List<IntegerEncoded> ListIntegerEncoded,
int NumberBitsPerValue)
{
// Implement the algorithm in section C.2.12
int[] m = new int[5];
int[] t = new int[5];
int T;
// Read the trit encoded block according to
// table C.2.14
m[0] = BitStream.ReadBits(NumberBitsPerValue);
T = BitStream.ReadBits(2);
m[1] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(2) << 2;
m[2] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(1) << 4;
m[3] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(2) << 5;
m[4] = BitStream.ReadBits(NumberBitsPerValue);
T |= BitStream.ReadBits(1) << 7;
int C = 0;
BitArrayStream Tb = new BitArrayStream(new BitArray(new int[] { T }));
if (Tb.ReadBits(2, 4) == 7)
{
C = (Tb.ReadBits(5, 7) << 2) | Tb.ReadBits(0, 1);
t[4] = t[3] = 2;
}
else
{
C = Tb.ReadBits(0, 4);
if (Tb.ReadBits(5, 6) == 3)
{
t[4] = 2;
t[3] = Tb.ReadBit(7);
}
else
{
t[4] = Tb.ReadBit(7);
t[3] = Tb.ReadBits(5, 6);
}
}
BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C }));
if (Cb.ReadBits(0, 1) == 3)
{
t[2] = 2;
t[1] = Cb.ReadBit(4);
t[0] = (Cb.ReadBit(3) << 1) | (Cb.ReadBit(2) & ~Cb.ReadBit(3));
}
else if (Cb.ReadBits(2, 3) == 3)
{
t[2] = 2;
t[1] = 2;
t[0] = Cb.ReadBits(0, 1);
}
else
{
t[2] = Cb.ReadBit(4);
t[1] = Cb.ReadBits(2, 3);
t[0] = (Cb.ReadBit(1) << 1) | (Cb.ReadBit(0) & ~Cb.ReadBit(1));
}
for (int i = 0; i < 5; i++)
{
IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Trit, NumberBitsPerValue)
{
BitValue = m[i],
TritValue = t[i]
};
ListIntegerEncoded.Add(IntEncoded);
}
}
public static void DecodeQuintBlock(
BitArrayStream BitStream,
List<IntegerEncoded> ListIntegerEncoded,
int NumberBitsPerValue)
{
// Implement the algorithm in section C.2.12
int[] m = new int[3];
int[] q = new int[3];
int Q;
// Read the trit encoded block according to
// table C.2.15
m[0] = BitStream.ReadBits(NumberBitsPerValue);
Q = BitStream.ReadBits(3);
m[1] = BitStream.ReadBits(NumberBitsPerValue);
Q |= BitStream.ReadBits(2) << 3;
m[2] = BitStream.ReadBits(NumberBitsPerValue);
Q |= BitStream.ReadBits(2) << 5;
BitArrayStream Qb = new BitArrayStream(new BitArray(new int[] { Q }));
if (Qb.ReadBits(1, 2) == 3 && Qb.ReadBits(5, 6) == 0)
{
q[0] = q[1] = 4;
q[2] = (Qb.ReadBit(0) << 2) | ((Qb.ReadBit(4) & ~Qb.ReadBit(0)) << 1) | (Qb.ReadBit(3) & ~Qb.ReadBit(0));
}
else
{
int C = 0;
if (Qb.ReadBits(1, 2) == 3)
{
q[2] = 4;
C = (Qb.ReadBits(3, 4) << 3) | ((~Qb.ReadBits(5, 6) & 3) << 1) | Qb.ReadBit(0);
}
else
{
q[2] = Qb.ReadBits(5, 6);
C = Qb.ReadBits(0, 4);
}
BitArrayStream Cb = new BitArrayStream(new BitArray(new int[] { C }));
if (Cb.ReadBits(0, 2) == 5)
{
q[1] = 4;
q[0] = Cb.ReadBits(3, 4);
}
else
{
q[1] = Cb.ReadBits(3, 4);
q[0] = Cb.ReadBits(0, 2);
}
}
for (int i = 0; i < 3; i++)
{
IntegerEncoded IntEncoded = new IntegerEncoded(EIntegerEncoding.Quint, NumberBitsPerValue)
{
BitValue = m[i],
QuintValue = q[i]
};
ListIntegerEncoded.Add(IntEncoded);
}
}
public static void DecodeIntegerSequence(
List<IntegerEncoded> DecodeIntegerSequence,
BitArrayStream BitStream,
int MaxRange,
int NumberValues)
{
// Determine encoding parameters
IntegerEncoded IntEncoded = CreateEncoding(MaxRange);
// Start decoding
int NumberValuesDecoded = 0;
while (NumberValuesDecoded < NumberValues)
{
switch (IntEncoded.GetEncoding())
{
case EIntegerEncoding.Quint:
{
DecodeQuintBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits);
NumberValuesDecoded += 3;
break;
}
case EIntegerEncoding.Trit:
{
DecodeTritBlock(BitStream, DecodeIntegerSequence, IntEncoded.NumberBits);
NumberValuesDecoded += 5;
break;
}
case EIntegerEncoding.JustBits:
{
IntEncoded.BitValue = BitStream.ReadBits(IntEncoded.NumberBits);
DecodeIntegerSequence.Add(IntEncoded);
NumberValuesDecoded++;
break;
}
}
}
}
}
}

2
Ryujinx.HLE/Gpu/Texture/LinearSwizzle.cs → Ryujinx.Graphics/Texture/LinearSwizzle.cs
View file

@ -1,4 +1,4 @@
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
class LinearSwizzle : ISwizzle
{

25
Ryujinx.HLE/Gpu/Texture/TextureFactory.cs → Ryujinx.Graphics/Texture/TextureFactory.cs
View file

@ -1,8 +1,8 @@
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using System;
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
static class TextureFactory
{
@ -10,12 +10,7 @@ namespace Ryujinx.HLE.Gpu.Texture
{
int[] Tic = ReadWords(Vmm, TicPosition, 8);
GalTextureType RType = (GalTextureType)((Tic[0] >> 7) & 7);
GalTextureType GType = (GalTextureType)((Tic[0] >> 10) & 7);
GalTextureType BType = (GalTextureType)((Tic[0] >> 13) & 7);
GalTextureType AType = (GalTextureType)((Tic[0] >> 16) & 7);
GalImageFormat Format = ImageFormatConverter.ConvertTexture((GalTextureFormat)(Tic[0] & 0x7f), RType, GType, BType, AType);
GalImageFormat Format = GetImageFormat(Tic);
GalTextureSource XSource = (GalTextureSource)((Tic[0] >> 19) & 7);
GalTextureSource YSource = (GalTextureSource)((Tic[0] >> 22) & 7);
@ -39,7 +34,7 @@ namespace Ryujinx.HLE.Gpu.Texture
{
int[] Tic = ReadWords(Vmm, TicPosition, 8);
GalTextureFormat Format = (GalTextureFormat)(Tic[0] & 0x7f);
GalImageFormat Format = GetImageFormat(Tic);
long TextureAddress = (uint)Tic[1];
@ -110,6 +105,18 @@ namespace Ryujinx.HLE.Gpu.Texture
BorderColor);
}
private static GalImageFormat GetImageFormat(int[] Tic)
{
GalTextureType RType = (GalTextureType)((Tic[0] >> 7) & 7);
GalTextureType GType = (GalTextureType)((Tic[0] >> 10) & 7);
GalTextureType BType = (GalTextureType)((Tic[0] >> 13) & 7);
GalTextureType AType = (GalTextureType)((Tic[0] >> 16) & 7);
GalTextureFormat Format = (GalTextureFormat)(Tic[0] & 0x7f);
return ImageUtils.ConvertTexture(Format, RType, GType, BType, AType);
}
private static int[] ReadWords(NvGpuVmm Vmm, long Position, int Count)
{
int[] Words = new int[Count];

45
Ryujinx.Graphics/Texture/TextureHelper.cs Normal file
View file

@ -0,0 +1,45 @@
using ChocolArm64.Memory;
using Ryujinx.Graphics.Gal;
using Ryujinx.Graphics.Memory;
using System;
namespace Ryujinx.Graphics.Texture
{
static class TextureHelper
{
public static ISwizzle GetSwizzle(TextureInfo Texture, int BlockWidth, int Bpp)
{
int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth;
int AlignMask = Texture.TileWidth * (64 / Bpp) - 1;
Width = (Width + AlignMask) & ~AlignMask;
switch (Texture.Swizzle)
{
case TextureSwizzle._1dBuffer:
case TextureSwizzle.Pitch:
case TextureSwizzle.PitchColorKey:
return new LinearSwizzle(Texture.Pitch, Bpp);
case TextureSwizzle.BlockLinear:
case TextureSwizzle.BlockLinearColorKey:
return new BlockLinearSwizzle(Width, Bpp, Texture.BlockHeight);
}
throw new NotImplementedException(Texture.Swizzle.ToString());
}
public static (AMemory Memory, long Position) GetMemoryAndPosition(
IAMemory Memory,
long Position)
{
if (Memory is NvGpuVmm Vmm)
{
return (Vmm.Memory, Vmm.GetPhysicalAddress(Position));
}
return ((AMemory)Memory, Position);
}
}
}

10
Ryujinx.HLE/Gpu/Texture/TextureInfo.cs → Ryujinx.Graphics/Texture/TextureInfo.cs
View file

@ -1,8 +1,8 @@
using Ryujinx.Graphics.Gal;
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
struct TextureInfo
public struct TextureInfo
{
public long Position { get; private set; }
@ -15,7 +15,7 @@ namespace Ryujinx.HLE.Gpu.Texture
public TextureSwizzle Swizzle { get; private set; }
public GalTextureFormat Format { get; private set; }
public GalImageFormat Format { get; private set; }
public TextureInfo(
long Position,
@ -34,7 +34,7 @@ namespace Ryujinx.HLE.Gpu.Texture
Swizzle = TextureSwizzle.BlockLinear;
Format = GalTextureFormat.A8B8G8R8;
Format = GalImageFormat.A8B8G8R8 | GalImageFormat.Unorm;
}
public TextureInfo(
@ -45,7 +45,7 @@ namespace Ryujinx.HLE.Gpu.Texture
int BlockHeight,
int TileWidth,
TextureSwizzle Swizzle,
GalTextureFormat Format)
GalImageFormat Format)
{
this.Position = Position;
this.Width = Width;

138
Ryujinx.HLE/Gpu/Texture/TextureReader.cs → Ryujinx.Graphics/Texture/TextureReader.cs
View file

@ -2,58 +2,20 @@ using ChocolArm64.Memory;
using Ryujinx.Graphics.Gal;
using System;
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
static class TextureReader
delegate byte[] TextureReaderDelegate(IAMemory Memory, TextureInfo Texture);
public static class TextureReader
{
public static byte[] Read(IAMemory Memory, TextureInfo Texture)
{
switch (Texture.Format)
{
case GalTextureFormat.R32G32B32A32: return Read16Bpp (Memory, Texture);
case GalTextureFormat.R16G16B16A16: return Read8Bpp (Memory, Texture);
case GalTextureFormat.R32G32: return Read8Bpp (Memory, Texture);
case GalTextureFormat.A8B8G8R8: return Read4Bpp (Memory, Texture);
case GalTextureFormat.A2B10G10R10: return Read4Bpp (Memory, Texture);
case GalTextureFormat.R32: return Read4Bpp (Memory, Texture);
case GalTextureFormat.BF10GF11RF11: return Read4Bpp (Memory, Texture);
case GalTextureFormat.Z24S8: return Read4Bpp (Memory, Texture);
case GalTextureFormat.A1B5G5R5: return Read5551 (Memory, Texture);
case GalTextureFormat.B5G6R5: return Read565 (Memory, Texture);
case GalTextureFormat.A4B4G4R4: return Read2Bpp (Memory, Texture);
case GalTextureFormat.G8R8: return Read2Bpp (Memory, Texture);
case GalTextureFormat.R16: return Read2Bpp (Memory, Texture);
case GalTextureFormat.R8: return Read1Bpp (Memory, Texture);
case GalTextureFormat.BC6H_SF16: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.BC6H_UF16: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.BC7U: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.BC1: return Read8Bpt4x4 (Memory, Texture);
case GalTextureFormat.BC2: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.BC3: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.BC4: return Read8Bpt4x4 (Memory, Texture);
case GalTextureFormat.BC5: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.ZF32: return Read4Bpp (Memory, Texture);
case GalTextureFormat.ZF32_X24S8: return Read8Bpp (Memory, Texture);
case GalTextureFormat.Astc2D4x4: return Read16BptCompressedTexture(Memory, Texture, 4, 4);
case GalTextureFormat.Astc2D5x5: return Read16BptCompressedTexture(Memory, Texture, 5, 5);
case GalTextureFormat.Astc2D6x6: return Read16BptCompressedTexture(Memory, Texture, 6, 6);
case GalTextureFormat.Astc2D8x8: return Read16BptCompressedTexture(Memory, Texture, 8, 8);
case GalTextureFormat.Astc2D10x10: return Read16BptCompressedTexture(Memory, Texture, 10, 10);
case GalTextureFormat.Astc2D12x12: return Read16BptCompressedTexture(Memory, Texture, 12, 12);
case GalTextureFormat.Astc2D5x4: return Read16BptCompressedTexture(Memory, Texture, 5, 4);
case GalTextureFormat.Astc2D6x5: return Read16BptCompressedTexture(Memory, Texture, 6, 5);
case GalTextureFormat.Astc2D8x6: return Read16BptCompressedTexture(Memory, Texture, 8, 6);
case GalTextureFormat.Astc2D10x8: return Read16BptCompressedTexture(Memory, Texture, 10, 8);
case GalTextureFormat.Astc2D12x10: return Read16BptCompressedTexture(Memory, Texture, 12, 10);
case GalTextureFormat.Astc2D8x5: return Read16BptCompressedTexture(Memory, Texture, 8, 5);
case GalTextureFormat.Astc2D10x5: return Read16BptCompressedTexture(Memory, Texture, 10, 5);
case GalTextureFormat.Astc2D10x6: return Read16BptCompressedTexture(Memory, Texture, 10, 6);
}
TextureReaderDelegate Reader = ImageUtils.GetReader(Texture.Format);
throw new NotImplementedException("0x" + ((int)Texture.Format).ToString("x2"));
return Reader(Memory, Texture);
}
private unsafe static byte[] Read1Bpp(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read1Bpp(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -86,7 +48,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read5551(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read5551(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -124,7 +86,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read565(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read565(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -161,7 +123,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read2Bpp(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read2Bpp(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -194,7 +156,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read4Bpp(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read4Bpp(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -227,7 +189,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read8Bpp(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read8Bpp(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -260,7 +222,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read16Bpp(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read16Bpp(IAMemory Memory, TextureInfo Texture)
{
int Width = Texture.Width;
int Height = Texture.Height;
@ -295,7 +257,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read8Bpt4x4(IAMemory Memory, TextureInfo Texture)
internal unsafe static byte[] Read8Bpt4x4(IAMemory Memory, TextureInfo Texture)
{
int Width = (Texture.Width + 3) / 4;
int Height = (Texture.Height + 3) / 4;
@ -328,7 +290,7 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
private unsafe static byte[] Read16BptCompressedTexture(IAMemory Memory, TextureInfo Texture, int BlockWidth, int BlockHeight)
internal unsafe static byte[] Read16BptCompressedTexture(IAMemory Memory, TextureInfo Texture, int BlockWidth, int BlockHeight)
{
int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth;
int Height = (Texture.Height + (BlockHeight - 1)) / BlockHeight;
@ -362,5 +324,75 @@ namespace Ryujinx.HLE.Gpu.Texture
return Output;
}
internal static byte[] Read16BptCompressedTexture4x4(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 4, 4);
}
internal static byte[] Read16BptCompressedTexture5x5(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 5, 5);
}
internal static byte[] Read16BptCompressedTexture6x6(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 6, 6);
}
internal static byte[] Read16BptCompressedTexture8x8(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 8, 8);
}
internal static byte[] Read16BptCompressedTexture10x10(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 10, 10);
}
internal static byte[] Read16BptCompressedTexture12x12(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 12, 12);
}
internal static byte[] Read16BptCompressedTexture5x4(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 5, 4);
}
internal static byte[] Read16BptCompressedTexture6x5(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 6, 5);
}
internal static byte[] Read16BptCompressedTexture8x6(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 8, 6);
}
internal static byte[] Read16BptCompressedTexture10x8(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 10, 8);
}
internal static byte[] Read16BptCompressedTexture12x10(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 12, 10);
}
internal static byte[] Read16BptCompressedTexture8x5(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 5, 5);
}
internal static byte[] Read16BptCompressedTexture10x5(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 10, 5);
}
internal static byte[] Read16BptCompressedTexture10x6(IAMemory Memory, TextureInfo Texture)
{
return Read16BptCompressedTexture(Memory, Texture, 10, 6);
}
}
}

4
Ryujinx.HLE/Gpu/Texture/TextureSwizzle.cs → Ryujinx.Graphics/Texture/TextureSwizzle.cs
View file

@ -1,6 +1,6 @@
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
enum TextureSwizzle
public enum TextureSwizzle
{
_1dBuffer = 0,
PitchColorKey = 1,

4
Ryujinx.HLE/Gpu/Texture/TextureWriter.cs → Ryujinx.Graphics/Texture/TextureWriter.cs
View file

@ -1,6 +1,8 @@
using ChocolArm64.Memory;
using Ryujinx.Graphics.Gal;
using Ryujinx.Graphics.Memory;
namespace Ryujinx.HLE.Gpu.Texture
namespace Ryujinx.Graphics.Texture
{
static class TextureWriter
{

12
Ryujinx.HLE/FileSystem/SaveDataType.cs Normal file
View file

@ -0,0 +1,12 @@
namespace Ryujinx.HLE.FileSystem
{
enum SaveDataType : byte
{
SystemSaveData,
SaveData,
BcatDeliveryCacheStorage,
DeviceSaveData,
TemporaryStorage,
CacheStorage
}
}

46
Ryujinx.HLE/FileSystem/SaveHelper.cs Normal file
View file

@ -0,0 +1,46 @@
using Ryujinx.HLE.HOS;
using System.IO;
using static Ryujinx.HLE.FileSystem.VirtualFileSystem;
namespace Ryujinx.HLE.FileSystem
{
static class SaveHelper
{
public static string GetSavePath(SaveInfo SaveMetaData, ServiceCtx Context)
{
string BaseSavePath = NandPath;
long CurrentTitleId = SaveMetaData.TitleId;
switch (SaveMetaData.SaveSpaceId)
{
case SaveSpaceId.NandUser:
BaseSavePath = UserNandPath;
break;
case SaveSpaceId.NandSystem:
BaseSavePath = SystemNandPath;
break;
case SaveSpaceId.SdCard:
BaseSavePath = Path.Combine(SdCardPath, "Nintendo");
break;
}
BaseSavePath = Path.Combine(BaseSavePath, "save");
if (SaveMetaData.TitleId == 0 && SaveMetaData.SaveDataType == SaveDataType.SaveData)
{
if (Context.Process.MetaData != null)
{
CurrentTitleId = Context.Process.MetaData.ACI0.TitleId;
}
}
string SavePath = Path.Combine(BaseSavePath,
SaveMetaData.SaveId.ToString("x16"),
SaveMetaData.UserId.ToString(),
SaveMetaData.SaveDataType == SaveDataType.SaveData ? CurrentTitleId.ToString("x16") : string.Empty);
return SavePath;
}
}
}

28
Ryujinx.HLE/FileSystem/SaveInfo.cs Normal file
View file

@ -0,0 +1,28 @@
using Ryujinx.HLE.HOS.SystemState;
namespace Ryujinx.HLE.FileSystem
{
struct SaveInfo
{
public long TitleId { get; private set; }
public long SaveId { get; private set; }
public UserId UserId { get; private set; }
public SaveDataType SaveDataType { get; private set; }
public SaveSpaceId SaveSpaceId { get; private set; }
public SaveInfo(
long TitleId,
long SaveId,
SaveDataType SaveDataType,
UserId UserId,
SaveSpaceId SaveSpaceId)
{
this.TitleId = TitleId;
this.UserId = UserId;
this.SaveId = SaveId;
this.SaveDataType = SaveDataType;
this.SaveSpaceId = SaveSpaceId;
}
}
}

10
Ryujinx.HLE/FileSystem/SaveSpaceId.cs Normal file
View file

@ -0,0 +1,10 @@
namespace Ryujinx.HLE.FileSystem
{
enum SaveSpaceId : byte
{
NandSystem,
NandUser,
SdCard,
TemporaryStorage
}
}

27
Ryujinx.HLE/VirtualFileSystem.cs → Ryujinx.HLE/FileSystem/VirtualFileSystem.cs
View file

@ -1,14 +1,18 @@
using Ryujinx.HLE.HOS;
using System;
using System.IO;
namespace Ryujinx.HLE
namespace Ryujinx.HLE.FileSystem
{
class VirtualFileSystem : IDisposable
{
private const string BasePath = "RyuFs";
private const string NandPath = "nand";
private const string SdCardPath = "sdmc";
private const string SystemPath = "system";
public const string BasePath = "RyuFs";
public const string NandPath = "nand";
public const string SdCardPath = "sdmc";
public const string SystemPath = "system";
public static string SystemNandPath = Path.Combine(NandPath, "system");
public static string UserNandPath = Path.Combine(NandPath, "user");
public Stream RomFs { get; private set; }
@ -17,6 +21,12 @@ namespace Ryujinx.HLE
RomFs = new FileStream(FileName, FileMode.Open, FileAccess.Read);
}
public void SetRomFs(Stream RomfsStream)
{
RomFs?.Close();
RomFs = RomfsStream;
}
public string GetFullPath(string BasePath, string FileName)
{
if (FileName.StartsWith("//"))
@ -44,10 +54,15 @@ namespace Ryujinx.HLE
public string GetSdCardPath() => MakeDirAndGetFullPath(SdCardPath);
public string GetGameSavesPath() => MakeDirAndGetFullPath(NandPath);
public string GetNandPath() => MakeDirAndGetFullPath(NandPath);
public string GetSystemPath() => MakeDirAndGetFullPath(SystemPath);
public string GetGameSavePath(SaveInfo Save, ServiceCtx Context)
{
return MakeDirAndGetFullPath(SaveHelper.GetSavePath(Save, Context));
}
public string SwitchPathToSystemPath(string SwitchPath)
{
string[] Parts = SwitchPath.Split(":");

204
Ryujinx.HLE/Gpu/Texture/TextureHelper.cs
View file

@ -1,204 +0,0 @@
using ChocolArm64.Memory;
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Memory;
using System;
namespace Ryujinx.HLE.Gpu.Texture
{
static class TextureHelper
{
public static ISwizzle GetSwizzle(TextureInfo Texture, int BlockWidth, int Bpp)
{
int Width = (Texture.Width + (BlockWidth - 1)) / BlockWidth;
int AlignMask = Texture.TileWidth * (64 / Bpp) - 1;
Width = (Width + AlignMask) & ~AlignMask;
switch (Texture.Swizzle)
{
case TextureSwizzle._1dBuffer:
case TextureSwizzle.Pitch:
case TextureSwizzle.PitchColorKey:
return new LinearSwizzle(Texture.Pitch, Bpp);
case TextureSwizzle.BlockLinear:
case TextureSwizzle.BlockLinearColorKey:
return new BlockLinearSwizzle(Width, Bpp, Texture.BlockHeight);
}
throw new NotImplementedException(Texture.Swizzle.ToString());
}
public static int GetTextureSize(GalImage Image)
{
switch (Image.Format)
{
case GalImageFormat.R32G32B32A32_SFLOAT:
case GalImageFormat.R32G32B32A32_SINT:
case GalImageFormat.R32G32B32A32_UINT:
return Image.Width * Image.Height * 16;
case GalImageFormat.R16G16B16A16_SFLOAT:
case GalImageFormat.R16G16B16A16_SINT:
case GalImageFormat.R16G16B16A16_SNORM:
case GalImageFormat.R16G16B16A16_UINT:
case GalImageFormat.R16G16B16A16_UNORM:
case GalImageFormat.D32_SFLOAT_S8_UINT:
case GalImageFormat.R32G32_SFLOAT:
case GalImageFormat.R32G32_SINT:
case GalImageFormat.R32G32_UINT:
return Image.Width * Image.Height * 8;
case GalImageFormat.A8B8G8R8_SINT_PACK32:
case GalImageFormat.A8B8G8R8_SNORM_PACK32:
case GalImageFormat.A8B8G8R8_UINT_PACK32:
case GalImageFormat.A8B8G8R8_UNORM_PACK32:
case GalImageFormat.A8B8G8R8_SRGB_PACK32:
case GalImageFormat.A2B10G10R10_SINT_PACK32:
case GalImageFormat.A2B10G10R10_SNORM_PACK32:
case GalImageFormat.A2B10G10R10_UINT_PACK32:
case GalImageFormat.A2B10G10R10_UNORM_PACK32:
case GalImageFormat.R16G16_SFLOAT:
case GalImageFormat.R16G16_SINT:
case GalImageFormat.R16G16_SNORM:
case GalImageFormat.R16G16_UINT:
case GalImageFormat.R16G16_UNORM:
case GalImageFormat.R32_SFLOAT:
case GalImageFormat.R32_SINT:
case GalImageFormat.R32_UINT:
case GalImageFormat.D32_SFLOAT:
case GalImageFormat.B10G11R11_UFLOAT_PACK32:
case GalImageFormat.D24_UNORM_S8_UINT:
return Image.Width * Image.Height * 4;
case GalImageFormat.B4G4R4A4_UNORM_PACK16:
case GalImageFormat.A1R5G5B5_UNORM_PACK16:
case GalImageFormat.B5G6R5_UNORM_PACK16:
case GalImageFormat.R8G8_SINT:
case GalImageFormat.R8G8_SNORM:
case GalImageFormat.R8G8_UINT:
case GalImageFormat.R8G8_UNORM:
case GalImageFormat.R16_SFLOAT:
case GalImageFormat.R16_SINT:
case GalImageFormat.R16_SNORM:
case GalImageFormat.R16_UINT:
case GalImageFormat.R16_UNORM:
case GalImageFormat.D16_UNORM:
return Image.Width * Image.Height * 2;
case GalImageFormat.R8_SINT:
case GalImageFormat.R8_SNORM:
case GalImageFormat.R8_UINT:
case GalImageFormat.R8_UNORM:
return Image.Width * Image.Height;
case GalImageFormat.BC1_RGBA_UNORM_BLOCK:
case GalImageFormat.BC4_SNORM_BLOCK:
case GalImageFormat.BC4_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 8);
}
case GalImageFormat.BC6H_SFLOAT_BLOCK:
case GalImageFormat.BC6H_UFLOAT_BLOCK:
case GalImageFormat.BC7_UNORM_BLOCK:
case GalImageFormat.BC2_UNORM_BLOCK:
case GalImageFormat.BC3_UNORM_BLOCK:
case GalImageFormat.BC5_SNORM_BLOCK:
case GalImageFormat.BC5_UNORM_BLOCK:
case GalImageFormat.ASTC_4x4_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 4, 4, 16);
}
case GalImageFormat.ASTC_5x5_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 5, 5, 16);
}
case GalImageFormat.ASTC_6x6_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 6, 6, 16);
}
case GalImageFormat.ASTC_8x8_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 8, 8, 16);
}
case GalImageFormat.ASTC_10x10_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 10, 10, 16);
}
case GalImageFormat.ASTC_12x12_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 12, 12, 16);
}
case GalImageFormat.ASTC_5x4_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 5, 4, 16);
}
case GalImageFormat.ASTC_6x5_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 6, 5, 16);
}
case GalImageFormat.ASTC_8x6_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 8, 6, 16);
}
case GalImageFormat.ASTC_10x8_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 10, 8, 16);
}
case GalImageFormat.ASTC_12x10_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 12, 10, 16);
}
case GalImageFormat.ASTC_8x5_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 8, 5, 16);
}
case GalImageFormat.ASTC_10x5_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 10, 5, 16);
}
case GalImageFormat.ASTC_10x6_UNORM_BLOCK:
{
return CompressedTextureSize(Image.Width, Image.Height, 10, 6, 16);
}
}
throw new NotImplementedException(Image.Format.ToString());
}
public static int CompressedTextureSize(int TextureWidth, int TextureHeight, int BlockWidth, int BlockHeight, int Bpb)
{
int W = (TextureWidth + (BlockWidth - 1)) / BlockWidth;
int H = (TextureHeight + (BlockHeight - 1)) / BlockHeight;
return W * H * Bpb;
}
public static (AMemory Memory, long Position) GetMemoryAndPosition(
IAMemory Memory,
long Position)
{
if (Memory is NvGpuVmm Vmm)
{
return (Vmm.Memory, Vmm.GetPhysicalAddress(Position));
}
return ((AMemory)Memory, Position);
}
}
}

217
Ryujinx.HLE/HOS/Horizon.cs
View file

@ -1,3 +1,4 @@
using LibHac;
using Ryujinx.HLE.HOS.Font;
using Ryujinx.HLE.HOS.Kernel;
using Ryujinx.HLE.HOS.SystemState;
@ -7,6 +8,7 @@ using Ryujinx.HLE.Logging;
using System;
using System.Collections.Concurrent;
using System.IO;
using System.Linq;
namespace Ryujinx.HLE.HOS
{
@ -30,6 +32,8 @@ namespace Ryujinx.HLE.HOS
internal KEvent VsyncEvent { get; private set; }
internal Keyset KeySet { get; private set; }
public Horizon(Switch Device)
{
this.Device = Device;
@ -52,6 +56,8 @@ namespace Ryujinx.HLE.HOS
Font = new SharedFontManager(Device, FontSharedMem.PA);
VsyncEvent = new KEvent();
LoadKeySet();
}
public void LoadCart(string ExeFsDir, string RomFsFile = null)
@ -103,7 +109,7 @@ namespace Ryujinx.HLE.HOS
}
}
if (!MainProcess.MetaData.Is64Bits)
if (!(MainProcess.MetaData?.Is64Bits ?? true))
{
throw new NotImplementedException("32-bit titles are unsupported!");
}
@ -119,6 +125,179 @@ namespace Ryujinx.HLE.HOS
MainProcess.Run();
}
public void LoadXci(string XciFile)
{
FileStream File = new FileStream(XciFile, FileMode.Open, FileAccess.Read);
Xci Xci = new Xci(KeySet, File);
Nca Nca = GetXciMainNca(Xci);
if (Nca == null)
{
Device.Log.PrintError(LogClass.Loader, "Unable to load XCI");
return;
}
LoadNca(Nca);
}
private Nca GetXciMainNca(Xci Xci)
{
if (Xci.SecurePartition == null)
{
throw new InvalidDataException("Could not find XCI secure partition");
}
Nca MainNca = null;
Nca PatchNca = null;
foreach (PfsFileEntry FileEntry in Xci.SecurePartition.Files.Where(x => x.Name.EndsWith(".nca")))
{
Stream NcaStream = Xci.SecurePartition.OpenFile(FileEntry);
Nca Nca = new Nca(KeySet, NcaStream, true);
if (Nca.Header.ContentType == ContentType.Program)
{
if (Nca.Sections.Any(x => x?.Type == SectionType.Romfs))
{
MainNca = Nca;
}
else if (Nca.Sections.Any(x => x?.Type == SectionType.Bktr))
{
PatchNca = Nca;
}
}
}
if (MainNca == null)
{
Device.Log.PrintError(LogClass.Loader, "Could not find an Application NCA in the provided XCI file");
}
MainNca.SetBaseNca(PatchNca);
return MainNca;
}
public void LoadNca(string NcaFile)
{
FileStream File = new FileStream(NcaFile, FileMode.Open, FileAccess.Read);
Nca Nca = new Nca(KeySet, File, true);
LoadNca(Nca);
}
public void LoadNsp(string NspFile)
{
FileStream File = new FileStream(NspFile, FileMode.Open, FileAccess.Read);
Pfs Nsp = new Pfs(File);
PfsFileEntry TicketFile = Nsp.Files.FirstOrDefault(x => x.Name.EndsWith(".tik"));
// Load title key from the NSP's ticket in case the user doesn't have a title key file
if (TicketFile != null)
{
// todo Change when Ticket(Stream) overload is added
Ticket Ticket = new Ticket(new BinaryReader(Nsp.OpenFile(TicketFile)));
KeySet.TitleKeys[Ticket.RightsId] = Ticket.GetTitleKey(KeySet);
}
foreach (PfsFileEntry NcaFile in Nsp.Files.Where(x => x.Name.EndsWith(".nca")))
{
Nca Nca = new Nca(KeySet, Nsp.OpenFile(NcaFile), true);
if (Nca.Header.ContentType == ContentType.Program)
{
LoadNca(Nca);
return;
}
}
Device.Log.PrintError(LogClass.Loader, "Could not find an Application NCA in the provided NSP file");
}
public void LoadNca(Nca Nca)
{
NcaSection RomfsSection = Nca.Sections.FirstOrDefault(x => x?.Type == SectionType.Romfs);
NcaSection ExefsSection = Nca.Sections.FirstOrDefault(x => x?.IsExefs == true);
if (ExefsSection == null)
{
Device.Log.PrintError(LogClass.Loader, "No ExeFS found in NCA");
return;
}
if (RomfsSection == null)
{
Device.Log.PrintError(LogClass.Loader, "No RomFS found in NCA");
return;
}
Stream RomfsStream = Nca.OpenSection(RomfsSection.SectionNum, false);
Device.FileSystem.SetRomFs(RomfsStream);
Stream ExefsStream = Nca.OpenSection(ExefsSection.SectionNum, false);
Pfs Exefs = new Pfs(ExefsStream);
Npdm MetaData = null;
if (Exefs.FileExists("main.npdm"))
{
Device.Log.PrintInfo(LogClass.Loader, "Loading main.npdm...");
MetaData = new Npdm(Exefs.OpenFile("main.npdm"));
}
else
{
Device.Log.PrintWarning(LogClass.Loader, $"NPDM file not found, using default values!");
}
Process MainProcess = MakeProcess(MetaData);
void LoadNso(string Filename)
{
foreach (PfsFileEntry File in Exefs.Files.Where(x => x.Name.StartsWith(Filename)))
{
if (Path.GetExtension(File.Name) != string.Empty)
{
continue;
}
Device.Log.PrintInfo(LogClass.Loader, $"Loading {Filename}...");
string Name = Path.GetFileNameWithoutExtension(File.Name);
Nso Program = new Nso(Exefs.OpenFile(File), Name);
MainProcess.LoadProgram(Program);
}
}
if (!MainProcess.MetaData.Is64Bits)
{
throw new NotImplementedException("32-bit titles are unsupported!");
}
LoadNso("rtld");
MainProcess.SetEmptyArgs();
LoadNso("main");
LoadNso("subsdk");
LoadNso("sdk");
MainProcess.Run();
}
public void LoadProgram(string FilePath)
{
bool IsNro = Path.GetExtension(FilePath).ToLower() == ".nro";
@ -156,6 +335,42 @@ namespace Ryujinx.HLE.HOS
MainProcess.Run(IsNro);
}
public void LoadKeySet()
{
string KeyFile = null;
string TitleKeyFile = null;
string ConsoleKeyFile = null;
string Home = Environment.GetFolderPath(Environment.SpecialFolder.UserProfile);
LoadSetAtPath(Path.Combine(Home, ".switch"));
LoadSetAtPath(Device.FileSystem.GetSystemPath());
KeySet = ExternalKeys.ReadKeyFile(KeyFile, TitleKeyFile, ConsoleKeyFile);
void LoadSetAtPath(string BasePath)
{
string LocalKeyFile = Path.Combine(BasePath, "prod.keys");
string LocalTitleKeyFile = Path.Combine(BasePath, "title.keys");
string LocalConsoleKeyFile = Path.Combine(BasePath, "console.keys");
if (File.Exists(LocalKeyFile))
{
KeyFile = LocalKeyFile;
}
if (File.Exists(LocalTitleKeyFile))
{
TitleKeyFile = LocalTitleKeyFile;
}
if (File.Exists(LocalConsoleKeyFile))
{
ConsoleKeyFile = LocalConsoleKeyFile;
}
}
}
public void SignalVsync() => VsyncEvent.WaitEvent.Set();
private Process MakeProcess(Npdm MetaData = null)

44
Ryujinx.HLE/HOS/Services/FspSrv/IFileSystemProxy.cs
View file

@ -1,5 +1,6 @@
using Ryujinx.HLE.FileSystem;
using Ryujinx.HLE.HOS.Ipc;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.HOS.SystemState;
using System.Collections.Generic;
namespace Ryujinx.HLE.HOS.Services.FspSrv
@ -14,13 +15,13 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv
{
m_Commands = new Dictionary<int, ServiceProcessRequest>()
{
{ 1, SetCurrentProcess },
{ 18, OpenSdCardFileSystem },
{ 22, CreateSaveDataFileSystem },
{ 51, OpenSaveDataFileSystem },
{ 200, OpenDataStorageByCurrentProcess },
{ 203, OpenPatchDataStorageByCurrentProcess },
{ 1005, GetGlobalAccessLogMode }
{ 1, SetCurrentProcess },
{ 18, OpenSdCardFileSystem },
{ 51, OpenSaveDataFileSystem },
{ 52, OpenSaveDataFileSystemBySystemSaveDataId },
{ 200, OpenDataStorageByCurrentProcess },
{ 203, OpenPatchDataStorageByCurrentProcess },
{ 1005, GetGlobalAccessLogMode }
};
}
@ -36,16 +37,16 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv
return 0;
}
public long CreateSaveDataFileSystem(ServiceCtx Context)
public long OpenSaveDataFileSystem(ServiceCtx Context)
{
Context.Device.Log.PrintStub(LogClass.ServiceFs, "Stubbed.");
LoadSaveDataFileSystem(Context);
return 0;
}
public long OpenSaveDataFileSystem(ServiceCtx Context)
public long OpenSaveDataFileSystemBySystemSaveDataId(ServiceCtx Context)
{
MakeObject(Context, new IFileSystem(Context.Device.FileSystem.GetGameSavesPath()));
LoadSaveDataFileSystem(Context);
return 0;
}
@ -70,5 +71,24 @@ namespace Ryujinx.HLE.HOS.Services.FspSrv
return 0;
}
public void LoadSaveDataFileSystem(ServiceCtx Context)
{
SaveSpaceId SaveSpaceId = (SaveSpaceId)Context.RequestData.ReadInt64();
long TitleId = Context.RequestData.ReadInt64();
UserId UserId = new UserId(
Context.RequestData.ReadInt64(),
Context.RequestData.ReadInt64());
long SaveId = Context.RequestData.ReadInt64();
SaveDataType SaveDataType = (SaveDataType)Context.RequestData.ReadByte();
SaveInfo SaveInfo = new SaveInfo(TitleId, SaveId, SaveDataType, UserId, SaveSpaceId);
MakeObject(Context, new IFileSystem(Context.Device.FileSystem.GetGameSavePath(SaveInfo, Context)));
}
}
}

2
Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASCtx.cs
View file

@ -1,4 +1,4 @@
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using System.Collections.Generic;
namespace Ryujinx.HLE.HOS.Services.Nv.NvGpuAS

2
Ryujinx.HLE/HOS/Services/Nv/NvGpuAS/NvGpuASIoctl.cs
View file

@ -1,5 +1,5 @@
using ChocolArm64.Memory;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using Ryujinx.HLE.HOS.Services.Nv.NvMap;
using Ryujinx.HLE.Logging;
using System;

2
Ryujinx.HLE/HOS/Services/Nv/NvHostChannel/NvHostChannelIoctl.cs
View file

@ -1,5 +1,5 @@
using ChocolArm64.Memory;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using Ryujinx.HLE.HOS.Services.Nv.NvGpuAS;
using Ryujinx.HLE.Logging;
using System;

2
Ryujinx.HLE/HOS/Services/Nv/NvMap/NvMapIoctl.cs
View file

@ -1,5 +1,5 @@
using ChocolArm64.Memory;
using Ryujinx.HLE.Gpu.Memory;
using Ryujinx.Graphics.Memory;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.Utilities;
using System.Collections.Concurrent;

13
Ryujinx.HLE/HOS/Services/Vi/NvFlinger.cs
View file

@ -1,5 +1,5 @@
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu.Texture;
using Ryujinx.Graphics.Texture;
using Ryujinx.HLE.HOS.Kernel;
using Ryujinx.HLE.HOS.Services.Nv.NvMap;
using Ryujinx.HLE.Logging;
@ -199,6 +199,11 @@ namespace Ryujinx.HLE.HOS.Services.Android
SendFrameBuffer(Context, Slot);
if (Context.Device.EnableDeviceVsync)
{
Context.Device.VsyncEvent.WaitOne();
}
return MakeReplyParcel(Context, 1280, 720, 0, 0, 0);
}
@ -303,7 +308,7 @@ namespace Ryujinx.HLE.HOS.Services.Android
int Right = Crop.Right;
int Bottom = Crop.Bottom;
Renderer.QueueAction(() => Renderer.FrameBuffer.SetTransform(FlipX, FlipY, Top, Left, Right, Bottom));
Renderer.QueueAction(() => Renderer.RenderTarget.SetTransform(FlipX, FlipY, Top, Left, Right, Bottom));
//TODO: Support double buffering here aswell, it is broken for GPU
//frame buffers because it seems to be completely out of sync.
@ -311,7 +316,7 @@ namespace Ryujinx.HLE.HOS.Services.Android
{
//Frame buffer is rendered to by the GPU, we can just
//bind the frame buffer texture, it's not necessary to read anything.
Renderer.QueueAction(() => Renderer.FrameBuffer.Set(FbAddr));
Renderer.QueueAction(() => Renderer.RenderTarget.Set(FbAddr));
}
else
{
@ -321,7 +326,7 @@ namespace Ryujinx.HLE.HOS.Services.Android
byte[] Data = TextureReader.Read(Context.Memory, Texture);
Renderer.QueueAction(() => Renderer.FrameBuffer.Set(Data, FbWidth, FbHeight));
Renderer.QueueAction(() => Renderer.RenderTarget.Set(Data, FbWidth, FbHeight));
}
Context.Device.Gpu.Renderer.QueueAction(() => ReleaseBuffer(Slot));

1
Ryujinx.HLE/Ryujinx.HLE.csproj
View file

@ -25,6 +25,7 @@
<ProjectReference Include="..\ChocolArm64\ChocolArm64.csproj" />
<ProjectReference Include="..\Ryujinx.Audio\Ryujinx.Audio.csproj" />
<ProjectReference Include="..\Ryujinx.Graphics\Ryujinx.Graphics.csproj" />
<PackageReference Include="LibHac" Version="0.1.1" />
</ItemGroup>
</Project>

29
Ryujinx.HLE/Switch.cs
View file

@ -1,11 +1,13 @@
using Ryujinx.Audio;
using Ryujinx.Graphics;
using Ryujinx.Graphics.Gal;
using Ryujinx.HLE.Gpu;
using Ryujinx.HLE.FileSystem;
using Ryujinx.HLE.HOS;
using Ryujinx.HLE.Input;
using Ryujinx.HLE.Logging;
using Ryujinx.HLE.Memory;
using System;
using System.Threading;
namespace Ryujinx.HLE
{
@ -27,6 +29,12 @@ namespace Ryujinx.HLE
public Hid Hid { get; private set; }
public bool EnableDeviceVsync { get; set; } = true;
public AutoResetEvent VsyncEvent { get; private set; }
public event EventHandler Finish;
public Switch(IGalRenderer Renderer, IAalOutput AudioOut)
{
if (Renderer == null)
@ -54,6 +62,8 @@ namespace Ryujinx.HLE
Statistics = new PerformanceStatistics();
Hid = new Hid(this, System.HidSharedMem.PA);
VsyncEvent = new AutoResetEvent(true);
}
public void LoadCart(string ExeFsDir, string RomFsFile = null)
@ -61,6 +71,21 @@ namespace Ryujinx.HLE
System.LoadCart(ExeFsDir, RomFsFile);
}
public void LoadXci(string XciFile)
{
System.LoadXci(XciFile);
}
public void LoadNca(string NcaFile)
{
System.LoadNca(NcaFile);
}
public void LoadNsp(string NspFile)
{
System.LoadNsp(NspFile);
}
public void LoadProgram(string FileName)
{
System.LoadProgram(FileName);
@ -93,6 +118,8 @@ namespace Ryujinx.HLE
if (Disposing)
{
System.Dispose();
VsyncEvent.Dispose();
}
}
}

103
Ryujinx.Tests/Cpu/CpuTest.cs
View file

@ -33,9 +33,10 @@ namespace Ryujinx.Tests.Cpu
static CpuTest()
{
UnicornAvailable = UnicornAArch64.IsAvailable();
if (!UnicornAvailable)
{
Console.WriteLine("WARNING: Could not find unicorn");
Console.WriteLine("WARNING: Could not find Unicorn.");
}
}
@ -43,7 +44,7 @@ namespace Ryujinx.Tests.Cpu
public void Setup()
{
Position = 0x1000;
Size = 0x1000;
Size = 0x1000;
EntryPoint = Position;
@ -79,10 +80,12 @@ namespace Ryujinx.Tests.Cpu
protected void Opcode(uint Opcode)
{
Thread.Memory.WriteUInt32(Position, Opcode);
if (UnicornAvailable)
{
UnicornEmu.MemoryWrite32((ulong)Position, Opcode);
}
Position += 4;
}
@ -97,14 +100,18 @@ namespace Ryujinx.Tests.Cpu
Thread.ThreadState.X1 = X1;
Thread.ThreadState.X2 = X2;
Thread.ThreadState.X3 = X3;
Thread.ThreadState.X31 = X31;
Thread.ThreadState.V0 = V0;
Thread.ThreadState.V1 = V1;
Thread.ThreadState.V2 = V2;
Thread.ThreadState.Overflow = Overflow;
Thread.ThreadState.Carry = Carry;
Thread.ThreadState.Zero = Zero;
Thread.ThreadState.Carry = Carry;
Thread.ThreadState.Zero = Zero;
Thread.ThreadState.Negative = Negative;
Thread.ThreadState.Fpcr = Fpcr;
Thread.ThreadState.Fpsr = Fpsr;
@ -114,14 +121,18 @@ namespace Ryujinx.Tests.Cpu
UnicornEmu.X[1] = X1;
UnicornEmu.X[2] = X2;
UnicornEmu.X[3] = X3;
UnicornEmu.SP = X31;
UnicornEmu.Q[0] = V0;
UnicornEmu.Q[1] = V1;
UnicornEmu.Q[2] = V2;
UnicornEmu.OverflowFlag = Overflow;
UnicornEmu.CarryFlag = Carry;
UnicornEmu.ZeroFlag = Zero;
UnicornEmu.CarryFlag = Carry;
UnicornEmu.ZeroFlag = Zero;
UnicornEmu.NegativeFlag = Negative;
UnicornEmu.Fpcr = Fpcr;
UnicornEmu.Fpsr = Fpsr;
}
@ -144,10 +155,7 @@ namespace Ryujinx.Tests.Cpu
}
}
protected AThreadState GetThreadState()
{
return Thread.ThreadState;
}
protected AThreadState GetThreadState() => Thread.ThreadState;
protected AThreadState SingleOpcode(uint Opcode,
ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0,
@ -166,23 +174,44 @@ namespace Ryujinx.Tests.Cpu
return GetThreadState();
}
protected void CompareAgainstUnicorn()
[Flags]
protected enum FPSR
{
None = 0,
/// <summary>Invalid Operation cumulative floating-point exception bit.</summary>
IOC = 1 << 0,
/// <summary>Divide by Zero cumulative floating-point exception bit.</summary>
DZC = 1 << 1,
/// <summary>Overflow cumulative floating-point exception bit.</summary>
OFC = 1 << 2,
/// <summary>Underflow cumulative floating-point exception bit.</summary>
UFC = 1 << 3,
/// <summary>Inexact cumulative floating-point exception bit.</summary>
IXC = 1 << 4,
/// <summary>Input Denormal cumulative floating-point exception bit.</summary>
IDC = 1 << 7,
/// <summary>Cumulative saturation bit.</summary>
QC = 1 << 27
}
protected void CompareAgainstUnicorn(FPSR FpsrMask = FPSR.None)
{
if (!UnicornAvailable)
{
return;
}
Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0]));
Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1]));
Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2]));
Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3]));
Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4]));
Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5]));
Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6]));
Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7]));
Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8]));
Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9]));
Assert.That(Thread.ThreadState.X0, Is.EqualTo(UnicornEmu.X[0]));
Assert.That(Thread.ThreadState.X1, Is.EqualTo(UnicornEmu.X[1]));
Assert.That(Thread.ThreadState.X2, Is.EqualTo(UnicornEmu.X[2]));
Assert.That(Thread.ThreadState.X3, Is.EqualTo(UnicornEmu.X[3]));
Assert.That(Thread.ThreadState.X4, Is.EqualTo(UnicornEmu.X[4]));
Assert.That(Thread.ThreadState.X5, Is.EqualTo(UnicornEmu.X[5]));
Assert.That(Thread.ThreadState.X6, Is.EqualTo(UnicornEmu.X[6]));
Assert.That(Thread.ThreadState.X7, Is.EqualTo(UnicornEmu.X[7]));
Assert.That(Thread.ThreadState.X8, Is.EqualTo(UnicornEmu.X[8]));
Assert.That(Thread.ThreadState.X9, Is.EqualTo(UnicornEmu.X[9]));
Assert.That(Thread.ThreadState.X10, Is.EqualTo(UnicornEmu.X[10]));
Assert.That(Thread.ThreadState.X11, Is.EqualTo(UnicornEmu.X[11]));
Assert.That(Thread.ThreadState.X12, Is.EqualTo(UnicornEmu.X[12]));
@ -204,17 +233,19 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Thread.ThreadState.X28, Is.EqualTo(UnicornEmu.X[28]));
Assert.That(Thread.ThreadState.X29, Is.EqualTo(UnicornEmu.X[29]));
Assert.That(Thread.ThreadState.X30, Is.EqualTo(UnicornEmu.X[30]));
Assert.That(Thread.ThreadState.X31, Is.EqualTo(UnicornEmu.SP));
Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0]));
Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1]));
Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2]));
Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3]));
Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4]));
Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5]));
Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6]));
Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7]));
Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8]));
Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9]));
Assert.That(Thread.ThreadState.V0, Is.EqualTo(UnicornEmu.Q[0]));
Assert.That(Thread.ThreadState.V1, Is.EqualTo(UnicornEmu.Q[1]));
Assert.That(Thread.ThreadState.V2, Is.EqualTo(UnicornEmu.Q[2]));
Assert.That(Thread.ThreadState.V3, Is.EqualTo(UnicornEmu.Q[3]));
Assert.That(Thread.ThreadState.V4, Is.EqualTo(UnicornEmu.Q[4]));
Assert.That(Thread.ThreadState.V5, Is.EqualTo(UnicornEmu.Q[5]));
Assert.That(Thread.ThreadState.V6, Is.EqualTo(UnicornEmu.Q[6]));
Assert.That(Thread.ThreadState.V7, Is.EqualTo(UnicornEmu.Q[7]));
Assert.That(Thread.ThreadState.V8, Is.EqualTo(UnicornEmu.Q[8]));
Assert.That(Thread.ThreadState.V9, Is.EqualTo(UnicornEmu.Q[9]));
Assert.That(Thread.ThreadState.V10, Is.EqualTo(UnicornEmu.Q[10]));
Assert.That(Thread.ThreadState.V11, Is.EqualTo(UnicornEmu.Q[11]));
Assert.That(Thread.ThreadState.V12, Is.EqualTo(UnicornEmu.Q[12]));
@ -238,11 +269,13 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Thread.ThreadState.V30, Is.EqualTo(UnicornEmu.Q[30]));
Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31]));
Assert.That(Thread.ThreadState.V31, Is.EqualTo(UnicornEmu.Q[31]));
Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr));
Assert.That(Thread.ThreadState.Fpsr & 0x08000000, Is.EqualTo(UnicornEmu.Fpsr & 0x08000000));
Assert.That(Thread.ThreadState.Fpcr, Is.EqualTo(UnicornEmu.Fpcr));
Assert.That(Thread.ThreadState.Fpsr & (int)FpsrMask, Is.EqualTo(UnicornEmu.Fpsr & (int)FpsrMask));
Assert.That(Thread.ThreadState.Overflow, Is.EqualTo(UnicornEmu.OverflowFlag));
Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag));
Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag));
Assert.That(Thread.ThreadState.Carry, Is.EqualTo(UnicornEmu.CarryFlag));
Assert.That(Thread.ThreadState.Zero, Is.EqualTo(UnicornEmu.ZeroFlag));
Assert.That(Thread.ThreadState.Negative, Is.EqualTo(UnicornEmu.NegativeFlag));
}

223
Ryujinx.Tests/Cpu/CpuTestAlu.cs
View file

@ -1,4 +1,4 @@
//#define Alu
#define Alu
using ChocolArm64.State;
@ -6,334 +6,185 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Alu"), Ignore("Tested: second half of 2018.")]
[Category("Alu")] // Tested: second half of 2018.
public sealed class CpuTestAlu : CpuTest
{
#if Alu
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
[Test, Description("CLS <Xd>, <Xn>")]
[Test, Pairwise, Description("CLS <Xd>, <Xn>")]
public void Cls_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC01400; // CLS X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CLS <Wd>, <Wn>")]
[Test, Pairwise, Description("CLS <Wd>, <Wn>")]
public void Cls_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC01400; // CLS W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Cls(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("CLZ <Xd>, <Xn>")]
[Test, Pairwise, Description("CLZ <Xd>, <Xn>")]
public void Clz_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC01000; // CLZ X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CLZ <Wd>, <Wn>")]
[Test, Pairwise, Description("CLZ <Wd>, <Wn>")]
public void Clz_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC01000; // CLZ W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Clz(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("RBIT <Xd>, <Xn>")]
[Test, Pairwise, Description("RBIT <Xd>, <Xn>")]
public void Rbit_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00000; // RBIT X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("RBIT <Wd>, <Wn>")]
[Test, Pairwise, Description("RBIT <Wd>, <Wn>")]
public void Rbit_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00000; // RBIT W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Rbit(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("REV16 <Xd>, <Xn>")]
[Test, Pairwise, Description("REV16 <Xd>, <Xn>")]
public void Rev16_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00400; // REV16 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("REV16 <Wd>, <Wn>")]
[Test, Pairwise, Description("REV16 <Wd>, <Wn>")]
public void Rev16_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00400; // REV16 W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Rev16(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("REV32 <Xd>, <Xn>")]
[Test, Pairwise, Description("REV32 <Xd>, <Xn>")]
public void Rev32_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00800; // REV32 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("REV <Wd>, <Wn>")]
[Test, Pairwise, Description("REV <Wd>, <Wn>")]
public void Rev32_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn)
{
uint Opcode = 0x5AC00800; // REV W0, W0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Rev32(Op[31], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("REV64 <Xd>, <Xn>")]
[Test, Pairwise, Description("REV64 <Xd>, <Xn>")]
public void Rev64_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn)
{
uint Opcode = 0xDAC00C00; // REV64 X0, X0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Rev64(Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
#endif

556
Ryujinx.Tests/Cpu/CpuTestAluImm.cs
View file

@ -1,4 +1,4 @@
//#define AluImm
#define AluImm
using ChocolArm64.State;
@ -6,824 +6,448 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("AluImm"), Ignore("Tested: second half of 2018.")]
[Category("AluImm")] // Tested: second half of 2018.
public sealed class CpuTestAluImm : CpuTest
{
#if AluImm
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
private const int RndCntImm = 2;
private const int RndCntImms = 2;
private const int RndCntImmr = 2;
[Test, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
public void Add_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("ADD <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
public void Add_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
[Test, Description("ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
public void Adds_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong _X31 = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
public void Adds_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint _W31 = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("AND <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
public void And_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x92400000; // AND X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("AND <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("AND <Xd|SP>, <Xn>, #<imm>")]
public void And_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x92000000; // AND X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("AND <Wd|WSP>, <Wn>, #<imm>")]
[Test, Pairwise, Description("AND <Wd|WSP>, <Wn>, #<imm>")]
public void And_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x12000000; // AND W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
[Test, Description("ANDS <Xd>, <Xn>, #<imm>")]
[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
public void Ands_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
if (Rd != 31)
{
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("ANDS <Xd>, <Xn>, #<imm>")]
[Test, Pairwise, Description("ANDS <Xd>, <Xn>, #<imm>")]
public void Ands_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
if (Rd != 31)
{
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("ANDS <Wd>, <Wn>, #<imm>")]
[Test, Pairwise, Description("ANDS <Wd>, <Wn>, #<imm>")]
public void Ands_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x72000000; // ANDS W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
if (Rd != 31)
{
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
public void Eor_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xD2400000; // EOR X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("EOR <Xd|SP>, <Xn>, #<imm>")]
public void Eor_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("EOR <Wd>, <Wn>, #<imm>")]
[Test, Pairwise, Description("EOR <Wd>, <Wn>, #<imm>")]
public void Eor_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x52000000; // EOR W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
[Test, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
public void Orr_N1_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, RndCntImms)] uint imms, // <imm>
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xB2400000; // ORR X0, X0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
[Test, Pairwise, Description("ORR <Xd|SP>, <Xn>, #<imm>")]
public void Orr_N0_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
AArch64.X((int)Rn, new Bits(Xn));
Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("ORR <Wd|WSP>, <Wn>, #<imm>")]
[Test, Pairwise, Description("ORR <Wd|WSP>, <Wn>, #<imm>")]
public void Orr_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // <imm>
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, RndCntImms)] uint imms, // <imm>
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr) // <imm>
{
uint Opcode = 0x32000000; // ORR W0, W0, #0x1
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
Bits Op = new Bits(Opcode);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
AArch64.X((int)Rn, new Bits(Wn));
Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
[Test, Description("SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}")]
public void Sub_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong SP = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP));
}
CompareAgainstUnicorn();
}
[Test, Description("SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("SUB <Wd|WSP>, <Wn|WSP>, #<imm>{, <shift>}")]
public void Sub_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint WSP = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP));
}
CompareAgainstUnicorn();
}
[Test, Description("SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}")]
public void Subs_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn_SP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Xn_SP);
AArch64.X((int)Rn, new Bits(Xn_SP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Xn_SP);
AArch64.SP(new Bits(Xn_SP));
}
Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
ulong _X31 = AArch64.SP(64).ToUInt64();
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
[Test, Pairwise, Description("SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}")]
public void Subs_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn_WSP,
[Values(0u, 4095u)] [Random(0u, 4095u, RndCntImm)] uint imm,
[Values(0b00u, 0b01u)] uint shift) // <LSL #0, LSL #12>
{
uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10);
Bits Op = new Bits(Opcode);
AThreadState ThreadState;
if (Rn != 31)
{
ThreadState = SingleOpcode(Opcode, X1: Wn_WSP);
AArch64.X((int)Rn, new Bits(Wn_WSP));
}
else
{
ThreadState = SingleOpcode(Opcode, X31: Wn_WSP);
AArch64.SP(new Bits(Wn_WSP));
}
Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]);
if (Rd != 31)
{
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
uint _W31 = AArch64.SP(32).ToUInt32();
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
#endif

1337
Ryujinx.Tests/Cpu/CpuTestAluRs.cs
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File diff suppressed because it is too large Load diff

825
Ryujinx.Tests/Cpu/CpuTestAluRx.cs
View file

File diff suppressed because it is too large Load diff

159
Ryujinx.Tests/Cpu/CpuTestBfm.cs
View file

@ -1,4 +1,4 @@
//#define Bfm
#define Bfm
using ChocolArm64.State;
@ -6,212 +6,127 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Bfm"), Ignore("Tested: second half of 2018.")]
[Category("Bfm")] // Tested: second half of 2018.
public sealed class CpuTestBfm : CpuTest
{
#if Bfm
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
private const int RndCntImmr = 2;
private const int RndCntImms = 2;
[Test, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("BFM <Xd>, <Xn>, #<immr>, #<imms>")]
public void Bfm_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Random(2)] ulong _Xd,
[Random(RndCnt)] ulong _Xd,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
{
uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Xd));
AArch64.X((int)Rn, new Bits(Xn));
Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("BFM <Wd>, <Wn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("BFM <Wd>, <Wn>, #<immr>, #<imms>")]
public void Bfm_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Random(2)] uint _Wd,
[Random(RndCnt)] uint _Wd,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
{
uint Opcode = 0x33000000; // BFM W0, W0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Wd));
AArch64.X((int)Rn, new Bits(Wn));
Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("SBFM <Xd>, <Xn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("SBFM <Xd>, <Xn>, #<immr>, #<imms>")]
public void Sbfm_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
{
uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("SBFM <Wd>, <Wn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("SBFM <Wd>, <Wn>, #<immr>, #<imms>")]
public void Sbfm_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
{
uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("UBFM <Xd>, <Xn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("UBFM <Xd>, <Xn>, #<immr>, #<imms>")]
public void Ubfm_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImmr)] uint immr,
[Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, RndCntImms)] uint imms)
{
uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("UBFM <Wd>, <Wn>, #<immr>, #<imms>")]
[Test, Pairwise, Description("UBFM <Wd>, <Wn>, #<immr>, #<imms>")]
public void Ubfm_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImmr)] uint immr,
[Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, RndCntImms)] uint imms)
{
uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
#endif

99
Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs
View file

@ -1,4 +1,4 @@
//#define CcmpImm
#define CcmpImm
using ChocolArm64.State;
@ -6,25 +6,20 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("CcmpImm"), Ignore("Tested: second half of 2018.")]
[Category("CcmpImm")] // Tested: second half of 2018.
public sealed class CpuTestCcmpImm : CpuTest
{
#if CcmpImm
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
private const int RndCntImm = 2;
private const int RndCntNzcv = 2;
[Test, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMN <Xn>, #<imm>, #<nzcv>, <cond>")]
public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
[Random(0u, 15u, 1)] uint nzcv,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -35,29 +30,18 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMN <Wn>, #<imm>, #<nzcv>, <cond>")]
public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
[Random(0u, 15u, 1)] uint nzcv,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -68,29 +52,18 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMP <Xn>, #<imm>, #<nzcv>, <cond>")]
public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
[Random(0u, 15u, 1)] uint nzcv,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -101,29 +74,18 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMP <Wn>, #<imm>, #<nzcv>, <cond>")]
public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
[Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm,
[Random(0u, 15u, 1)] uint nzcv,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0u, 31u)] [Random(0u, 31u, RndCntImm)] uint imm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -134,20 +96,9 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
#endif

102
Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs
View file

@ -1,4 +1,4 @@
//#define CcmpReg
#define CcmpReg
using ChocolArm64.State;
@ -6,27 +6,21 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("CcmpReg"), Ignore("Tested: second half of 2018.")]
[Category("CcmpReg")] // Tested: second half of 2018.
public sealed class CpuTestCcmpReg : CpuTest
{
#if CcmpReg
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
private const int RndCntNzcv = 2;
[Test, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMN <Xn>, <Xm>, #<nzcv>, <cond>")]
public void Ccmn_64bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
[Random(0u, 15u, 1)] uint nzcv,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -37,32 +31,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMN <Wn>, <Wm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMN <Wn>, <Wm>, #<nzcv>, <cond>")]
public void Ccmn_32bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
[Random(0u, 15u, 1)] uint nzcv,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -73,32 +55,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMP <Xn>, <Xm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMP <Xn>, <Xm>, #<nzcv>, <cond>")]
public void Ccmp_64bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
[Random(0u, 15u, 1)] uint nzcv,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -109,32 +79,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
[Test, Description("CCMP <Wn>, <Wm>, #<nzcv>, <cond>")]
[Test, Pairwise, Description("CCMP <Wn>, <Wm>, #<nzcv>, <cond>")]
public void Ccmp_32bit([Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
[Random(0u, 15u, 1)] uint nzcv,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Random(0u, 15u, RndCntNzcv)] uint nzcv,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -145,21 +103,9 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N));
Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z));
Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C));
Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V));
});
CompareAgainstUnicorn();
}
#endif

189
Ryujinx.Tests/Cpu/CpuTestCsel.cs
View file

@ -1,4 +1,4 @@
//#define Csel
#define Csel
using ChocolArm64.State;
@ -6,27 +6,20 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Csel"), Ignore("Tested: second half of 2018.")]
[Category("Csel")] // Tested: second half of 2018.
public sealed class CpuTestCsel : CpuTest
{
#if Csel
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
[Test, Description("CSEL <Xd>, <Xn>, <Xm>, <cond>")]
[Test, Pairwise, Description("CSEL <Xd>, <Xn>, <Xm>, <cond>")]
public void Csel_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -37,34 +30,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Csel(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSEL <Wd>, <Wn>, <Wm>, <cond>")]
[Test, Pairwise, Description("CSEL <Wd>, <Wn>, <Wm>, <cond>")]
public void Csel_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -75,34 +54,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Csel(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSINC <Xd>, <Xn>, <Xm>, <cond>")]
[Test, Pairwise, Description("CSINC <Xd>, <Xn>, <Xm>, <cond>")]
public void Csinc_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -113,34 +78,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Csinc(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSINC <Wd>, <Wn>, <Wm>, <cond>")]
[Test, Pairwise, Description("CSINC <Wd>, <Wn>, <Wm>, <cond>")]
public void Csinc_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -151,34 +102,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Csinc(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSINV <Xd>, <Xn>, <Xm>, <cond>")]
[Test, Pairwise, Description("CSINV <Xd>, <Xn>, <Xm>, <cond>")]
public void Csinv_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -189,34 +126,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Csinv(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSINV <Wd>, <Wn>, <Wm>, <cond>")]
[Test, Pairwise, Description("CSINV <Wd>, <Wn>, <Wm>, <cond>")]
public void Csinv_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -227,34 +150,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Csinv(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSNEG <Xd>, <Xn>, <Xm>, <cond>")]
[Test, Pairwise, Description("CSNEG <Xd>, <Xn>, <Xm>, <cond>")]
public void Csneg_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -265,34 +174,20 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Csneg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("CSNEG <Wd>, <Wn>, <Wm>, <cond>")]
[Test, Pairwise, Description("CSNEG <Wd>, <Wn>, <Wm>, <cond>")]
public void Csneg_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // <EQ, NE, CS/HS, CC/LO,
0b0100u, 0b0101u, 0b0110u, 0b0111u, // MI, PL, VS, VC,
0b1000u, 0b1001u, 0b1010u, 0b1011u, // HI, LS, GE, LT,
@ -303,23 +198,9 @@ namespace Ryujinx.Tests.Cpu
Opcode |= ((cond & 15) << 12);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
Base.Csneg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
#endif

66
Ryujinx.Tests/Cpu/CpuTestMisc.cs
View file

@ -88,7 +88,7 @@ namespace Ryujinx.Tests.Cpu
Opcode(0xD65F03C0);
ExecuteOpcodes();
Assert.That(Sse41.Extract(GetThreadState().V0, 0), Is.EqualTo(16f));
Assert.That(Sse41.Extract(GetThreadState().V0, (byte)0), Is.EqualTo(16f));
}
[TestCase(-20d, -5d)] // 18 integer solutions.
@ -137,7 +137,7 @@ namespace Ryujinx.Tests.Cpu
Opcode(0xD65F03C0);
ExecuteOpcodes();
Assert.That(VectorExtractDouble(GetThreadState().V0, 0), Is.EqualTo(16d));
Assert.That(VectorExtractDouble(GetThreadState().V0, (byte)0), Is.EqualTo(16d));
}
[Test]
@ -163,27 +163,27 @@ namespace Ryujinx.Tests.Cpu
}
/*
0x0000000000000000: MOV W4, W0
0x0000000000000004: CBZ W0, #0x3C
0x0000000000000008: CMP W0, #1
0x000000000000000C: B.LS #0x48
0x0000000000000010: MOVZ W2, #0x2
0x0000000000000014: MOVZ X1, #0x1
0x0000000000000018: MOVZ X3, #0
0x000000000000001C: ADD X0, X3, X1
0x0000000000000020: ADD W2, W2, #1
0x0000000000000024: MOV X3, X1
0x0000000000000028: MOV X1, X0
0x000000000000002C: CMP W4, W2
0x0000000000000030: B.HS #0x1C
0x0000000000000034: BRK #0
0x0000000000000038: RET
0x000000000000003C: MOVZ X0, #0
0x0000000000000040: BRK #0
0x0000000000000044: RET
0x0000000000000048: MOVZ X0, #0x1
0x000000000000004C: BRK #0
0x0000000000000050: RET
0x0000000000001000: MOV W4, W0
0x0000000000001004: CBZ W0, #0x3C
0x0000000000001008: CMP W0, #1
0x000000000000100C: B.LS #0x48
0x0000000000001010: MOVZ W2, #0x2
0x0000000000001014: MOVZ X1, #0x1
0x0000000000001018: MOVZ X3, #0
0x000000000000101C: ADD X0, X3, X1
0x0000000000001020: ADD W2, W2, #1
0x0000000000001024: MOV X3, X1
0x0000000000001028: MOV X1, X0
0x000000000000102C: CMP W4, W2
0x0000000000001030: B.HS #0x1C
0x0000000000001034: BRK #0
0x0000000000001038: RET
0x000000000000103C: MOVZ X0, #0
0x0000000000001040: BRK #0
0x0000000000001044: RET
0x0000000000001048: MOVZ X0, #0x1
0x000000000000104C: BRK #0
0x0000000000001050: RET
*/
SetThreadState(X0: A);
@ -219,11 +219,11 @@ namespace Ryujinx.Tests.Cpu
const ulong Result = 5;
/*
0x0000000000000000: MOV X0, #2
0x0000000000000004: MOV X1, #3
0x0000000000000008: ADD X0, X0, X1
0x000000000000000C: BRK #0
0x0000000000000010: RET
0x0000000000001000: MOV X0, #2
0x0000000000001004: MOV X1, #3
0x0000000000001008: ADD X0, X0, X1
0x000000000000100C: BRK #0
0x0000000000001010: RET
*/
Opcode(0xD2800040);
@ -238,11 +238,11 @@ namespace Ryujinx.Tests.Cpu
Reset();
/*
0x0000000000000000: MOV X0, #3
0x0000000000000004: MOV X1, #2
0x0000000000000008: ADD X0, X0, X1
0x000000000000000C: BRK #0
0x0000000000000010: RET
0x0000000000001000: MOV X0, #3
0x0000000000001004: MOV X1, #2
0x0000000000001008: ADD X0, X0, X1
0x000000000000100C: BRK #0
0x0000000000001010: RET
*/
Opcode(0xD2800060);

127
Ryujinx.Tests/Cpu/CpuTestMov.cs
View file

@ -1,4 +1,4 @@
//#define Mov
#define Mov
using ChocolArm64.State;
@ -6,23 +6,16 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Mov"), Ignore("Tested: second half of 2018.")]
[Category("Mov")] // Tested: second half of 2018.
public sealed class CpuTestMov : CpuTest
{
#if Mov
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCntImm = 2;
[Test, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVK <Xd>, #<imm>{, LSL #<shift>}")]
public void Movk_64bit([Values(0u, 31u)] uint Rd,
[Random(12)] ulong _Xd,
[Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm,
[Random(RndCntImm)] ulong _Xd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0
@ -30,29 +23,16 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Xd));
Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVK <Wd>, #<imm>{, LSL #<shift>}")]
public void Movk_32bit([Values(0u, 31u)] uint Rd,
[Random(12)] uint _Wd,
[Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm,
[Random(RndCntImm)] uint _Wd,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0
@ -60,28 +40,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rd, new Bits(_Wd));
Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVN <Xd>, #<imm>{, LSL #<shift>}")]
public void Movn_64bit([Values(0u, 31u)] uint Rd,
[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0
@ -89,27 +56,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVN <Wd>, #<imm>{, LSL #<shift>}")]
public void Movn_32bit([Values(0u, 31u)] uint Rd,
[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0
@ -117,27 +72,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVZ <Xd>, #<imm>{, LSL #<shift>}")]
public void Movz_64bit([Values(0u, 31u)] uint Rd,
[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u, 32u, 48u)] uint shift)
{
uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0
@ -145,27 +88,15 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
[Test, Pairwise, Description("MOVZ <Wd>, #<imm>{, LSL #<shift>}")]
public void Movz_32bit([Values(0u, 31u)] uint Rd,
[Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm,
[Values(0u, 65535u)] [Random(0u, 65535u, RndCntImm)] uint imm,
[Values(0u, 16u)] uint shift)
{
uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0
@ -173,21 +104,9 @@ namespace Ryujinx.Tests.Cpu
Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
#endif

257
Ryujinx.Tests/Cpu/CpuTestMul.cs
View file

@ -1,4 +1,4 @@
//#define Mul
#define Mul
using ChocolArm64.State;
@ -6,378 +6,223 @@ using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Mul"), Ignore("Tested: second half of 2018.")]
[Category("Mul")] // Tested: second half of 2018.
public sealed class CpuTestMul : CpuTest
{
#if Mul
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
private const int RndCnt = 2;
[Test, Description("MADD <Xd>, <Xn>, <Xm>, <Xa>")]
[Test, Pairwise, Description("MADD <Xd>, <Xn>, <Xm>, <Xa>")]
public void Madd_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("MADD <Wd>, <Wn>, <Wm>, <Wa>")]
[Test, Pairwise, Description("MADD <Wd>, <Wn>, <Wm>, <Wa>")]
public void Madd_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa)
{
uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Wa));
Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("MSUB <Xd>, <Xn>, <Xm>, <Xa>")]
[Test, Pairwise, Description("MSUB <Xd>, <Xn>, <Xm>, <Xa>")]
public void Msub_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("MSUB <Wd>, <Wn>, <Wm>, <Wa>")]
[Test, Pairwise, Description("MSUB <Wd>, <Wn>, <Wm>, <Wa>")]
public void Msub_32bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa)
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wa)
{
uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
uint _W31 = TestContext.CurrentContext.Random.NextUInt();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Wa));
Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
uint Wd = AArch64.X(32, (int)Rd).ToUInt32();
Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd));
}
else
{
Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31));
}
CompareAgainstUnicorn();
}
[Test, Description("SMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
[Test, Pairwise, Description("SMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
public void Smaddl_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Smaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("UMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
[Test, Pairwise, Description("UMADDL <Xd>, <Wn>, <Wm>, <Xa>")]
public void Umaddl_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("SMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
[Test, Pairwise, Description("SMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
public void Smsubl_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Smsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("UMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
[Test, Pairwise, Description("UMSUBL <Xd>, <Wn>, <Wm>, <Xa>")]
public void Umsubl_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(3u, 31u)] uint Ra,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wn,
[Values(0x00000000u, 0x7FFFFFFFu,
0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm,
0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint Wm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xa)
{
uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0
Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Wn));
AArch64.X((int)Rm, new Bits(Wm));
AArch64.X((int)Ra, new Bits(Xa));
Base.Umsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("SMULH <Xd>, <Xn>, <Xm>")]
[Test, Pairwise, Description("SMULH <Xd>, <Xn>, <Xm>")]
public void Smulh_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm)
{
uint Opcode = 0x9B407C00; // SMULH X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Smulh(Op[20, 16], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
[Test, Description("UMULH <Xd>, <Xn>, <Xm>")]
[Test, Pairwise, Description("UMULH <Xd>, <Xn>, <Xm>")]
public void Umulh_64bit([Values(0u, 31u)] uint Rd,
[Values(1u, 31u)] uint Rn,
[Values(2u, 31u)] uint Rm,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xn,
[Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm)
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(RndCnt)] ulong Xm)
{
uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
ulong _X31 = TestContext.CurrentContext.Random.NextULong();
AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31);
if (Rd != 31)
{
Bits Op = new Bits(Opcode);
AArch64.X((int)Rn, new Bits(Xn));
AArch64.X((int)Rm, new Bits(Xm));
Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]);
ulong Xd = AArch64.X(64, (int)Rd).ToUInt64();
Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd));
}
else
{
Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31));
}
CompareAgainstUnicorn();
}
#endif

1058
Ryujinx.Tests/Cpu/CpuTestSimd.cs
View file

File diff suppressed because it is too large Load diff

391
Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs
View file

@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
{
public class CpuTestSimdArithmetic : CpuTest
{
[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)] // FMAX S0, S1, S2
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
[TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)]
@ -22,17 +22,19 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)]
[TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)]
[TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)]
[TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)]
[TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)] // FMAX D0, D1, D2
[TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
[TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)]
public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result)
{
// FMAX S0, S1, S2
AThreadState ThreadState = SingleOpcode(Opcode,
V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
@ -51,19 +53,23 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)]
public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
{
uint Opcode = 0x4E22F420;
uint Opcode = 0x4E22F420; // FMAX V0.4S, V1.4S, V2.4S
Vector128<float> V1 = MakeVectorE0E1(A, B);
Vector128<float> V2 = MakeVectorE0E1(C, D);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
[TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
[TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)] // FMIN S0, S1, S2
[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)]
[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
[TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)]
@ -76,17 +82,19 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul)]
[TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul)]
[TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul)]
[TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)] // FMIN D0, D1, D2
[TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
[TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)]
public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result)
{
// FMIN S0, S1, S2
AThreadState ThreadState = SingleOpcode(Opcode,
V1: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, A)),
V2: Sse.StaticCast<ulong, float>(Sse2.SetVector128(0, B)));
Assert.AreEqual(Result, Sse41.Extract(Sse.StaticCast<float, ulong>(ThreadState.V0), 0));
Vector128<float> V1 = MakeVectorE0(A);
Vector128<float> V2 = MakeVectorE0(B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
@ -105,15 +113,19 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au)]
public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
{
uint Opcode = 0x4EA2F420;
uint Opcode = 0x4EA2F420; // FMIN V0.4S, V1.4S, V2.4S
Vector128<float> V1 = MakeVectorE0E1(A, B);
Vector128<float> V2 = MakeVectorE0E1(C, D);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
@ -125,6 +137,7 @@ namespace Ryujinx.Tests.Cpu
V0: Sse.SetVector128(0, B, 0, 0));
Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B));
CompareAgainstUnicorn();
}
@ -137,21 +150,27 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x007FF000u, 0x7E800000u)]
public void Frecpe_S(uint A, uint Result)
{
uint Opcode = 0x5EA1D820; // FRECPE S0, S1
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x5EA1D820, V1: V1);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[Test, Description("FRECPS D0, D1, D2")]
[Test, Description("FRECPS D0, D1, D2"), Ignore("Not accurate enough.")]
public void Frecps_S([Random(10)] double A, [Random(10)] double B)
{
AThreadState ThreadState = SingleOpcode(0x5E62FC20,
V1: MakeVectorE0(A),
V2: MakeVectorE0(B));
Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(2 - (A * B)));
//CompareAgainstUnicorn(); // Not accurate enough
Assert.That(VectorExtractDouble(ThreadState.V0, (byte)0), Is.EqualTo(2 - (A * B)));
CompareAgainstUnicorn();
}
[Test, Description("FRECPS V4.4S, V2.4S, V0.4S")]
@ -170,6 +189,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(Result));
Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(Result));
});
CompareAgainstUnicorn();
}
@ -177,7 +197,7 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x3F99999Au, false, 0x3F800000u)]
[TestCase(0x404CCCCDu, false, 0x40400000u)]
[TestCase(0x40733333u, false, 0x40800000u)]
[TestCase(0x3fc00000u, false, 0x40000000u)]
[TestCase(0x3FC00000u, false, 0x40000000u)]
[TestCase(0x40200000u, false, 0x40400000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
@ -213,42 +233,53 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frinta_S(uint A, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E264020; // FRINTA S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[Ignore("Wrong opcodes.")]
[TestCase(0x6E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTA V0.2D, V1.2D
[TestCase(0x6E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
[TestCase(0x6E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTX V0.4S, V1.4S
[TestCase(0x6E219820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S
[TestCase(0x2E219820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)] // FRINTA V0.2S, V1.2S
[TestCase(0x2E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x2E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frinta_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
@ -294,36 +325,31 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frinti_S(uint A, char RoundType, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E27C020; // FRINTI S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
switch(RoundType)
{
case 'N':
FpcrTemp = 0x0;
break;
case 'P':
FpcrTemp = 0x400000;
break;
case 'M':
FpcrTemp = 0x800000;
break;
case 'Z':
FpcrTemp = 0xC00000;
break;
case 'N': FpcrTemp = 0x0; break;
case 'P': FpcrTemp = 0x400000; break;
case 'M': FpcrTemp = 0x800000; break;
case 'Z': FpcrTemp = 0xC00000; break;
}
if(DefaultNaN)
{
FpcrTemp |= 1 << 25;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E27C020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTI V0.2D, V1.2D
[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)]
@ -331,14 +357,14 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6EE19820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6EE19820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
[TestCase(0x6EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
[TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTI V0.4S, V1.4S
[TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)]
[TestCase(0x6EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)]
[TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTI V0.2S, V1.2S
[TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'P', false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x2EA19820u, 0x0000000080000000ul, 0x0000000000000000ul, 'M', false, 0x0000000080000000ul, 0x0000000000000000ul)]
@ -357,36 +383,29 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x2EA19820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frinti_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
switch(RoundType)
{
case 'N':
FpcrTemp = 0x0;
break;
case 'P':
FpcrTemp = 0x400000;
break;
case 'M':
FpcrTemp = 0x800000;
break;
case 'Z':
FpcrTemp = 0xC00000;
break;
case 'N': FpcrTemp = 0x0; break;
case 'P': FpcrTemp = 0x400000; break;
case 'M': FpcrTemp = 0x800000; break;
case 'Z': FpcrTemp = 0xC00000; break;
}
if(DefaultNaN)
{
FpcrTemp |= 1 << 25;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
@ -394,7 +413,7 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x3F99999Au, false, 0x3F800000u)]
[TestCase(0x404CCCCDu, false, 0x40400000u)]
[TestCase(0x40733333u, false, 0x40400000u)]
[TestCase(0x3fc00000u, false, 0x3F800000u)]
[TestCase(0x3FC00000u, false, 0x3F800000u)]
[TestCase(0x40200000u, false, 0x40000000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
@ -430,47 +449,58 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frintm_S(uint A, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E254020; // FRINTM S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E254020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x4E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTM V0.2D, V1.2D
[TestCase(0x4E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x4E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
[TestCase(0xE219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
[TestCase(0xE219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0xE219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0xE219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x4E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)] // FRINTM V0.4S, V1.4S
[TestCase(0x0E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F8000003F800000ul, 0x0000000000000000ul)] // FRINTM V0.2S, V1.2S
[TestCase(0x0E219820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x0E219820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x0E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frintm_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
[Ignore("Wrong opcode.")]
[TestCase(0x3FE66666u, false, 0x40000000u)]
[TestCase(0x3F99999Au, false, 0x3F800000u)]
[TestCase(0x404CCCCDu, false, 0x40400000u)]
[TestCase(0x40733333u, false, 0x40800000u)]
[TestCase(0x3fc00000u, false, 0x40000000u)]
[TestCase(0x3FC00000u, false, 0x40000000u)]
[TestCase(0x40200000u, false, 0x40400000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
@ -506,42 +536,52 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frintn_S(uint A, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E264020; // FRINTA S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E264020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x4E618820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTN V0.2D, V1.2D
[TestCase(0x4E618820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x4E618820u, 0x3FF8000000000000ul, 0x3FF8000000000000ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x4E218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
[TestCase(0x4E218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0xE218820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x3f80000040000000ul, 0x0000000000000000ul)]
[TestCase(0xE218820u, 0x3fc000003fc00000ul, 0x3fc000003fc00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0xE218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0xE218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0xE218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x4E218820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTN V0.4S, V1.4S
[TestCase(0x4E218820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x0E218820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTN V0.2S, V1.2S
[TestCase(0x0E218820u, 0x3FC000003FC00000ul, 0x3FC000003FC00000ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x0E218820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x0E218820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x0E218820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frintn_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
@ -549,7 +589,7 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x3F99999Au, false, 0x40000000u)]
[TestCase(0x404CCCCDu, false, 0x40800000u)]
[TestCase(0x40733333u, false, 0x40800000u)]
[TestCase(0x3fc00000u, false, 0x40000000u)]
[TestCase(0x3FC00000u, false, 0x40000000u)]
[TestCase(0x40200000u, false, 0x40400000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
[TestCase(0x00000000u, false, 0x00000000u)]
@ -585,39 +625,49 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frintp_S(uint A, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E24C020; // FRINTP S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E24C020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x4EE18820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, false, 0x4000000000000000ul, 0x4000000000000000ul)] // FRINTP V0.2D, v1.2D
[TestCase(0x4EE18820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x4EA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0xEA18820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0xEA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0xEA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0xEA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x4EA18820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x4000000040000000ul, 0x4000000040000000ul)] // FRINTP V0.4S, v1.4S
[TestCase(0x0EA18820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, false, 0x4000000040000000ul, 0x0000000000000000ul)] // FRINTP V0.2S, v1.2S
[TestCase(0x0EA18820u, 0x0000000080000000ul, 0x0000000000000000ul, false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x0EA18820u, 0x7F800000FF800000ul, 0x0000000000000000ul, false, 0x7F800000FF800000ul, 0x0000000000000000ul)]
[TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, false, 0xFFC000017FC00002ul, 0x0000000000000000ul, Ignore = "NaN test.")]
[TestCase(0x0EA18820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frintp_V(uint Opcode, ulong A, ulong B, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
if(DefaultNaN)
{
FpcrTemp = 0x2000000;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
@ -663,36 +713,31 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x7FC00002u, 'Z', true, 0x7FC00000u, Ignore = "NaN test.")]
public void Frintx_S(uint A, char RoundType, bool DefaultNaN, uint Result)
{
uint Opcode = 0x1E274020; // FRINTX S0, S1
Vector128<float> V1 = MakeVectorE0(A);
int FpcrTemp = 0x0;
switch(RoundType)
{
case 'N':
FpcrTemp = 0x0;
break;
case 'P':
FpcrTemp = 0x400000;
break;
case 'M':
FpcrTemp = 0x800000;
break;
case 'Z':
FpcrTemp = 0xC00000;
break;
case 'N': FpcrTemp = 0x0; break;
case 'P': FpcrTemp = 0x400000; break;
case 'M': FpcrTemp = 0x800000; break;
case 'Z': FpcrTemp = 0xC00000; break;
}
if(DefaultNaN)
{
FpcrTemp |= 1 << 25;
}
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x1E274020, V1: V1, Fpcr: FpcrTemp);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'N', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)] // FRINTX V0.2D, V1.2D
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'N', false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)]
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'P', false, 0x4000000000000000ul, 0x4000000000000000ul)]
@ -700,14 +745,14 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'M', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6E619820u, 0x3FF3333333333333ul, 0x3FF3333333333333ul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6E619820u, 0x3FFCCCCCCCCCCCCDul, 0x3FFCCCCCCCCCCCCDul, 'Z', false, 0x3FF0000000000000ul, 0x3FF0000000000000ul)]
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x3f80000040000000ul)]
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
[TestCase(0x6E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x3f8000003f800000ul)]
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'N', false, 0x3f80000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'M', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3f99999a3fe66666ul, 0x3f99999a3fe66666ul, 'Z', false, 0x3f8000003f800000ul, 0x0000000000000000ul)]
[TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x3F80000040000000ul)] // FRINTX V0.4S, V1.4S
[TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x4000000040000000ul)]
[TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)]
[TestCase(0x6E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x3F8000003F800000ul)]
[TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'N', false, 0x3F80000040000000ul, 0x0000000000000000ul)] // FRINTX V0.2S, V1.2S
[TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'P', false, 0x4000000040000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'M', false, 0x3F8000003F800000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x3F99999A3FE66666ul, 0x3F99999A3FE66666ul, 'Z', false, 0x3F8000003F800000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'N', false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'P', false, 0x0000000080000000ul, 0x0000000000000000ul)]
[TestCase(0x2E219820u, 0x0000000080000000ul, 0x0000000000000000ul, 'M', false, 0x0000000080000000ul, 0x0000000000000000ul)]
@ -726,45 +771,43 @@ namespace Ryujinx.Tests.Cpu
[TestCase(0x2E219820u, 0xFF8000017FC00002ul, 0x0000000000000000ul, 'Z', true, 0x7FC000007FC00000ul, 0x0000000000000000ul, Ignore = "NaN test.")]
public void Frintx_V(uint Opcode, ulong A, ulong B, char RoundType, bool DefaultNaN, ulong Result0, ulong Result1)
{
Vector128<float> V1 = MakeVectorE0E1(A, B);
int FpcrTemp = 0x0;
switch(RoundType)
{
case 'N':
FpcrTemp = 0x0;
break;
case 'P':
FpcrTemp = 0x400000;
break;
case 'M':
FpcrTemp = 0x800000;
break;
case 'Z':
FpcrTemp = 0xC00000;
break;
case 'N': FpcrTemp = 0x0; break;
case 'P': FpcrTemp = 0x400000; break;
case 'M': FpcrTemp = 0x800000; break;
case 'Z': FpcrTemp = 0xC00000; break;
}
if(DefaultNaN)
{
FpcrTemp |= 1 << 25;
}
Vector128<float> V1 = MakeVectorE0E1(A, B);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, Fpcr: FpcrTemp);
Assert.Multiple(() =>
{
Assert.AreEqual(Result0, GetVectorE0(ThreadState.V0));
Assert.AreEqual(Result1, GetVectorE1(ThreadState.V0));
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result0));
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(Result1));
});
CompareAgainstUnicorn();
}
[TestCase(0x41200000u, 0x3EA18000u)]
public void Frsqrte_S(uint A, uint Result)
{
uint Opcode = 0x7EA1D820; // FRSQRTE S0, S1
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(0x7EA1D820, V1: V1);
Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(Result));
CompareAgainstUnicorn();
}
}

52
Ryujinx.Tests/Cpu/CpuTestSimdCmp.cs
View file

@ -24,12 +24,15 @@ namespace Ryujinx.Tests.Cpu
}
#endregion
private const int RndCnt = 2;
[Test, Description("FCMEQ D0, D1, D2 | FCMGE D0, D1, D2 | FCMGT D0, D1, D2")]
public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(8)] double A,
[ValueSource("_doubles_")] [Random(8)] double B,
public void Fcmeq_Fcmge_Fcmgt_Reg_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A,
[ValueSource("_doubles_")] [Random(RndCnt)] double B,
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
{
uint Opcode = 0x5E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
Vector128<float> V0 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble()));
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(A));
Vector128<float> V2 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(B));
@ -52,15 +55,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMEQ S0, S1, S2 | FCMGE S0, S1, S2 | FCMGT S0, S1, S2")]
public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(8)] float A,
[ValueSource("_floats_")] [Random(8)] float B,
public void Fcmeq_Fcmge_Fcmgt_Reg_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[ValueSource("_floats_")] [Random(RndCnt)] float B,
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
{
uint Opcode = 0x5E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
Vector128<float> V1 = Sse.SetScalarVector128(A);
Vector128<float> V2 = Sse.SetScalarVector128(B);
@ -85,15 +90,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMEQ V0.2D, V1.2D, V2.2D | FCMGE V0.2D, V1.2D, V2.2D | FCMGT V0.2D, V1.2D, V2.2D")]
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(8)] double A,
[ValueSource("_doubles_")] [Random(8)] double B,
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A,
[ValueSource("_doubles_")] [Random(RndCnt)] double B,
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
{
uint Opcode = 0x4E62E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(A));
Vector128<float> V2 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(B));
@ -115,15 +122,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
});
CompareAgainstUnicorn();
}
[Test, Description("FCMEQ V0.2S, V1.2S, V2.2S | FCMGE V0.2S, V1.2S, V2.2S | FCMGT V0.2S, V1.2S, V2.2S")]
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(8)] float A,
[ValueSource("_floats_")] [Random(8)] float B,
public void Fcmeq_Fcmge_Fcmgt_Reg_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[ValueSource("_floats_")] [Random(RndCnt)] float B,
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
{
uint Opcode = 0x0E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
Vector128<float> V1 = Sse.SetVector128(0, 0, A, A);
Vector128<float> V2 = Sse.SetVector128(0, 0, B, B);
@ -148,15 +157,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMEQ V0.4S, V1.4S, V2.4S | FCMGE V0.4S, V1.4S, V2.4S | FCMGT V0.4S, V1.4S, V2.4S")]
public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(8)] float A,
[ValueSource("_floats_")] [Random(8)] float B,
public void Fcmeq_Fcmge_Fcmgt_Reg_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[ValueSource("_floats_")] [Random(RndCnt)] float B,
[Values(0u, 1u, 3u)] uint EU) // EQ, GE, GT
{
uint Opcode = 0x4E22E420 | ((EU & 1) << 29) | ((EU >> 1) << 23);
Vector128<float> V1 = Sse.SetAllVector128(A);
Vector128<float> V2 = Sse.SetAllVector128(B);
@ -180,15 +191,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp));
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp));
});
CompareAgainstUnicorn();
}
[Test, Description("FCMGT D0, D1, #0.0 | FCMGE D0, D1, #0.0 | FCMEQ D0, D1, #0.0 | FCMLE D0, D1, #0.0 | FCMLT D0, D1, #0.0")]
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(8)] double A,
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_D([ValueSource("_doubles_")] [Random(RndCnt)] double A,
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
[Values(0u, 1u)] uint bit13) // "LT"
{
uint Opcode = 0x5EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
Vector128<float> V0 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(TestContext.CurrentContext.Random.NextDouble()));
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetScalarVector128(A));
@ -219,15 +232,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
Assert.That(VectorExtractDouble(ThreadState.V0, (byte)1), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMGT S0, S1, #0.0 | FCMGE S0, S1, #0.0 | FCMEQ S0, S1, #0.0 | FCMLE S0, S1, #0.0 | FCMLT S0, S1, #0.0")]
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(8)] float A,
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_S_S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
[Values(0u, 1u)] uint bit13) // "LT"
{
uint Opcode = 0x5EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
Vector128<float> V1 = Sse.SetScalarVector128(A);
@ -260,15 +275,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMGT V0.2D, V1.2D, #0.0 | FCMGE V0.2D, V1.2D, #0.0 | FCMEQ V0.2D, V1.2D, #0.0 | FCMLE V0.2D, V1.2D, #0.0 | FCMLT V0.2D, V1.2D, #0.0")]
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(8)] double A,
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2D([ValueSource("_doubles_")] [Random(RndCnt)] double A,
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
[Values(0u, 1u)] uint bit13) // "LT"
{
uint Opcode = 0x4EE0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
Vector128<float> V1 = Sse.StaticCast<double, float>(Sse2.SetAllVector128(A));
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
@ -298,15 +315,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)0)), Is.EquivalentTo(Exp));
Assert.That(BitConverter.GetBytes(VectorExtractDouble(ThreadState.V0, (byte)1)), Is.EquivalentTo(Exp));
});
CompareAgainstUnicorn();
}
[Test, Description("FCMGT V0.2S, V1.2S, #0.0 | FCMGE V0.2S, V1.2S, #0.0 | FCMEQ V0.2S, V1.2S, #0.0 | FCMLE V0.2S, V1.2S, #0.0 | FCMLT V0.2S, V1.2S, #0.0")]
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(8)] float A,
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_2S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
[Values(0u, 1u)] uint bit13) // "LT"
{
uint Opcode = 0x0EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
Vector128<float> V0 = Sse.SetAllVector128(TestContext.CurrentContext.Random.NextFloat());
Vector128<float> V1 = Sse.SetVector128(0, 0, A, A);
@ -339,15 +358,17 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(ThreadState.V0, (byte)2), Is.Zero);
Assert.That(Sse41.Extract(ThreadState.V0, (byte)3), Is.Zero);
});
CompareAgainstUnicorn();
}
[Test, Description("FCMGT V0.4S, V1.4S, #0.0 | FCMGE V0.4S, V1.4S, #0.0 | FCMEQ V0.4S, V1.4S, #0.0 | FCMLE V0.4S, V1.4S, #0.0 | FCMLT V0.4S, V1.4S, #0.0")]
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(8)] float A,
public void Fcmgt_Fcmge_Fcmeq_Fcmle_Fcmlt_Zero_V_4S([ValueSource("_floats_")] [Random(RndCnt)] float A,
[Values(0u, 1u, 2u, 3u)] uint opU, // GT, GE, EQ, LE
[Values(0u, 1u)] uint bit13) // "LT"
{
uint Opcode = 0x4EA0C820 | (((opU & 1) & ~bit13) << 29) | (bit13 << 13) | (((opU >> 1) & ~bit13) << 12);
Vector128<float> V1 = Sse.SetAllVector128(A);
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
@ -379,6 +400,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)2)), Is.EquivalentTo(Exp));
Assert.That(BitConverter.GetBytes(Sse41.Extract(ThreadState.V0, (byte)3)), Is.EquivalentTo(Exp));
});
CompareAgainstUnicorn();
}
}

8
Ryujinx.Tests/Cpu/CpuTestSimdCrypto.cs
View file

@ -22,6 +22,7 @@ namespace Ryujinx.Tests.Cpu
{
uint Opcode = 0x4E285800; // AESD V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH);
Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH);
@ -37,6 +38,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL));
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH));
});
CompareAgainstUnicorn();
}
@ -52,6 +54,7 @@ namespace Ryujinx.Tests.Cpu
{
uint Opcode = 0x4E284800; // AESE V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Vector128<float> V0 = MakeVectorE0E1(RoundKeyL ^ ValueL, RoundKeyH ^ ValueH);
Vector128<float> V1 = MakeVectorE0E1(RoundKeyL, RoundKeyH);
@ -67,6 +70,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE0(ThreadState.V1), Is.EqualTo(RoundKeyL));
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(RoundKeyH));
});
CompareAgainstUnicorn();
}
@ -80,6 +84,7 @@ namespace Ryujinx.Tests.Cpu
{
uint Opcode = 0x4E287800; // AESIMC V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Vector128<float> V = MakeVectorE0E1(ValueL, ValueH);
AThreadState ThreadState = SingleOpcode(
@ -100,6 +105,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH));
});
}
CompareAgainstUnicorn();
}
@ -113,6 +119,7 @@ namespace Ryujinx.Tests.Cpu
{
uint Opcode = 0x4E286800; // AESMC V0.16B, V0.16B
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Vector128<float> V = MakeVectorE0E1(ValueL, ValueH);
AThreadState ThreadState = SingleOpcode(
@ -133,6 +140,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(GetVectorE1(ThreadState.V1), Is.EqualTo(ValueH));
});
}
CompareAgainstUnicorn();
}
}

4
Ryujinx.Tests/Cpu/CpuTestSimdCvt.cs
View file

@ -23,7 +23,8 @@ namespace Ryujinx.Tests.Cpu
[TestCase((ushort)0x0001, 0x33800000u)] // 5.96046448e-8 (Smallest Subnormal)
public void Fcvtl_V_f16(ushort Value, uint Result)
{
uint Opcode = 0x0E217801;
uint Opcode = 0x0E217801; // FCVTL V1.4S, V0.4H
Vector128<float> V0 = Sse.StaticCast<ushort, float>(Sse2.SetAllVector128(Value));
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0);
@ -35,6 +36,7 @@ namespace Ryujinx.Tests.Cpu
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)2), Is.EqualTo(Result));
Assert.That(Sse41.Extract(Sse.StaticCast<float, uint>(ThreadState.V1), (byte)3), Is.EqualTo(Result));
});
CompareAgainstUnicorn();
}
}

1772
Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
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File diff suppressed because it is too large Load diff

143
Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs Normal file
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@ -0,0 +1,143 @@
#define SimdRegElem
using ChocolArm64.State;
using NUnit.Framework;
using System.Runtime.Intrinsics;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdRegElem")] // Tested: second half of 2018.
public sealed class CpuTestSimdRegElem : CpuTest
{
#if SimdRegElem
#region "ValueSource"
private static ulong[] _2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
#endregion
private const int RndCnt = 2;
[Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mla_Ve_4H_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[ValueSource("_4H_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
uint H = (Index & 4) >> 2;
uint L = (Index & 2) >> 1;
uint M = (Index & 1) >> 0;
uint Opcode = 0x2F400000; // MLA V0.4H, V0.4H, V0.H[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (M << 20) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mla_Ve_2S_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_2S_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
uint H = (Index & 2) >> 1;
uint L = (Index & 1) >> 0;
uint Opcode = 0x2F800000; // MLA V0.2S, V0.2S, V0.S[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mls_Ve_4H_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[ValueSource("_4H_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
uint H = (Index & 4) >> 2;
uint L = (Index & 2) >> 1;
uint M = (Index & 1) >> 0;
uint Opcode = 0x2F404000; // MLS V0.4H, V0.4H, V0.H[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (M << 20) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("MLS <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]")]
public void Mls_Ve_2S_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[ValueSource("_2S_")] [Random(RndCnt)] ulong B,
[Values(0u, 1u, 2u, 3u)] uint Index,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
uint H = (Index & 2) >> 1;
uint L = (Index & 1) >> 0;
uint Opcode = 0x2F804000; // MLS V0.2S, V0.2S, V0.S[0]
Opcode |= ((Rm & 15) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (L << 21) | (H << 11);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
Vector128<float> V2 = MakeVectorE0E1(B, B * H);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
CompareAgainstUnicorn();
}
#endif
}
}

344
Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs Normal file
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@ -0,0 +1,344 @@
#define SimdShImm
using ChocolArm64.State;
using NUnit.Framework;
using System.Runtime.Intrinsics;
namespace Ryujinx.Tests.Cpu
{
[Category("SimdShImm")] // Tested: second half of 2018.
public sealed class CpuTestSimdShImm : CpuTest
{
#if SimdShImm
#region "ValueSource (Types)"
private static ulong[] _1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B_()
{
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
}
#endregion
#region "ValueSource (Opcodes)"
private static uint[] _ShrImm_S_D_()
{
return new uint[]
{
0x5F402400u, // SRSHR D0, D0, #64
0x5F403400u, // SRSRA D0, D0, #64
0x5F400400u, // SSHR D0, D0, #64
0x5F401400u, // SSRA D0, D0, #64
0x7F402400u, // URSHR D0, D0, #64
0x7F403400u, // URSRA D0, D0, #64
0x7F400400u, // USHR D0, D0, #64
0x7F401400u // USRA D0, D0, #64
};
}
private static uint[] _ShrImm_V_8B_16B_()
{
return new uint[]
{
0x0F082400u, // SRSHR V0.8B, V0.8B, #8
0x0F083400u, // SRSRA V0.8B, V0.8B, #8
0x0F080400u, // SSHR V0.8B, V0.8B, #8
0x0F081400u, // SSRA V0.8B, V0.8B, #8
0x2F082400u, // URSHR V0.8B, V0.8B, #8
0x2F083400u, // URSRA V0.8B, V0.8B, #8
0x2F080400u, // USHR V0.8B, V0.8B, #8
0x2F081400u // USRA V0.8B, V0.8B, #8
};
}
private static uint[] _ShrImm_V_4H_8H_()
{
return new uint[]
{
0x0F102400u, // SRSHR V0.4H, V0.4H, #16
0x0F103400u, // SRSRA V0.4H, V0.4H, #16
0x0F100400u, // SSHR V0.4H, V0.4H, #16
0x0F101400u, // SSRA V0.4H, V0.4H, #16
0x2F102400u, // URSHR V0.4H, V0.4H, #16
0x2F103400u, // URSRA V0.4H, V0.4H, #16
0x2F100400u, // USHR V0.4H, V0.4H, #16
0x2F101400u // USRA V0.4H, V0.4H, #16
};
}
private static uint[] _ShrImm_V_2S_4S_()
{
return new uint[]
{
0x0F202400u, // SRSHR V0.2S, V0.2S, #32
0x0F203400u, // SRSRA V0.2S, V0.2S, #32
0x0F200400u, // SSHR V0.2S, V0.2S, #32
0x0F201400u, // SSRA V0.2S, V0.2S, #32
0x2F202400u, // URSHR V0.2S, V0.2S, #32
0x2F203400u, // URSRA V0.2S, V0.2S, #32
0x2F200400u, // USHR V0.2S, V0.2S, #32
0x2F201400u // USRA V0.2S, V0.2S, #32
};
}
private static uint[] _ShrImm_V_2D_()
{
return new uint[]
{
0x4F402400u, // SRSHR V0.2D, V0.2D, #64
0x4F403400u, // SRSRA V0.2D, V0.2D, #64
0x4F400400u, // SSHR V0.2D, V0.2D, #64
0x4F401400u, // SSRA V0.2D, V0.2D, #64
0x6F402400u, // URSHR V0.2D, V0.2D, #64
0x6F403400u, // URSRA V0.2D, V0.2D, #64
0x6F400400u, // USHR V0.2D, V0.2D, #64
0x6F401400u // USRA V0.2D, V0.2D, #64
};
}
#endregion
private const int RndCnt = 2;
[Test, Pairwise, Description("SHL <V><d>, <V><n>, #<shift>")]
public void Shl_S_D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A,
[Range(0u, 63u)] uint Shift)
{
uint ImmHB = (64 + Shift) & 0x7F;
uint Opcode = 0x5F405400; // SHL D0, D0, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (ImmHB << 16);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
public void Shl_V_8B_16B([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A,
[Range(0u, 7u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <8B, 16B>
{
uint ImmHB = (8 + Shift) & 0x7F;
uint Opcode = 0x0F085400; // SHL V0.8B, V0.8B, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (ImmHB << 16);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
public void Shl_V_4H_8H([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[Range(0u, 15u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
uint ImmHB = (16 + Shift) & 0x7F;
uint Opcode = 0x0F105400; // SHL V0.4H, V0.4H, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (ImmHB << 16);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
public void Shl_V_2S_4S([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[Range(0u, 31u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
uint ImmHB = (32 + Shift) & 0x7F;
uint Opcode = 0x0F205400; // SHL V0.2S, V0.2S, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (ImmHB << 16);
Opcode |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("SHL <Vd>.<T>, <Vn>.<T>, #<shift>")]
public void Shl_V_2D([Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A,
[Range(0u, 63u)] uint Shift)
{
uint ImmHB = (64 + Shift) & 0x7F;
uint Opcode = 0x4F405400; // SHL V0.2D, V0.2D, #0
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcode |= (ImmHB << 16);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void ShrImm_S_D([ValueSource("_ShrImm_S_D_")] uint Opcodes,
[Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A,
[Range(1u, 64u)] uint Shift)
{
uint ImmHB = (128 - Shift) & 0x7F;
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcodes |= (ImmHB << 16);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0(A);
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void ShrImm_V_8B_16B([ValueSource("_ShrImm_V_8B_16B_")] uint Opcodes,
[Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_8B_")] [Random(RndCnt)] ulong Z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong A,
[Range(1u, 8u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <8B, 16B>
{
uint ImmHB = (16 - Shift) & 0x7F;
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcodes |= (ImmHB << 16);
Opcodes |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void ShrImm_V_4H_8H([ValueSource("_ShrImm_V_4H_8H_")] uint Opcodes,
[Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong A,
[Range(1u, 16u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <4H, 8H>
{
uint ImmHB = (32 - Shift) & 0x7F;
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcodes |= (ImmHB << 16);
Opcodes |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void ShrImm_V_2S_4S([ValueSource("_ShrImm_V_2S_4S_")] uint Opcodes,
[Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong A,
[Range(1u, 32u)] uint Shift,
[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
{
uint ImmHB = (64 - Shift) & 0x7F;
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcodes |= (ImmHB << 16);
Opcodes |= ((Q & 1) << 30);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
[Test, Pairwise]
public void ShrImm_V_2D([ValueSource("_ShrImm_V_2D_")] uint Opcodes,
[Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn,
[ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong A,
[Range(1u, 64u)] uint Shift)
{
uint ImmHB = (128 - Shift) & 0x7F;
Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
Opcodes |= (ImmHB << 16);
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
Vector128<float> V1 = MakeVectorE0E1(A, A);
AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
CompareAgainstUnicorn();
}
#endif
}
}

7346
Ryujinx.Tests/Cpu/Tester/Instructions.cs
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1740
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
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File diff suppressed because it is too large Load diff

282
Ryujinx.Tests/Cpu/Tester/Types/Bits.cs
View file

@ -1,282 +0,0 @@
// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Bits.cs
// https://github.com/dotnet/corefx/blob/master/src/System.Collections/src/System/Collections/BitArray.cs
using System;
using System.Collections;
using System.Numerics;
namespace Ryujinx.Tests.Cpu.Tester.Types
{
internal sealed class Bits : ICollection, IEnumerable, IEquatable<Bits>
{
private BitArray bits;
public Bits(bool[] values) => bits = new BitArray(values);
public Bits(byte[] bytes) => bits = new BitArray(bytes);
public Bits(Bits bits) => this.bits = new BitArray(bits.bits); // Clone: deep copy.
public Bits(int length) => bits = new BitArray(length);
public Bits(int length, bool defaultValue) => bits = new BitArray(length, defaultValue);
private Bits(BitArray bitArray) => bits = new BitArray(bitArray);
public Bits(ulong value) => bits = new BitArray(BitConverter.GetBytes(value));
public Bits(uint value) => bits = new BitArray(BitConverter.GetBytes(value));
public Bits(BigInteger value) => bits = new BitArray(value.ToByteArray());
private BitArray ToBitArray() => new BitArray(bits);
public ulong ToUInt64()
{
byte[] dst = new byte[8];
bits.CopyTo(dst, 0);
return BitConverter.ToUInt64(dst, 0);
}
public uint ToUInt32()
{
byte[] dst = new byte[4];
bits.CopyTo(dst, 0);
return BitConverter.ToUInt32(dst, 0);
}
public BigInteger ToBigInteger()
{
if (bits.Count != 64 &&
bits.Count != 32 &&
bits.Count != 16 &&
bits.Count != 8)
{
throw new InvalidOperationException();
}
byte[] dst = new byte[bits.Count / 8];
bits.CopyTo(dst, 0);
return new BigInteger(dst);
}
public bool this[int index] // ASL: "<>".
{
get
{
return bits.Get(index);
}
set
{
bits.Set(index, value);
}
}
public Bits this[int highIndex, int lowIndex] // ASL: "<:>".
{
get
{
if (highIndex < lowIndex)
{
throw new IndexOutOfRangeException();
}
bool[] dst = new bool[highIndex - lowIndex + 1];
for (int i = lowIndex, n = 0; i <= highIndex; i++, n++)
{
dst[n] = bits.Get(i);
}
return new Bits(dst);
}
set
{
if (highIndex < lowIndex)
{
throw new IndexOutOfRangeException();
}
for (int i = lowIndex, n = 0; i <= highIndex; i++, n++)
{
bits.Set(i, value.Get(n));
}
}
}
public bool IsReadOnly { get => false; } // Mutable.
public int Count { get => bits.Count; } // Not resizable.
public bool IsSynchronized { get => bits.IsSynchronized; }
public object SyncRoot { get => bits.SyncRoot; }
public Bits And(Bits value) => new Bits(new BitArray(this.bits).And(value.bits)); // Immutable.
public void CopyTo(Array array, int index) => bits.CopyTo(array, index);
public bool Get(int index) => bits.Get(index);
public IEnumerator GetEnumerator() => bits.GetEnumerator();
//public Bits LeftShift(int count) => new Bits(new BitArray(bits).LeftShift(count)); // Immutable.
public Bits Not() => new Bits(new BitArray(bits).Not()); // Immutable.
public Bits Or(Bits value) => new Bits(new BitArray(this.bits).Or(value.bits)); // Immutable.
//public Bits RightShift(int count) => new Bits(new BitArray(bits).RightShift(count)); // Immutable.
public void Set(int index, bool value) => bits.Set(index, value);
public void SetAll(bool value) => bits.SetAll(value);
public Bits Xor(Bits value) => new Bits(new BitArray(this.bits).Xor(value.bits)); // Immutable.
public static Bits Concat(Bits highBits, Bits lowBits) // ASL: ":".
{
if (((object)lowBits == null) || ((object)highBits == null))
{
throw new ArgumentNullException();
}
bool[] dst = new bool[lowBits.Count + highBits.Count];
lowBits.CopyTo(dst, 0);
highBits.CopyTo(dst, lowBits.Count);
return new Bits(dst);
}
public static Bits Concat(bool bit3, bool bit2, bool bit1, bool bit0) // ASL: ":::".
{
return new Bits(new bool[] {bit0, bit1, bit2, bit3});
}
public static implicit operator Bits(bool value) => new Bits(1, value);
public static implicit operator Bits(string value)
{
if (String.IsNullOrEmpty(value))
{
throw new InvalidCastException();
}
bool[] dst = new bool[value.Length];
for (int i = value.Length - 1, n = 0; i >= 0; i--, n++)
{
if (value[i] == '1')
{
dst[n] = true;
}
else if (value[i] == '0')
{
dst[n] = false;
}
else
{
throw new InvalidCastException();
}
}
return new Bits(dst);
}
public static explicit operator bool(Bits bit)
{
if (((object)bit == null) || (bit.Count != 1))
{
throw new InvalidCastException();
}
return bit.Get(0);
}
public static Bits operator +(Bits left, BigInteger right) // ASL: "+".
{
if (((object)left == null) || ((object)right == null))
{
throw new ArgumentNullException();
}
BigInteger dst = left.ToBigInteger() + right;
return dst.SubBigInteger(left.Count - 1, 0);
}
public static Bits operator +(Bits left, Bits right) // ASL: "+".
{
if (((object)left == null) || ((object)right == null))
{
throw new ArgumentNullException();
}
if (left.Count != right.Count)
{
throw new InvalidOperationException();
}
BigInteger dst = left.ToBigInteger() + right.ToBigInteger();
return dst.SubBigInteger(left.Count - 1, 0);
}
public static Bits operator -(Bits left, Bits right) // ASL: "-".
{
if (((object)left == null) || ((object)right == null))
{
throw new ArgumentNullException();
}
if (left.Count != right.Count)
{
throw new InvalidOperationException();
}
BigInteger dst = left.ToBigInteger() - right.ToBigInteger();
return dst.SubBigInteger(left.Count - 1, 0);
}
public static bool operator ==(Bits left, Bits right) // ASL: "==".
{
if (((object)left == null) || ((object)right == null))
{
throw new ArgumentNullException();
}
if (left.Count != right.Count)
{
return false;
}
for (int i = 0; i <= left.Count - 1; i++)
{
if (left.Get(i) != right.Get(i))
{
return false;
}
}
return true;
}
public static bool operator !=(Bits left, Bits right) // ASL: "!=".
{
return !(left == right);
}
public bool Equals(Bits right) // ASL: "==".
{
if ((object)right == null)
{
throw new ArgumentNullException();
}
Bits left = this;
if (left.Count != right.Count)
{
return false;
}
for (int i = 0; i <= left.Count - 1; i++)
{
if (left.Get(i) != right.Get(i))
{
return false;
}
}
return true;
}
public override bool Equals(object obj)
{
if (obj == null)
{
throw new ArgumentNullException();
}
Bits right = obj as Bits;
return Equals(right);
}
public override int GetHashCode() => bits.GetHashCode();
}
}

42
Ryujinx.Tests/Cpu/Tester/Types/Integer.cs
View file

@ -1,42 +0,0 @@
// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Integer.cs
using System;
using System.Numerics;
namespace Ryujinx.Tests.Cpu.Tester.Types
{
internal static class Integer
{
public static Bits SubBigInteger(this BigInteger x, int highIndex, int lowIndex) // ASL: "<:>".
{
if (highIndex < lowIndex)
{
throw new IndexOutOfRangeException();
}
Bits src = new Bits(x);
bool[] dst = new bool[highIndex - lowIndex + 1];
for (int i = lowIndex, n = 0; i <= highIndex; i++, n++)
{
if (i <= src.Count - 1)
{
dst[n] = src[i];
}
else
{
dst[n] = (x.Sign != -1 ? false : true); // Zero / Sign Extension.
}
}
return new Bits(dst);
}
public static bool SubBigInteger(this BigInteger x, int index) // ASL: "<>".
{
Bits dst = x.SubBigInteger(index, index);
return (bool)dst;
}
}
}

2
Ryujinx/Config.cs
View file

@ -36,6 +36,8 @@ namespace Ryujinx
Device.System.State.DockedMode = Convert.ToBoolean(Parser.Value("Docked_Mode"));
Device.EnableDeviceVsync = Convert.ToBoolean(Parser.Value("Enable_Vsync"));
string[] FilteredLogClasses = Parser.Value("Logging_Filtered_Classes").Split(',', StringSplitOptions.RemoveEmptyEntries);
GamePadEnable = Boolean.Parse(Parser.Value("GamePad_Enable"));

3
Ryujinx/Ryujinx.conf
View file

@ -28,6 +28,9 @@ Docked_Mode = false
#Whether or not to enable Controller support
GamePad_Enable = true
#Enable Game Vsync
Enable_Vsync = true
#Device Mappings
#Valid Mappings:

11
Ryujinx/Ui/GLScreen.cs
View file

@ -75,7 +75,7 @@ namespace Ryujinx
{
ResizeEvent = false;
Renderer.FrameBuffer.SetWindowSize(Width, Height);
Renderer.RenderTarget.SetWindowSize(Width, Height);
}
Ticks += Chrono.ElapsedTicks;
@ -98,7 +98,7 @@ namespace Ryujinx
Visible = true;
Renderer.FrameBuffer.SetWindowSize(Width, Height);
Renderer.RenderTarget.SetWindowSize(Width, Height);
Context.MakeCurrent(null);
@ -295,20 +295,23 @@ namespace Ryujinx
private new void RenderFrame()
{
Renderer.FrameBuffer.Render();
Renderer.RenderTarget.Render();
Device.Statistics.RecordSystemFrameTime();
double HostFps = Device.Statistics.GetSystemFrameRate();
double GameFps = Device.Statistics.GetGameFrameRate();
NewTitle = $"Ryujinx | Host FPS: {HostFps:0.0} | Game FPS: {GameFps:0.0}";
NewTitle = $"Ryujinx | Host FPS: {HostFps:0.0} | Game FPS: {GameFps:0.0} | Game Vsync: " +
(Device.EnableDeviceVsync ? "On" : "Off");
TitleEvent = true;
SwapBuffers();
Device.System.SignalVsync();
Device.VsyncEvent.Set();
}
protected override void OnUnload(EventArgs e)

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