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Address nits
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parent
4a257bf7a1
commit
d86dcaa13d
7 changed files with 32 additions and 29 deletions
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@ -1,9 +1,11 @@
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using ARMeilleure.State;
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namespace ARMeilleure.Decoders
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namespace ARMeilleure.Decoders
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{
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{
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class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm
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class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm
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{
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{
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public int Rd => 13;
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public int Rd => RegisterAlias.Aarch32Sp;
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public int Rn => 13;
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public int Rn => RegisterAlias.Aarch32Sp;
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public bool? SetFlags => false;
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public bool? SetFlags => false;
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@ -1,4 +1,5 @@
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using ARMeilleure.Instructions;
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using ARMeilleure.Instructions;
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using System;
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namespace ARMeilleure.Decoders
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namespace ARMeilleure.Decoders
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{
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{
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@ -50,7 +51,7 @@ namespace ARMeilleure.Decoders
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Immediate = ((opCode >> 6) & 0x1f) << 1;
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Immediate = ((opCode >> 6) & 0x1f) << 1;
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break;
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break;
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default:
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default:
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throw new System.InvalidOperationException();
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throw new InvalidOperationException();
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}
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}
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}
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}
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}
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}
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@ -1,9 +1,11 @@
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namespace ARMeilleure.Decoders
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using ARMeilleure.State;
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namespace ARMeilleure.Decoders
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{
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{
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class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem
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class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem
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{
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{
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public int Rt { get; }
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public int Rt { get; }
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public int Rn => 15;
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public int Rn => RegisterAlias.Aarch32Pc;
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public bool WBack => false;
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public bool WBack => false;
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public bool IsLoad => true;
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public bool IsLoad => true;
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@ -13,6 +15,7 @@
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public int Immediate { get; }
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public int Immediate { get; }
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode);
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode);
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public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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Rt = (opCode >> 8) & 7;
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Rt = (opCode >> 8) & 7;
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@ -16,26 +16,18 @@ namespace ARMeilleure.Decoders
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public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
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{
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{
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RegisterMask = opCode & 0xff;
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Rn = (opCode >> 8) & 7;
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int regCount = BitOperations.PopCount((uint)RegisterMask);
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int regCount = BitOperations.PopCount((uint)RegisterMask);
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switch (inst.Name)
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RegisterMask = opCode & 0xff;
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Rn = (opCode >> 8) & 7;
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Offset = 0;
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PostOffset = 4 * regCount;
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IsLoad = inst.Name switch
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{
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{
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case InstName.Stm:
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InstName.Ldm => true,
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IsLoad = false;
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InstName.Stm => false,
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Offset = 0;
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_ => throw new InvalidOperationException()
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PostOffset = 4 * regCount;
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};
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break;
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case InstName.Ldm:
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IsLoad = true;
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Offset = 0;
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PostOffset = 4 * regCount;
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break;
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default:
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throw new InvalidOperationException();
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}
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}
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}
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}
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}
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}
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}
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@ -1,9 +1,11 @@
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namespace ARMeilleure.Decoders
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using ARMeilleure.State;
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namespace ARMeilleure.Decoders
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{
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{
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class OpCodeT16MemSp : OpCodeT16, IOpCode32Mem
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class OpCodeT16MemSp : OpCodeT16, IOpCode32Mem
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{
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{
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public int Rt { get; }
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public int Rt { get; }
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public int Rn => 13;
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public int Rn => RegisterAlias.Aarch32Sp;
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public bool WBack => false;
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public bool WBack => false;
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public bool IsLoad { get; }
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public bool IsLoad { get; }
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@ -1,4 +1,5 @@
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using ARMeilleure.Instructions;
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using ARMeilleure.Instructions;
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using ARMeilleure.State;
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using System;
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using System;
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using System.Numerics;
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using System.Numerics;
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@ -6,7 +7,7 @@ namespace ARMeilleure.Decoders
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{
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{
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class OpCodeT16MemStack : OpCodeT16, IOpCode32MemMult
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class OpCodeT16MemStack : OpCodeT16, IOpCode32MemMult
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{
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{
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public int Rn => 13;
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public int Rn => RegisterAlias.Aarch32Sp;
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public int RegisterMask { get; }
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public int RegisterMask { get; }
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public int PostOffset { get; }
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public int PostOffset { get; }
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public bool IsLoad { get; }
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public bool IsLoad { get; }
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@ -1,9 +1,11 @@
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using ARMeilleure.State;
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namespace ARMeilleure.Decoders
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namespace ARMeilleure.Decoders
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{
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{
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class OpCodeT16SpRel : OpCodeT16, IOpCode32AluImm
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class OpCodeT16SpRel : OpCodeT16, IOpCode32AluImm
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{
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{
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public int Rd { get; }
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public int Rd { get; }
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public int Rn => 13;
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public int Rn => RegisterAlias.Aarch32Sp;
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public bool? SetFlags => false;
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public bool? SetFlags => false;
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