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Address nits

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This commit is contained in:
merry 2022-02-14 21:48:10 +00:00
parent 4a257bf7a1
commit d86dcaa13d
7 changed files with 32 additions and 29 deletions
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6
ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
View file

@ -1,9 +1,11 @@
using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm
{
public int Rd => 13;
public int Rn => 13;
public int Rd => RegisterAlias.Aarch32Sp;
public int Rn => RegisterAlias.Aarch32Sp;
public bool? SetFlags => false;

3
ARMeilleure/Decoders/OpCodeT16MemImm5.cs
View file

@ -1,4 +1,5 @@
using ARMeilleure.Instructions;
using System;
namespace ARMeilleure.Decoders
{
@ -50,7 +51,7 @@ namespace ARMeilleure.Decoders
Immediate = ((opCode >> 6) & 0x1f) << 1;
break;
default:
throw new System.InvalidOperationException();
throw new InvalidOperationException();
}
}
}

7
ARMeilleure/Decoders/OpCodeT16MemLit.cs
View file

@ -1,9 +1,11 @@
namespace ARMeilleure.Decoders
using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem
{
public int Rt { get; }
public int Rn => 15;
public int Rn => RegisterAlias.Aarch32Pc;
public bool WBack => false;
public bool IsLoad => true;
@ -13,6 +15,7 @@
public int Immediate { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode);
public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rt = (opCode >> 8) & 7;

28
ARMeilleure/Decoders/OpCodeT16MemMult.cs
View file

@ -11,31 +11,23 @@ namespace ARMeilleure.Decoders
public int PostOffset { get; }
public bool IsLoad { get; }
public int Offset { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemMult(inst, address, opCode);
public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int regCount = BitOperations.PopCount((uint)RegisterMask);
RegisterMask = opCode & 0xff;
Rn = (opCode >> 8) & 7;
int regCount = BitOperations.PopCount((uint)RegisterMask);
switch (inst.Name)
Offset = 0;
PostOffset = 4 * regCount;
IsLoad = inst.Name switch
{
case InstName.Stm:
IsLoad = false;
Offset = 0;
PostOffset = 4 * regCount;
break;
case InstName.Ldm:
IsLoad = true;
Offset = 0;
PostOffset = 4 * regCount;
break;
default:
throw new InvalidOperationException();
}
InstName.Ldm => true,
InstName.Stm => false,
_ => throw new InvalidOperationException()
};
}
}
}

6
ARMeilleure/Decoders/OpCodeT16MemSp.cs
View file

@ -1,9 +1,11 @@
namespace ARMeilleure.Decoders
using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCodeT16MemSp : OpCodeT16, IOpCode32Mem
{
public int Rt { get; }
public int Rn => 13;
public int Rn => RegisterAlias.Aarch32Sp;
public bool WBack => false;
public bool IsLoad { get; }

7
ARMeilleure/Decoders/OpCodeT16MemStack.cs
View file

@ -1,4 +1,5 @@
using ARMeilleure.Instructions;
using ARMeilleure.State;
using System;
using System.Numerics;
@ -6,19 +7,19 @@ namespace ARMeilleure.Decoders
{
class OpCodeT16MemStack : OpCodeT16, IOpCode32MemMult
{
public int Rn => 13;
public int Rn => RegisterAlias.Aarch32Sp;
public int RegisterMask { get; }
public int PostOffset { get; }
public bool IsLoad { get; }
public int Offset { get; }
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemStack(inst, address, opCode);
public OpCodeT16MemStack(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
int extra = (opCode >> 8) & 1;
int regCount = BitOperations.PopCount((uint)opCode & 0x1ff);
switch (inst.Name)
{
case InstName.Push:

4
ARMeilleure/Decoders/OpCodeT16SpRel.cs
View file

@ -1,9 +1,11 @@
using ARMeilleure.State;
namespace ARMeilleure.Decoders
{
class OpCodeT16SpRel : OpCodeT16, IOpCode32AluImm
{
public int Rd { get; }
public int Rn => 13;
public int Rn => RegisterAlias.Aarch32Sp;
public bool? SetFlags => false;