FICTURE7 1aa6bde574 Merge integer & vector register set ... Improve handling of caller saved registers as well.		2022-09-05 00:01:49 +04:00
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CodeGen	Merge integer & vector register set	2022-09-05 00:01:49 +04:00
Common	A few minor documentation fixes. (#3599)	2022-08-19 18:21:06 -03:00
Decoders	Implement some 32-bit Thumb instructions (#3614)	2022-08-25 09:59:34 +00:00
Diagnostics	Add an early TailMerge pass (#2721)	2021-10-18 19:51:22 -03:00
Instructions	ARMeilleure: Hardware accelerate SHA256 (#3585)	2022-08-25 10:12:13 +00:00
IntermediateRepresentation	Improve HyrbidAllocator	2022-09-05 00:01:47 +04:00
Memory	Replace CacheResourceWrite with more general "precise" write (#2684)	2021-09-29 02:27:03 +02:00
Signal	Removed unused usings. (#3593)	2022-08-18 18:04:54 +02:00
State	Refactor CPU interface to allow the implementation of other CPU emulators (#3362)	2022-05-31 16:29:35 -03:00
Translation	Optimize kernel memory block lookup and consolidate RBTree implementations (#3410)	2022-08-26 18:21:48 +00:00
Allocators.cs	Optimize LSRA (#2563)	2021-10-08 18:15:44 -03:00
ARMeilleure.csproj	Remove usage of Mono.Posix.NETStandard accross all projects (#2906)	2021-12-08 18:24:26 -03:00
Optimizations.cs	ARMeilleure: Hardware accelerate SHA256 (#3585)	2022-08-25 10:12:13 +00:00
Statistics.cs	Suppress warnings from fields never used or never assigned (CS0169 and CS0649) (#919)	2020-04-21 07:59:59 +10:00