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Convert T32 CPU tests to xUnit
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@ -1,4 +1,4 @@
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// #define T32Alu
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#define T32Alu
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using Xunit;
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@ -8,18 +8,6 @@ namespace Ryujinx.Tests.Cpu
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public sealed class CpuTestT32Alu : CpuTest32
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{
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#if T32Alu
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[Test]
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public void TestT32AluRsImm([ValueSource(nameof(RsImmTestCases))] PrecomputedThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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[Test]
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public void TestT32AluImm([ValueSource(nameof(ImmTestCases))] PrecomputedThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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public static readonly PrecomputedThumbTestCase[] RsImmTestCases =
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{
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// TST (reg)
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@ -1013,6 +1001,23 @@ namespace Ryujinx.Tests.Cpu
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FinalRegs = new uint[] { 0x2bb00694, 0x1c56a4c0, 0xc5cc4a3e, 0xc627c1ab, 0xe0cc0e5c, 0x1f3d71a4, 0x897d57b8, 0x0d4a7208, 0x433b7b88, 0xaaf24fd6, 0x2438f5f8, 0x9875e64a, 0xda475f22, 0x66d5e2e7, 0x00000001, 0x700001f0 },
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},
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};
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public static readonly EnumerableTheoryData<PrecomputedThumbTestCase> TestData_RsImm = new(RsImmTestCases);
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public static readonly EnumerableTheoryData<PrecomputedThumbTestCase> TestData_Imm = new(ImmTestCases);
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[Theory]
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[MemberData(nameof(TestData_RsImm))]
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public void TestT32AluRsImm(PrecomputedThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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[Theory]
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[MemberData(nameof(TestData_Imm))]
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public void TestT32AluImm(PrecomputedThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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#endif
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}
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}
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@ -1,4 +1,4 @@
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// #define T32Flow
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#define T32Flow
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using ARMeilleure.State;
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using Xunit;
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@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu
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public sealed class CpuTestT32Flow : CpuTest32
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{
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#if T32Flow
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[Test]
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[Fact]
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public void TestT32B1()
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{
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// BNE label
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@ -27,7 +27,7 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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[Fact]
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public void TestT32B2()
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{
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// BNE label1
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@ -51,7 +51,7 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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[Fact]
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public void TestT32B3()
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{
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// B.W label
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@ -69,7 +69,7 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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[Fact]
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public void TestT32B4()
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{
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// B.W label1
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@ -93,7 +93,7 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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}
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[Test]
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[Fact]
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public void TestT32Bl()
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{
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// BL label
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@ -112,10 +112,10 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
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Assert.Equal(CodeBaseAddress + 0x5, GetContext().GetX(0));
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}
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[Test]
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[Fact]
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public void TestT32Blx1()
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{
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// BLX label
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@ -136,11 +136,11 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x5));
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Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
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Assert.Equal(CodeBaseAddress + 0x5, GetContext().GetX(0));
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Assert.False(GetContext().GetPstateFlag(PState.TFlag));
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}
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[Test]
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[Fact]
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public void TestT32Blx2()
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{
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// NOP
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@ -163,8 +163,8 @@ namespace Ryujinx.Tests.Cpu
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ExecuteOpcodes(runUnicorn: false);
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Assert.That(GetContext().GetX(0), Is.EqualTo(CodeBaseAddress + 0x7));
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Assert.That(GetContext().GetPstateFlag(PState.TFlag), Is.EqualTo(false));
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Assert.Equal(CodeBaseAddress + 0x7, GetContext().GetX(0));
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Assert.False(GetContext().GetPstateFlag(PState.TFlag));
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}
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#endif
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}
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@ -1,5 +1,6 @@
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// #define T32Mem
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#define T32Mem
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using System;
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using Xunit;
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namespace Ryujinx.Tests.Cpu
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@ -8,12 +9,6 @@ namespace Ryujinx.Tests.Cpu
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public sealed class CpuTestT32Mem : CpuTest32
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{
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#if T32Mem
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[Test]
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public void TestT32MemImm([ValueSource(nameof(ImmTestCases))] PrecomputedMemoryThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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public static readonly PrecomputedMemoryThumbTestCase[] ImmTestCases =
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{
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// STRB (imm8)
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@ -519,6 +514,15 @@ namespace Ryujinx.Tests.Cpu
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MemoryDelta = Array.Empty<(ulong Address, ushort Value)>(),
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},
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};
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public static readonly EnumerableTheoryData<PrecomputedMemoryThumbTestCase> TestData = new(ImmTestCases);
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[Theory]
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[MemberData(nameof(TestData))]
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public void TestT32MemImm(PrecomputedMemoryThumbTestCase test)
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{
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RunPrecomputedTestCase(test);
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}
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#endif
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}
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}
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